Power semiconductor device and method for manufacturing a power semiconductor device

Abstract

A power semiconductor device (1), comprising a semiconductor body (10) configured to conduct a forward load current between a first load terminal (11) and a second load terminal (12); a main control terminal (13-1); an auxiliary control terminal (13-2) isolated from the main control terminal (13-1); a control electrode structure (14, 15) comprising: a main control electrode (141) electrically connected to the main control terminal (13-1) and configured to control the forward load current, and auxiliary control electrodes (151) electrically connected to the auxiliary control terminal (13-2) and configured to control an overload current;and an overload structure (155) electrically connected between the second load terminal (12) and the auxiliary control terminal (13-2), wherein the overload structure is configured to apply an auxiliary control voltage greater than a threshold voltage to the auxiliary control trench electrodes (151) when a voltage between the first load terminal (11) and the second load terminal (12) exceeds a maximum value and / or when the voltage between the second load terminal (12) and the auxiliary control terminal (13-2) is above a breakdown voltage of the overload structure (155);

Description

Technical area

[0001] This description relates to embodiments of a power semiconductor device and to embodiments of a method for manufacturing a power semiconductor device. The power semiconductor device may have a voltage self-clamping configuration. background

[0002] Many functions of modern devices in automotive, consumer, and industrial applications, such as converting electrical energy and driving an electric motor or machine, rely on power semiconductor devices. For example, insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor field-effect transistors (MOSFETs), and diodes, to name a few, have been used for various applications, including but not limited to switches in power supplies and power converters.

[0003] A power semiconductor device comprises a semiconductor body configured to conduct a forward load current along a load current path between two load terminals of the device. The load current is conducted by an active region of the power semiconductor device. The active region is surrounded by an edge termination region, which is terminated by an edge of the chip.

[0004] In the case of a controllable power semiconductor device, e.g., a transistor, the load current path can be controlled by means of insulated electrodes, commonly referred to as gate electrodes. For example, upon receiving a corresponding control signal, e.g., from a driver unit and via a control terminal of the device, the control electrodes can place the power semiconductor device between a forward conducting state and a blocking state.

[0005] Furthermore, some devices provide reverse load current capability; that is, the active region of the semiconductor body is further configured to conduct a reverse load current along a reverse load current path between the two load terminals of the device. For example, the RC (reverse current) IGBT is one example of such devices. In an RC-IGBT, a single chip combines an IGBT structure and a diode structure.

[0006] In a typical IGBT design, the gate electrodes are housed in a trench structure that extends into the semiconductor body. The trench structure defines sections of the semiconductor body, typically referred to as mesas, where conductive channels can be formed to allow the flow of forward load current. The conductive channels, typically based on a semiconductor source region and a semiconductor body region of the opposite conductivity type to the source region, are controlled based on the adjacent control electrodes.

[0007] Even when switched off, an overvoltage can force a current through the device. For example, such a current is forced through an inductor, a luminous discharge, or the like. Some devices are configured to handle such a situation, at least for a certain period of time or with a certain amount of dissipated energy, without being destroyed. Such a device is commonly referred to as a "voltage self-clamping device" or an "avalanche-robust device."

[0008] Two modes of self-clamping can be distinguished: One is known as "power clamp," in which the device remains off and the heat generated by the forced current through the device is dissipated through the active region. The other mode is known as "active clamp," in which, when the overvoltage is detected, the device is turned on by subjecting the gate electrode to a corresponding control signal.

[0009] The present disclosure relates to the “active clamping” mode. SUMMARY

[0010] The subject matter of the independent claims is presented. Features of embodiments are defined in the dependent claims.

[0011] According to one embodiment, a power semiconductor device comprises: an active region surrounded by an edge termination region; a semiconductor body extending into both the active region and the edge termination region and comprising, in the active region, a semiconductor drift region of a first conductivity type; a first load terminal on a first side of the semiconductor body; a second load terminal on a second side of the semiconductor body opposite the first side, wherein the power semiconductor device is configured to conduct a forward load current between the first load terminal and the second load terminal in the active region; a main control terminal; an auxiliary control terminal isolated from the main control terminal;in the active region, a trench structure extending along a vertical direction from the first side to the second side, the trench structure comprising main control trenches, each of the main control trenches including a main control trench electrode electrically connected to the main control terminal and configured to control the forward load current, and auxiliary control trenches, each of the auxiliary control trenches including an auxiliary control trench electrode electrically connected to the auxiliary control terminal and configured to control an overload current;an overload structure connected between the second load terminal and the auxiliary control terminal, the overload structure being configured to apply an auxiliary control voltage greater than a threshold voltage to the auxiliary control trench electrodes when a voltage between the first load terminal and the second load terminal exceeds a maximum value and / or when the voltage between the second load terminal and the auxiliary control terminal is above a breakdown voltage of the overload structure;

[0012] According to another embodiment, a power semiconductor device comprises: a semiconductor body; a first load terminal; a second load terminal, wherein the power semiconductor device is configured to conduct a forward load current between the first load terminal and the second load terminal; a main control terminal; an auxiliary control terminal isolated from the main control terminal; a control electrode structure comprising: main control electrodes electrically connected to the main control terminal and configured to control the forward load current, and auxiliary control electrodes electrically connected to the auxiliary control terminal and configured to control an overload current;an overload structure electrically connected between the second load terminal and the auxiliary control terminal, the overload structure being configured to apply an auxiliary control voltage greater than a threshold voltage to the auxiliary control electrodes when a voltage between the first load terminal and the second load terminal exceeds a maximum value and / or when the voltage between the second load terminal and the auxiliary control terminal is above a breakdown voltage of the overload structure;

[0013] According to another embodiment, a method for manufacturing a power semiconductor device comprises forming the following components: an active region surrounded by an edge termination region; a semiconductor body extending into both the active region and the edge termination region and comprising, in the active region, a semiconductor drift region of a first conductivity type; a first load terminal on a first side of the semiconductor body; a second load terminal on a second side of the semiconductor body opposite the first side, wherein the power semiconductor device is configured to conduct a forward load current between the first load terminal and the second load terminal in the active region; a main control terminal; an auxiliary control terminal isolated from the main control terminal;in the active region, a trench structure extending along a vertical direction from the first side to the second side, the trench structure comprising main control trenches, each of the main control trenches including a main control trench electrode electrically connected to the main control terminal and configured to control the forward load current, and auxiliary control trenches, each of the auxiliary control trenches including an auxiliary control trench electrode electrically connected to the auxiliary control terminal and configured to control an overload current;an overload structure connected between the second load terminal and the auxiliary control terminal, the overload structure being configured to apply an auxiliary control voltage greater than a threshold voltage to the auxiliary control trench electrodes when a voltage between the first load terminal and the second load terminal exceeds a maximum value and / or when the voltage between the second load terminal and the auxiliary control terminal is above a breakdown voltage of the overload structure;

[0014] According to yet another embodiment, a method of manufacturing a power semiconductor device comprises forming the following components: a semiconductor body; a first load terminal; a second load terminal, wherein the power semiconductor device is configured to conduct a forward load current between the first load terminal and the second load terminal; a main control terminal; an auxiliary control terminal isolated from the main control terminal; a control electrode structure comprising: main control electrodes electrically connected to the main control terminal and configured to control the forward load current, and auxiliary control electrodes electrically connected to the auxiliary control terminal and configured to control an overload current;an overload structure electrically connected between the second load terminal and the auxiliary control terminal, the overload structure being configured to apply an auxiliary control voltage greater than a threshold voltage to the auxiliary control electrodes when a voltage between the first load terminal and the second load terminal exceeds a maximum value and / or when the voltage between the second load terminal and the auxiliary control terminal is above a breakdown voltage of the overload structure;

[0015] According to embodiments described herein, in order to actively turn on the device in the event of an overload situation, auxiliary electrodes are provided separately from the regular control electrodes used to control the load current under nominal conditions. To provide the auxiliary control electrodes with a separate control signal, an appropriately configured overload structure can be coupled to the auxiliary control electrodes. The separately provided auxiliary control electrodes can be integrated into the active region, e.g., as part of a mesa trench pattern. The control of the auxiliary control electrodes can be independent of the control of the main control electrodes. That is, the auxiliary control electrodes can be electrically isolated from each other and provided with separate control signals.

[0016] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings. Short description of the drawings

[0017] The parts in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. Furthermore, like reference numerals designate corresponding parts throughout the figures. In the drawings: Fig. 1 schematically and exemplarily shows a horizontal projection of a power semiconductor device according to one or more embodiments; Fig. 2 schematically and by way of example, a vertical cross section of a power semiconductor device according to one or more embodiments; Fig. 3 schematically and exemplarily shows a circuit diagram of a power semiconductor device according to an example; Fig. 4 schematically and exemplarily shows a circuit diagram of a power semiconductor device according to one or more embodiments; Fig. 5 schematically and exemplarily shows a horizontal projection of a power semiconductor device according to one or more embodiments; Fig. 6 schematically and exemplarily shows four views of sections of a power semiconductor device according to one or more embodiments; Fig. 7 schematically and exemplarily shows four views of sections of some embodiments of a power semiconductor device; Fig. 8 schematically and by way of example, a horizontal projection of two variants of an overload structure of a power semiconductor device according to one or more embodiments; Fig. 9 schematically and exemplarily shows a horizontal projection of a power semiconductor device according to one or more embodiments; Fig. 10 schematically and exemplarily shows a portion of a vertical cross section of a power semiconductor device according to one or more embodiments; Fig. 11 schematically and exemplarily shows a horizontal projection of a power semiconductor device according to one or more embodiments; and Fig. 12 schematically and exemplarily shows a horizontal projection of a power semiconductor device according to one or more embodiments. Detailed description

[0018] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced.

[0019] In this regard, directional terminology such as "top," "bottom," "below," "front," "back," "rear," "leading," "trailing," "over," etc., may be used with reference to the orientation of the described figures. Because portions of embodiments may be positioned in a number of different orientations, the directional terminology is used for illustrative purposes and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

[0020] Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Each example is provided for illustration and is not intended to be limiting of the invention. For example, features illustrated or described as part of one embodiment may be used on or in conjunction with other embodiments to yield yet another embodiment. It is intended that the present invention include such modifications and variations. The examples are described using specific language that should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only.For the sake of clarity, the same elements or manufacturing steps in the different drawings have been designated by the same reference numerals unless otherwise indicated.

[0021] The term "horizontal" as used in this specification is intended to describe an orientation substantially parallel to a horizontal surface of a semiconductor substrate or structure. This may, for example, be the surface of a semiconductor wafer, die, or chip. For example, both the first lateral direction X and the second lateral direction Y mentioned below may be horizontal directions, and the first lateral direction X and the second lateral direction Y may be perpendicular to each other.

[0022] The term "vertical" as used in this specification is intended to describe an orientation that is substantially perpendicular to the horizontal surface, i.e., parallel to the normal direction of the surface of the semiconductor wafer / chip / die. For example, the extension direction Z mentioned below may be an extension direction that is perpendicular to both the first lateral direction X and the second lateral direction Y.

[0023] In this specification, n-doped is referred to as the "first conductivity type," while p-doped is referred to as the "second conductivity type." Alternatively, opposite doping relationships can be used, so that the first conductivity type can be p-doped and the second conductivity type can be n-doped.

[0024] In the context of the present description, the terms “in ohmic contact”, “in electrical contact”, “in ohmic connection” and “electrically connected” are intended to describe that there is a low-resistance electrical connection or a low-resistance current path between two regions, sections, zones, portions or parts of a semiconductor device, or between different terminals of one or more devices, or between a terminal or metallization or electrode and a portion or part of a semiconductor device, where “low-resistance” may mean that the properties of the respective contact are substantially unaffected by the ohmic resistance. Furthermore, the term “in contact” in the context of the present description is intended to describe that there is a direct physical connection between two elements of the respective semiconductor device; e.g.a transition between two elements that are in contact with each other cannot include any further intermediate element or the like.

[0025] Additionally, in the context of the present description, the term "electrical isolation," unless otherwise stated, is used in the context of its generally accepted understanding and thus intends to describe that two or more components are positioned separately from each other and that there is no ohmic connection connecting these components. However, components that are electrically isolated from each other may nevertheless be coupled to each other, for example, mechanically coupled and / or capacitively coupled and / or inductively coupled and / or electrostatically coupled (for example, in the case of a junction). To give an example, two electrodes of a capacitor may be electrically isolated from each other and simultaneously mechanically and capacitively coupled to each other, e.g., by means of insulation, e.g., a dielectric.

[0026] Specific embodiments described in this specification relate to, but are not limited to, a power semiconductor device that can be used within a power converter or a power supply. Thus, in one embodiment, such a power semiconductor device may be configured to carry a load current to be supplied to a load and / or provided by a power source, respectively. For example, the power semiconductor device may comprise one or more active power semiconductor unit cells, such as a monolithically integrated diode cell, a derivative of a monolithically integrated diode cell, a monolithically integrated transistor cell, e.g., a monolithically integrated IGBT or MOSFET cell, and / or derivatives thereof. Such diode / transistor cells may be integrated within a single chip.A plurality of such cells may form a cell array arranged within an active region of the power semiconductor device.

[0027] The term "off-state" of the power semiconductor device may refer to conditions when the power semiconductor is in a state configured to block load current flow while an external voltage is applied. In particular, the power semiconductor device may be configured to block forward load current through the power semiconductor device while a forward voltage bias is applied. In comparison, the power semiconductor device may be configured to conduct the forward load current in a "conducting state" of the power semiconductor device while a forward voltage bias is applied. A transition between the off-state and the conducting state may be controlled by a control electrode or, in particular, a potential of the control electrode.Of course, the electrical properties can only be valid within a predetermined operating range of the external voltage and current density within the power semiconductor device. The term "forward-biased off-state" can therefore refer to conditions where the power semiconductor device is in the off-state while a forward bias voltage is applied.

[0028] The term "power semiconductor device" as used in this specification is intended to describe a single-chip power semiconductor device with high voltage blocking and / or high current carrying capabilities. In other words, such a power semiconductor device is intended for high current, typically in the ampere range, e.g., up to several tens or hundreds of amperes, and / or high voltages, typically above 15 V, more typically 100 V and above, e.g., up to at least 600 V or even more, e.g., up to at least 1.2 kV or even up to 6 kV or more, depending on the particular application.

[0029] For example, the term “power semiconductor device” as used in this specification is not directed to logic semiconductor devices used, for example, for storing data, computing data, and / or other types of semiconductor-based data processing.

[0030] For example, the power semiconductor device described below may be a single semiconductor chip having, for example, a strip cell configuration (or a cell / needle cell configuration) and may be configured to be used as a power component in a low, medium, and / or high voltage application.

[0031] In relation to Fig. 1 and Fig. 2, aspects relating to a possible general configuration of the power semiconductor device 1 are to be explained:

[0032] The power semiconductor device 1, also referred to herein as "device 1," comprises, for example, in a single chip, a semiconductor body 10 configured to conduct a load current in an active region 1-2 between a first load terminal 11 on a first side 110 of the semiconductor body 10 and a second load terminal 12 on a second side 120 of the semiconductor body 10. The device 1 may, for example, be an IGBT (or a derivative thereof, such as an RC-IGBT) or, for example, a MOSFET (or a derivative thereof). Accordingly, the first load terminal 11 may be an emitter terminal (or source terminal) and the second load terminal 12 may be a collector terminal (or drain terminal).

[0033] As in Fig. 1, the active region 1-2 of the device 1 is surrounded by an edge termination region 1-3. In the active region 1-2, a trench structure (see also Fig. 10, reference numerals 14, 15, 16) form a cell array, which is explained further below. The edge termination region 1-3 is typically not used for load current conduction, as is known to those skilled in the art. The edge termination region 1-3 is terminated by the chip edge 1-4.

[0034] As in Fig. 2, the first side 110 and the second side 120 may be arranged opposite each other. For example, the first side 110 is a front side of the device 1 and the second side 120 is a back side of the device 1. Accordingly, the device 1 may have a vertical configuration, according to which the load current within the device 1 follows a path parallel to the vertical direction Z. The semiconductor body 10 may be sandwiched between the first load terminal 11 and the second load terminal 12 and have a vertical extension d, e.g., in the range of 40 µm to 500 µm, depending, e.g., on the maximum blocking voltage that the device 1 is intended to have.

[0035] The device 1 further comprises a drift region 100 of a first conductivity type within the semiconductor body 10. The term "drift region" is used herein with the meaning typically associated with it by those skilled in the art in the field of power semiconductor devices. For example, the vertical extension of the drift region 100 influences the voltage blocking capabilities (e.g., the maximum blocking voltage) of the device 1.

[0036] As in Fig. 10, the device 1 may further comprise a trench structure 14, 15, 16 extending from the first side 110 into the semiconductor body 10 to the second side 120, e.g., along the vertical direction Z.

[0037] The trench structure may comprise main control trenches 14, each of the main control trenches 14 including a main control trench electrode 141 electrically connected to a main control terminal 13-1 (see Fig. 1) and configured to control the forward load current under nominal conditions. Each main control trench 14 may include a main control trench insulator 142 that electrically isolates the main control trench electrode 141 from the semiconductor body 10.

[0038] The trench structure may further comprise auxiliary control trenches 15, each of the auxiliary control trenches 15 including an auxiliary control trench electrode 151 electrically connected to an auxiliary control terminal 13-2 and configured to control an overload current. Each auxiliary control trench 15 may include an auxiliary control trench insulator 152 electrically isolating the auxiliary control trench electrode 151 from the semiconductor body 10.

[0039] The trench structure may further comprise source trenches 16, each of the source trenches 16 including a source trench electrode 161 electrically connected to the first load terminal 11. Each source trench 16 may include a source trench insulator 162 electrically isolating the source trench electrode 161 from the semiconductor body 10.

[0040] As shown schematically in Fig. 2 and more detailed in Fig. 10, the semiconductor body 10 may comprise on the first side 110 a semiconductor body region 102 of the second conductivity type electrically connected to the first load terminal 11 and a semiconductor source region 101 of the first conductivity type electrically connected to the first load terminal 11, wherein the semiconductor source region 101 is insulated from the drift region 100 by at least the semiconductor body region 102.

[0041] The main control trench electrode 141 of the trench structure may be configured to induce an inversion channel in the semiconductor body region 102 when exposed to a corresponding ON control signal (e.g., provided by a driver unit) via a control terminal 13. This process may place the device 1 in the conducting state. The control trench electrode 141 may further be configured to turn off the inversion channel in the semiconductor body region 102 when exposed to a corresponding OFF control signal, which may place the device 1 in the forward-biased blocking state.

[0042] The semiconductor source region 101 and the semiconductor body region 102 may be accommodated within mesas that are laterally delimited by the main control trenches 14, the auxiliary control trenches 15, and the optionally provided source trenches 16. For example, mesas 17 of the first type are electrically connected to the first load terminal 11, e.g., via first contact plugs 111 that penetrate an insulating layer 19, as shown in Fig. 10. The mesas 17 of the first type may be configured to conduct the forward load current. For example, mesas 18 of the second type are not connected to the first load terminal 11 in this manner.

[0043] It is understood that the source trenches 16 are optionally provided and that based on the main control trenches 14, the auxiliary control trenches 15 and the optionally provided source trenches 16, any trench mesa patterns may be formed in the active region 1-2 according to some embodiments.

[0044] With further reference to Fig. 2, a doped region 108 of the semiconductor body 10 below the drift region 100, which is adjacent to the second load terminal 12 on the second side 120, may be configured according to the designated property of the device 1.

[0045] For example, if the device 1 is to have an IGBT configuration, the doped region 108 may be an emitter region of the second conductivity type. The doped region 108 is arranged in contact with the second load terminal 12. If the device 1 is to have an RC-IGBT configuration, the doped region 108 may be an emitter region of the second conductivity type, which includes portions of the first conductivity type, as is known to those skilled in the art.

[0046] If the device 1 is to have a MOSFET configuration, the doped region 108 may be a highly doped region of the first conductivity type adjacent to the second load terminal 12.

[0047] In addition, a field stop region (not shown) of the first conductivity type may be provided between the drift region 100 and the second load terminal 12, wherein the field stop region has a larger dopant concentration than the drift region 100.

[0048] Fig. Figure 3 illustrates schematically and by way of example a circuit diagram of an exemplary power semiconductor device 1'. The device 1' may, for example, have a configuration as described with respect to Fig. 1, Fig. 2 and Fig. 10, but without the auxiliary control trenches 15. There, an overload structure 155 is provided. For example, the overload structure 155 may include a plurality of Zener diodes 156 connected in series. The overload structure 155 is connected to the second load terminal 12 and, via the resistor 140 (R1), to the control terminal 13. The overload structure 155 is further connected, via the resistor 150 (R2), to the first load terminal 11. For example, in an overload situation during which, for example, the voltage between the first load terminal 11 and the second load terminal 12 exceeds a maximum value, e.g., corresponding to the maximum reverse voltage of the device 1', the overload structure 15 may become conductive and thereby generate a voltage at the control terminal 13 based on the resistor 150 (R2), which voltage may place the device 1 into the forward conducting state (active voltage clamping).A portion of the forward load current is then conducted through the device 1' and another (usually much smaller) portion of it through the overload structure 155 and the resistor 150 (R2).

[0049] Fig. Figure 4 schematically illustrates, by way of example, a circuit diagram of the power semiconductor device 1 according to an embodiment. The device 1 may, for example, have a configuration as described with reference to Fig. 1, Fig. 2 and Fig. 10, but now including the auxiliary tax ditches 15.

[0050] Before the Fig. 4, it should be understood that the present disclosure is not limited to devices having a trench structure and / or a vertical configuration. For example, the technical teachings explained herein may equally be applied to planar devices, wherein the electrodes 141, 151, and 161 are implemented as planar electrodes and wherein the semiconductor body 10 is configured to enable a lateral (rather than a vertical) forward load current. Regardless of whether the electrodes 141, 151, and 161 are provided in a trench structure or not, the overload structure 155 may be provided and configured according to the embodiments described below.

[0051] With further reference to Fig. 4, as illustrated, the device 1 includes both a main control terminal 13-1 and an auxiliary control terminal 13-2. Each main control (trench) electrode 141 is electrically connected to the main control terminal 13-1 and configured to control the forward load current under rated conditions. Each of the auxiliary control (trench) electrodes 151 is electrically connected to the auxiliary control terminal 13-2 and configured to control the overload current. For this purpose, the device 1 includes the overload structure 155 connected between the second load terminal 12 and the auxiliary control terminal 13-2.The overload structure 155 is configured to apply an auxiliary control voltage greater than a threshold voltage to the auxiliary control (trench) electrodes 151 when a voltage between the first load terminal 11 and the second load terminal 12 exceeds a maximum value and / or when the voltage between the second load terminal 12 and the auxiliary control terminal 13-2 is above a breakdown voltage of the overload structure 155.

[0052] According to one embodiment, the auxiliary control voltage is independent of the voltage applied to the main control terminal 13-1. Furthermore, the auxiliary control (trench) electrodes 151 may be electrically isolated from the main control (trench) electrodes 141.

[0053] The maximum value of the voltage between the first load terminal 11 and the second load terminal 12 may correspond to the maximum specified reverse voltage for which the device 1 was designed. In one embodiment, the breakdown voltage of the overload structure 155 is lower than the maximum reverse voltage of the power semiconductor device 1. For example, the maximum reverse voltage of the power semiconductor device 1 is in the range of 660 V to 720 V, or more generally 110% to 120% of the rated voltage of the power semiconductor device 1. The breakdown voltage of the overload structure 155 may be in the range of 660 V to 720 V. For example, the breakdown voltage of the overload structure 155 is in the range of 100% to 110% of the maximum specified reverse voltage of the power semiconductor device 1.

[0054] The threshold voltage may be the minimum voltage required to induce a conductive channel in the semiconductor body 10 adjacent to the auxiliary control (trench) electrodes 151 for conducting the overload current.

[0055] For example, the overload structure 155 is configured in a blocking state when the voltage drop across the overload structure 155 is below the breakdown voltage of the overload structure 155. This state may exist when the device 1 is operating under nominal conditions. The overload structure 155 may be configured in a conducting state when the voltage drop across the overload structure 155 is above the breakdown voltage. This state may exist when the device is not operating under nominal conditions but is in an overload situation (active voltage clamping).

[0056] With further reference to the circuit diagram of Fig. 4, in one embodiment, the device 1 further includes an ohmic structure 159 electrically connected between the first load terminal 11 and the auxiliary control terminal 13-2, wherein, for example, the ohmic structure has a resistance of at least 200 Ω, e.g., approximately 500 Ω. Accordingly, a portion of the voltage between the first load terminal 11 and the second load terminal 12 drops across both the ohmic structure 159 and the overload structure 155.

[0057] Due to the ohmic structure 159, the auxiliary control (trench) electrodes 151 have the electrical potential of the first load terminal 11 according to one embodiment during nominal operation of the device 1. Thus, during nominal operation, ie, when there is no overload situation, the auxiliary control (trench) electrodes 151 can function similarly to the optionally provided source (trench) electrodes 161.

[0058] Furthermore, based on the resistance of the resistive structure 159, the amount of current in the overload structure 155 may be limited, e.g., to the maximum capabilities of its Zener diodes 156 described below.

[0059] It should be noted here that, unlike the group consisting of the first load terminal 11, the second load terminal 12, and the main control terminal 13-1, the auxiliary control terminal 13-2 may, but need not, be connectable to external means. As explained in more detail below, the auxiliary control voltage applied to the auxiliary control (trench) electrodes 151 may be generated internally within the device. The control signal for the main control (trench) electrodes 141 is, according to one embodiment, generated externally from the device, e.g., by a driver unit applying a voltage between the first load terminal 11 and the main control terminal 13. For example, the auxiliary control voltage is independent of the voltage applied to the main control terminal 13-1.

[0060] In one embodiment, as exemplified in Fig. 4, the overload structure 155 comprises Zener diodes 156 connected in series. For example, the breakdown voltage corresponds to the sum of the Zener voltages of the Zener diodes 156. For example, as shown in Fig. 4, the Zener diodes 156 are connected in series with each other with changing polarity, e.g. such that the breakdown voltage corresponds to the sum of the Zener voltages of half of the Zener diodes 156 and the forward voltages of the other half of the Zener diodes.

[0061] According to one embodiment (see also Fig. 5) The overload structure 155 is arranged on the first side 110, e.g., to define a laterally extending path between the potential of the auxiliary control terminal 13-2 (e.g., provided by the auxiliary control terminal contact 13-21) and the potential of the second load terminal 12 (e.g., provided by the load terminal contact 121). Furthermore, according to one embodiment, the overload structure 155 is arranged in the edge termination region 1-3. For example, the overload structure 155 does not extend into the active region 1-2. Furthermore, according to one embodiment, the overload structure 155 may overlap laterally, e.g., in the edge termination region 1-3, with a variation range of the lateral doping, VLD, of the semiconductor body 10, as will be explained in more detail below.

[0062] Two variants of a configuration of the overload structure 155 are shown as examples in Fig. 8. For example, the series connection of the Zener diodes 156 is implemented in a portion of the semiconductor body 10. Each Zener diode 156 may include a first semiconductor region 1561 of the first conductivity type and, in contact therewith, a second semiconductor region 1562 of the second conductivity type. For example, the Zener diodes 156 are connected in series with each other, the polarity in this adjacent second semiconductor region 1562 sharing one of the first semiconductor region 1561, as in Fig. 8. To establish the electrical connection between the overload structure 155 and the second load terminal 12, a load terminal contact 121 may be used, which is coupled, for example, to one of the second semiconductor regions 1562 that initiates the series connection of the Zener diodes 156. To establish the electrical connection between the overload structure 155 and the auxiliary control terminal 13-2, an auxiliary control terminal contact 13-21 may be used, which is coupled, for example, to another of the second semiconductor regions 1562 that terminates the series connection of the Zener diodes 156.

[0063] According to variant (1), which is Fig. 8, the spacing p of each of the Zener diodes 156 may be constant along the (e.g., lateral) extent of the overload structure 155.

[0064] According to variant (2), which is Fig. 8, the spacing of the Zener diodes 156 may vary, e.g., along the lateral extent of the overload structure 155. For example, the Zener diodes 156 closer to the load terminal contact 121 are configured with a larger spacing p2, whereas the Zener diodes closer to the auxiliary control terminal contact 13-21 are configured with a smaller spacing p1. In another unillustrated embodiment, the Zener diodes 156 closer to the load terminal contact 121 may be configured with a smaller spacing, whereas the Zener diodes closer to the auxiliary control terminal contact 13-21 are configured with a larger spacing.

[0065] For example, the spacing of the series connection of Zener diodes (diode chain) 156 varies according to the electric field strength in the edge termination region 1-3. Accordingly, the same or at least similar field distribution can be achieved in the edge termination region 1-3 and the overload structure 155 in the device off-state. For regions with higher field strengths in the edge termination region 1-3, the spacing may be smaller (spacing p1), whereas for regions with lower field strengths, the spacing may be larger (spacing p2). To achieve the varying spacings, the lateral extensions of the first semiconductor regions 1561 and / or the second semiconductor regions 1562 can be varied, e.g., based on a corresponding masked implantation.

[0066] Furthermore, according to one embodiment, the resistor 140 (R1) which is connected with respect to Fig. 3, may be omitted for the power semiconductor device 1. Instead, the connection between the main control terminal 13-1 and the main control trench electrodes 141 may be a low-resistance connection, e.g., with a resistance of less than 100 Ω or even less than 20 Ω.

[0067] As stated above and still referring to Fig. 4, the power semiconductor device 1 may be a transistor, such as a MOSFET or an IGBT, and may be configured to operate at a switching frequency of at least 5 kHz or even more than 30 kHz. For example, such a configuration for a high switching frequency of at least 10 kHz includes the low-resistance connection between the main control terminal 13-1 and the main control trench electrodes 141 of less than 100 Ω. Furthermore, based on the overload structure 155 and the auxiliary control (trench) electrodes 151, the device 1 may be configured as a voltage self-clamping device, e.g., as an active voltage self-clamping device.

[0068] Furthermore, according to one embodiment, the active region 1-2 comprises a plurality of power unit cells, each power unit cell comprising at least one of the main control trenches 14 and at least one of the auxiliary control trenches 15. This optional aspect is described in more detail below with reference to the remaining drawings.

[0069] Still referring to Fig. 4, according to one embodiment, the power semiconductor device 1 further comprises a gate-emitter clamping structure 158 coupled between the auxiliary control terminal 13-2 and the first load terminal 11. For example, the gate-emitter clamping structure 158 includes a plurality of Zener diodes 1581 connected in series. For example, as shown in Fig. As shown in Figure 4, the Zener diodes 1581 of the gate-emitter clamp structure 158 are connected in series with each other, with the polarity changing. The gate-emitter clamp structure 158 is optional and not necessary for the function of the overload structure 155.

[0070] In another embodiment, instead of the Zener diodes 156, the overload structure 155 may comprise an auxiliary transistor and / or one or more other structural elements configured to apply the auxiliary control voltage greater than a threshold voltage to the auxiliary control trench electrodes 151 when the voltage between the first load terminal 11 and the second load terminal 12 exceeds a maximum value and / or when the voltage between the second load terminal 12 and the auxiliary control terminal 13-2 is above a breakdown voltage of the overload structure 155. That is, the term "breakdown voltage" does not necessarily imply that the overload structure 155 has a breakdown configuration.

[0071] Fig. 5(A) schematically illustrates, by way of example, a horizontal projection of the power semiconductor device 1 and Fig. 5(B) a more detailed view of the lower right corner with a modification regarding the connection of the overload structure 155.

[0072] In Fig. 5(A), the chip edge 1-4, the edge termination region 1-3, and the active region 1-2 are illustrated. For example, based on a first front-side metallization 115 in the active region 1-2, an electrical connection is established between the first contact plugs 111 (see Fig. 10) and the first load terminal 11. Based on a second front-side metallization 125 in the edge termination region 1-3, the potential of the second load terminal 12 is made available at the front side 110. For example, based on the second front-side metallization 125, an electrical connection is established between the load terminal contact 121 (see Fig. 8), ie the overload structure 155, and the second load terminal 12.

[0073] According to one embodiment, see Fig. 5(B), a third front side metallization 13-25 is used to provide the electrical connection between the auxiliary control terminal contact 13-21 (see also Fig. 8), the auxiliary control (trench) electrodes 151 and the overload structure 155.

[0074] As in Fig. As illustrated in Figure 5, the overload structure 155 may be arranged in the edge termination region 1-3, e.g., in a corner region thereof. Furthermore, the overload structure 155 may laterally overlap with the above-mentioned variation region of the lateral doping, VLD, 109 of the semiconductor body 10. For example, the VLD region 109 is of the second conductivity type. Furthermore, the VLD region 109 may be electrically connected to the potential of the first load terminal 11.

[0075] As in Fig. 5(A), the main control terminal 13-1 can also be arranged at the front of the device 1, e.g., in another corner area. In contrast to the illustration in Fig. 5(A), the main control terminal 13-1 could also be arranged in the upper left corner, e.g., diagonally opposite the overload structure 155. The optionally provided gate-emitter clamping structure 158 can also be arranged in the edge termination region 1-3.

[0076] Fig. 6 schematically illustrates four views (1) to (4) of another embodiment of the power semiconductor device 1 by way of example. In this embodiment, the power semiconductor device 1 further comprises a damping resistor 153 (see view (2)) between the auxiliary control terminal 13-2 and the auxiliary control (trench) electrodes 151. For example, the resistance of the damping resistor 153 is in the range of 10 Ω to 100 Ω. Apart from the damping resistor 153, view (2) corresponds Fig. 4 and the corresponding description also applies there. Views (4) and (3) essentially correspond Fig. 3(A) and Fig. 3(B) and the associated description also applies there.

[0077] The views (1) and (3) of Fig. 6 schematically illustrate an exemplary trench-mesa pattern that can be implemented in the active area 1-2. For example, see view (1), each power unit cell comprises three main control trenches 14 and two auxiliary control trenches 15. The three main control trenches 14 can be interconnected based on small transverse trench units that bridge the two mesas 17 of the first type, which are laterally delimited by the three control trenches, as shown. The first contact plugs 111 are used to establish the electrical connection between the mesas 17 of the first type and the first load terminal 11, as already described with respect to Fig. 10. Each of the mesas 17 of the first type is arranged laterally adjacent to at least one of the main control trenches 14 and / or at least one of the auxiliary control trenches 15.

[0078] Also in Fig. 6, view (1), the source regions 101 in the mesas 17 of the first type are illustrated. Based on the source regions 101 in the mesas 17 of the first type, a channel width can be configured in the respective mesas of the first type.

[0079] According to one embodiment, a first channel width that is not present within the trenches 17 of the first type laterally adjacent to at least one of the auxiliary control trenches 15 differs from a second channel width that is present in the mesas 17 of the first type laterally adjacent to at least one of the auxiliary control trenches 15. For example, as in Fig. 6, view (1), illustrates the second channel width being larger than the first channel width. For example, more source regions 101 are provided in the mesas 17 of the first type that are laterally bounded by at least one of the auxiliary control trenches 15, compared to the mesas 17 of the first type that are not laterally bounded by at least one of the auxiliary control trenches 15.

[0080] With reference to views (2) and (3) of Fig. 6, the ohmic structure 159 electrically connected between the first load terminal 11 and the auxiliary control terminal 13-2 may be formed by one or more extended trenches, depending on the designator resistance of the ohmic structure 159.

[0081] A fourth front-side metallization 13-15, which has, for example, a runner configuration, partially surrounds the active region 1-2 to provide the electrical potential of the main control terminal 13-1 for each of the main control trenches 14. The third front-side metallization 13-25 may also have a runner configuration.

[0082] Aspects of further embodiments of the power semiconductor device 1 are described based on the four views (1) to (4) of Fig. 7 is illustrated schematically.

[0083] For example, view (1) illustrates another trench mesa pattern that can be implemented in the active area 1-2. There, each power unit cell can include a main control trench 14, two source trenches 16, and an auxiliary control trench 15 disposed between the two source trenches 16. Second contact plugs 112 can be used to connect the source trench electrodes 161 (see Fig. 10) electrically connected to the potential of the first load terminal 11. View (2) of Fig. Figure 7 illustrates a portion of a vertical cross-section taken along the line 1-1 indicated in view (1).

[0084] View (3) of Fig. 7 illustrates another trench mesa pattern that can be implemented in the active region 1-2. No separate source trenches 16 are provided there. Instead, each power unit cell includes one main control trench 14 and three auxiliary control trenches 15. As described above, when the device 1 operates under nominal conditions (i.e., no overload situation), the electrical potential of the auxiliary control trench electrodes 151 is substantially the same as the potential of the first load terminal 11; i.e., under nominal conditions, the auxiliary control trenches 15 can act as source trenches 16. As also explained above, the channel width in the first-type mesas 17, which are laterally bounded by at least one of the auxiliary control trenches 15, can vary from mesas 17 of the first type that are laterally bounded by only one or more of the main control trenches 14 and / or by one or more of the source trenches 16 (if provided).According to one embodiment, the source regions 101 at the main control trenches 14 are provided with a first pitch, and the source regions 101 at the auxiliary control trenches 15 are provided with a second pitch. For example, the first pitch (e.g., along the second lateral direction Y) is the same as the second pitch (e.g., along the second lateral direction Y). In another embodiment, the second pitch differs from the first pitch.

[0085] View (4) of Fig. Figure 7 illustrates another trench mesa pattern that can be implemented in the active region 1-2. Again, no separate source trenches 16 are provided. Instead, each power unit cell includes a main control trench 14 and an auxiliary control trench 15.

[0086] As can be seen from the above description, the auxiliary control trenches 15 can be easily integrated into various trench mesa patterns.

[0087] According to the graben mesa pattern shown by views (1) and (2) of Fig. 9 (where (2) illustrates a close portion of the area indicated by the dashed lines in view (1)), each main control trench 14 is arranged between two source trenches 16, and each auxiliary control trench 15 is also arranged between two source trenches 16. As explained above, both the third front-side metallization 13-25 (used to establish the electrical connection between the overload structure 155 and the auxiliary control trench electrodes 151) and the fourth front-side metallization 13-15 (used to establish the electrical connection between the main control terminal 13-1 and the main control trench electrodes 141) may have a runner configuration at least partially surrounding the active region 1-2. For example, similar to the second contact plugs 112 used to connect the source trench electrodes 161 to the first front-side metallization 115 (i.e.to the first load terminal 11), fourth contact plugs 114 may be used to electrically connect the main control trench electrodes 141 to the fourth front-side metallization 13-15 (i.e., to the main control terminal 13-1), and third contact plugs 118 may be used to electrically connect the auxiliary control trench electrodes 151 to the third front-side metallization 13-25 (i.e., to the overload structure 155). To ensure a reliable connection, each auxiliary control trench electrode 151 may be connected to the third front-side metallization 13-25 (i.e., to the overload structure 155) based on at least two separately arranged third contact plugs 118. For this purpose, the third front-side metallization 13-25 may extend both along the upper portion of the edge termination region 1-3, which is shown in view (1), and along the lower portion of the edge termination region 1-3.Alternatively or additionally, other contacting schemes may be used, e.g., small transverse trench elements as described in relation to . Fig. 6, view (1), for which the main control ditches 14 are explained.

[0088] With further reference to Fig. 9, as described above, the ohmic structure 159 electrically connected between the first load terminal 11 and the auxiliary control terminal 13-2 may be formed by one or more (e.g., two, as illustrated) extended trenches, depending on the designator resistance of the ohmic structure 159. For example, the ohmic structure 159 may be formed by using source trenches 16 without source regions 101 at the edge of the active region 1-2, e.g., at the area(s) shown in view (1) of Fig. 9, indicated by reference numeral 159. One end of the trench(es) used to form the ohmic structure 159 can be contacted with the third front-side metallization 13-25 and the other end with the first front-side metallization 115.

[0089] According to the embodiment of Fig. 9, the overload structure 155 is arranged in the upper right corner of the power semiconductor device 1. There, the overload structure 155 is contacted by a metal ring 12-25 on one side and by the third front-side metallization 13-25 (configured as a metal ring) on ​​the other side. For example, each of the auxiliary control electrodes 151 is connected to the third front-side metallization 13-25 (configured as a metal ring) based on two of the third contact plugs 118, e.g., by a third contact plug 118 in a region corresponding to an upper portion of Fig. 9, and by another third contact plug 118 in an area corresponding to a lower section of Fig. 9 (wherein the trenches 14, 15 extend along the second lateral direction from the upper portion to the lower portion). Alternatively or additionally, such redundancy may also be achieved by one or more (not illustrated) transverse trenches at one of the ends of the auxiliary control trenches 15. Then, the third front-side metallization 13-25 (metal runner) is only required on one side of the chip, e.g., in either the upper or lower portion.

[0090] According to a further embodiment described in Fig. As illustrated in Figure 11, the overload structure 155 is omitted in the power semiconductor device 1, and the auxiliary control terminal 13-2 is provided on the front side of the power semiconductor device 1. The auxiliary control terminal 13-2 is coupled to a terminal 2-15 of an external clamping chip 2, e.g., via a bonding wire 21.

[0091] The external clamping chip 2 may have a diode configuration, e.g., an avalanche diode configuration, e.g., with an avalanche voltage lower than the avalanche voltage of the power semiconductor device 1. Both the power semiconductor device 1 and the external clamping chip 2 may be integrated within the same package. The external clamping chip 2 may be controlled based on the voltage at the auxiliary control terminal 13-2.

[0092] The Fig. 12 illustrated embodiment corresponds to the embodiment of Fig. 11, wherein neither an external chip 2 nor the overload structure 155 is provided in the power semiconductor device 1. Rather, an avalanche structure 154 is provided below the auxiliary control terminal 12, i.e., within the edge termination region 1-3 and as part of the semiconductor body 10, which is configured to conduct at least a portion of the load current in an overload situation. For example, the avalanche structure 154 comprises a deep semiconductor region of the second conductivity type and / or is implemented in a trench structure within the edge termination region 1-3.

[0093] A method for manufacturing a power semiconductor device is also presented herein.

[0094] For example, the method of manufacturing a power semiconductor device comprises forming the following components: an active region surrounded by an edge termination region; a semiconductor body extending into both the active region and the edge termination region and comprising, in the active region, a semiconductor drift region of a first conductivity type; a first load terminal on a first side of the semiconductor body; a second load terminal on a second side of the semiconductor body opposite the first side, wherein the power semiconductor device is configured to conduct a forward load current between the first load terminal and the second load terminal in the active region; a main control terminal; an auxiliary control terminal isolated from the main control terminal;in the active region, a trench structure extending along a vertical direction from the first side to the second side, the trench structure comprising main control trenches, each of the main control trenches including a main control trench electrode electrically connected to the main control terminal and configured to control the forward load current, and auxiliary control trenches, each of the auxiliary control trenches including an auxiliary control trench electrode electrically connected to the auxiliary control terminal and configured to control an overload current;an overload structure connected between the second load terminal and the auxiliary control terminal, the overload structure being configured to apply an auxiliary control voltage greater than a threshold voltage to the auxiliary control trench electrodes when a voltage between the first load terminal and the second load terminal exceeds a maximum value and / or when the voltage between the second load terminal and the auxiliary control terminal is above a breakdown voltage of the overload structure;

[0095] In another example, the method of manufacturing a power semiconductor device comprises forming the following components: a semiconductor body; a first load terminal; a second load terminal, wherein the power semiconductor device is configured to conduct a forward load current between the first load terminal and the second load terminal; a main control terminal; an auxiliary control terminal isolated from the main control terminal; a control electrode structure comprising: main control electrodes electrically connected to the main control terminal and configured to control the forward load current, and auxiliary control electrodes electrically connected to the auxiliary control terminal and configured to control an overload current;an overload structure electrically connected between the second load terminal and the auxiliary control terminal, the overload structure being configured to apply an auxiliary control voltage greater than a threshold voltage to the auxiliary control electrodes when a voltage between the first load terminal and the second load terminal exceeds a maximum value and / or when the voltage between the second load terminal and the auxiliary control terminal is above a breakdown voltage of the overload structure;

[0096] Embodiments of the methods described above correspond to the embodiments of the power semiconductor device 1 described above. Accordingly, these embodiments of the method are not described verbatim herein, but reference is made to the above.

[0097] For example, to form the overload structure 155 (e.g. as shown in Fig. 4 to Fig. 9 and described with reference thereto), a deposited, e.g., ~500 nm thick, undoped polysilicon is first lightly doped, e.g., n-doped. Then, based on a masked, e.g., p-doping, a diode chain of the above-described series connection of Zener diodes 156 can be formed. The unneeded polysilicon can be etched away.

[0098] For example, to form the overload structure 155 (e.g. as in Fig. x and described with reference thereto) by introducing a region of reduced avalanche voltage through, for example, a deep well region of the second conductivity type in the power semiconductor device 1. This deep well can be integrated in combination with a trench bottom implant.

[0099] In the above, embodiments relating to power semiconductor devices and corresponding manufacturing methods have been explained.

[0100] For example, these power semiconductor devices are based on silicon (Si). Accordingly, a monocrystalline semiconductor region or layer, e.g., the semiconductor body and its regions / zones, e.g., regions, etc., may be a monocrystalline Si region or layer. In other embodiments, polycrystalline or amorphous silicon may be used.

[0101] However, it is understood that the semiconductor body and its regions / zones may be made of any semiconductor material suitable for fabricating a semiconductor device. Examples of such materials include, but are not limited to, elemental semiconductor materials such as silicon (Si) or germanium (Ge), Group IV compound semiconductor materials such as silicon carbide (SiC) or silicon germanium (SiGe), binary, ternary, or quaternary III-V semiconductor materials such as gallium nitride (GaN), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium gallium phosphide (InGaPa), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), indium gallium nitride (InGaN), aluminum gallium indium nitride (AlGaInN), or indium gallium arsenide phosphide (InGaAsP), and binary or ternary II-VI semiconductor materials such as cadmium telluride (CdTe) and mercury cadmium telluride (HgCdTe), to name a few.The above-mentioned semiconductor materials are also referred to as "homojunction semiconductor materials." When two different semiconductor materials are combined, a heterojunction semiconductor material is formed. Examples of heterojunction semiconductor materials include, but are not limited to, aluminum gallium nitride (AlGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-aluminum gallium indium nitride (AlGaInN), indium gallium nitride (InGaN)-gallium nitride (GaN), aluminum gallium nitride (AlGaN)-gallium nitride (GaN), indium gallium nitride (InGaN)-aluminum gallium nitride (AlGaN), silicon-silicon carbide (SiC1-x), and silicon-SiGe heterojunction semiconductor materials. Currently, Si, SiC, GaAs, and GaN materials are mainly used for power semiconductor switching applications.

[0102] Spatially relative terms such as "below," "under," "lower," "above," "upper," and the like are used for convenience of description to explain the positioning of one element relative to a second element. These terms are intended to encompass various orientations of the respective device in addition to orientations other than those illustrated in the figures. Furthermore, terms such as "first," "second," and the like are also used to describe various elements, regions, sections, etc., and are also not intended to be limiting. Like terms may refer to like elements throughout the description.

Claims

[1] Power semiconductor device (1), comprising - an active area (1-2) surrounded by an edge termination area (1-3); - a semiconductor body (10) which extends both into the active region (1-2) and into the edge termination region (1-3) and comprises a semiconductor drift region (100) of a first conductivity type in the active region (1-2); - a first load terminal (11) on a first side (110) of the semiconductor body (10); - a second load terminal (12) on a second side (120) of the semiconductor body (10) opposite the first side (110), wherein the power semiconductor device (1) is configured to conduct a forward load current between the first load terminal (11) and the second load terminal (12) in the active region (1-2); - a main control connection (13-1); - an auxiliary control terminal (13-2) isolated from the main control terminal (13-1); - in the active region (1-2), a trench structure (14, 15, 16) extending along a vertical direction (Z) from the first side (110) to the second side (120), the trench structure (14, 15, 16) comprising: ◯ main control trenches (14), each of the main control trenches (14) including a main control trench electrode (141) electrically connected to the main control terminal (13-1) and configured to control the forward load current, and ◯ auxiliary control trenches (15), each of the auxiliary control trenches (15) including an auxiliary control trench electrode (151) electrically connected to the auxiliary control terminal (13-2) and configured to control an overload current; - an overload structure (155) connected between the second load terminal (12) and the auxiliary control terminal (13-2), wherein the overload structure (155) is configured to apply an auxiliary control voltage greater than a threshold voltage to the auxiliary control trench electrodes (151) when a voltage between the first load terminal (11) and the second load terminal (12) exceeds a maximum value and / or when the voltage between the second load terminal (12) and the auxiliary control terminal (13-2) is above a breakdown voltage of the overload structure (155). [2] The power semiconductor device (1) according to claim 1, wherein the overload structure (155) is configured to ◯ to be in a blocking state when the voltage drop across the overload structure (155) is below the breakdown voltage of the overload structure (155); and ◯ to be in a conductive state when the voltage drop across the overload structure (155) is above the breakdown voltage. [3] The power semiconductor device (1) according to claim 1 or 2, further comprising an ohmic structure (159) electrically connected between the first load terminal (11) and the auxiliary control terminal (13-2), the ohmic structure having a resistance of at least 200 Ω. [4] Power semiconductor device (1) according to one of the preceding claims, wherein the overload structure (155) comprises Zener diodes (156) connected in series, the breakdown voltage corresponding to the sum of the Zener voltages of the Zener diodes (156). [5] The power semiconductor device (1) according to claim 4, wherein a distance in the series circuit of the Zener diodes (156) varies. [6] Power semiconductor device (1) according to one of the preceding claims, wherein the overload structure (155) is arranged on the first side (110) to define a laterally extending path between the potential of the auxiliary control terminal (13-2) and the potential of the second load terminal (12). [7] Power semiconductor device (1) according to one of the preceding claims, wherein the overload structure (155) is arranged in the edge termination region (1-3). [8] Power semiconductor device (1) according to one of the preceding claims, wherein the overload structure (155) laterally overlaps with a variation range of the lateral doping, VLD, (109) of the semiconductor body (10). [9] Power semiconductor device (1) according to one of the preceding claims, wherein the connection between the main control terminal (13-1) and the main control trench electrodes (141) is a low-resistance connection with a resistance of less than 100 Ω. [10] Power semiconductor device (1) according to one of the preceding claims, wherein the power semiconductor device (1) is a transistor configured to operate at a switching frequency of at least 5 kHz. [11] Power semiconductor device (1) according to one of the preceding claims, wherein the active region (1-2) comprises a plurality of power unit cells, each power unit cell comprising at least one of the main control trenches (14) and at least one of the auxiliary control trenches (15). [12] Power semiconductor device (1) according to one of the preceding claims, wherein the trench structure (14, 15, 16) further comprises source trenches (16), each source trench (16) including a source trench electrode (161) electrically connected to the first load terminal (11). [13] Power semiconductor device (1) according to one of the preceding claims, wherein the power semiconductor device (1) is a voltage self-clamping device. [14] The power semiconductor device (1) according to any one of the preceding claims, further comprising a damping resistor (153) between the auxiliary control terminal (13-2) and the auxiliary control trench electrodes (151). [15] Power semiconductor device (1) according to one of the preceding claims, wherein the trench structure (14, 15, 16) laterally delimits a plurality of mesas (17) of the first type, each of which is arranged laterally adjacent to at least one of the main control trenches (14) and / or at least one of the auxiliary control trenches (15). [16] The power semiconductor device (1) of claim 15, wherein a first channel width that is not present laterally adjacent to at least one of the auxiliary control trenches (15) within the mesas (17) of the first type is different from a second channel width that is present laterally adjacent to at least one of the auxiliary control trenches (15) in the mesas (17) of the first type. [17] Power semiconductor device (1) according to one of the preceding claims, wherein the breakdown voltage of the overload structure (155) is lower than a maximum blocking voltage of the power semiconductor device (1). [18] Power semiconductor device (1) according to one of the preceding claims, wherein the auxiliary control trench electrodes (151) have the electrical potential of the first load terminal (11) during nominal operation of the power semiconductor device (1). [19] Power semiconductor device (1), comprising - a semiconductor body (10); - a first load connection (11); - a second load terminal (12), wherein the power semiconductor device (1) is configured to conduct a forward load current between the first load terminal (11) and the second load terminal (12); - a main control connection (13-1); - an auxiliary control terminal (13-2) isolated from the main control terminal (13-1); - a control electrode structure (14, 15) comprising: ◯ main control electrodes (141) electrically connected to the main control terminal (13-1) and configured to control the forward load current, and ◯ auxiliary control electrodes (151) electrically connected to the auxiliary control terminal (13-2) and configured to control an overload current; - an overload structure (155) electrically connected between the second load terminal (12) and the auxiliary control terminal (13-2), wherein the overload structure is configured to apply an auxiliary control voltage greater than a threshold voltage to the auxiliary control electrodes (151) when a voltage between the first load terminal (11) and the second load terminal (12) exceeds a maximum value and / or when the voltage between the second load terminal (12) and the auxiliary control terminal (13-2) is above a breakdown voltage of the overload structure (155). [20] A method (2) for manufacturing a power semiconductor device (1), comprising forming the components of the power semiconductor device (1) according to claim 1 or claim 19.

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