Semiconductor device with current spreading region and method of manufacturing

Abstract

wherein the semiconductor device comprises a base layer (200) and a transistor layer (100), wherein the base layer (200) is based on single-crystalline silicon carbide and comprises a current spreading region (230) of a first conductivity type and a non-depletable shielding structure (260) of a second conductivity type, wherein the transistor layer (100) is based on epitaxially grown single-crystalline silicon carbide and comprises a transistor cell (TC) configured to control a current through the current spreading region (230), wherein the transistor layer (100) is formed on the base layer (200) after the formation of the shielding structure (260) in the base layer (200), so that an epitaxial interface (201) is formed between the base layer (200) and the transistor layer (100), wherein the current spreading region (230) extends from the epitaxial interface (201) extends between adjacent partial regions of the shielding structure (260),wherein along a vertical line orthogonal to the epitaxial interface (201) and through a pn junction between the shielding structure (260) and a region of the first conductivity type in the transistor layer (100) there is a net dopant concentration of at least 1e17 1 / cm, 3 per 0.1 µm at the position of the pn junction.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a silicon carbide-based semiconductor device having a current spreading region. The present disclosure further relates to a method for manufacturing a silicon carbide-based semiconductor device. BACKGROUND

[0002] In planar-gate silicon carbide MOSFETs, the gate dielectric and gate conductor are formed on the first main surface. In trench silicon carbide MOSFETs, the gate dielectric and gate conductor are formed in gate trenches extending from a first main surface at a front side of a silicon carbide portion into the silicon carbide portion. In both types of silicon carbide MOSFETs (SiC MOSFETs), the gate dielectric separates the gate conductor from lightly doped p-type body regions formed in the silicon carbide portion. In the on-state of the SiC MOSFET, an electron channel forms in a channel portion of the body region along the gate dielectric. An n-type drift layer is formed in a portion of the silicon carbide portion between the body region and a second main surface of the silicon carbide portion opposite the first main surface.Heavily doped p-type shielding regions formed between the lightly doped p-type body region and the drift layer shield the body regions with the channel section from the potential of the drift layer and reduce the electric field in the body regions. For SiC MOSFETs with planar gates, the acceptor ions are implanted through the first main surface, using high implantation energies to achieve an implantation depth deeper than the lightly doped p-type body region.

[0003] Publication DE 10 2017 209 017 A1 discloses a silicon carbide semiconductor device with gate trenches and a manufacturing method for a silicon carbide semiconductor device. Publication DE 10 2016 226 235 A1 also discloses a silicon carbide semiconductor device with gate trenches and a corresponding manufacturing method. In the disclosed manufacturing methods, n- and p-doped layers of the silicon carbide semiconductor device are provided by means of separate epitaxy steps, with further processing steps, such as implantations and / or structuring, being performed between the epitaxy steps.

[0004] There is a constant need to improve the on-state resistance of SiC MOSFETs, such as trench-gate SiC MOSFETs and planar-gate SiC MOSFETs. SUMMARY

[0005] A semiconductor device according to the present disclosure comprises a base layer and a transistor layer, wherein the base layer is based on single-crystal silicon carbide and comprises a current spreading region of a first conductivity type and a non-depletable shielding structure of a second conductivity type, wherein the transistor layer is based on epitaxially grown single-crystal silicon carbide and comprises a transistor cell that controls a current through the current spreading region, wherein the transistor layer is formed on the base layer after the formation of the shielding structure in the base layer, wherein an epitaxial interface is formed between the base layer and the transistor layer, wherein the current spreading region extends from the epitaxial interface between adjacent subregions of the shielding structure,wherein along a vertical line orthogonal to the epitaxial interface and through a pn junction between the shielding structure and a region of the first conductivity type in the transistor layer, a net dopant concentration at the position of the pn junction increases by at least 1e17 1 / cm, 3 per 0.1 µm,

[0006] Since the acceptor ions for the shielding structure can be implanted before the transistor layer is formed, the acceptor ions do not pass through the transistor layer. Lateral pitting can be reduced. The formation of implantation tails in the transistor layer can be prevented or at least mitigated. The absence of implantation tails can facilitate the formation of narrow current paths through the shielding structure. Since the energy required to implant the shielding structure into the base layer can be comparatively low, the implantation mask can be made significantly thinner than if the acceptor ions are implanted through the transistor layer. As a result, the lateral dimension of the shielding structure and the lateral transitions between the shielding structure and the current paths can be defined more precisely.The semiconductor device can combine a low on-state resistance RDSon with a highly efficient shielding for the body area.

[0007] The disclosure relates to semiconductor devices based on silicon carbide and having transistor cells. Specific examples of such a semiconductor device include an n-channel SiC MOSFET with a planar gate or an n-channel SiC TMOSFET. However, the disclosure is also applicable to p-channel SiC MOSFETs.

[0008] Those skilled in the art will recognize additional features and advantages by reading the following detailed description and examining the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are provided to further understand the embodiments and form an integral part of this description. The drawings illustrate embodiments of a semiconductor device and a method for manufacturing a semiconductor device and, together with the description, explain the principles underlying the embodiments. Further embodiments are described in the following detailed description and in the claims. Features of the various embodiments can be combined with one another. Fig. 1A is a schematic vertical cross-sectional view of a portion of a semiconductor device having a current spreading region laterally bounded by regions of a non-depletable shielding structure, according to one embodiment. Fig. Figure 1B is a schematic diagram showing the dopant concentration along a vertical line BB in Fig. 1A according to one embodiment. Fig. Figure 1C is a schematic diagram showing the dopant concentration along a horizontal line CC in Fig. 1A according to one embodiment. Fig. 2 is a schematic vertical cross-sectional view of a portion of a semiconductor device having a current spreading region laterally bounded by regions of a non-depletable shield structure, according to an embodiment relating to planar gate transistor cells. Fig. 3 is a schematic vertical cross-sectional view of a portion of a semiconductor device having a current spreading region laterally bounded by regions of a non-depletable shield structure, according to an embodiment relating to trench gate structures in direct contact with the shield structure. Fig. 4 is a schematic vertical cross-sectional view of a portion of a semiconductor device having a current spreading region laterally bounded by regions of a non-depletable shield structure, according to an embodiment relating to trench gate structures spaced from the shield structure. Fig. 5 is a schematic diagram illustrating the dopant concentration gradient along a vertical line through the epitaxial interface between a current spreading region and a current collecting region according to one embodiment. Fig. 6A is a schematic diagram illustrating the dopant concentration gradient along a vertical line through the epitaxial interface between a shield structure and an interconnect region according to one embodiment. Fig. 6B is a schematic diagram illustrating the dopant concentration gradient along a vertical line through the epitaxial interface between a shield structure and a current collection region of a trench gate transistor cell according to one embodiment. Fig. 7 and Fig. 8 are schematic vertical cross-sectional views of a portion of a semiconductor device according to an embodiment relating to transistor cells with planar gate electrodes. Fig. 9 is a schematic vertical cross-sectional view of a portion of a semiconductor device according to an embodiment relating to transistor cells with trench gate electrodes and a single-sided transistor channel. Fig. 10 is a schematic vertical cross-sectional view of a portion of a semiconductor device according to an embodiment relating to transistor cells with trench gate electrodes and a two-sided transistor channel. Fig. 11 is a schematic vertical cross-sectional view of a portion of a semiconductor device according to an embodiment relating to transistor cells with metal contact plugs extending from a top surface into the transistor layer 100. Fig. 12 is a schematic horizontal cross-sectional view of a portion of a semiconductor device having stripe-shaped trench gate structures according to an embodiment with n-type conducting source regions and p-type conducting contact regions alternating along a horizontal longitudinal axis of the trench gate structures. Fig. 13A and Fig. 13B are schematic vertical cross-sectional views along lines II and II-II of Fig. 12 according to an embodiment relating to wide n conductive channel sections that are laterally bounded by the shielding structure. Fig. 14A and Fig. 14B are schematic vertical cross-sectional views along lines II and II-II of Fig. 12 according to an embodiment relating to narrow conductive channel sections laterally bounded by the shielding structure. Fig. 15A and Fig. 15B are schematic vertical cross-sectional views along lines II and II-II of Fig. 12 according to an embodiment relating to narrow n conductive channel sections and trench gate structures that do not reach the ground layer. Fig. 16A and Fig. 16B are schematic vertical cross-sectional views along lines II and II-II of Fig. 12 according to an embodiment relating to p-type narrow auxiliary regions vertically separating the trench gate structures and the shielding structure, wherein pillars of a compensation structure run parallel to stripe-shaped trench gate structures. Fig. 17A, Fig. 17B, Fig. 17C are schematic vertical cross-sectional views along lines II, II-II and IV-IV of Fig. 12 according to an embodiment relating to p-type narrow auxiliary regions vertically separating the trench gate structures and a grid-shaped shielding structure, wherein pillars of a compensation structure are orthogonal to stripe-shaped trench gate structures. Fig. 17D is a schematic vertical cross-sectional view taken along a line parallel to the line II of Fig. 12 according to an embodiment, wherein columns of a compensation structure run orthogonal to strip-shaped trench gate structures and strip-shaped subregions of the shielding structure run parallel to strip-shaped trench gate structures. Fig. 18A and Fig. 18B are schematic vertical cross-sectional views along lines II and II-II of Fig. 12 according to an embodiment, wherein pillars of a compensation structure are orthogonal to stripe-shaped trench gate structures and the shielding structure comprises laterally separated shielding islands. Fig. 19A, Fig. 19B and Fig. 19C are schematic vertical cross-sectional views along lines II, II-II and III-III of Fig. 12 according to an embodiment, wherein columns of a compensation structure and strip-shaped subregions of the shielding structure extend orthogonally to strip-shaped trench gate structures. Fig. 20 is a schematic vertical cross-sectional view of a portion of a semiconductor device according to an embodiment relating to a current spreading region having a central channel portion and heavily doped sidewall portions between the central channel portion and the shield structure. Fig. 21A to Fig. 21B are schematic vertical cross-sectional views of a portion of a semiconductor device illustrating a method of manufacturing a semiconductor device according to an embodiment before and after forming a transistor layer on a base layer in which a shield structure is formed. Fig. 22A to Fig. 22D are schematic vertical cross-sectional views of a portion of a semiconductor device illustrating a method of manufacturing a semiconductor device with a compensation structure according to another embodiment. Fig. 23A to Fig. 23D are schematic vertical cross-sectional views of a portion of a semiconductor device illustrating a method of manufacturing a semiconductor device according to an embodiment relating to a current spreading region having a central channel portion and heavily doped sidewall portions between the central channel portion and the shield structure. DETAILED DESCRIPTION

[0010] In the following detailed description, reference is made to the accompanying drawings, which form a part of this document, and in which certain embodiments of a semiconductor device and a method of manufacturing a semiconductor device are shown by way of illustration. Structural or logical changes may be made to the illustrated embodiments without departing from the scope of the present disclosure. For example, features shown or described for one embodiment may be used on or in conjunction with other embodiments, resulting in a different embodiment. This disclosure is intended to include such modifications and variations. The embodiments are described in a manner that should not be construed as limiting the scope of the appended claims. The drawings are not to scale and are for illustrative purposes only.Corresponding elements are designated by the same reference numerals in the various drawings unless otherwise indicated.

[0011] The terms "having," "containing," "including," "comprising," and the like are open-ended, and the terms indicate the presence of certain structures, elements, or features, but do not preclude the presence of additional elements or features. The articles "a," "an," and "the" include both the plural and the singular, unless the context clearly indicates otherwise.

[0012] The terms "signal-connected" and "electrically connected" may include a permanent, low-resistance ohmic connection between electrically connected elements, for example, a direct contact between the elements in question or a low-resistance connection via a metal and / or heavily doped semiconductor material, but do not exclude the presence of other passive and / or active elements in the signal path between the "signal-connected" or "electrically connected" elements. For example, the other elements may include resistors, resistive traces, capacitors and / or inductors, transistors, semiconductor diodes, Schottky diodes, transformers, optocouplers, and others.

[0013] The term “directly electrically connected” can describe a permanent low-resistance ohmic connection between electrically connected elements, for example a direct contact between the elements in question or a low-resistance connection via a metal and / or heavily doped semiconductor material.

[0014] The term “power semiconductor device” refers to semiconductor devices with a high voltage blocking capability of at least 30 V, for example 48 V, 100 V, 600 V, 1.6 kV, 3.3 kV or more and with a nominal on-state current or forward current of at least 200 mA, for example 1 A, 10 A or more.

[0015] A safe operating area (SOA) of a semiconductor device is defined as the voltage and current conditions over which the semiconductor device can be expected to operate without self-damage.

[0016] An ohmic contact describes a non-rectifying electrical junction between two conductors, e.g., between a semiconductor material and a metal. The ohmic contact exhibits a linear or nearly linear current-voltage (IV) curve in the first and third quadrants of the IV diagram, as per Ohm's law.

[0017] Ranges specified for physical dimensions include the limiting values. For example, a range for a parameter y from a to b is a ≤ y ≤ b. The same applies to ranges with a limit such as "at most" and "at least."

[0018] The term "on" should not be interpreted to mean only "directly on." Rather, if an element is positioned "on" another element (e.g., a layer is "on" another layer or "on" a substrate), another component (e.g., another layer) may be positioned between the two elements (e.g., another layer may be positioned between a layer and a substrate if the layer is "on" the substrate).

[0019] Two adjacent doping regions in a semiconductor layer form a semiconductor junction. Two adjacent doping regions of the same conductivity type and with different dopant concentrations form a unipolar junction, e.g., an n / n+ or p / p+ junction along an interface between the two doping regions. At the unipolar junction, a dopant concentration profile orthogonal to the unipolar junction may exhibit a step or inflection point where the dopant concentration profile changes from concave to convex or vice versa. Two adjacent doping regions of complementary conductivity form a pn junction.

[0020] The figures illustrate relative doping concentrations by indicating "-" or "+" next to the doping type "n" or "p." For example, "n-" indicates a doping concentration lower than the doping concentration of an "n" doping region, while an "n+" doping region has a higher doping concentration than an "n" doping region. Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different "n" doping regions may have the same or different absolute doping concentrations.

[0021] The shield regions limit the transistor on-state current in the lateral directions and increase the on-state resistance RDSon of SiC MOSFETs with planar gates and trench gates. High-energy implantation through the first principal surface results in a large lateral pit that obscures the lateral edges of the shield regions. High-energy implantation also requires a thick implantation mask to prevent acceptor ions from reaching the current paths between the shield regions. With increasing thickness, undesirable side effects of the implantation mask become more pronounced. A slight tilt of the mask edges results in a lateral pit and only partial blockage of the ions. This partial blockage causes implantation tails ("ducktails") to reach the first principal surface. The implantation tails can increase the channel resistance and / or change the threshold voltage of the SiC MOSFET.Negative side effects of high-energy implantations can be mitigated by increasing the lateral distance between adjacent gate trenches, which in turn reduces the area efficiency.

[0022] The present disclosure relates to a semiconductor device comprising a base layer and a transistor layer, wherein the base layer is based on single-crystal silicon carbide and comprises a current spreading region of a first conductivity type and a non-depletable shielding structure of a second conductivity type, wherein the transistor layer is based on epitaxially grown single-crystal silicon carbide and comprises a transistor cell configured to control a current through the current spreading region, wherein the transistor layer is formed on the base layer after the formation of the shielding structure in the base layer, such that an epitaxial interface is formed between the base layer and the transistor layer, wherein the current spreading region extends from the epitaxial interface between adjacent subregions of the shielding structure,wherein along a vertical line orthogonal to the epitaxial interface and through a pn junction between the shielding structure and a region of the first conductivity type in the transistor layer, a net dopant concentration at the position of the pn junction increases by at least 1e17 1 / cm, 3 per 0.1 µm, e.g. by at least 2e17 1 / cm 3 per 0.1 µm, wherein, according to one example, the first conductivity type is n-conductivity and the second conductivity type is p-conductivity, wherein, according to another example, the first conductivity type is p-conductivity and the second conductivity type is n-conductivity, wherein the base layer may have two rectangular main surfaces extending in two substantially parallel horizontal planes, wherein a distance between a first main surface on a front side (base layer surface) and a second main surface opposite the first main surface defines a thickness of the base layer in a vertical direction orthogonal to the horizontal planes, wherein current spreading regions and the shielding structure may extend from the epitaxial interface into the base layer, wherein the transistor layer can be formed directly on the base layer surface, wherein the transistor layer can be formed by epitaxial growth of crystalline silicon carbide after the formation of the shielding structure, wherein the transistor layer may comprise further components to provide the functionality of a plurality of transistor cells, wherein the transistor layer may, for example, comprise structures made of materials other than monocrystalline silicon carbide, e.g., dielectric structures and / or metal structures. Apart from trench gate electrodes and metal contact structures extending from an exposed surface on a front side of the transistor layer into the transistor layer, a top surface of the transistor layer may be substantially planar, wherein a drain current of the transistor cells is controlled by controlling an electric field that modulates the drain current through the transistor cells, wherein the drain current passes through the current spreading regions, wherein the epitaxial growth transforms the base layer surface into an epitaxial interface between the base layer and the transistor layer, wherein the epitaxial interface may be substantially planar or may comprise coplanar first sections and coplanar second sections at a vertical distance from the first sections, wherein the first sections and the second sections may be connected by further sections, wherein in other examples the interface (201) may be corrugated or may have a zigzag-like shape, wherein on opposite sides of the epitaxial interface the content of one or more electrically active and / or electrically inactive impurities may be significantly different, for example an average concentration of nitrogen, sulfur, iodine, oxygen and / or hydrogen in the transistor layer may be significantly different from an average concentration of the same element in the base layer, wherein the shielding structure can be formed directly along the epitaxial interface, wherein the shielding structure can be composed of partial regions (shielding regions) that are separated from one another in at least one horizontal direction, wherein, for example, a rectangular, circular, or oval gap with an opposite doping type to that of the shielding structure separates adjacent partial regions of the shielding structure, wherein the shielding structure can comprise a plurality of strip-shaped partial regions that are separated from one another along a horizontal direction by strip-shaped regions with an opposite doping type, or can comprise shielding islands that are separated from one another along two orthogonal horizontal directions by a grid-like region with an opposite doping type, wherein sections of the shielding structure that are effective for the same transistor cell TC and the same current spreading region,which may also be referred to as shielding areas below, whereby the shielding structure is not completely depleted under operating conditions within the safe operating area (SOA), wherein the steep change in the net dopant concentration along a vertical line through the pn junction between the shielding structure and a region of the first conductivity type in the transistor layer indicates the absence of implantation tails, as is typically observed in connection with high-energy ion implantation through openings in a thick implantation mask, whereby, without implantation tails, gaps in the shielding structure can be designed narrower and with better-defined dimensions and doping distributions, Alternatively or additionally, the net dopant concentration at the position of the pn junction can be increased by at least 1e17 1 / cm 3 per 0.1 µm, e.g. by at least 2e17 1 / cm 3per 0.1 µm along a horizontal line parallel to the epitaxial interface and through a pn junction formed between the current spreading region and the shielding structure, Alternatively or additionally, a width w0 of the current spreading region, which is defined by the shortest horizontal distance between two points of zero net doping on opposite sides of the current spreading region, may be at most 0.6 µm, for example at most 0.1 µm, a vertical extension v0 of the shielding structure may be at least 0.8 µm, for example at least 0.4 µm, and / or an aspect ratio v0 / w0 of the gap in the shielding structure may be at least 0.3, at least 0.5, at least 1 or at least 5.

[0023] The current spreading region and a region of the shielding structure adjacent to the current spreading region define a JFET structure that has a strong influence on the on-state resistance RDSon of the semiconductor device. The various embodiments allow precisely defined JFET structures even with small lateral center-to-center distances between adjacent transistor cells TC. The number of transistor cells TC per unit area can be increased, and the total on-state resistance RDSon can be further reduced. Furthermore, a JFET design with a high channel length / channel width aspect ratio can facilitate an improved compromise between low on-state resistance RDSon and long short-circuit endurance.

[0024] According to one embodiment, the base layer may comprise a current drift portion of the first conductivity type, wherein the current spreading region extends to the current drift portion.

[0025] The current drift section may be a continuous horizontal layer that extends laterally through the base layer in the vertical projection of some or all of the transistor cells formed in the transistor layer. Alternatively, the current drift section may be part of a compensation structure. The current spreading region and the current drift section may form a unipolar junction.

[0026] Along a vertical line orthogonal to the epitaxial interface and through a pn junction formed between the shielding structure and the current drift section, a net dopant concentration can increase by at least 1e16 1 / cm 3 per 0.1 µm, e.g., by at least 2e16 1 / cm 3 per 0.1 µm.

[0027] According to one embodiment, the semiconductor device may comprise an interconnection region of the second conductivity type, wherein the interconnection region extends through the transistor layer to the shielding structure and is in direct contact with the shielding structure along a first portion of the epitaxial interface. A vertical dopant profile through the first portion of the epitaxial interface may exhibit a step at the epitaxial interface. The interconnection region may extend through the entire transistor layer or only through a vertical portion of the transistor layer down to the shielding structure.

[0028] If an average dopant concentration in the interconnect region is higher or lower than an average dopant concentration in the shielding structure, then a vertical dopant profile through the interconnect region and the shielding structure may show a steep slope at the epitaxial interface, with the net dopant concentration changing by at least 1e18 1 / cm 3 per 0.1 µm, e.g., by at least 2e18 1 / cm 3 per 0.1 µm.

[0029] The steep slope may be a result of the transistor layer being formed after the shielding structure is formed in the base layer.

[0030] When a metal contact plug extends from a plane coplanar with a top surface of the transistor layer into the transistor layer, the connection region 160 may include a buried portion extending from a bottom of the metal contact plug to or into the shield structure, wherein a doping tip is formed in the buried portion directly beneath the metal for improved contacting.

[0031] According to one embodiment, the connection region may extend from an upper surface of the transistor layer to the shielding structure.

[0032] The top surface may be parallel to the epitaxial interface. The epitaxial interface and the top surface are located on opposite sides of the transistor layer. The interconnect region may extend downward to the epitaxial interface or beyond it, so that the interconnect region extends into the base layer.

[0033] According to one embodiment, the transistor cell may be configured to control a current through a body region between a source region and a current collection region, wherein the current collection region may be electrically connected to the current spreading region.

[0034] The current collection region may be in direct contact with the current spreading region or may be electrically connected to the current spreading region by a low-resistance ohmic connection, for example, by another doped region having a net dopant concentration different from the net dopant concentrations in the current collection region and the current spreading region.

[0035] The current collection region can receive the dopants that define the conductivity of the current collection region during or after formation of the transistor layer. For example, the current collection region can be doped in-situ during epitaxial growth of the transistor layer.

[0036] The current spreading region may include a channel portion and a spreading portion. The channel portion extends through a gap in the shielding structure, wherein a vertical extension of the channel portion and a vertical extension of the shielding structure 260 are equal. The spreading portion separates the shielding structure and the current drift portion along the vertical direction. The channel portion and the spreading portion of the current spreading region may have the same dopant concentration. The dopant concentration in the spreading portion of the current spreading region may be higher than the dopant concentration in the current drift portion. For example, the dopant concentration in the spreading portion is at least twice or at least ten times higher than in the current drift portion.

[0037] According to one embodiment, the body region may separate the source region and the current collection region in a horizontal direction parallel to the epitaxial interface. The transistor cell controls a horizontal current flow between the source region and the current collection region through the body region.

[0038] According to another embodiment, the body region vertically separates the source region and the current collection region. The transistor cell controls a vertical or near-vertical current flow between the source region and the current collection region through the body region.

[0039] According to one embodiment, a trench gate structure may extend from a top surface of the transistor layer into the transistor layer, wherein the source region, the body region, and the current collection region are in direct contact with a sidewall of the trench gate structure.

[0040] According to one embodiment, the current collection region and the current spreading region may be in direct contact with each other along a second portion of the epitaxial interface, wherein a vertical dopant profile through the second portion of the epitaxial interface shows a step at the epitaxial interface.

[0041] If the average dopant concentration in the current collection region is higher or lower than the average dopant concentration in the current spreading region, a vertical dopant profile through the current collection region and the current spreading region may exhibit a steep slope at the epitaxial interface. A net dopant concentration change of at least 2e17 1 / cm 3 per 0.1 µm, e.g. B. at least 4e17 1 / cm 3per 0.1 µm. The steep slope may be the result of the transistor layer with the current collection region being formed after the current spreading region is formed in the base layer.

[0042] According to one embodiment, the trench gate structure may terminate in the transistor layer, and an auxiliary region of the second conductivity type may extend from a bottom of the trench gate structure to the shielding structure. The auxiliary region may be formed self-aligned to the trench gate structure.

[0043] According to one embodiment, the current spreading region may extend vertically through a gap in the shielding structure, wherein the gap has a vertical extent v0 and a horizontal width w0, and wherein an aspect ratio v0 / w0 of the gap in the shielding structure may be at least 1.

[0044] The aspect ratio v0 / w0 of the gap is equal to the aspect ratio of the channel portion of the current spreading region. The width w0 is measured parallel to the first horizontal direction. The aspect ratio v0 / w0 can be at least 0.5. For example, the aspect ratio v0 / w0 is at least 1, e.g., at least 5. A high aspect ratio v0 / w0 of at least 1 or 5 facilitates a long maximum short-circuit lifetime.

[0045] According to one embodiment, the semiconductor device may further comprise a depletable first pillar region of the first conductivity type and depletable second pillar regions of the second conductivity type, wherein the first pillar region is formed in the base layer in direct contact with the current spreading region and wherein the second pillar regions are formed in the base layer in direct contact with the shielding structure.

[0046] The doped first pillar regions 241 may alternate with doped second pillar regions 242 of the complementary conductivity type along the horizontal direction(s), wherein the first and second pillar regions 241, 242 form a compensation structure configured to be fully depleted at a nominal breakdown voltage of the semiconductor device within the SOA.

[0047] According to one embodiment, the transistor cells may be strip-shaped with horizontal longitudinal axes along a first horizontal direction, wherein the first and second column regions may be strip-shaped with horizontal longitudinal axes along the first horizontal direction.

[0048] The strip-shaped transistor cells TC comprise strip-shaped planar gate structures or strip-shaped trench gate structures with horizontal longitudinal axes parallel to the first horizontal direction. The horizontal longitudinal axes of the gate structures and the horizontal longitudinal axes of the first and second column regions run parallel to each other.

[0049] According to one embodiment, the transistor cells are strip-shaped with longitudinal axes along a first horizontal direction and the first and second column regions are strip-shaped with horizontal longitudinal axes oblique to the first horizontal direction.

[0050] The strip-shaped transistor cells TC comprise strip-shaped planar gate structures or strip-shaped trench gate structures, wherein horizontal longitudinal axes of the strip-shaped gate structures and horizontal longitudinal axes of the first and second column regions are inclined to each other in the horizontal plane by at least 10 degrees, e.g., by 30 degrees, by 45 degrees, or by 90 degrees.

[0051] According to one embodiment, the current spreading region may comprise a central portion formed in a gap in the shielding structure and a heavily doped sidewall portion between the central channel portion and the shielding structure.

[0052] The heavily doped sidewall section can laterally separate the central section and the shielding structure. The central section and the sidewall section form a channel section of the current spreading region.

[0053] According to one embodiment, a method for forming a semiconductor device may comprise forming a base layer based on single-crystalline silicon carbide, wherein the base layer comprises a non-depletable shield structure of a second conductivity type and a current spreading region of a first conductivity type extending from a base layer surface of the base layer through a gap in the shield structure. wherein the transistor layer comprises a transistor cell configured to control a current through the current spreading region, wherein along a vertical line orthogonal to an epitaxial interface between the transistor layer and the base layer and through a pn junction between the shield structure and a region of the first conductivity type in the transistor layer, a net dopant concentration of at least 1e17 1 / cm 3 per 0.1 µm, at least 2e17 1 / cm 3per 0.1 µm or at least 4e17 1 / cm 3 per 0.1 µm. wherein at a pn junction between the current spreading region and the shielding structure a net dopant concentration of at least 1e17 1 / cm 3 per 0.1 µm along a horizontal line parallel to the epitaxial interface,

[0054] According to one embodiment, forming the transistor layer may comprise growing the transistor layer on the base layer surface by epitaxy after forming the shielding structure in the base layer.

[0055] The current spreading region may comprise a spreading section formed between and vertically separating the shielding region and a current drift section of the first conductivity type, wherein the current drift section is formed between the spreading section and a drain layer on the backside of the base layer, and wherein the dopant concentration in the shielding region is at least twice, e.g., at least ten times, higher than in the current drift section. Forming the spreading section may comprise implanting dopants prior to epitaxial growth of the transistor layer.

[0056] According to one embodiment, forming the base layer may comprise forming depletable first pillar regions of the first conductivity type and depletable second pillar regions of the second conductivity type in the base layer prior to forming the shielding structure, wherein the shielding structure is formed between the base layer surface and the first and second pillar regions.

[0057] Forming the base layer may include forming at least a lower portion of the first pillar regions and second pillar regions in a first base layer for the base layer, then growing a second base layer of the base layer on a first base layer surface of the first base layer, and then forming the shielding structure, or forming an upper portion of the first pillar regions and second pillar regions and the shielding structure on the lower portions of the first pillar regions and second pillar regions.

[0058] According to one embodiment, forming the transistor layer may comprise forming a gate trench extending from a main surface of the transistor layer into the transistor layer, implanting dopants of the first conductivity type through a bottom of the gate trench to form an auxiliary region between the gate trench and the shield structure, and forming a trench-gate structure in the gate trench.

[0059] The dopants of the first conductivity type may be acceptor ions. The auxiliary region may extend from the bottom of the gate trench to or into the shielding structure.

[0060] According to one embodiment, forming the base layer may comprise forming, prior to forming the transistor layer, a channel trench in the gap of the shielding structure and filling the channel trench with doped semiconductor material to form at least a portion of the current spreading region.

[0061] The channel trench can be filled during the epitaxial process that forms the transistor layer. The gaps in the shielding structure can result from etching the channel trenches in a continuous shielding layer, and the shielding structure can be obtained from the unetched portion of the shielding layer.

[0062] According to one embodiment, dopant atoms may be implanted in sidewalls of the channel trench before filling the channel trench.

[0063] Fig. 1A shows a semiconductor device having a base layer 200 and a transistor layer 100. The base layer 200 and the transistor layer 100 are made of monocrystalline silicon carbide of the 4H polytype and are formed on opposite sides of a horizontal epitaxial interface 201.

[0064] The base layer 200 has two substantially parallel, rectangular main surfaces, with a first main surface extending in a first horizontal plane on a front side and a second main surface extending in a second horizontal plane on a back side. The base layer 200 has a thickness in a vertical direction orthogonal to the two horizontal planes.

[0065] An n-type current drift section 240, n-type current spreading regions 230 and a non-depletable p-type shielding structure 260 are formed as doped regions in the base layer 200.

[0066] The current drift section 240 is formed as a continuous horizontal layer extending laterally through the base layer 200. The current spreading regions 230 are formed between portions of the shielding structure 260 and extend from the epitaxial interface 201 to the n-type current drift section 240. The n-type current drift section 240 and the n-type current spreading regions 230 form horizontal unipolar junctions.

[0067] The shielding structure 260 extends from the epitaxial interface 201 into the base layer 200. Portions of the shielding structure 260 on opposite sides of a current spreading region 230 may be separated from each other or may be laterally connected to each other in a plane parallel to the cross-sectional plane to form a continuous, one-piece shielding structure 260. Within the shielding structure 260, the dopant concentration is approximately uniform along the horizontal directions. The shielding structure 260 is not completely depleted under operating conditions within the safe operating range of the semiconductor device.

[0068] The transistor layer 100 is formed by epitaxy on the first main surface of the base layer 200 after the formation of the shielding structure 260 in the base layer 200, whereby the silicon and carbon atoms continue the monocrystalline crystal lattice of the base layer 200. Apart from trench gate electrodes and / or metal contact structures extending from the exposed upper surface 101 at a front side of the transistor layer 100 into the transistor layer 100, the upper surface 101 of the transistor layer 100 is substantially planar. The transistor layer 100 comprises a plurality of transistor cells TC. Load paths of the transistor cells TC between a source electrode S and the current drift section 240 are electrically connected in parallel to each other.

[0069] A suitable potential applied to the gate electrode G of the transistor cells TC controls a load current through the transistor cells TC by field effect. The load current through the transistor cells TC flows through the current spreading regions 230.

[0070] Fig. Figure 1B shows a vertical net dopant concentration gradient (vertical doping profile) along line BB in Fig. 1A. N1 indicates the donor concentration (donor density). N2 indicates the acceptor concentration (acceptor density). The position of the horizontal axis indicates a level of zero net doping.

[0071] A first section of the line BB crosses an upper pn junction 261 between the p-type shielding structure 260 and an n-type region in the transistor layer 100. Near the upper pn junction 261, a net dopant concentration change ΔNc / Δyc is at least 1e17 1 / cm 3 per 0.1 µm, e.g. at least 2e17 1 / cm3 per 0.1 µm.

[0072] A second section of the line BB crosses a lower pn junction 262 between the p-type shielding structure 260 and the current drift section 240. Near the second pn junction 262, a net dopant concentration change ΔNb / Δyb is at least 1e16 1 / cm 3 per 0.1 µm, e.g. B. at least 2e16 1 / cm 3 per 0.1 µm. The net dopant concentration change ΔNc / Δyc at the upper pn junction 261 is a factor of 5...10 larger (steeper) than the net dopant concentration change ΔNb / Δyb at the lower pn junction 262.

[0073] A thickness v0 of the shielding structure 260 is defined by the vertical distance between the upper pn junction 261 and the lower pn junction 262. For a trench-gate semiconductor device, the thickness v0 may be equal to the distance between the bottom of the trench-gate structure and the pn junction in the direction of the drift layer. The thickness v0 of the shielding structure 260 is approximately uniform and ranges from 400 nm to 0.8 µm.

[0074] Fig. Figure 1C shows a horizontal dopant concentration gradient in the base layer 200 in a horizontal plane intersecting the current spreading region 230 and the shielding structure 260, as indicated by the line CC in Fig. 1A is indicated.

[0075] At the vertical pn junctions 263 between the shielding structure 260 and the current spreading region 230, the net dopant concentration change ΔNa / Δxa is at least 1e17 1 / cm 3 per 0.1 µm, e.g. B. at least 2e17 1 / cm3 per 0.1 µm.

[0076] A width w0 of the current spreading region 230 is defined by the horizontal distance between the vertical pn junctions 263 on opposite sides of the current spreading region 230. The width w0 of the current spreading region 230 is in a range from 100 nm to 600 µm.

[0077] The aspect ratio v0 / w0 of a gap in the shielding structure 260 is at least 1, for example, at least 5. The current spreading region 230 completely fills the gap and forms the channel region of a JFET structure, which generates the on-state resistance RDSon. A JFET design with a high aspect ratio v0 / w0 of length / width enables an improved compromise between low RDSon and long short-circuit endurance.

[0078] Each of the Fig. 2, Fig. 3 and Fig. 4 shows details of various transistor cells TC in combination with p-type connection regions 160 extending from the top surface 101 of the transistor layer 100 downwards to the p-type shielding structure 260.

[0079] Each transistor cell TC includes an n-type source region 110, a p-type body region 120, an n-type current collection region 130, a gate conductor 155 electrically connected to a gate electrode G, and a gate dielectric 151 separating the gate conductor 155 and the body region 120. The body region 120 separates the source region 110 and the current collection region 130 from each other. A potential applied to the gate electrode G controls a current between the source region 110 and the current collection region 130 through the body region 120 by field effect.

[0080] Current collection region 130 and current spreading region 230 are in direct contact with each other and may have the same dopant concentration or may form a unipolar junction. Current collection region 130 may receive the dopants that define its conductivity during or after the formation of transistor layer 100. For example, current collection region 130 may be doped in-situ during epitaxial growth of transistor layer 100.

[0081] The interconnection regions 160 are in direct contact with the shielding structure 260, with the interconnection regions 160 and the shielding structure 260 forming horizontal unipolar junctions along first sections of the epitaxial interface 201. A vertical dopant profile through the first section of the epitaxial interface 201 reveals a step at the epitaxial interface 201.

[0082] Fig. Figure 2 shows a semiconductor device with planar gate structures 150, wherein the gate conductor 155 and the gate dielectric 151 are formed on the top surface 101 of the transistor layer 100. The source region 110, the body region 120, and the current collection region 130 are formed in the transistor layer 100 along the top surface 101 in this order, with the body region 120 separating the source region 110 and the current collection region 130 in a horizontal direction parallel to the epitaxial interface 201.

[0083] A first vertical pn junction is formed between the current collection region 130 and the body region 120. A second vertical pn junction is formed between the body region 120 and the source region 110. The gate conductor 155 is formed on the transistor layer 100 and extends from approximately above the first vertical pn junction to approximately above the second vertical pn junction. The gate dielectric 151 separates the gate conductor 155 and the transistor layer 100 from each other. The gate conductor 155 is capacitively coupled to the body region 120.

[0084] A shield structure 260 is formed along the epitaxial interface 201 of the base layer 200 in direct contact with the body region 120 and the source region 110. A p-type connection region 160 with a higher average dopant concentration than the body region 120 extends adjacent to the source region 110 from the top surface 101 of the transistor layer 100 to the shield structure 260.

[0085] The current spreading region 230 includes a channel section 231 and a spreading section 232. The channel section 231 extends through a gap in the shielding structure 260 or between two adjacent tip-shaped partial regions of the shielding structure 260 (shielding regions). A vertical extension of the channel section 231 and a vertical extension of the shielding structure 260 are equal. The spreading section 232 separates the shielding structure 260 and the current drift section 240 along the vertical direction. The channel section 231 and the spreading section 232 of the current spreading region 230 have the same dopant concentration.

[0086] Fig. 3 and Fig. 4 illustrate semiconductor devices with trench gate structures 150 extending from the top surface 101 of the transistor layer 100 into or through the transistor layer 100. Each trench gate structure 150 includes a gate conductor 155 and a gate dielectric 151, with the gate dielectric 151 lining a gate trench and the gate conductor 155 filling the remainder of the gate trench. The gate dielectric 151 separates the gate conductor 155 from the transistor layer 100 and, if applicable, from the primer layer 200. The source region 110, the body region 120, and the current collection region 130 are formed along at least one sidewall of the trench gate structure 150 in that order and are in direct contact with a sidewall of the trench gate structure 150. The source region 110 extends from the top surface 101 into the transistor layer 100. The body region 120 vertically separates the source region 110 and the current collection region 130.

[0087] Fig. 3 shows a semiconductor device with trench gate structures 150 and transistor cells TC with a single-sided transistor channel. The channel portion 231 of the current spreading region 230 is formed at a lateral distance from the trench gate structure 150. A bottom portion of the trench gate structure 150 is in direct contact with the shield structure 260. The connection regions 160 may be formed on a side of the trench gate structures 150 opposite the body regions 120 and extend from the top surface 101 downwards toward or into the shield structure 260, or on the same side as the transistor channel in a plane parallel to the cross-sectional plane.

[0088] In Fig. 4, the channel portion 231 of the current spreading region 230 is formed without a lateral spacing from the trench gate structure 150. The channel portion 231 laterally separates a bottom portion of the trench gate structure 150 from the shielding structure 260.

[0089] In each of the semiconductor devices of Fig. 3 and Fig. 4, the current collection regions 130 and the current spreading regions 230 are in direct contact with each other along second sections of the epitaxial interface 201. The current collection regions 130 and the channel sections 231 of the current spreading regions 230 may have the same dopant content. Otherwise, a vertical dopant profile through the second sections of the epitaxial interface 201 may have a steep step at the epitaxial interface 201.

[0090] Fig. 5 refers to an example with an average donor concentration ND1 in the current collection region 130 that is lower than an average donor concentration ND2 in the current spreading region 230. The vertical dopant profile through the current collection region 130 and the current spreading region 230 shows a steep slope at the epitaxial interface 201. A net dopant concentration change is at least 2e17 1 / cm 3 per 0.1 µm, e.g. B. at least 4e17 1 / cm 3 per 0.1 µm. The steep slope may be the result of the transistor layer 100 with the current collection region 130 being formed by epitaxy after the formation of the current spreading region 230 in the base layer 200.

[0091] Fig. 6A refers to an example with an average acceptor concentration NA2 in the interconnect region 160 that is lower than an average acceptor concentration NA1 in the shielding structure 260. Then, the vertical dopant profile through the interconnect region 160 and the shielding structure 260 may exhibit a steep slope at the epitaxial interface 201.

[0092] A net dopant concentration change is at least 1e18 1 / cm 3 per 0.1 µm, e.g. B. at least 2e18 1 / cm 3 per 0.1 µm. The steep slope may result from the transistor layer 100 being formed after the formation of the shielding structure 260 in the base layer 200.

[0093] Fig. 6B refers to transistor cells with trench gate structures. For example, in Fig. 3, the current spreading region 230 may comprise a layered spreading section 232 formed between the shielding structure 260 and the current drift section 240. When the dopants for the spreading section 232 are implanted through the transistor layer 100, an implantation tail extends into the current collecting region 130 and the body region 120. In contrast, the formation of the transistor layer 100 after the implantation of the dopants for the spreading section 232 and the shielding region 260 forms a well-defined sharp transition at the pn junction between the shielding region 260 and the current collecting region 130. The doping in the body region 120 and the current collecting region 130 can be precisely defined. The net dopant concentration change at the epitaxial interface 201 is at least 1e17 1 / cm 3 per 0.1 µm, e.g. B. at least 2e17 1 / cm 3 per 0.1 µm.

[0094] Fig. 7 and Fig. 8 shows symmetrical transistor cells TC with planar gate structures 150. The symmetry planes 490 are orthogonal to the upper surface 101 of the transistor layer 100 and run in the lateral centers of a current collection region 130 and a channel section 231 of a current spreading region 230. The current collection region 130 and the channel section 231 are shared by the two symmetrical transistor cells TC.

[0095] The current drift section 240 is homogeneously doped and vertically separates the current spreading region 230 from a heavily doped drain layer 290 formed along a back surface 202 of the base layer 200. A dopant concentration in the drain layer 290 is sufficiently high to form an ohmic contact with a back metallization 320, which forms or is electrically connected to a drain electrode D of the semiconductor device. At the front side, an interlayer dielectric 305 separates the gate conductor 155 from a front metallization 310. The front metallization 310 forms ohmic contacts with the source regions 110 and the connection regions 160 and forms or is electrically connected to a source electrode S of the semiconductor device.

[0096] In Fig. 7, the gate conductor 155 extends completely over the current collection area 130. In Fig. 8, the gate conductor 155 is split into two parts and is missing over a central portion of the current collection region 130.

[0097] The Fig. 9 comprises transistor cells TC with single-sided transistor channel, as described with reference to Fig. 3. Strip-shaped trench gate structures 150 with horizontal longitudinal axes along a first horizontal direction orthogonal to the cross-sectional plane extend from the top surface 101 of the transistor layer 100 into the shielding structure 260. The channel portions 231 of the current spreading region 230 are formed at a lateral distance from the trench gate structures 150. The connection regions 160 are formed on a side of the trench gate structures 150 opposite the body regions 120 and extend along the sidewalls of the trench gate structures 150 from the top surface 101 downward to the shielding structure 260.

[0098] The Fig. 10 comprises transistor cells TC with two-sided transistor channels, as described with reference to Fig. 4. Strip-shaped trench gate structures 150 with horizontal longitudinal axes along a first horizontal direction orthogonal to the cross-sectional plane extend downwards to or into the base layer 200 and the channel portions 231 of the current spreading regions 230. The channel portions 231 of the current spreading regions 230 are in direct contact with the trench gate structures 150. The connection regions 160 extend between adjacent transistor cells TC from the upper surface 101 downwards to the shielding structure 260. The shielding structure 260 comprises strip-shaped subregions with horizontal longitudinal axes orthogonal to the cross-sectional plane or forms a grid with the channel portions 231 of the current spreading regions formed in the meshes of the grid.

[0099] The semiconductor devices in Fig. 9 and Fig. 10 further include depletable n-type first pillar regions 241 and depletable p-type second pillar regions 242. The first pillar regions 241 are formed in the base layer 200 in direct contact with the current spreading regions 230. The second pillar regions 242 are formed in the base layer 200 in direct contact with the shielding structure 260.

[0100] The n-type first pillar regions 241 and the p-type second pillar regions 242 are strip-shaped with horizontal longitudinal axes along the first horizontal direction. The n-type first pillar regions 241, the p-type second pillar regions 242, and the trench gate structures 150 run parallel to each other. The n-type first pillar regions 241 and the p-type second pillar regions 242 alternate along a second horizontal direction (x-axis) orthogonal to the first horizontal direction. The first and second pillar regions 241, 242 form a compensation structure configured to be fully depleted at a nominal breakdown voltage of the semiconductor device within the SOA.

[0101] In Fig. 11, metal contact plugs 315 extend from the top surface 101 into the interconnect regions 160 in the transistor layer 100. The interconnect regions 160 are in contact with the bottom and sidewalls of the metal contact plugs 315. The metal contact plugs 315 and the interconnect regions 160 form low-resistance ohmic contacts. The interconnect regions 160 include portions extending from the bottom of the metal contact plugs 315 to or into the shielding structure 260, with a doping tip directly below the metal contact plug 315 improving the ohmic contact. Alternatively, the metal contact plugs 315 may extend into the shielding structure 260.

[0102] While in Fig. 10 and Fig. 11 shows the connection regions 160 between adjacent source regions 110 of adjacent strip-shaped transistor cells TC and alternating with the source regions 110 along the second horizontal direction (x-axis), Fig. 12 shows the connection regions 160, which alternate with the source regions 110 along the first horizontal direction (y-axis). Each connection region 160 extends along the second horizontal direction (x-axis) from a first trench gate structure 150 to an adjacent second trench gate structure 150. Each source region 110 extends along the second horizontal direction from the first trench gate structure 150 to the adjacent second trench gate structure 150. Connection regions 160 and source regions 110 alternate strictly along the first horizontal direction (y-axis).

[0103] Fig. 13A and Fig. 13B show parallel cross sections for the planar transistor cell layout of Fig. 12 for an example with the n-type pillar regions 241 in direct contact with the channel portions 231 of the current spreading regions.

[0104] Fig. 14A and Fig. 14B show parallel cross sections for the planar transistor cell layout of Fig. 12 for an example with narrow channel sections 231. An aspect ratio v0 / w0 of the channel sections 231 is at least 1 or at least 5.

[0105] In Fig. 15A and Fig. 15B, the trench gate structures 150 are formed entirely in the transistor layer 100 and terminate at a distance from the base layer 200.

[0106] In Fig. 16A and Fig. 16B, the trench gate structures 150 terminate in the transistor layer 100. P-type auxiliary regions 170 extend from a bottom of the trench gate structures 150 to the shielding structure 260. The p-type auxiliary regions 170 and the shielding structure 260 are in direct contact and form a unipolar junction along the epitaxial interface 201. A vertical dopant profile through the unipolar junction between a p-type auxiliary region 170 and the shielding structure 260 may have a steep slope at the epitaxial interface 201.

[0107] The auxiliary region 170 can be formed self-aligned to the trench gate structure 150. Alignment requirements between the trench gate structure 150 in the transistor layer 100 and the gaps in the shield structure 260 in the base layer 200 are more relaxed.

[0108] In Fig. 17A, Fig. 17B, Fig. 17C and Fig. 17D, strip-shaped first and second pillar regions 241, 242 have horizontal longitudinal axes orthogonal to the second horizontal direction (x-axis). The strip-shaped transistor cells comprise strip-shaped planar gate structures 150 or strip-shaped trench gate structures 150 with horizontal longitudinal axes parallel to the first horizontal direction. The first and second pillar regions 241, 242 extend orthogonally to the gate structures 150.

[0109] Fig. 17A, Fig. 17B and Fig. 17C show a grid-shaped shielding structure 260 with openings directly below and in direct contact with the n-conducting current collection regions 130.

[0110] As in Fig. As illustrated in Figure 17A, the shield structure 260 connects the p-type second pillar regions 242 to a plurality of connection regions 160.

[0111] According to Fig. 17B, ​​n conductive current spreading regions 230 in the openings of the shielding structure 260 connect each n conductive first column region 241 to a plurality of current collecting regions 130.

[0112] Fig. 17C shows that a p-type second pillar region 242, which is wider than the p+ type connection region 160, undercuts the comparatively wide transistor region with the n+ type source regions 110 and n-type current collection regions 130. In the illustrated cross-section, the shield region 260 is formed between the second pillar regions 242 and the n-type current collection regions 130.

[0113] Fig. 17D shows a shielding structure 260 having strip-shaped subregions with horizontal longitudinal axes along the first horizontal direction parallel to the gate structure 150. Each subregion of the shielding structure 260 connects a p-conducting second pillar region 242 to a plurality of connection regions 160. N conductive current spreading regions 230 laterally separate the subregions of the shielding structure 260 from one another.

[0114] Similar to Fig. 17B, ​​the conductive current spreading regions 230 connect each n conductive first column region 241 to a plurality of current collecting regions 130.

[0115] In Fig. 18A and Fig. 18B, the shielding structure 260 is structured along the first horizontal direction. The shielding structure 260 includes shielding islands that are laterally separated from each other along the first and second horizontal directions above the n-conducting first pillars 241. At the expense of the area for the shielding structure 260, the area for the current spreading regions is increased to improve the efficiency of the current spreading function of the current spreading region 230.

[0116] In Fig. 19A to Fig. 19C, the n-type first column regions 241 and the p-type second column regions 242 extend with the horizontal longitudinal axes parallel to the second horizontal direction (x-axis) and are laterally aligned with the source regions 110 and the connection regions 160 in the transistor layer 100. The shielding structure 260 comprises strip-shaped subregions with horizontal longitudinal axes parallel to the second horizontal direction (x-axis). Strip-shaped current spreading regions 230 above the n-type first columns 241 laterally separate the strip-shaped subregions of the shielding structure 260 from one another. Each strip-shaped current spreading region 230 connects an n-type first column region 241 to a plurality of current collecting regions 130. Each strip-shaped subregion of the shielding structure 260 connects a p-type second column region 242 to a plurality of connection regions 160.

[0117] Fig. Figure 20 shows a current spreading region 230 comprising a channel section 231 with a central section 237 and heavily doped sidewall sections 238 between the central section 237 and the shielding structure 260. The heavily doped sidewall sections 238 separate the central section 237 from the shielding structure 260. The heavily doped sidewall sections 238 allow for precise tuning of the JFET structure and may result from tilted ion implantation.

[0118] Fig. 21A to Fig. 21B illustrates a method for fabricating a semiconductor device. A first implantation mask 410 is formed on a base layer surface 205 at a front side of a base layer 200 by photolithography, wherein the base layer 200 is based on single-crystal silicon carbide with an n-type background doping. Acceptor ions are implanted through openings in the first implantation mask 410.

[0119] Fig. 21A shows a p-type shielding structure 260 obtained by activating the acceptor ions implanted in regions of the base layer 200 exposed by the first implantation mask 410. A portion of the base layer 200 covered by the first implantation mask 410 forms an n-type current spreading region 230. A portion of the base layer 200 below the shielding structure 260 and the current spreading region 230 forms a current drift region 240.

[0120] Then, a transistor layer 100 is formed on the base layer surface 205 by epitaxy. Doped regions and gate structures of transistor cells TC are formed in the transistor layer 100.

[0121] Fig. Figure 21B shows the transistor layer 100 and the base layer 200 having a horizontal epitaxial interface 201 in the plane of the base layer surface 205 of Fig. 21A. The transistor cells TC in the transistor layer 100 control a drain current IC through the current spreading region 230 in the base layer 200. Along a vertical line orthogonal to the epitaxial interface 201 and through a pn junction between the shielding structure 260 and an n-type region in the transistor layer 100, a net dopant concentration of at least 1e17 1 / cm 3 per 0.1 µm,

[0122] Fig. 22A to Fig. 22D illustrates a method using epitaxy on base layers with pre-formed doped regions. A first auxiliary implantation mask 420 is formed on a first base layer surface 215 at a front side of a first base layer 210 by photolithography, wherein the first base layer 210 is based on single-crystal silicon carbide with an n-type background doping. Acceptor ions are implanted through openings in the first auxiliary implantation mask 420.

[0123] Fig. 22A shows p-type second pillar regions 242 obtained from activated acceptor ions implanted through the openings in the auxiliary implantation mask 420 and n-type first pillar regions 241 formed in portions of the first base layer 210 covered by the auxiliary implantation mask 420.

[0124] The first auxiliary implantation mask 420 is removed, and a second base layer 220 is formed on the first base layer surface 215 by epitaxy. The second base layer 220 may be in-situ doped with donor atoms. The first base layer 210 and the second base layer 220 form a base layer 200 with an exposed base layer surface 205. A second auxiliary implantation mask 430 is formed on the base layer surface 205 using photolithography. Acceptor atoms are implanted into the second base layer 220 by ion implantation.

[0125] Fig. 22B shows a p-type shielding structure 260 obtained by activating the acceptor ions implanted through the openings in the second auxiliary implantation mask 430, and n-type current spreading regions 230 formed in portions of the second base layer 220 covered by the second auxiliary implantation mask 430. Each p-type shielding structure 260 is in direct contact with a p-type second pillar region 242. Each n-type current spreading region 230 is in direct contact with an n-type first pillar region 241.

[0126] An epitaxial base interface 211 is formed between the first base layer 210 and the second base layer 220. A thickness v1 of the second base layer 220 and a vertical extension v0 of the shielding structure 260 are at least approximately equal.

[0127] The second auxiliary implantation mask 430 is removed, and a transistor layer 100 is grown epitaxially on the base layer surface 205. The transistor layer 100 may be in-situ doped with donor atoms or acceptor atoms. A trench etch mask is formed on a top surface 101 of the transistor layer 100. Gate trenches 159 are etched into the transistor layer 100 above the shield structure 260. A sacrificial oxide 440 is formed on exposed surfaces of the transistor layer 100. Acceptor atoms are implanted through the bottom of the gate trenches 159.

[0128] Fig. Figure 22C shows p-type auxiliary regions 170 obtained from activated acceptor ions implanted through the bottom of the gate trenches 159. Each p-type auxiliary region 170 is in direct contact with the p-type shielding structure 260. The auxiliary regions 170 extend from the trench gate structures 150 to the shielding structure 260.

[0129] Sacrificial oxide 440 is removed. A dielectric liner is formed on exposed surfaces of transistor layer 100, e.g., by oxidation and / or deposition. A conductive material, e.g., heavily doped polycrystalline silicon, is deposited and removed from the top surface 101.

[0130] Fig. Figure 22D shows gate structures 150 with a gate conductor 155 formed from the deposited conductive material forming the gate trenches 159 of Fig. 22C fills.

[0131] Fig. 23A to Fig. 23D illustrate a method for more precisely defining the JFET structure. A hard mask 450 is formed on a base layer surface 205 at a front side of a base layer 200, wherein the base layer 200 includes a shield structure 260 or a continuous p-type layer formed along the base layer surface 205.

[0132] As in Fig. As illustrated in Figure 23A, the hard mask 450 covers the shielding structure 260 and exposes portions of the base layer 200 between or surrounded by the shielding structure 260. Using the hard mask 450 as an etch mask, channel trenches 239 are etched into the base layer 200.

[0133] Fig. Figure 23B shows a channel trench 239. Sidewalls of the channel trench 239 expose the p-type shielding structure 260. Donor atoms are implanted through the sidewalls of the channel trench 239 by tilted ion implantation.

[0134] According to Fig. 23C, heavily doped n-type sidewall portions 238 of a channel portion of a current spreading region are formed on opposite sides of the channel trench. A transistor layer 100 is then grown on the base layer surface 205 by epitaxy as described above. The transistor layer 100 may be doped in-situ with donor atoms.

[0135] According to Fig. 23D, a portion of the grown transistor layer 100 fills the channel trench 239 of Fig. 23C. The in-situ doped portion of the transistor layer 100 in the channel trench 239 of Fig. 23C forms a lightly doped central portion 237 of the channel portion 231 of a current spreading region.

Claims

[1] A semiconductor device comprising: a base layer (200) based on single-crystal silicon carbide and comprising a current spreading region (230) of a first conductivity type and a non-depletable shielding structure (260) of a second conductivity type, and a transistor layer (100) based on epitaxially grown single-crystal silicon carbide and comprising a transistor cell (TC) configured to control a current through the current spreading region (230); wherein the transistor layer (100) was formed on the base layer (200) after the formation of the shielding structure (260) in the base layer (200), so that an epitaxial interface (201) is formed between the base layer (200) and the transistor layer (100); wherein the current spreading region extends from the epitaxial interface (201) between adjacent partial regions of the shielding structure (260); and wherein along a vertical line orthogonal to the epitaxial interface (201) and through a pn junction between the shielding structure (260) and a region of the first conductivity type in the transistor layer (100) a net dopant concentration of at least 1e17 1 / cm 3 per 0.1 µm at the position of the pn junction. [2] The semiconductor device according to the preceding claim, wherein the base layer (200) further comprises a current drift portion (240, 241) of a first conductivity type, and wherein the current spreading region (230) extends to the current drift portion (240, 241). [3] A semiconductor device according to any one of the preceding claims, further comprising: a connection region (160) of the second conductivity type, wherein the connection region (160) extends through the transistor layer (100) to the shielding structure (260) and is in direct contact with the shielding structure (260) along a first portion of the epitaxial interface (201), and wherein a vertical dopant profile through the first portion of the epitaxial interface (201) shows a step at the epitaxial interface (201). [4] A semiconductor device according to the preceding claim, wherein the connection region (160) extends from an upper surface (101) of the transistor layer (100) to the shielding structure (260). [5] A semiconductor device according to any one of the preceding claims, wherein the transistor cell (TC) is configured to control a current through a body region (120) between a source region (110) and a current collection region (130), and wherein the current collection region (130) is electrically connected to the current spreading region (230). [6] A semiconductor device according to the preceding claim, wherein the body region (120) separates the source region (110) and the current collection region (130) in a horizontal direction parallel to the epitaxial interface (201). [7] The semiconductor device according to claim 5, wherein the body region (120) vertically separates the source region (110) and the current collection region (130). [8] A semiconductor device according to the preceding claim, further comprising: a trench gate structure (150) extending from a top surface (101) of the transistor layer (100) into the transistor layer (100), wherein the source region (110), the body region (120) and the current collection region (130) are in direct contact with a sidewall of the trench gate structure (150). [9] A semiconductor device according to the preceding claim, wherein the current collecting region (130) and the current spreading region (230) are in direct contact with each other along a second portion of the epitaxial interface (201), and wherein a vertical dopant profile through the second portion of the epitaxial interface (201) shows a step at the epitaxial interface (201). [10] A semiconductor device according to any one of the two preceding claims, wherein the trench gate structure (150) terminates in the transistor layer (100) and wherein an auxiliary region (160) of the second conductivity type extends from a bottom of the trench gate structure (150) to the shielding structure (260). [11] A semiconductor device according to any one of the preceding claims, wherein the current spreading region (230) extends vertically through a gap in the shielding structure (260), the gap having a vertical extent v0 and a horizontal width w0, and an aspect ratio v0 / w0 of the gap in the shielding structure (260) being at least 0.3, for example at least 1 or at least 5. [12] A semiconductor device according to any one of the preceding claims, further comprising: a depletable first pillar region (241) of the first conductivity type and depletable second pillar regions (242) of the second conductivity type, wherein the first pillar region (241) is formed in the base layer (200) in direct contact with the current spreading region (230) and wherein the second pillar regions (242) are formed in the base layer (200) in direct contact with the shielding structure (260). [13] A semiconductor device according to the preceding claim, wherein the transistor cells (TC) are strip-shaped with horizontal longitudinal axes along a first horizontal direction and wherein the first and second pillar regions (241, 242) are strip-shaped with horizontal longitudinal axes along the first horizontal direction. [14] A semiconductor device according to claim 12, wherein the transistor cells (TC) are strip-shaped with longitudinal axes along a first horizontal direction, and wherein the first and second pillar regions (241, 242) are strip-shaped with horizontal longitudinal axes oblique to the first horizontal direction. [15] A semiconductor device according to any one of the preceding claims, wherein the current spreading region (230) comprises a central portion (237) in the gap in the shielding structure (260) and a heavily doped sidewall portion (238) between the central portion (237) and the shielding structure (260). [16] A method of manufacturing a semiconductor device, the method comprising: Forming a base layer (200) based on single-crystal silicon carbide, the base layer (200) comprising a non-depletable shielding structure (260) of a second conductivity type and a current spreading region (230) of a first conductivity type extending from a base layer surface (205) of the base layer (200) through a gap in the shielding structure (260); and Forming a transistor layer (100) on the base layer surface (205), wherein the transistor layer (100) comprises a transistor cell (TC) configured to control a current through the current spreading region (230), wherein along a vertical line orthogonal to an epitaxial interface (201) between the transistor layer (100) and the base layer (200) and through a pn junction between the shielding structure (260) and a region of the first conductivity type in the transistor layer (100), a net dopant concentration of at least 1e17 1 / cm 3 per 0.1 µm at the position of the pn junction. [17] The method of the preceding claim, wherein forming the transistor layer (100) comprises growing the transistor layer (100) on the base layer surface (205) by epitaxy after forming the shielding structure (260) in the base layer (200). [18] The method of any one of the two preceding claims, wherein forming the base layer (200) comprises forming depletable first pillar regions (241) of the first conductivity type and depletable second pillar regions (242) of the second conductivity type in the base layer (200) prior to forming the shielding structure (260), the shielding structure (260) being formed between the epitaxial interface (201) and the first and second pillar regions (241, 242). [19] The method of any one of the three preceding claims, wherein forming the transistor layer (100) comprises forming a gate trench (159) extending from a main surface (101) of the transistor layer (100) into the transistor layer (100), implanting dopants of the first conductivity type through a bottom of the gate trench (159) to form an auxiliary region (160) between the gate trench (159) and the shielding structure (260), and forming a trench-gate structure (150) in the gate trench (159). [20] The method of any one of the four preceding claims, wherein forming the base layer (200) comprises forming, prior to forming the transistor layer (100), a channel trench (239) in the gap of the shielding structure (260) and filling the channel trench (239) with doped semiconductor material to form at least a portion of the current spreading region (230). [21] Method according to the preceding claim, further comprising: Implanting dopant atoms into sidewalls of the channel trench (239) before filling the channel trench (239).

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