METHOD FOR MANUFACTURING A VERTICAL RF BIPOLEAN TRANSISTOR, VERTICAL RF BIPOLEAN TRANSISTOR AND SEMICONDUCTOR DEVICE

Abstract

Method for manufacturing a vertical RF bipolar transistor, wherein the method comprises: Creating a structure, wherein the structure has: a collector (16A) formed in a substrate (10), a base (34) which is arranged above the collector (16A), an emitter (38A) arranged above the base (34), a side wall spacer (36A) extending on a side wall of the emitter (38A), a first layer (30A), wherein a first section of the first layer (30A) is arranged on the side wall spacer (36A) such that the side wall spacer (36A) is located in a lateral direction between the emitter (38A) and the first layer (30A), and wherein an outer side wall of the first section of the first layer (30A) is exposed, wherein the first layer (30A) directly touches the base (34) in a vertical direction and in the lateral direction, a conductive layer (24) extending in the lateral direction, wherein a second section of the first layer (30A) is arranged in the lateral direction between the base (34) and the conductive layer (24), After the structure has been constructed, at least the second section of the first layer (30A) is removed to form a space (46) between the base (34) and the conductive layer (24), and Applying semiconductor material to the space (46) to connect the base (34) to the conductive layer (24).

Description

TECHNICAL AREA

[0001] The present disclosure relates to the manufacture of vertical RF bipolar transistors. BACKGROUND

[0002] In many applications, such as radar, wireless communication, and medical devices, vertical RF bipolar transistors are used to generate signals with frequencies in the GHz range or even higher. Future applications may require the maximum operating frequency of vertical RF bipolar transistors to increase to higher values. These future challenges necessitate that the vertical RF bipolar transistor be capable of achieving high maximum operating frequencies and high performance. It is therefore desirable to have a concept that enables the fabrication of vertical RF bipolar transistors with improved operating characteristics.

[0003] US 2020 / 0066885A1 describes the device structure and fabrication process for a bipolar transistor. A trench insulation region surrounds an active region containing a collector. A base layer is placed above the active region, and a semiconductor layer is placed on top of the base layer. The semiconductor layer has a stepped profile with a first section of a wider width adjacent to the base layer and a second section of a narrower width. An emitter is placed on the second section of the semiconductor layer. SUMMARY

[0004] According to one aspect, a method for fabricating a vertical RF bipolar transistor comprises fabricating a structure, the structure comprising: a collector formed in a substrate, a base arranged above the collector, an emitter arranged above the base, a sidewall spacer extending on a sidewall of the emitter, a first layer, wherein a first section of the first layer is arranged on the sidewall spacer such that the sidewall spacer is located in a lateral direction between the emitter and the first layer, and wherein an outer sidewall of the first section of the first layer is exposed, the first layer directly touching the base in the vertical and lateral directions, and a conductive layer extending in the lateral direction.In the fabricated structure, a second section of the first layer is arranged laterally between the base and the conductive layer. After fabrication, at least the second section of the first layer is removed to create a space between the base and the conductive layer, and semiconductor material is deposited in this space to connect the base to the conductive layer.

[0005] According to another aspect, a vertical RF bipolar transistor comprises a substrate having a first primary surface and a collector located within the substrate. A base is located above the collector, an emitter is located above the base, and a sidewall spacer is located laterally to the emitter. An insulating layer is located above the first primary surface of the substrate. The vertical RF bipolar transistor includes a base junction, with the base junction extending laterally along the insulating layer. A conductive interface region electrically connects the base junction to the base. The conductive interface region comprises monocrystalline semiconductor material. The base and the conductive interface region overlap in a top view, and the conductive interface region is not in direct contact with any upper surface of the base. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure is illustrated by way of example and without limitation in the figures of the accompanying drawings, in which the same reference symbols refer to similar or identical elements. The elements of the drawings are not necessarily to scale relative to one another. The features of the various examples shown may be combined, provided they are not mutually exclusive. Fig. 1-1 to Fig. Figures 1-25 show schematic cross-sectional views of an example of a manufacturing process for producing a vertical RF bipolar transistor. Fig. Figure 2-1 shows a schematic cross-sectional view of an initial structure of another example of a manufacturing process. Fig. Figure 3 shows a schematic cross-sectional view of an example of a vertical RF bipolar transistor. Fig. Figure 4 shows a schematic cross-sectional view of another example of a vertical RF bipolar transistor. Fig. Figure 5 shows a schematic cross-sectional view of another example of a vertical RF bipolar transistor. Fig. Figure 6 shows a schematic cross-sectional view of another example of a vertical RF bipolar transistor. Fig. Figure 7 shows a diagram of actions in an exemplary manufacturing process. DETAILED DESCRIPTION

[0007] The following examples describe a new concept for a vertical RF bipolar transistor. In the fabrication of vertical RF bipolar transistors, such as heterojunction vertical RF bipolar transistors, the interface between a base and a base junction has a significant influence on the transistor's behavior. Imperfections introduced into the base-to-base junction can lead to a deterioration in the transistor's performance. Furthermore, for behavioral reasons, the base of vertical RF bipolar transistors is typically monocrystalline, while the base junction is typically polycrystalline. To achieve high performance, a high degree of monocrystalline material is also desirable in the interface region connecting the base to the base junction.Accordingly, joining the monocrystalline base to the polycrystalline base compound is crucial and presents challenges in such manufacturing processes. Another significant limiting factor for the performance of the RF bipolar transistor is the collector-base capacitance. Therefore, the area of ​​the structural base-collector interface should be reduced to the necessary minimum, thereby avoiding the generation of parasitic components that do not directly contribute to current conduction. Similarly, the parasitic capacitances between the base and collector should be reduced to the absolute minimum.

[0008] The challenges are even greater for vertical RF bipolar transistors with a maximum operating frequency (fmax) of 600 GHz, 800 GHz, 1000 GHz, or even higher. Such vertical RF bipolar transistors require new approaches. Furthermore, integration into a BiCMOS process is desirable, in which CMOS transistors are fabricated in addition to the vertical RF bipolar transistor.

[0009] The concept presented here utilizes the formation of the interface region after the main parts of the vertical RF bipolar transistor (i.e., at least the collector, base, and emitter with their respective dopants and doping concentrations) have been formed. This self-aligned seed layer concept allows for a simpler and less complex approach. Additionally, the concept employs a defined layer (which can be considered a sacrificial layer or a sacrificial side-space layer) that is removed to define a temporarily empty space between the base and the conductive layer. This concept allows the interface between the base and the conductive layer to be placed in the ideal position. The temporarily empty space is filled by depositing semiconductor material using epitaxial growth. The layer defining the space contacts the base in both a lateral and a vertical direction.Consequently, when the layer is removed, lateral and vertical sidewall sections of the base are exposed, enabling epitaxial growth from the base into the empty space of monocrystalline base surfaces extending laterally and vertically. This allows the semiconductor material connecting the base and the conductive layer to be grown at the desired location with high quality and a high degree of monocrystalline sections, as the surface area of ​​the monocrystalline material from which growth can begin is increased. Furthermore, this concept also reduces parasitic capacitances, since the interface between the base and the conductive layer can be fabricated in the optimal position.

[0010] The combination of the manufacturing steps described above results in a new fabrication of a high-performance vertical RF bipolar transistor that operates at very high frequencies with reduced manufacturing complexity and improved BiCMOS integration.

[0011] With reference to Fig. 1-1 to Fig. In 1-25 an example of a process for manufacturing a vertical RF bipolar transistor is now explained. Fig. 1-1 to Fig. Figures 1-25 show the process in a cross-sectional view of the depicted structures. The described process is capable of fabricating vertical RF bipolar transistors in a semiconductor device that are able to operate in the extremely high frequency range (30 to 300 GHz) or even the extremely high frequency range (300 GHz to 3 THz) of the radio spectrum. In some examples, the resulting vertical RF bipolar transistor is capable of operating in a frequency range above 250 GHz. In some examples, the resulting vertical RF bipolar transistor is capable of operating in a frequency range above 300 GHz. Furthermore, the process can be integrated into a BiCMOS process, which makes it possible to fabricate the vertical RF bipolar transistor on the same chip as CMOS transistors.

[0012] Fig. Figure 1-1 shows a pre-processed starting substrate 10 comprising a semiconductor material section 12 and an insulating section 14. The insulating section 14 extends over the upper portion of the substrate 10 and comprises electrically insulating material, such as semiconductor oxide material. The insulating section 14 is positioned between a collector region 16 (sometimes referred to as a collector sink) and a collector junction region 18 and may surround the collector region 16 to provide electrical isolation. The collector region 16 and the collector junction region 18 comprise doped semiconductor material, such as doped monocrystalline silicon. The collector region 16 and / or the collector junction region 18 may be formed by implantation, epitaxial growth, or a combination thereof.A collector connection layer 20 extends beneath the insulation section 14 to electrically connect the collector area 16 to the collector connection area 18. In the Fig. In the example shown in 1-1, the insulation can be a shallow trench insulation and the insulation section 14 can comprise a shallow trench insulation oxide. However, the concept described is not limited to this. Fig. 1-1 comprises a main surface of the substrate 10, an upper surface of the insulation section 14, the upper surface of the collector area 16, and the upper surface of the collector connection area 18. The upper surface of the insulation section 14, the upper surface of the collector area 16, and the upper surface of the collector connection area 18 can be flush with each other, as shown in Fig. Shown in Figure 1-1. The main surface extends in a lateral direction (in Fig. 1-1 shown as the x-axis). A vertical direction perpendicular to the lateral direction is in Fig. 1-1 is shown as the z-axis. In the following, the terms "above" or "above" refer to a relationship between different planes or an orientation relative to the vertical direction. Similarly, the terms "below" or "below" refer to a relationship between different planes or an orientation relative to the vertical direction.

[0013] With reference to Fig. In step 1-2, a stack of layers is deposited over the substrate 10. The stack of layers includes a first insulating layer 22 in direct contact with the upper surface of the substrate 10, a conductive layer 24 over the first insulating layer 22, and a second insulating layer 26 over the conductive layer 24. The first insulating layer 22 and the second insulating layer 26 can be electrically insulating. The first insulating layer 22 can be a thin oxide layer in the range of 10 to 40 nm. The conductive layer 24 can be a heavily doped semiconductor layer, for example, a p-doped polycrystalline silicon layer with a net doping concentration in the range of 1 e19 to 5 e20 cm⁻³. The thickness of the conductive layer 24 can be between 20 and 70 nm. As described below, a section of the conductive layer 24 will later form a section of a base compound.The second insulating layer 26 can be an oxide layer and can be thicker than the first insulating layer 22, for example in the range of 100 to 400 nm.

[0014] Fig. Figures 1-3 show the structure of Fig. 1-2 after applying and structuring a lithography mask 28 to define an emitter window region. The structured lithography mask 28 is used to etch a cavity into the second insulating layer 26 and the conductive layer 24 to create an emitter window in the emitter window region. Fig. Figures 1-4 show the structure of Fig. 1-3 after etching the emitter window. While the cavity may have vertical sidewalls, as in Fig. As shown in Figures 1-4, it is understood that in some examples the cavity may have nearly vertical sidewalls (e.g., less than 15° deviation from the vertical direction). During the etching of the emitter window, the first insulating layer 22 remains completely or at least partially within the emitter window region. Accordingly, the etching is either performed selectively to stop at the upper surface of the first insulating layer 22 or is time-controlled to stop within the first insulating layer 22. After the formation of the emitter window, the lithography mask 28 is removed, see Figure 1-4. Fig. 1-5.

[0015] An electrically insulating spacer layer 30 is formed on the surface of the cavity and the upper surface of the second insulating layer 26, see Fig. 1-6. The spacer layer 30 can, in one example, consist of nitride and can have a thickness of less than 100 nm, in some examples between 20 and 60 nm. However, other materials can also be used to form the spacer layer 30. The spacer layer 30 can also comprise a stack of layers in some examples. The spacer layer 30 is removed from the upper surface of the second insulating layer 26 and from the first insulating layer 22 in the emitter window region, see Fig. 1-7. The remaining section of the spacer layer 30 forms a first layer 30A, which extends onto the side walls of the cavity in a similar shape to a side wall spacer. As shown from Fig. As can be seen in Figures 1-7, the first layer 30A extends laterally to the side surfaces of the conductive layer 24 and the second insulating layer 26. The first layer 30A directly contacts the lateral ends of the conductive layer 24 and the second insulating layer 26.

[0016] The first layer 30A can be considered a sacrificial sidewall spacer that is later removed to create a space. The cross-sectional view shows two opposing sections of the first layer 30A. These sections can be separate or connected. In the examples described, the first layer 30A completely surrounds the emitter region in a plan view. As described later, the first layer 30A provides protection for the conductive layer 24 in the subsequent fabrication steps and is used to define an interface region for the base connection. Furthermore, the first layer 30A can define the collector implantation area.

[0017] Fig. Figures 1-8 show the structure of Fig. 1-7 after implanting a collector 16A into the collector area 16. In some examples, an additional mask can be used for implantation; however, in other examples, the collector 16A can be implanted without an additional mask. The collector 16A can have a doping gradient in the vertical direction. Furthermore, the lateral dimensions of the cavity and the thickness of the first layer 30A can be selected such that a section of the collector area 16 is less doped or undoped by the implantation process. Accordingly, as in Fig. As can be seen in Figures 1-8, an extrinsic collector region 16B surrounds the collector 16A. The doping in the extrinsic collector region 16B is significantly lower than in the collector 16A. In this example, the collector 16A can also be considered an intrinsic collector region. However, in other examples, the lateral dimensions of the cavity and the thickness of the first layer 30A can be selected such that the collector 16A is formed along the entire lateral dimension of the collector region 16. Accordingly, in such examples, an extrinsic collector region cannot be formed.

[0018] After implantation of the collector 16A, the first insulating layer 22 is removed in the emitter window region and under a section of the first layer 30A. Removing the first insulating layer 22 may involve etching the first insulating layer 22 using the first layer 30A as a mask to protect any etching of the conductive layer 24. The etching must be timed such that the first layer 30A is completely removed in the area defined by the first layer 30A and additionally completely under a section of the first layer 30A. Accordingly, the first layer 30A must be undercut to define a gap 32 between the undercut section of the first layer 30A and the collector region 16. The etching must further be timed such that the conductive layer 24 remains sealed by the first insulating layer 22 and the first layer 30A.In other words, the etching process must be time-controlled to avoid completely under-etching the first layer 30A, which would result in contact between the conductive layer 24 and the etchant. Such contact would significantly degrade the performance of the vertical RF bipolar transistor.

[0019] In some examples, the thickness of the first layer 30A is chosen such that, after subsequent etching sequences of the first insulating layer 22, a section of the first insulating layer 22 still remains under layer 30A and covers the conductive layer 24.

[0020] Etching can be wet etching, dry etching, or a combination thereof. Wet etching is less aggressive and can allow better control of gap 32 formation without breaking the seal of the conductive layer 24. In one example, dry etching is followed by wet etching. The dry etching essentially acts without lateral removal and removes the first insulating layer 22 in the area defined by the inner walls of the first layer 30A.

[0021] The wet chemical etching essentially removes the material below the first layer 30A to form the gap 32. Fig. Figures 1-9 show the structure after etching, with the gap 32 formed between a section of the first layer 30A and the collector area 16.

[0022] In a subsequent step, a base 34 is deposited by epitaxial growth. This epitaxial growth can be selective, so that semiconductor material is grown only from the monocrystalline material of the collector region 16. The growth of the base 34 can, in some examples, involve the growth of multiple base layers, such as a SiGe layer and a cover layer. The base 34 can, in some examples, have a lateral dimension between 50 and 400 nm. Fig. Figures 1-10 show the structure after the base 34 has grown. It is important to note that, due to the gap 32 formed in the previous step, a lower section of the base 34 extends further in a lateral direction away from a central axis C than the inner sidewalls (sidewalls facing the central axis C of the vertical RF bipolar transistor) of the first layer 30A. An upper section of the base 34 does not extend further in a lateral direction away from the central axis C than the inner sidewalls of the first layer 30A. In other words, the base 34 can have different lateral dimensions for different vertical planes, with the upper part being smaller than the lower part. This further increases the contact area between the base and the base junction, thus helping to further reduce the overall base resistance.Relative terms such as "outside" and "inside" or "outward" and "inward" can be considered relative to the central axis C (e.g., outward as pointing away from the central axis C, and inward as pointing toward the central axis C). The central axis C can be determined, for example, by a virtual vertical line through the arithmetic midpoint of a region of the base when viewed from above.

[0023] After the base is formed, a lower end of the first layer 30A is arranged in the vertical direction between a lower level of base 34 and an upper level of base 34.

[0024] In the next step, another insulating layer 36 is applied. As shown in the diagram... Fig. As can be seen in Figures 1-11, the additional insulating layer 36 extends within the cavity onto the inner side walls of the first layer 30A and onto the upper surface of the base 34. Outside the cavity, the additional insulating layer 36 extends onto the upper surface of the second insulating layer 26. The additional insulating layer 36 may, for example, comprise oxide material or other electrically insulating material. It should be noted that in other examples, the additional insulating layer 36 may comprise a layer system consisting of multiple layers of different materials. The additional insulating layer 36 should therefore be considered to have one layer or more layers.

[0025] The further insulating layer 36 is etched to form a sidewall spacer 36A which extends in the vertical or near-vertical direction (e.g. less than 15° deviation from the vertical direction) on the inner sidewalls of the first layer 30A, see Fig. 1-12. Anisotropic etching can be used to remove the laterally extending parts of the further insulating layer 36 to form the side wall spacer 36A.

[0026] In a subsequent step, emitter material 38 is applied in the cavity and on the upper surface of the second insulation layer 26, see Fig. 1-13. Emitter material 38 can be n-doped silicon with a net doping concentration in the range of 5 × 10 19 cm -3 up to 1 × 10 21 cm -3 include.

[0027] The emitter material 38, which is applied outside the cavity, is removed as shown in Fig. Figures 1-14 show the removal process. Removal involves etching or chemical-mechanical polishing, or a combination thereof. The emitter material 38 remains in the cavity, forming an emitter 38A. In some examples, the fabricated emitter 38A may have a lateral extent between 60 and 150 nm. In some examples, the first layer 30A and the sidewall spacer 36A may be formed such that they do not extend vertically, resulting in an outward increase in the lateral dimension of the emitter 38A in the vertical direction. The emitter 38A can be flush with the second insulating layer 26, i.e., on the same vertical plane as the second insulating layer 26. In other examples, further etching can be carried out to further reduce the height of the emitter 38A in the cavity, so that the vertical plane of the emitter 38A is below the vertical plane of the second insulating layer 26.Reducing the emitter height reduces the emitter resistance of 38A.

[0028] With reference to Fig. In steps 1-15, a protective layer 40 is applied after the emitter 38A has been formed. The protective layer 40 protects the emitter 38A during further processing to create the base compound. The protective layer 40 can be a single layer or consist of multiple layers of different materials.

[0029] A lithography mask 42 is applied, extending over the emitter 38A and further laterally to the first layer 30A, as shown in Fig. Shown 1-16.

[0030] With reference to Fig. In steps 1-17, the protective layer 40 and the second insulating layer 26 outside the mask area are removed by etching, providing access to the first layer 30A. The second insulating layer 26 may be made of a material different from that of the first layer 30A, so the etching stops at the outer sidewall of the first layer 30A. After etching, an outer sidewall of a first section of the first layer 30A is exposed. In other words, no further layer is in direct contact with the outer sidewall of the first section of the first layer 30A. A second section of the first layer 30A, located laterally between the base 34 and the conductive layer 24, and in direct contact with both the base 34 and the conductive layer 24, remains non-exposed.Furthermore, a third section of the first layer 30A, which is arranged in a lateral direction between the side wall spacer 36A and the conductive layer 24 and is in direct contact with the side wall spacer 36A and the conductive layer 24, also remains non-exposed.

[0031] The first layer 30A is then removed from the exposed outer wall by etching. The etching leaves an empty space 46 between the base 34 and the conductive layer 24, see Fig. 1-19. Since the first layer 30A extends in a vertical or near-vertical direction with a shape similar to a sidewall spacer before removal, the amount of material removed by etching is reduced, and good etching control is achieved. Another advantage of this approach is that the material of the first layer 30A differs from the material of the sidewall spacer 36A. This results in a well-controlled etching process and selectivity, ensuring the integrity of the sidewall spacer 36A and enabling the separation of the base interconnect region from the emitter. Isotropic etching can be used to remove the first layer 30A. Removing the first layer 30A exposes surface sections of the base 34 in both horizontal and vertical directions. Furthermore, a sidewall of the conductive layer 24 is exposed by removing the first layer 30A.

[0032] After forming the void 46, the structure for connecting the base 34 to the conductive layer 24 is prepared. For this purpose, highly doped semiconductor material is deposited in the void 46 by selective epitaxial growth. In the regions near the surfaces of the base 34, the semiconductor material will be monocrystalline, providing a high-quality electrical connection. As mentioned above, due to the void 46 contacting the base 34 in both vertical and horizontal directions, the exposed surface area of ​​the base 34 is increased compared to growth from only a vertical exposed surface. The lower end of the void 46 in the vertical direction is located between a lower surface of the base 34 and an upper surface of the base 34.In other words, the empty space 46 does not extend to the collector area 16 and there will be no connection with the collector area 16, which further reduces parasitic effects and improves the property.

[0033] The conductive layer 24 acts as a seed layer during epitaxial growth, enabling the growth of polycrystalline material on the conductive layer 24. Due to the high doping of the conductive layer 24 and the semiconductor material grown on it, a high-quality electrical connection can be established. As shown in Fig. As can be seen in Figures 1-20, the thickness of the conductive layer 24 is increased due to the growth of semiconductor material. It should be noted that the sidewall spacer 36A prevents the grown semiconductor material from coming into contact with the upper surface of the base 34. The previously empty space 46 is now filled with doped semiconductor material, forming an interface 46A between the base 34 and the increased thickness of the conductive layer 24. Given the high degree of monocrystalline material in the interface 46A, combined with the high doping concentration of the conductive layer 24, a high-quality electrical base connection with low electrical resistance is achieved.

[0034] In a further step, the remaining protective layer 42 is removed, see Fig. 1-21. A lithography mask 48 is formed, covering the emitter 38A, the sidewall spacer 36A and a section of the conductive layer 24, as shown in Fig. Figures 1-22 show the process. The thickened conductive layer 24 and the first insulating layer 22 are then etched using the lithography mask 48. The remaining portion of the thickened conductive layer 24 forms a base junction 24A, which is electrically insulated towards the substrate by the remaining portion 22A of the first insulating layer 22, as shown in Figures 1-22. Fig. 1-23. The lithography mask 48 is then removed, as shown in Fig. Shown 1-24.

[0035] A silicide and metallization process is applied to further improve conductivity and prepare the structure to provide contact structures. Fig. Figures 1-25 show the structure after the silicidal and metallization process. As can be seen, the upper section of emitter 38a is converted into a metallized silicidal region 38B, the upper section of base compound 24A is converted into a metallized silicidal region 24B, and the upper region or collector compound region 18 is converted into a metallized silicidal region 18A.

[0036] After silicide application, conventional processing steps, including the formation of contacts to the emitter 38A, the collector junction area 18, and the base junction 24A, can be used to complete the semiconductor device. In some examples of a BiCMOS process, CMOS transistors arranged in the substrate 10 can be completed before, after, or following the described process. Such processing steps are conventional and are not described herein.

[0037] Fig. 2-1 shows a modification of the original structure of Fig. 1-1, which is used in the manufacturing process. In the manufacturing process, which determines the structure of Fig. Using 2-1 as the starting structure, the insulation section 14, which may, for example, comprise a shallow trench insulation oxide, is thinned with respect to the collector area 16. As can be seen, the upper surface of the collector area 14 is therefore raised above the upper surface of the insulation section 14. Using the processing steps as described in Fig. 1-2 to Fig. 1-25 described, in a similar way on the starting substrate, which is in Fig. As shown in 2-1, this results in a vertical RF bipolar transistor in which the base 34 is further raised by the isolation section 14. Furthermore, the use of the output structure shown in Fig. Figure 2-1 shows how to manufacture a vertical RF bipolar transistor where the lateral extent D1 of the collector region 16 at the collector-base interface is equal to or less than the lateral extent D2 of the base at the collector-base interface, further enhancing the behavior of the vertical RF bipolar transistor.

[0038] A more detailed schematic cross-sectional view of an example of a vertical RF bipolar transistor, which can be fabricated as described above, is shown in Fig. 3 shown. In Fig. Figure 3 shows that the base 34 comprises several base layers 34A, 34B, and 34C. The bottommost base layer 34A is a SiGe layer with a high concentration of germanium. The intermediate base layer 34B is a SiGe layer with a germanium concentration that is lower than in the bottommost base layer 34A. Fig. Figure 3 shows the base layers 34A and 34B as separate layers; it should be noted that in other examples the germanium concentration can decrease continuously from the lower part to the upper part, so that layers 34A and 34B are replaced by a layer with decreasing germanium concentration.

[0039] The upper base layer 34C is a cover layer with Si or SiGe with a very low germanium concentration.

[0040] Fig. Figure 3 further shows a monocrystalline region 50 and a polycrystalline region 51 of the base compound. The interface 46A between the base 34 and the base compound 24A, defined by the former empty space 46, is shown in dashed lines. It can be seen that, in a plan view (view along the vertical axis), the interface 46A overlaps with the base 34. More precisely, in the plan view, the interface 46A overlaps with the lower part of the base 34. However, due to the use of the first sacrificial layer 30A in the manufacturing process described above, the interface 46A is not in direct contact with the upper surface of the base 34. In other words, in a plan view, the interface 46A does not overlap with the upper surface of the base, and consequently, the interface 46A does not extend over the upper surface of the base 34 (here, the upper base layer 34C).Since the interface region 46A does not extend over the upper surface of the base 34, no area of ​​the upper surface of the base 34 is occupied by the interface region. This allows the area available for forming a base-emitter interface to be maximized, making the concept very suitable for shrinking. Furthermore, parasitic effects can be reduced.

[0041] It should be noted that the interface region 46A comprises a high degree of highly conductive monocrystalline material 50. In some examples, the volume of monocrystalline material 50 in the interface region 46A is at least 20%, and in others at least 50%, compared to the volume of polycrystalline material in the interface region 46A. It is further evident that the interface region 46A extends in a lateral direction closer to the central axis C of the vertical RF bipolar transistor than the insulating layer 22A. In other words, the interface region 46A is located in the lateral direction closer to the central axis C than the insulating layer 22A. Furthermore, as can be seen from Fig. As can be seen in Figure 3, the interface area 46A is in direct contact with an outer surface of the side wall spacer 36A. Therefore, a defined electrical insulation between the emitter 38A and the interface area is provided by the side wall spacer 36A.

[0042] Fig. Figure 4 shows a schematic cross-sectional view of another example of a vertical RF bipolar transistor, which can be fabricated as described above. In the vertical RF bipolar transistor according to Fig. In Figure 4, the sidewall spacer 36 is manufactured such that it is not vertical. As a result, the lateral dimension of the emitter 38A increases in a direction away from the substrate 10. Such a non-vertical emitter has an additional advantage for the emitter resistance due to its upward lateral extension, thus reducing the emitter resistance. It should be noted that the non-vertical sidewall spacer 36A and the increasing lateral dimension of the emitter 38A are not related to the example of Figure 4. Fig. 4 are limited, but can be applied to one of the examples described herein. The non-vertical shape is achieved by uneven etching of the cavity that defines the first layer 30A and the side wall spacer 36A.

[0043] Fig. Figure 5 shows a schematic cross-sectional view of another example of a vertical RF bipolar transistor, which can be fabricated as described above. The example is a modification of the one described in Fig. 4 vertical RF bipolar transistors shown. In the case of the vertical RF bipolar transistor according to Fig. 4. The lateral extent D1 of the collector region 16 at the collector-base interface is larger than the lateral extent D2 of the base at the collector-base interface. In contrast, for the vertical RF bipolar transistor according to Fig. 5. The lateral extent D1 of the collector area 16 at the collector-base interface is reduced to a value that is smaller than the lateral extent D2 of the base 34 at the collector-base interface. The collector area 16 according to Fig. 5 no longer includes an extrinsic region 16B. Furthermore, reducing the lateral extent of the collector region 16 reduces parasitic effects (e.g., parasitic emitter-collector capacitances) and increases the maximum operating frequency to even higher frequencies. Furthermore, in Fig. 4 and Fig. 5. A lateral distance D3 between lateral outer boundary locations of the lower section of the side wall spacer 36A is smaller than the lateral extent D2 of the base 34. In other words, an outer boundary of at least one section of the side wall spacer 36A (for example, the lower section of the side wall spacer 36A) is therefore closer in a lateral direction to the central axis C of the vertical RF bipolar transistor than an outer boundary of the base 34.

[0044] Fig. Figure 6 shows a schematic cross-sectional view of another example of a vertical RF bipolar transistor, which can be fabricated as described above. In the example of Fig. 6. The side wall spacer 36A is formed by an electrical insulating layer 52A and an additional electrical insulating layer 52B. This approach further strengthens the spacer's resistance. The thickness of at least one of the electrical insulating layers 52A and 52B (here, the electrical insulating layer 52A) decreases in the vertical direction away from the substrate 10. As can be seen from Fig. As can be seen in Figure 6, the electrical insulation layer 52A is thinned in an upper area. For better understanding, the area corresponding to the removed first layer 30A is also shown in dashed lines. Fig. Figure 6 further shows an emitter metal contact 54 that contacts the emitter 38A from above. As can be seen, the emitter 38A is arranged between respective sections of the electrical insulation layer 52A and also between respective sections of the further electrical insulation layer 52B of the side wall spacer 36A. However, an upper section of the emitter metal contact 54 is arranged only between respective sections of the electrical insulation layer 52A and not between respective sections of the further electrical insulation layer 52B. In addition, the emitter metal contact 54 is arranged between respective thinned sections of the electrical insulation layer 52A, thus enabling a self-aligning contact concept. Fig. Figure 6 shows that the side wall spacer 36A comprises two electrical insulation layers 52A and 52B; it should be noted that in other examples the side wall spacer 36A may comprise a layer arrangement with more than two electrical insulation layers or only one electrical insulation layer.

[0045] With reference to Fig. Section 7 now describes an exemplary diagram of the manufacturing process. The diagram begins with operation S10 of manufacturing a structure, wherein the structure comprises: a collector formed in a substrate, a base arranged above the collector, an emitter arranged above the base, a sidewall spacer extending on a sidewall of the emitter, a first layer, wherein a first section of the first layer is arranged on the sidewall spacer such that the sidewall spacer is located in a lateral direction between the emitter and the first layer, with an outer sidewall of the first section of the first layer exposed, wherein the first layer directly contacts the base in a vertical and lateral direction, and wherein the structure further comprises a conductive layer extending in a lateral direction.wherein a second section of the first layer is arranged in the lateral direction between the base and the conductive layer. The structure can be, for example, manufactured according to the processes described with reference to the , Fig. described in 1-1 to 1-18, are manufactured, but are not limited to them.

[0046] After the structure is fabricated, at least the second section of the first layer is removed to create a space between the base and the conductive layer, see procedure S20. The removal of the first layer and the resulting structure can be carried out, for example, according to the Fig. 1-19 and the corresponding description, but is not limited to that.

[0047] Process S30 involves depositing semiconductor material in the space to connect the base to the conductive layer. Process S30 and the resulting structure can be, for example, according to Fig.21 and the corresponding description, but are not limited to that.

[0048] A new concept for fabricating a vertical RF bipolar transistor has been described. As outlined above, this concept enables vertical RF bipolar transistors to operate at very high or extreme RF frequencies. Furthermore, the new concepts allow the vertical RF bipolar transistors to exhibit high-quality electrical performance with low parasitic effects and low power loss. The process can be easily integrated into a BiCMOS process.

[0049] In addition to the examples above, the following examples of the concept described herein are presented.

[0050] Example 1 is a method for manufacturing a vertical RF bipolar transistor, wherein the method comprises: Creating a structure, wherein the structure has: a collector (16A) formed in a substrate (10), a base (34) which is arranged above the collector (16A), an emitter (38A) arranged above the base (34), a side wall spacer (36A) extending on a side wall of the emitter (38A), a first layer (30A), wherein a first section of the first layer (30A) is arranged on the side wall spacer (36A) such that the side wall spacer (36A) is located in a lateral direction between the emitter (38A) and the first layer (30A), and wherein an outer side wall of the first section of the first layer (30A) is exposed, wherein the first layer (30A) directly touches the base (34) in a vertical direction and in the lateral direction, a conductive layer (24) extending in the lateral direction, wherein a second section of the first layer (30A) is arranged in the lateral direction between the base (34) and the conductive layer (24), After the structure has been constructed, at least the second section of the first layer (30A) is removed to form a space (46) between the base (34) and the conductive layer (24), and Applying semiconductor material to the space (46) to connect the base (34) to the conductive layer (24).

[0051] Example 2 is the method according to Example 1, wherein the side wall spacer (36A) is an arrangement of several layers (52A, 52B).

[0052] Example 3 is the method according to Example 1 or 2, wherein the application of semiconductor material comprises the growth of semiconductor material in the space (46) and wherein, during the growth of semiconductor material in the space (46), further semiconductor material is grown on the conductive layer (24) to increase the thickness of the conductive layer (24).

[0053] Example 4 is the method according to one of the preceding examples, wherein the application of semiconductor material in the space (46) comprises the epitaxial growth of crystalline semiconductor material in the space (46).

[0054] Example 5 is the method according to Example 4, wherein the epitaxial growth of crystalline semiconductor material in space (46) at least partially features the growth of monocrystalline semiconductor in space (46).

[0055] Example 6 is the method according to one of the preceding examples, wherein the side wall spacer (36A) is in direct contact with the base (34).

[0056] Example 7 is the method according to one of the preceding examples, wherein the base (34) extends in a vertical direction between a lower base plane and an upper base plane, and wherein a lower end of the first layer (30A) lies in the vertical direction between the lower base plane and the upper base plane.

[0057] Example 8 is the method according to one of the preceding examples, wherein the first layer (30A) directly contacts the conductive layer (24) in the lateral direction.

[0058] Example 9 is the method according to one of the preceding examples, which further comprises generating a mask (48) covering the emitter (38A), the sidewall spacer (36A) and a section of the conductive layer (24), and structuring the conductive layer (24) using the mask (48) after depositing semiconductor material in the space (46).

[0059] Example 10 is the procedure according to one of the preceding examples, wherein the production of the structure exhibits: Generating a stack of layers on the substrate (10), wherein the stack of layers comprises a first electrical insulation layer (22), the conductive layer (24) and a second electrical insulation layer (26), Forming a cavity by removing a section of the second electrical insulation layer (26) and a section of the conductive layer (24) in a cavity area, wherein the conductive layer (24) remains outside the cavity area, and Forming the first layer (30A) on a side wall of the cavity, wherein the first layer (30A) defines a first window and wherein the first layer (30A) extends on a side wall of the conductive layer (24) and wherein the first layer (30A) directly contacts a surface of the first electrical insulation layer (22).

[0060] Example 11 is the method according to Example 10, wherein the first layer (30A) directly contacts the surface of the first electrical insulation layer (22) in a vertical direction.

[0061] Example 12 is the method according to Example 11, wherein the first layer (30A) comprises material that is different from a material of the first electrical insulation layer (22), and wherein the method further comprises etching the first electrical insulation layer (22) to partially expose a surface of the second section of the first layer (30A).

[0062] Example 13 is the procedure according to Example 12, further comprising: Etching of the first electrical insulating layer (22) in an area of ​​the first window and partially under the first layer (30A) to form a gap (32) under the first layer (30A), and Growth of the base (34) in the first window and in the gap (32).

[0063] Example 14 is the method according to one of Examples 12 or 13, further comprising: doping the collector (16A) through the first window prior to etching the first electrical insulating layer (22).

[0064] Example 15 is the method according to one of Examples 12 to 14, which further includes forming the sidewall spacer (36A) on the first layer (30A) to define an emitter region, and Formation of the emitter (38A) in the emitter area.

[0065] Example 16 is the procedure according to one of the preceding examples, wherein the removal of the first layer (30A) comprises the complete removal of the first layer (30A).

[0066] Example 17 is the method according to one of the preceding examples, wherein the first layer (30A) has a thickness in the lateral direction of less than 100 nm.

[0067] Example 18 is the method according to one of the preceding examples, wherein the structure is arranged in a shallow trench, wherein the collector (16A) is surrounded by a shallow trench insulation material (14).

[0068] Example 19 is a vertical RF bipolar transistor that exhibits: a substrate (10) having a first main surface, a collector (16A) which is arranged in the substrate (10), a base (34) which is arranged above the collector (16A), an emitter (38A) arranged above the base (34), a sidewall spacer (36A) arranged laterally to the emitter (38A), an insulating layer (22A) arranged over the first main surface of the substrate (10), a base connection (24A), wherein the base connection (24A) extends in a lateral direction on the insulation layer (22A), a conductive interface region (46A) wherein the conductive interface region (46A) electrically connects the base connection (24A) to the base (34) wherein the conductive interface region (46A) comprises monocrystalline semiconductor material, wherein the base (34) and the conductive interface region (46A) overlap in a top view and wherein the conductive interface region (46A) is not in direct contact with an upper surface of the base (34).

[0069] Example 20 is the vertical RF bipolar transistor according to Example 19, wherein the monocrystalline semiconductor material of the conductive interface region (46A) is arranged in a top view within a collector region (16).

[0070] Example 21 is the vertical RF bipolar transistor according to Example 19, wherein a dimension of the collector (16A) in a lateral direction is smaller than a dimension of the base (34) in the lateral direction.

[0071] Example 22 is the vertical RF bipolar transistor according to one of Examples 19 to 21, wherein an outer boundary of at least one section of the sidewall spacer (36A) is closer in a lateral direction to a central axis of the vertical RF bipolar transistor than an outer boundary of the base (34).

[0072] Example 23 is the vertical RF bipolar transistor according to one of Examples 19 to 22, wherein the conductive interface region (46A) is arranged in a lateral direction closer to a central axis of the vertical RF bipolar transistor than the insulating layer (22A).

[0073] Example 24 is the vertical RF bipolar transistor according to one of Examples 19 to 23, wherein the conductive interface region (46A) is in direct contact with an outer surface of the sidewall spacer (36A).

[0074] Example 25 is the vertical RF bipolar transistor according to one of Examples 19 to 24, wherein the conductive interface region (46A) comprises monocrystalline and polycrystalline material.

[0075] Example 26 is the vertical RF bipolar transistor according to one of Examples 19 to 25, wherein the interface region (46A) is not in direct contact with the collector (16A).

[0076] Example 27 is the vertical RF bipolar transistor according to one of Examples 19 to 26, wherein the sidewall spacer (36A) has a plurality of electrical insulating layers (52A, 52B) wherein a thickness of at least one of the electrical insulating layers (52A, 52B) decreases in a vertical direction away from the substrate (10).

[0077] Example 28 is a semiconductor device comprising a vertical RF bipolar transistor according to one of Examples 19 to 27.

[0078] Although specific examples have been illustrated and described here, the person skilled in the art will recognize that a variety of alternative and / or equivalent implementations can replace the specific examples shown and described.

[0079] It should be noted that the methods and devices, including their preferred embodiments, as set forth in this document, can be used alone or in combination with the other methods and devices disclosed herein. Furthermore, the features set forth in connection with a device are also applicable to a corresponding method and vice versa. Moreover, all aspects of the methods and devices set forth in this document can be combined in any way. In particular, the features of the claims can be combined with one another in any manner.

[0080] It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems.

Claims

[1] Method for manufacturing a vertical RF bipolar transistor, wherein the method comprises: Creating a structure, wherein the structure has: a collector (16A) formed in a substrate (10), a base (34) which is arranged above the collector (16A), an emitter (38A) arranged above the base (34), a side wall spacer (36A) extending on a side wall of the emitter (38A), a first layer (30A), wherein a first section of the first layer (30A) is arranged on the side wall spacer (36A) such that the side wall spacer (36A) is located in a lateral direction between the emitter (38A) and the first layer (30A), and wherein an outer side wall of the first section of the first layer (30A) is exposed, wherein the first layer (30A) directly touches the base (34) in a vertical direction and in the lateral direction, a conductive layer (24) extending in the lateral direction, wherein a second section of the first layer (30A) is arranged in the lateral direction between the base (34) and the conductive layer (24), After the structure has been constructed, at least the second section of the first layer (30A) is removed to form a space (46) between the base (34) and the conductive layer (24), and Applying semiconductor material to the space (46) to connect the base (34) to the conductive layer (24). [2] Method according to claim 1, wherein the side wall spacer (36A) is an arrangement of several layers (52A, 52B). [3] Method according to claim 1 or 2, wherein the application of semiconductor material comprises growing semiconductor material in the space (46) and wherein, during the growth of semiconductor material in the space (46), further semiconductor material is grown on the conductive layer (24) to increase the thickness of the conductive layer (24). [4] Method according to any of the preceding claims, wherein the application of semiconductor material in the space (46) comprises an epitaxial growth of crystalline semiconductor material in the space (46). [5] Method according to claim 4, wherein the epitaxial growth of crystalline semiconductor material in the space (46) at least partially comprises a growth of monocrystalline semiconductor in the space (46). [6] Method according to one of the preceding claims, wherein the side wall spacer (36A) is in direct contact with the base (34). [7] Method according to any of the preceding claims, wherein the base (34) extends in the vertical direction between a lower base plane and an upper base plane and wherein a lower end of the first layer (30A) lies in the vertical direction between the lower base plane and the upper base plane. [8] Method according to any of the preceding claims, wherein the first layer (30A) directly contacts the conductive layer (24) in the lateral direction. [9] Method according to any of the preceding claims, further comprising generating a mask (48) covering the emitter (38A), the sidewall spacer (36A) and a section of the conductive layer (24), and structuring the conductive layer (24) using the mask (48) after depositing semiconductor material in the space (46). [10] A method according to any of the preceding claims, wherein the production of the structure comprises: Generating a stack of layers on the substrate (10), wherein the stack of layers comprises a first electrical insulation layer (22), the conductive layer (24) and a second electrical insulation layer (26), Forming a cavity by removing a section of the second electrical insulation layer (26) and a section of the conductive layer (24) in a cavity area, wherein the conductive layer (24) remains outside the cavity area, and Forming the first layer (30A) on a side wall of the cavity, wherein the first layer (30A) defines a first window and wherein the first layer (30A) extends on a side wall of the conductive layer (24) and wherein the first layer (30A) directly contacts a surface of the first electrical insulation layer (22). [11] Method according to claim 10, wherein the first layer (30A) directly contacts the surface of the first electrical insulation layer (22) in the vertical direction. [12] Method according to claim 11, wherein the first layer (30A) comprises material that differs from a material of the first electrical insulation layer (22), wherein the method further comprises etching the first electrical insulation layer (22) to partially expose a surface of the second section of the first layer (30A). [13] Method according to claim 12, further comprising: Etching of the first electrical insulating layer (22) in an area of ​​the first window and partially under the first layer (30A) to form a gap (32) under the first layer (30A), and Growth of the base (34) in the first window and in the gap (32). [14] Method according to one of claims 12 or 13, further comprising: Doping of the collector (16A) via the first window prior to etching the first electrical insulation layer (22). [15] Method according to any one of claims 12 to 14, further comprising forming the side wall spacer (36A) on the first layer (30A) to define an emitter region, and forming the emitter (38A) in the emitter region. [16] Method according to any of the preceding claims, wherein the removal of the first layer (30A) comprises a complete removal of the first layer (30A). [17] Method according to any of the preceding claims, wherein the first layer (30A) has a thickness in the lateral direction of less than 100 nm. [18] Method according to one of the preceding claims, wherein the structure is arranged in a shallow trench, wherein the collector (16A) is surrounded by a shallow trench insulation material (14). [19] Vertical RF bipolar transistor, which features: a substrate (10) having a first main surface, a collector (16A) which is arranged in the substrate (10), a base (34) which is arranged above the collector (16A), an emitter (38A) arranged above the base (34), a side wall spacer (36A) which is arranged laterally to the emitter (38A), an insulating layer (22A) arranged over the first main surface of the substrate (10), a base connection (24A), wherein the base connection (24A) extends in a lateral direction on the insulation layer (22A), a conductive interface region (46A), wherein the conductive interface region (46A) electrically connects the base connection (24A) to the base (34), wherein the conductive interface region (46A) comprises monocrystalline semiconductor material, wherein the base (34) and the conductive interface region (46A) overlap in a top view and wherein the conductive interface region (46A) is not in direct contact with an upper surface of the base (34). [20] Vertical RF bipolar transistor according to claim 19, wherein the monocrystalline semiconductor material of the conductive interface region (46A) is arranged in the top view within a collector region (16). [21] Vertical RF bipolar transistor according to claim 19, wherein a dimension of the collector (16A) in a lateral direction is smaller than a dimension of the base (34) in the lateral direction. [22] Vertical RF bipolar transistor according to one of claims 19 to 21, wherein an outer boundary of at least one section of the side wall spacer (36A) is closer in a lateral direction to a central axis of the vertical RF bipolar transistor than an outer boundary of the base (34). [23] Vertical RF bipolar transistor according to one of claims 19 to 22, wherein the conductive interface region (46A) is arranged in a lateral direction closer to a central axis of the vertical RF bipolar transistor than the insulating layer (22A). [24] Vertical RF bipolar transistor according to one of claims 19 to 23, wherein the conductive interface area (46A) is in direct contact with an outer surface of the side wall spacer (36A). [25] Vertical RF bipolar transistor according to any one of claims 19 to 24, wherein the conductive interface region (46A) comprises monocrystalline material and polycrystalline material. [26] Vertical RF bipolar transistor according to one of claims 19 to 25, wherein the interface area (46A) is not in direct contact with the collector (16A). [27] Vertical RF bipolar transistor according to any one of claims 19 to 26, wherein the side wall spacer (36A) has a plurality of electrical insulating layers (52A, 52B), wherein the thickness of at least one of the electrical insulating layers (52A, 52B) decreases in a vertical direction away from the substrate (10). [28] Semiconductor device comprising a vertical RF bipolar transistor according to any one of claims 19 to 27.

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