Power control circuit for managing power delivered to a load based on a control signal and a current sensor signal

Abstract

A power control circuit includes an input terminal, an output terminal, and a current sensor. It is configured to generate a power signal corresponding to an electrical signal delivered from a power source to a load. The power control circuit is configured to receive a control signal from a controller via the input terminal. This control signal consists of a sequence of control signal pulses occurring at a control signal frequency. Based on this power signal, the sequence of control signal pulses, and the control signal frequency, the power control circuit generates an output signal. This output signal is then provided via the output terminal to control a gate driver circuit, which manages the power signal delivered from the power source to the load.

Description

TECHNICAL FIELDThis disclosure relates to circuits for controlling power delivered to a load.BACKGROUNDDriver circuits are often used to control a voltage, current, or power across a load. For example, a set of semiconductor devices may be part of one or more circuits that provide an electrical signal to a load. The set of semiconductor devices may be part of power converters, power supply devices, bypass circuits, or other types of circuits. Gate driver circuits may, in some cases, control the set of semiconductor devices by providing electrical signals to respective gate terminals of the set of semiconductor devices. One or more circuits may provide control signals to cause the gate driver circuits to control the set of semiconductor devices.SUMMARYGenerally, this disclosure is directed to apparatuses, systems, and techniques for managing power delivered to a load based on a power signal generated by a current sensor. For example, a power control circuit may include a current sensor that generates a power signal indicative of an amount of power delivered from a power source to a load. The power signal may indicate one or both of a current supplied to the load and a voltage supplied to the load. The power control circuit may receive a control signal from the controller. In some cases, the power control circuit may control the power output to the load based on the control signal and the power signal generated by the current sensor.In some examples, one or more power transistors may be connected to a node between the power source and the load. When the one or more transistors are turned on, at least a portion of the current output by the power source may flow through the one or more power transistors without flowing to the load. When the one or more transistors are off, current may flow from the power source to the load without at least a portion of the current flowing through the one or more power transistors. The power control circuit manages the power delivered to the load by controlling the one or more power transistors. For example, the power control circuit may lower at least a portion of the power away from the load by turning on the one or more power transistors and allow power to flow to the load by turning off the one or more power transistors.The techniques of this disclosure may provide one or more advantages. For example, the power control circuit may manage the power output to the load based on a modulated control signal received from the controller and the power signal generated by the current sensor. The power control circuit may more efficiently control the power delivered to the load compared to systems that use mixed signal control to control the power delivered to a load. That is, using a power control circuit to manage the power output to a load can eliminate a need for control to include mixing circuits for processing the power signal generated by the current sensor.In some examples, a power control circuit includes an input terminal, an output terminal, and a current sensor configured to sense a power signal output from a power source to a load. The power control circuit is configured to receive from a controller, via the input terminal, a control signal comprising a sequence of control signal pulses occurring at a control signal frequency and to generate an output signal based on the power signal, the sequence of control signal pulses, and the control signal frequency. The power control circuit is also configured to provide the output signal via the output terminal to control a gate driver circuit to manage the power signal output from the power source to the load.In some examples, a method includes sensing, by a current sensor of a power control circuit, a power signal output from a power source to a load and receiving, by a power control circuit, a control signal from a controller via an input terminal of the power control circuit, the control signal comprising a sequence of control signal pulses occurring at a control signal frequency. The method also includes generating, by the power control circuit, an output signal based on the power signal, the sequence of control signal pulses, and the control signal frequency; and supplying, by the power control circuit, the output signal via an output terminal to control a gate driver circuit to manage the power signal output from the power source to the load.In some examples, a system includes a controller, a gate driver circuit, and a power control circuit. The power control circuit includes an input terminal, an output terminal, and a current sensor configured to detect a power signal output from a power source to a load. The power control circuit is configured to receive from the controller, via the input terminal, a control signal comprising a sequence of control signal pulses occurring at a control signal frequency, to generate an output signal based on the power signal, the sequence of control signal pulses, and the control signal frequency, and to provide, via the output terminal, the output signal to control the gate driver circuit to manage the power signal output from the power source to the load.The summary is intended to provide an overview of the subject matter described in this disclosure. It is not intended to provide an exclusive or exhaustive explanation of the systems, apparatuses, and methods described in detail in the accompanying drawings and the following description. Further details of one or more examples of this disclosure are set forth in the accompanying drawings and the following description. Other features, objects and advantages will be apparent from the description and drawings and from the claims.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is a block diagram illustrating a system for controlling power delivered to a load in accordance with this disclosure. FIG. 2 is a circuit diagram illustrating a system including a power control circuit for controlling power delivered from a power source to a load, in accordance with this disclosure. FIG. 3 is a circuit diagram illustrating an exemplary configuration of a power control circuit according to this disclosure. FIG. 4 is a flow diagram illustrating an example operation for using a power control circuit to control power to a load based on a control signal and a power signal, in accordance with one or more techniques of this disclosure.DETAILED DESCRIPTIONFIG. 1 is a block diagram illustrating a system 100 for controlling power delivered to a load in accordance with this disclosure. As seen in FIG. 1, the system 100 includes a controller 110 including a control circuit 111, a processing circuit 112, and a memory 114. The system 100 also includes a power control circuit 120 that includes an input terminal 122, an output terminal 124, and a current sensor 126. The system 100 also includes a power source 132, a load 134, a gate driver circuit 136, and a power stage 137 that includes one or more power transistors 138. The system 100 also includes a node 142 connected to one or more power transistors 138, and a node 144 connected to the load 134.The controller 110 may include a control circuit 111. The control circuit 111 may be configured to control the power control circuit 120 to manage the power delivered to the load 134 by controlling one or more power transistors 138, in some examples. In some examples, the control circuit 111 may include an analog-to-digital (ADC) converter, other types of power converters, a physical processing unit (PPU), a central processing unit (CPU), a timing circuit, or any combination thereof. In some examples, the control circuit 111 may represent a microcontroller unit (MCU). The control circuit 111 may receive an analog signal from the node 144, in some examples. The control circuit 111 may convert the analog signal into a digital signal for processing and output an analog signal to the power control circuit 120. In some examples, the control circuit 111 may output a modulated digital signal to the power control circuit.The control circuit 111 may include a processing circuit 112. The processing circuit 112 may include, for example, one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or equivalent discrete or integrated logic circuits, or a combination of any of the foregoing devices or circuits. Accordingly, processing circuit 112 may include any suitable structure, whether in hardware, software, firmware, or any combination thereof, to perform the functions herein ascribed to controller 110.The controller 110 may include a memory 114 in communication with the processing circuit 112. In some examples, the memory 114, in communication with the processing circuit 112, includes computer readable instructions that, when executed by the processing circuit 112, cause the system 100 to perform various functions attributed to the first system 100 herein. The memory 114 may include any volatile, non-volatile, magnetic, optical, or electrical media, such as random access memory (RAM), read only memory (ROM), non-volatile RAM (NVRAM), electrically erasable programmable ROM (EEPROM), flash memory, or any other digital media capable of storing information.The power control circuit 120 may be configured to receive a control signal from the controller 110 via the input connection 122. In some examples, the control signal may represent a modulated signal that includes a sequence of control signal pulses occurring at a control signal frequency. In some examples, the modulated signal may include a frequency, a sequence of pulses each including an amplitude, a duty cycle, or any combination thereof. In some examples, the control signal received via the input link 122 may represent an analog signal, but this is not required. In some examples, the control signal may represent a modulated digital signal. In some cases, the power control circuit 120 may control the power output to the load 134 based on the control signal received from the controller 110 without receiving other signals from the controller 110. In some cases, the power control circuit 120 may control the power output to the load 134 based on the control signal and one or more other signals received from the controller 110.In some examples, the control signal received from the controller 110 may represent a single pulse width modulation (PWM) signal driven by a timing circuit of the control circuit 111. A PWM signal may represent a signal that achieves analog results with a digital signal. For example, a PWM signal may comprise a sequence of square-wave pulses, each square-wave pulse of the sequence of square-wave pulses including an amplitude and a duration. In some examples, a PWM signal may include pulses other than square pulses, such as triangular pulses. By outputting the control signal including a single PWM signal to the power control circuit 120, the controller 110 may be configured to operate in a closed loop system where the controller 110 does not need to process an analog power signal generated by the current sensor 126.The current sensor 126 may be configured to sense a current output from the power source 132. For example, the current sensor 126 may generate a power signal indicative of a current of an electrical signal output from the power source 132, a voltage of an electrical signal output from the power source 132, a magnetic field corresponding to the electrical signal, or any combination thereof. In some examples, current sensor 126 may comprise a Hall effect sensor. A Hall-effect sensor is a type of transducer or sensor configured to detect a magnetic field. Hall effect sensors may use the principle of Hall effect, a phenomenon in which an electric voltage is generated across a conductor or semiconductor when the conductor or semiconductor is exposed to a perpendicular magnetic field and an electric current flows through the conductor or semiconductor. This means that the Hall effect may be configured to sense a magnetic field, an electric current, a voltage, or any combination thereof.Hall effect sensors can measure current indirectly by detecting a magnetic field generated by a current carrying conductor. Additionally or alternatively, Hall effect sensors may measure current by measuring the magnetic field strength near the conductor. The current sensor 126 may include an open loop Hall effect sensor and / or a closed loop Hall effect sensor. Open loop Hall effect sensors can measure current by sensing a magnetic field around a current carrying conductor. For example, an open loop Hall effect may be near a conductor carrying a current. When current flows through a conductor, it generates a magnetic field around the conductor according to Ampere's law. An open loop Hall effect sensor can detect this magnetic field. The open loop Hall sensor may convert the detected magnetic field into an electrical voltage (e.g., a Hall voltage). The Hall voltage is proportional to the current flowing through the conductor and may be determined accordingly. The output voltage of the open loop Hall sensor may be amplified and processed to obtain a measurement of current through the conductor.Additionally or alternatively, the current sensor 126 may include a closed loop Hall effect sensor. Closed loop Hall effect current sensors may be configured for current measurement and provide high accuracy and linearity. Closed loop Hall effect current sensors operate based on a feedback mechanism to maintain a constant magnetic field within the sensor. A closed loop Hall sensor may be placed around a current carrying conductor. For example, the conductor may pass through a central opening in the current sensor 126. A closed loop Hall sensor may include a magnetic field generator (e.g., a permanent magnet or a current carrying coil). This internal magnetic field can be maintained at a constant level. When current flows through the conductor, it causes an opposing magnetic field to be sensed by the closed loop Hall sensor. The Hall sensor may adjust an output voltage (e.g., a Hall voltage) to cancel an effect of the magnetic field. The Hall voltage required to maintain an internal magnetic field at a constant level is proportional to a current flowing through the conductor. The output voltage of the closed loop Hall sensor may be measured and calibrated to provide a measurement of the current.The power source 132 is configured to provide power to the load 134. In some examples, power source 132 includes a battery and a power generation circuit to generate operating power. In some examples, power source 132 is rechargeable to enable extended operation. The power source 132 may include one or more of a variety of different types of batteries, such as nickel-cadmium batteries and lithium-ion batteries. In some examples, a maximum voltage output of power source 132 is about 12 V, but this is not required. In some examples, a maximum voltage output of power source 132 is greater than 100 V (e.g., 400 V).The load 134 may define a collection of electrical components that consume power. In some examples, the load 134 includes a collection of circuit components such as resistors, inductors, capacitors, diodes, and other semiconductor elements. The load 134 may include one or more post regulator circuits. In some examples, the load 134 includes electric motors and other electrical components (e.g., dashboards, control panels, heating / cooling systems, and lights) of a vehicle. Exemplary vehicles include cars, trucks, buses, bicycles, golf cars, off-road vehicles (ATVs), snowmobiles, aircraft, and watercraft. In other examples, the load 134 includes electric motors and electrical components used in other applications.The gate driver circuit 136 may control whether each power transistor of the one or more power transistors 138 is turned on or off. To control the power supplied to the load 134, the power control circuit 120 may generate an output signal for supply to the gate driver circuit 136 to control whether each power transistor of the one or more power transistors 138 is turned on or off. For example, a duty cycle of each power transistor of the one or more power transistors 138 may determine an amount of current flowing through the power stage 137 instead of flowing through the load 134. The power control circuit 120 may control a duty cycle of each power transistor of the one or more power transistors 138 by transmitting the output signal to the gate driver circuit 136 via the output terminal 124.The power stage 137 may be configured to control power supplied from the power source 132 to the load 134. A power stage may manage the delivery of power to a load, such as a motor, an LED, or any other device that requires electrical energy to function. The power stage 137 may regulate voltage and current to ensure that the load 134 receives a correct amount of power efficiently and reliably. Power stages can be used in various electronic systems, including power supplies, motor control circuits, amplifiers, and voltage regulators. The power stage 137 may include one or more power transistors 138, in some examples.The power transistor(s) 138 may / may represent semiconductor transistor devices or other types of switches configured for power delivery. Each power transistor of the power transistor(s) 138 may include a power switch in some cases, such as, but not limited to, any type of field effect transistor (FET) including one or a combination of a metal oxide semiconductor field effect transistor (MOSFET), a bipolar transistor (BJT), an insulated gate bipolar transistor (IGBT), a junction field effect transistor (JFET), a high electron mobility transistor (HEMT), or other types of elements that use voltage or current for control. Additionally, each power transistor of the power transistor(s) 138 may include one or a combination of n-transistors, p-transistors, and other types of power transistors. In some examples, each power transistor of the power transistor(s) 138 includes vertical transistors, lateral transistors, and / or horizontal transistors. In some examples, each power transistor of the power transistor(s) 138 includes other analog devices, such as diodes and / or thyristors. In some examples, each power transistor of the power transistor(s) 138 may operate as a switch and / or operate as an analog device.In some examples, each power transistor of the power transistor(s) 138 includes three terminals: two load terminals and a control terminal. When a power transistor is a MOSFET, the power transistor may include a drain terminal, a source terminal, and at least one gate terminal, wherein the control terminal is a gate terminal. When a power transistor is a BJT switch, the control terminal may be a base terminal. Current may flow between the two load terminals of a power transistor based on the voltage at the respective control terminal. Therefore, electric current may flow through the power transistor based on control signals provided to the control terminal of the power transistor. In one example, when a voltage applied to the control terminal of the power transistor is greater than or equal to a voltage threshold, the power transistor may be activated, allowing the power transistor to conduct electricity. Further, the power transistor may be deactivated when the voltage applied to the control terminal of the power transistor is below the threshold voltage, thereby preventing the power transistor from conducting electricity. The power control circuit 120 may be configured to control each of the power transistor(s) 138 by transmitting an output signal to the gate driver circuit 136 via the output terminal 124.Each power transistor(s) 138 may include various material compounds, such as silicon, silicon carbide, gallium nitride, or any other combination of one or more semiconductor materials. In some examples, silicon carbide switches may experience lower switching power losses. Improvements in magnetics and faster switching, such as gallium nitride switches, may allow a power transistor to draw short current surges. These higher frequency devices may require control signals (e.g., voltage signals provided to the control terminal of the power transistor) to be transmitted at more precise timing, as compared to lower frequency devices.In some examples, the power transistor(s) 138 may / may include a single power transistor connected to node 142. In some examples, the power transistor(s) 138 may / may include more than one power transistor. In either case, the power transistor(s) 138 may be / may be connected to the node 142 such that when the power transistor(s) 138 are turned on, at least a portion of the current of an electrical signal output from the power source 132 may flow through the power transistor(s) 138, rather than flowing through the load 134. When the power transistor(s) 138 are turned off, current of the electrical signal output from the power source 132 may flow to the load 134 without a portion of the current flowing through the power transistor(s) 138.To generate the output signal, the power control circuit 120 may generate the output signal such that a sequence of gate control pulses for controlling the power transistor(s) 138 is included. Each gate control pulse of the sequence of gate control pulses may be configured to cause a power transistor of the power transistor(s) 138 to turn on and off according to a power transistor switching cycle. In order to provide the output signal to the gate driver circuit 136, the power control circuit 120 is configured to provide the output signal to the gate driver circuit 136 such that the gate driver circuit 136 controls a gate terminal of the power transistor(s) 138 such that the power transistor(s) 138 turns off and on according to the sequence of gate control pulses.In some examples, the power control circuit 120 includes a signal sum unit. The power control circuit 120 is configured to cause the sum signal unit to receive a first sum signal input based on the power signal from the current sensor 126. The power control circuit 120 is configured to cause the signal sum unit to receive a second signal sum input based on the control signal received from the controller 110 via the input connection 122. The power control circuit may generate a signal sum output based on the first signal sum input and the second signal sum input using the signal sum unit. The signal sum output may include a sum of the first signal sum input and the second signal sum input. That is, the signal sum unit may combine the control signal received from the controller 110 with the power signal received from the current sensor 126 to generate a combined signal. The power control circuit 120 may generate the output signal transmitted to the gate driver circuit 136 based on the signal sum output.The power control circuit 120 may include a signal ramp unit in some examples. The power control circuit 120 may generate, using the signal ramp unit, the second signal sum input for the signal sum unit based on the control signal received via the input connection 122. The second signal sum input may include a sequence of ramp signal pulses corresponding to the sequence of control signal pulses of the control signal occurring at the control signal frequency. That is, in some examples, the signal sum output may include a ramp signal corresponding to a sum of the second signal sum input and the power signal received from the current sensor 126.In some examples, the power control circuit 120 may include a comparator. To generate the output signal for transmission to the gate driver circuit 136 via the output connection 124, the power control circuit 120 is configured to cause the comparator to receive a first comparator input and a second comparator input. In some examples, the first comparator input is based on the control signal from the controller 110 and the power signal from the current sensor 126. In some examples, the second comparator input is based on the control signal from the controller 110. The power control circuit 120 may generate a comparator output based on the first comparator input and the second comparator input using the comparator. The comparator output may include the output signal provided to the gate driver circuit 136.The power control circuit 120 may include a first signal ramp unit and a second signal ramp unit, in some examples. In some examples, the first signal ramp unit may represent the signal ramp unit that generates the second signal sum input for the signal sum unit. To cause the comparator to receive the first comparator input based on the control signal from the controller 110 and the power signal from the current sensor 126, the power control circuit 120 is configured to generate, using the first signal ramp unit, a first sequence of ramp signal pulses corresponding to the sequence of control signal pulses occurring at the control signal frequency. The power control circuit 120 is configured to generate the first comparator input based on the first sequence of ramp signal pulses and the power signal from the current sensor 126. In order to cause the comparator to receive the second comparator input based on the control signal from the controller 110, the power control circuit 120 is configured to generate the second comparator input using the second signal ramp unit such that a second sequence of ramp signal pulses corresponding to the sequence of control signal pulses occurring at the control signal frequency is included.The control circuit 111 of the controller 110 may generate the control signal for output to the power control circuit 120 based on a feedback signal received from the node 144, in some examples. For example, the control circuit 111 may receive a feedback signal from the node 144 indicative of a current at the node 144, a voltage at the node 144, a magnetic field corresponding to an electrical signal at the node 144, or any combination thereof. That is, the system 100 may be a closed loop system. In some examples, the feedback signal may represent an analog signal. In some examples, the control signal output from the controller 110 to the power control circuit 120 may represent an analog signal, but this is not required. In some examples, the control signal output from the controller 110 to the power control circuit 120 may represent a modulated digital signal.By controlling power to the load 134 based on a single control signal received from the controller 110 and a power signal received from the current sensor 126, the power control circuit 120 may control power to the load 134 more efficiently and with fewer circuit components compared to systems that rely on control to process a control signal and a power signal. In other words, the power control circuit 120 may efficiently control the power transistor(s) 138 to decrease current, if necessary, and allow current to reach the load 134, if necessary, in a manner that does not require complex processing at the controller 110 to process the power signal from the current sensor 126 and the control signal generated by the controller 110 based on a feedback signal.FIG. 2 is a circuit diagram illustrating a system 200 including a power control circuit 220 for controlling power delivered from a power source 232 to a load 234, in accordance with this disclosure. As seen in FIG. 2, the system 200 includes a controller 210 that includes a control circuit 211, a memory 214, an output terminal 218, and input terminals 219. The control circuit 211 may include an ADC 215, a processing unit 216, and a timer circuit 217. The ADC 215, the processing unit 216, and the timer circuit 217 may be part of a processing circuit of the control circuit 211. The system 200 also includes a power control circuit 220 that includes an input terminal 222 and an output terminal 224. The system 200 includes a power source 232, a load 234, a gate driver circuit 236, a power transistor 238, an inductor 252, a diode 254, a capacitor 256, a first resistor 258, and a second resistor 259.The controller 210 may be an example of the controller 110 of FIG. 1. The control circuit 211 may be an example of the control circuit 111 of FIG. 1. The memory 214 may be an example of the memory 114 of FIG. 1. The power control circuit 220 may be an example of the power control circuit 120 of FIG. 1. The input terminal 222 may be an example of the input terminal 122 of FIG. 1. The output terminal 224 may be an example of the output terminal 124 of FIG. 1. Current sensor 226 may be an example of current sensor 126 of FIG. 1. Power source 232 may be an example of power source 132 of FIG. 1. The load 234 may be an example of the load 134 of FIG. 1. The gate driver circuit 236 may be an example of the gate driver circuit 136 of FIG. 1. The power transistor 238 may be an example of the power transistor(s) 138 of FIG. 1.The controller 210 may include a control circuit 211. The control circuit 211, in some examples, may be configured to control the power control circuit 220 to manage the power output to the load 234 by controlling the power transistor 238. The control circuit 211 may be configured to generate a control signal output via the output terminal 218 based on a feedback signal received via the input terminals 219. That is, the control circuit 211 may be part of a closed loop system for controlling the power delivered from the power source 232 to the load 234. For example, the control circuit 211 may be configured to output a control signal to the power control circuit 220 via the output terminal 218 of the controller 210 to cause the power control circuit 220 to control the gate drive circuit 236 to manage the power transistor 238. Whether the power transistor 238 is turned on or off may control an amount of power that reaches the load 234.The processing circuitry of the control circuit 211 may include, for example, one or more microprocessors, DSPs, ASICs, FPGAs, or equivalent discrete or integrated logic circuits, or a combination of any of the foregoing devices or circuits. Accordingly, the processing circuitry of the control circuit 211 may include any suitable structure, whether in hardware, software, firmware, or any combination thereof, to perform the functions herein ascribed to the controller 210.The controller 210 may include a memory 214 in communication with the processing circuit of the control circuit 211. In some examples, memory 214, in communication with the processing circuitry of control circuit 211, includes computer readable instructions that, when executed by the processing circuitry of control circuit 211, cause system 200 to perform various functions attributed to system 200 herein. The memory 214 may include any volatile, non-volatile, magnetic, optical, or electrical media, such as RAM, ROM, NVRAM, EEPROM, flash memory, or any other digital media capable of storing information.The control circuit 211 may include an ADC 215. An ADC may convert a continuous analog signal into a sequence of discrete digital values for processing by digital devices such as microcontrollers, computers, or digital signal processors. For example, an analog signal may include a voltage signal that varies continuously over time. To convert the voltage signal to a digital signal, the ADC 215 may sample the voltage signal at regular intervals. This may include taking discrete samples of the continuous analog voltage signal at specific time intervals (e.g., each second, each millisecond (ms), each microsecond (μs), or any other interval).In response to sampling values of the analog signal, ADC 215 may perform quantization. Quantization may include mapping each of the sampled analog values to a corresponding discrete digital value. These digital values may represent binary values (0s and 1s) and indicate the magnitude of the analog signal at each sampling point. The ADC 215 may then encode the quantized digital values into a binary number format, which is represented as a binary code. Exemplary coding schemes include a binary code, a gray code, and the complement of two. The final output of ADC 215 is a digital representation of the analog input signal. The digital representation of the analog input signal is digital data that can be processed, stored, or used for various purposes in digital systems.The ADC 215 may receive a feedback signal via the input terminals 219 of the controller 210. The feedback signal may represent an analog signal. In some examples, the analog signal may represent a voltage signal, but this is not required. In some examples, the analog signal may represent a current signal or another type of signal that may be indicative of power. The ADC 215 may generate a digital representation of the analog signal for output to the processing unit 216. The processing unit 216 may include a PPU and / or a CPU configured to process a digital signal output by the ADC 215. Because the digital signal output by the ADC 215 may include a digital representation of the analog feedback signal received via the input terminals 219, the processing unit 216 may generate a digital response to the feedback signal for output to the timing circuit 217.The timer circuit 217 may generate a control signal for output to the power control circuit 220 via the output terminal 218 of the controller 210 and the input terminal 222 of the power control circuit 220 based on the output from the processing unit 216. The timing circuit 217 may generate the control signal to include a PWM signal for controlling the power transistor 238. The PWM signal may include a sequence of pulses having a frequency. The PWM signal output by the timing circuit 217 may control whether the power transistor 238 is on or off, which in turn may control the power output to the load 234. For example, when the power transistor 238 is turned on, a smaller amount of power may reach the load 234, and when the power transistor 238 is turned off, a larger amount of power may reach the load 234.The power source 232 may be configured to provide power to the load 234 via the current sensor 226 of the power control circuit 220. The power control circuit 220 may receive the control signal from the timer circuit 217 via the input terminal 222 of the power control circuit 220. The power control circuit 220 may receive a power signal from the current sensor 226 indicative of one or more parameters of an electrical signal output from the power source 232 to the load 234. For example, the power signal may indicate a current of the electrical signal, a voltage of the electrical signal, a magnetic field associated with the electrical signal, or any combination thereof. Based on the control signal received from the controller 210 and the power signal generated by the current sensor 226, the power control circuit 220 may generate an output signal and transmit the output signal to the gate drive circuit 236 via the output terminal 224.The gate driver circuit 236 may receive the output signal from the power control circuit 220 and control the power transistor 238 based on the output signal. In some examples, the output signal received by the gate driver circuit 236 from the power control circuit 220 may include a sequence of pulses. The sequence of pulses may command the gate driver circuit 236 to turn on and off the power transistor 238 according to a sequence of switching cycles. In some examples, the sequence of switching cycles may include a sequence of turn-on cycles and a sequence of turn-off cycles nested within the sequence of turn-on cycles.When the power transistor 238 is off, electrical current 241 may pass through the node 242 as electrical current 243 without a portion of the electrical current 241 passing through the power transistor 238 as electrical current 243'. This is because when the power transistor 238 is off, there may not be a current path across the power transistor 238, so that electrical current cannot cross the power transistor 238 when the power transistor 238 is off. When the power transistor 238 is turned on, the electrical current 241 at node 242 may split into electrical current 243 and electrical current 243'. Electrical current 243 may flow to load 234 via diode 254 and electrical current 243' may flow through power transistor 238 without flowing to load 234. This means that when the power transistor 238 is turned on, a portion of the electric current 241 may "sink" away from the load 234 as electric current 243' through the power transistor 238.The inductor 252 is an electrical circuit component that resists a change in a magnitude of the electric current flowing through the inductor 252. In some examples, the inductor 252 is defined by an electrically conductive wire wound into a coil. When electric current flows through the coil of the inductor 252, a magnetic field is generated in the coil and the magnetic field induces a voltage across the inductor. The inductor 252 defines an inductance value, and the inductance value is the ratio of the voltage across the inductor 252 to the rate of change of the current flowing through the inductor 252.The diode 254 may be a semiconductor device that functions as a diode. In the field of circuit electronics, diodes include semiconductor components that allow current to flow in a first direction (e.g., "forward direction") across the diode and prevent current from flowing in a second direction (e.g., "reverse direction") across the diode. A diode may include an anode and a cathode, and current may be capable of passing through the diode in the forward direction from the anode to the cathode. However, current may not be able to pass through the diode in the reverse direction from the cathode to the anode. For example, current may flow in the forward direction from node 242 to node 244 via diode 254.Capacitor 256 is an electrical circuit component configured to store electrical potential energy. Capacitor 256 may assume a "charged" state, in some examples, where capacitor 256 stores a maximum amount of potential electrical energy. Additionally, capacitor 256 may assume a "discharged" state, with capacitor 256 storing little or no potential electrical energy. Capacitor 256 may also transition between the charged state and the discharged state. When capacitor 256 charges, a current flows across capacitor 256, increasing the potential electrical energy stored by capacitor 256. When capacitor 256 discharges, the electrical potential energy stored by capacitor 256 is released, causing capacitor 256 to emit an electrical current.The first resistor 258 and the second resistor 259 may be connected in series with the node 244 in some examples. In some examples, a portion of the electrical current 243 output from the node 242 may flow as electrical current 245 to the load 234 via the node 244. In some examples, a portion of the electrical current 243 output from the node 242 may flow as electrical current 245' across the first resistor 258 and the second resistor 259. In some examples, a magnitude of the electric current 245 is greater than the electric current 245'. In some examples, the first resistor 258 and / or the second resistor 259 may represent a sensor for generating a feedback signal indicative of one or more parameters at the node 244 (e.g., a voltage at the node 244, a current at the node 244, or another parameter of an electrical signal at the node 244). For example, a feedback signal may flow from the second resistor 259 to the controller 210 via the input terminals 219 of the controller 210.The system 200 may include a closed loop feedback system. For example, the control circuit 211 may generate a control signal for output to the power control circuit 220 based on a feedback signal received via the input terminals 219 of the controller 210. The power control circuit 220 may generate an output signal to control the gate driver circuit 236, to control the power transistor 238 to manage the power supplied from the power source 232 to the load 234. That is, the power control circuit 220 may control the electrical signal at the node 244 based on the control signal received from the controller 210. The controller 210 may receive the feedback signal indicative of one or more parameters of the electrical signal at the node 244 and generate the control signal based on the feedback signal, thereby completing the closed loop system.FIG. 3 is a circuit diagram illustrating an exemplary configuration of a power control circuit 320 according to this disclosure. As seen in FIG. 3, the power control circuit 320 includes an input terminal 322, an output terminal 324, a current sensor 326, a signal sum unit 362, a comparator 366, a first signal ramp unit 368, a second signal ramp unit 369, a first voltage unit 372, a second voltage unit 374, a blank unit 376, a first sample and hold (S&H) circuit 382, and a second S&H circuit 384. The power control circuit 320 may be an example of the power control circuit 120 of FIG. 1. The input terminal 322 may be an example of the input terminal 122 of FIG. 1. The output terminal 324 may be an example of the output terminal 124 of FIG. 1. Current sensor 326 may be an example of current sensor 126 of FIG. 1.The power control circuit 320 may receive a control signal from the controller 110 via the input terminal 322. In some examples, the control signal may represent a PWM signal. The control signal may represent an analog signal in some examples, but this is not required. In some examples, when the control signal is a PWM signal, the control signal may represent a modulated digital signal. The current sensor 326 of the power control circuit 320 may generate a power signal indicative of one or more parameters of an electrical signal (e.g., the electrical signal output from the power source 132). For example, the power signal may be indicative of a current, voltage, and / or other parameter of the electrical signal.The signal sum unit 362 may receive a first signal sum input 361 based on the power signal from the current sensor 326, and a second signal sum input 361' based on the control signal received from the controller 110 via the input connection 322, in some examples. In some examples, the signal sum unit 362 may generate a signal sum output 363 based on the first signal sum input 361 and the second signal sum input 361'. The signal sum output 363 may represent a sum of the first signal sum input 361 and the second signal sum input 361'.In some examples, the signal sum unit 362 may represent an analog signal sum unit and the first signal sum input 361 and the second signal sum input 361' may represent analog signals. An analog signal summing unit may include circuitry that combines multiple analog signals into a single output signal. The signal summation unit 362 may sum the voltages of input signals to generate a resulting output voltage. For example, the signal sum unit 362 may take the first signal sum input 361 and the second signal sum input 361' as inputs. In some examples, each input signal may flow to a respective input resistance of the signal summation unit 362. The values of the input resistors may determine a weight of each input signal in the final output. In a sum signal unit in which input signals have a same weight, the input resistors have the same resistance value, but the resistance values may vary for different weighting schemes.In some examples, the signal summing unit 362 may include a summing amplifier for performing an addition operation. A summing amplifier may employ an operational amplifier in an inverting configuration. Input resistors of the signal summing unit 362 may be connected to an inverting terminal of the summing amplifier. The inverting terminal may be connected to a feedback resistor that provides negative feedback in some examples. An output of the summing amplifier may be connected to the inverting terminal through the feedback resistor. The summing amplifier of the signal summing unit 362 may transmit the signal sum output 363 via an output terminal of the summing amplifier. The signal sum output 363 may represent an algebraic sum of the input voltages of the first signal sum input 361 and the second signal sum input 361' weighted by resistance values of the input resistors of the signal sum unit 362.The comparator 366 may include electronic circuitry that compares the first comparator input 365 and the second comparator input 365' and generates a comparator output 367 based on the comparison. An exemplary function of comparator 366 is to determine which of first comparator input 365 and second comparator input 365' is larger. Another exemplary function of the comparator 366 is to determine whether one of the first comparator input 365 and the second comparator input 365' is higher or lower than a reference voltage. Comparator 366 may include an inverting input (-) and a non-inverting input (+). As seen in FIG. 3, the first comparator input 365 flows to the noninverting input and the second comparator input 365' flows to the inverting input.In some examples, the inverting input is a terminal that receives an input signal for comparison to another value. In some examples, the non-inverting input is a terminal that receives an input signal for comparison to another value or reference voltage with which the input to the inverting input is compared. When a voltage at the noninverting input (+) (e.g., a voltage of the first comparator input 365) of the comparator 366 is greater than the voltage at the inverting input (-) (e.g., a voltage of the second comparator input 365') of the comparator 366, an output from the comparator 366 may be a high voltage. When a voltage at the inverting input (-) (e.g., a voltage of the second comparator input 365') of the comparator 366 is greater than a voltage at the noninverting input (+) (e.g., a voltage of the first comparator input 365) of the comparator 366, an output from the comparator 366 may be a low voltage.The power control circuit 320 may cause the comparator 366 to receive the first comparator input 365 based on a control signal received from the controller 110 via the input connection 122 and a power signal received from the current sensor 126. In some examples, the first comparator input 365 is substantially equivalent to the signal sum output 363. Because the first comparator input 365 is based on both the control signal from the controller 110 and the power signal from the current sensor 326, the comparator 366 may be configured to generate an output based on both the control signal from the controller 110 and the power signal from the current sensor 326. The power control circuit 320 may cause the comparator 366 to receive the second comparator input 365' based on the control signal received from the controller 110 via the input link 322. The comparator 366 may generate a comparator output 367 based on the first comparator input 365 and the second comparator input 365'. The comparator output may represent the output signal provided to the gate driver circuit 136 via the output terminal 324.In some examples, in response to the first comparator input 365 being larger than the second comparator input 365', the comparator 366 generates the comparator output 367 to include a high voltage that causes the gate driver circuit 136 to turn on the power transistor(s) 138. In some examples, in response to the first comparator input 365 being no greater than the second comparator input 365', the comparator 366 generates the comparator output 367 to include a low voltage that causes the gate driver circuit 136 to turn on the power transistor(s) 138. As the first comparator input 365 is based at least in part on the power signal from the current sensor 326, this means that the comparator 366 may turn on the power transistor(s) 138 in response to a current across the current sensor 326 being high and turn off the power transistor(s) 138 in response to a current across the current sensor 326 being low.For example, in response to a current across current sensor 326 being high, the closed loop system including power control circuit 320 may turn on power transistor(s) 138 to decrease a portion of the current output from power source 132 across power transistor(s) 138. In response to a current across current sensor 326 being low, the closed loop system including power control circuit 320 may turn off power transistor(s) 138 such that the current output from power source 132 reaches load 134 without a portion of the current across power transistor(s) 138 sinking. The comparator 366 may generate the comparator output 367 to control whether the gate driver circuit 136 turns on or off the power transistor(s) 138.The power control circuit 320 may process the control signal received from the controller 110 via the input connection 322 for input to the signal sum unit 362 and the comparator 366. In some examples, the control signal received from the controller 110 via the input connection 322 may represent a modulated digital signal comprising a sequence of square waves at a pulse frequency. The first voltage unit 372 and the second voltage unit 374 may process the control signal received from the controller 110 via the input link 322. In some examples, the first voltage unit 372 may generate an output for delivery to the first signal ramp unit 368 and the second signal ramp unit 369. In some examples, the second voltage unit 374 may generate an output for delivery to the first S&H circuit 382.In some examples, the first signal ramp unit 368 may generate a first sequence of ramp pulses based on the control signal received from the controller 110 via the input link 322. In some examples, to cause the comparator 366 to receive the first comparator input 365 based on the control signal from the controller 110 and the power signal from the current sensor 326, the power control circuit 320 is configured to generate, using the first signal ramp unit 368, a first sequence of ramp signal pulses corresponding to a sequence of control signal pulses occurring at a control signal frequency. For example, the control signal may comprise the sequence of control signal pulses occurring at the control signal frequency. The first signal ramp unit 368 may generate the second signal sum input 361' to include the first sequence of ramp signal pulses such that the signal sum unit 362 generates the signal sum output 363 based on the first signal sum input 361 and the second signal sum input 361'.To generate a ramp signal from a sequence of square waves, the first signal ramp unit 368 may use a circuit that integrates the square wave input to generate a linear voltage ramp. This integration process may include accumulating a charge over time, resulting in a ramp voltage. For example, a square wave may alternate between two voltage levels (e.g., a high voltage and a low voltage) at a pulse frequency. The first signal ramp unit 368 may include an integrator comprising an operational amplifier and a capacitor. The integrator may generate an output comprising a voltage proportional to an integral of an input voltage over time. When the input to the first signal ramp unit 368 is a high voltage (e.g., during each of the sequence of square-wave pulses), the integrator of the first signal ramp unit 368 may charge the capacitor at a constant rate. This may result in a linear increase in the voltage across the capacitor. When the input to the first signal ramp unit 368 is a low voltage (e.g., between successive square-wave pulses of the sequence of square-wave pulses), the capacitor may discharge through a resistor, causing the voltage to decrease.The second signal ramp unit 369 may be substantially the same as the first signal ramp unit 368 except that the second signal ramp unit 369 generates an output for delivery to the first S&H circuit 382, whereas the first signal ramp unit 368 generates an output for delivery to the signal sum unit 362. In some examples, to cause the comparator 366 to receive a second comparator input based on the control signal from the controller 110, the power control circuit 320 is configured to generate an output using the second signal ramp unit 369 such that a second sequence of ramp signal pulses corresponding to the sequence of control signal pulses of the control signal occurring at the control signal frequency is included. In some examples, the second sequence of ramp signal pulses output from the second signal ramp unit 369 may be further processed by the first S&H circuit 382 and the second S&H circuit 384 to generate the second comparator input 365'.The first S&H circuit 382 may capture and store a signal at a specific time, making it available as a constant voltage for further processing or conversion. For example, the first S&H circuit 382 may sample an incoming analog signal. A sampling switch, often controlled by a clock signal or a trigger, may be used to connect the input signal to a storage capacitor. The input signal may be connected to the capacitor during the sampling phase. The storage capacitor may charge to a voltage level of the input signal. This may allow the first S&H circuit to detect a snapshot of a voltage of the input signal at a particular time. In some examples, the first S&H circuit 382 may open a sampling switch after a sampling phase, thereby disconnecting an input signal from the storage capacitor. The first S&H circuit 382 may close a hold switch, thereby connecting the capacitor to an output of the first S&H circuit. A buffer amplifier may be placed between a storage capacitor and an output in some examples. The buffer may maintain the sensed voltage and reduce a load on the storage capacitor, thereby ensuring that the voltage remains relatively constant during the hold phase.The second S&H circuit 384 may be substantially the same as the first S&H circuit, except that the second S&H circuit 384 receives inputs from the first voltage unit 372 and the first S&H circuit 382, whereas the first S&H circuit 382 receives inputs from the second voltage unit 374 and the second signal ramp unit 369. The blank unit 376 may receive an input from the first voltage unit 372 and generate an output to the comparator 366.FIG. 4 is a flow diagram illustrating an example operation for using a power control circuit to control power to a load based on a control signal and a power signal, in accordance with one or more techniques of this disclosure. FIG. 4 is described with respect to the system 100 of FIG. 1. However, the techniques of FIG. 4 may be performed by various components of the system 100, or by additional or alternative systems.The power control circuit 120 may generate a power signal corresponding to an electrical signal provided from the power source 132 to the load 134 using the current sensor 126 ( 402). For example, the power source 132 may provide an electrical signal to the load 134, the electrical signal flowing through the current sensor 126 of the power control circuit 120. In some examples, the electrical signal includes a current and a voltage. In some examples, a magnetic field is associated with the electrical signal. It may be advantageous for the power control circuit 120 to control the power delivered to the load 134 based on the power signal generated by the current sensor 126. For example, it may be advantageous to prevent the current and / or voltage at the load 134 from exceeding or falling below a high threshold.The power control circuit 120 may receive from the controller 110 via the input terminal 122 of the power control circuit 120 a control signal comprising a sequence of control signal pulses occurring at a control signal frequency ( 404). In some examples, the sequence of control signal pulses may include a sequence of square pulses. In some examples, the control signal may represent a digital PWM signal. The control signal frequency may represent a frequency for controlling the power transistor(s) 138, in some examples. That is, the power control circuit 120 may control the power transistor(s) 138 based in part on the control signal including the sequence of control signal pulses at the control signal frequency.The power control circuit 120 may generate an output signal based on the power signal, the sequence of control signal pulses, and the control signal frequency ( 406). For example, the power control circuit 120 may generate the output signal based on the power signal and the control signal. For example, the control signal may include a frequency for controlling the power transistor(s) 138. The power signal may indicate a need to decrease power away from the load 134. For example, if the power signal indicates a higher current, it may be advantageous to control the power transistor(s) 138 to decrease current away from the load 134, and if the power signal indicates a lower current, it may be advantageous to control the power transistor(s) 138 to not decrease current away from the load 134. The power control circuit 120 may provide the output signal via the output terminal 124 of the power control circuit 120 to control the gate driver circuit 136 to manage the power signal provided from the power source 132 to the load 134 ( 408).The following numbered clause may demonstrate one or more aspects of the disclosure.Clause 1: A power control circuit includes an input terminal, an output terminal, and a current sensor configured to generate a power signal corresponding to an electrical signal supplied from a power source to a load. The power control circuit is configured to receive from a controller, via the input terminal, a control signal comprising a sequence of control signal pulses occurring at a control signal frequency and to generate an output signal based on the power signal, the sequence of control signal pulses, and the control signal frequency. The power control circuit is configured to provide the output signal via the output terminal, to control a gate drive circuit to manage the power signal provided from the power source to the load.Clause 2: The power control circuit of Clause 1, wherein to generate the output signal, the power control circuit is configured to generate the output signal to include a sequence of gate control pulses, wherein each gate control pulse of the sequence of gate control pulses is configured to cause a power transistor to turn on and off according to a power transistor switching cycle, and wherein to provide the output signal, the power control circuit is configured to provide the output signal to the gate drive circuit such that the gate drive circuit controls a gate terminal of the power transistor such that the power transistor turns off and on according to the sequence of gate control pulses.Clause 3: The power control circuit of Clause 2, wherein the power transistor is connected to a node located between the power source and the load, such that when the power control circuit provides the output signal to the gate driver circuit to control the power transistor, the power control circuit is configured to: cause at least a portion of the power signal to flow through the power transistor in response to the power transistor being turned on; and cause the power signal to flow from the power source to the load without flowing through the power transistor in response to the power transistor being turned off.Clause 4: The power control circuit of any of Clause 1-3, wherein the power control circuit further comprises a signal sum unit, and wherein the power control circuit is further configured to: cause the signal sum unit to receive a first signal sum input based on the power signal from the current sensor; cause the signal sum unit to receive a second signal sum input based on the control signal from the input terminal; generate, using the signal sum unit, a signal sum output based on the first signal sum input and the second signal sum input, the signal sum output comprising a sum of the first signal sum input and the second signal sum input; and generate the output signal based on the signal sum output.Clause 5: The power control circuit of Clause 4, wherein the power control circuit further comprises a signal ramp unit, and wherein the power control circuit is further configured to generate, using the signal ramp unit, the second signal sum input based on the control signal from the input terminal, wherein the second signal sum input comprises a sequence of ramp signal pulses corresponding to the sequence of control signal pulses occurring at the control signal frequency.Clause 6: The power control circuit of any of Clause 1-5, wherein the power control circuit further comprises a comparator, and wherein to generate the output signal, the power control circuit is configured to: cause the comparator to receive a first comparator input based on the control signal from the controller and the power signal from the current sensor; cause the comparator to receive a second comparator input based on the control signal from the controller; and generate a comparator output based on the first comparator input and the second comparator input using the comparator, wherein the comparator output comprises the output signal provided to the gate driver circuit.Clause 7: The power control circuit of Clause 6, wherein the power control circuit further comprises a first signal ramp unit and a second signal ramp unit, wherein to cause the comparator to receive the first comparator input based on the control signal from the controller and the power signal from the current sensor, the power control circuit is configured to: generate, using the first signal ramp unit, a first sequence of ramp signal pulses corresponding to the sequence of control signal pulses occurring at the control signal frequency; and generating the first comparator input based on the first sequence of ramp signal pulses and the power signal from the current sensor, and wherein, to cause the comparator to receive the second comparator input based on the control signal from the controller, the power control circuit is configured to generate, using the second signal ramp unit, the second comparator input such that a second sequence of ramp signal pulses corresponding to the sequence of control signal pulses occurring at the control signal frequency is included.Clause 8: The power control circuit of any of Clause 1-7, wherein the control signal comprises an analog control signal, wherein by providing the output signal to the gate driver circuit to control the power signal provided from the power source to the load, the power control circuit is configured to cause the controller to receive an analog feedback signal, wherein the analog feedback signal indicates one or more parameters of the power signal provided from the power source to the load, and wherein the analog control signal is based on the analog feedback signal.Clause 9: The power control circuit of any of Clause 1-8, wherein the control signal comprises a modulated digital signal.Clause 10: The power control circuit according to any of Clause 1-9, wherein to provide the output signal for controlling the gate driver circuit to manage the power signal, the power control circuit is configured to provide the output signal to the gate driver circuit.Clause 11: The power control circuit of any of Clause 1-10, wherein to provide the output signal to control the gate driver circuit to manage the power signal, the power control circuit is configured to provide the output signal to the controller, thereby causing the controller to control the gate driver circuit to manage the power signal.Clause 12: The power control circuit of any of Clause 1-11, wherein the current sensor comprises a Hall-effect sensor configured to sense a magnetic field corresponding to a current of the power signal.Clause 13: A method includes generating, by a current sensor of a power control circuit, a power signal corresponding to an electrical signal output from a power source to a load, and receiving, by a power control circuit, a control signal from a controller via an input terminal of the power control circuit, the control signal comprising a sequence of control signal pulses occurring at a control signal frequency. The method also includes generating, by the power control circuit, an output signal based on the power signal, the sequence of control signal pulses, and the control signal frequency, and supplying, by the power control circuit, the output signal via an output terminal to control a gate driver circuit to manage the power signal output from the power source to the load.Clause 14: The method of Clause 13, wherein generating the output signal comprises generating, by the power control circuit, the output signal to include a sequence of gate control pulses, wherein each gate control pulse of the sequence of gate control pulses is configured to cause a power transistor to turn on and off according to a power transistor switching cycle, and wherein supplying the output signal comprises supplying, by the power control circuit, the output signal to the gate drive circuit such that the gate drive circuit controls a gate terminal of the power transistor such that the power transistor turns off and turns on according to the sequence of gate control pulses.Clause 15: The method of Clause 14, wherein the power transistor is connected to a node located between the power source and the load, such that when the power control circuit provides the output signal to the gate driver circuit to control the power transistor, the method comprises: causing, by the power control circuit, at least a portion of the power signal to flow through the power transistor in response to the power transistor being turned on; and causing, by the power control circuit, the power signal to flow from the power source to the load without flowing through the power transistor in response to the power transistor being turned off.Clause 16: The method of any of Clause 13-15, wherein the power control circuit further comprises a signal sum unit, and wherein the method further comprises: causing, by the power control circuit, the signal sum unit to receive a first signal sum input based on the power signal from the current sensor; causing, by the power control circuit, the signal sum unit to receive a second signal sum input based on the control signal from the input terminal; generating, by the power control circuit, a signal sum output using the signal sum unit based on the first signal sum input and the second signal sum input, the signal sum output comprising a sum of the first signal sum input and the second signal sum input; and generating, by the power control circuit, the output signal based on the signal sum output.Clause 17: The method of Clause 16, wherein the power control circuit further comprises a signal ramp unit, and wherein the method further comprises generating, by the power control circuit, the second signal sum input using the signal ramp unit based on the control signal from the input terminal, wherein the second signal sum input comprises a sequence of ramp signal pulses corresponding to the sequence of control signal pulses occurring at the control signal frequency.Clause 18: The method of any of Clause 13-17, wherein the power control circuit further comprises a comparator, and wherein generating the output signal comprises: causing, by the power control circuit, the comparator to receive a first comparator input based on the control signal from the controller and the power signal from the current sensor; causing, by the power control circuit, the comparator to receive a second comparator input based on the control signal from the controller; and generating, by the power control circuit, a comparator output using the comparator based on the first comparator input and the second comparator input, the comparator output comprising the output signal provided to the gate driver circuit.Clause 19: The method of Clause 18, wherein the power control circuit further comprises a first signal ramp unit and a second signal ramp unit, wherein causing the comparator to receive the first comparator input based on the control signal from the controller and the power signal from the current sensor comprises: generating, by the power control circuit, a first sequence of ramp signal pulses corresponding to the sequence of control signal pulses occurring at the control signal frequency using the first signal ramp unit; generating, by the power control circuit, the first comparator input based on the first sequence of ramp signal pulses and the power signal from the current sensor, and wherein causing the comparator to receive the second comparator input based on the control signal from the controller comprises generating, by the power control circuit, the second comparator input using the second signal ramp unit to include a second sequence of ramp signal pulses corresponding to the sequence of control signal pulses occurring at the control signal frequency.Clause 20: A system includes a controller, a gate driver circuit, and a power control circuit. The power control circuit includes an input terminal, an output terminal, and a current sensor configured to generate a power signal corresponding to an electrical signal supplied from a power source to a load. The power control circuit is configured to receive from the controller, via the input terminal, a control signal comprising a sequence of control signal pulses occurring at a control signal frequency, to generate an output signal based on the power signal, the sequence of control signal pulses, and the control signal frequency, and to provide, via the output terminal, the output signal to control the gate driver circuit to manage the power signal provided from the power source to the load.The techniques described in this disclosure may be implemented, at least in part, in hardware, software, firmware, or any combination thereof. For example, various aspects of the described techniques may be implemented within one or more processors, including one or more microprocessors, DSPs, ASICs, FPGAs, or any other equivalent integrated or discrete logic circuits, as well as any combinations of such components. The term "processor" or "processing circuitry" may generally refer to any of the above logic circuits alone or in combination with other logic circuits or any other equivalent circuits. A controller comprising hardware may also perform one or more of the techniques of this disclosure.Such hardware, software, and firmware may be implemented within the same device or within separate devices to support the various operations and functions described in this disclosure. In addition, any of the described units, modules, or components may be implemented together or separately as discrete, but interoperable logic devices. The depiction of various features as modules or units is intended to emphasize various functional aspects and does not necessarily imply that such modules or units must be implemented by separate hardware or software components. Rather, the functionality associated with one or more modules or units may be performed by separate hardware or software components or integrated into common or separate hardware or software components.The techniques described in this disclosure may also be embodied or encoded in a computer readable medium, such as a computer readable storage medium containing instructions. Instructions embedded or encoded in a computer readable storage medium may cause a programmable processor or other processor to perform the method, e.g., when the instructions are executed. Computer readable storage media may include RAM, ROM, programmable read only memory (PROM), erasable programmable read only memory (EPROM), EEPROM, flash memory, a hard disk, compact disk read only memory (CD-ROM), a floppy disk, a cassette, magnetic media, optical media, or other computer readable media.Various examples have been described. These and other examples are within the scope of the following claims.

Claims

A power control circuit (120, 220, 320) comprising: an input terminal (122, 219, 222, 322); an output terminal (124, 218, 224, 324); and a current sensor (126, 226, 326) configured to generate a power signal corresponding to an electrical signal provided from a power source (132, 232) to a load (134, 234), wherein the power control circuit (120, 220, 320) is configured to: receive from a controller (110, 210), via the input terminal (122, 219, 222, 322), a control signal comprising a sequence of control signal pulses occurring at a control signal frequency; generate an output signal based on the power signal, the sequence of control signal pulses, and the control signal frequency; and providing the output signal via the output terminal (124, 218, 224, 324) to control a gate driver circuit (136, 236) to manage the power signal provided from the power source (132, 232) to the load (134, 234).The power control circuit (120, 220, 320) of claim 1, wherein to generate the output signal, the power control circuit (120, 220, 320) is configured to generate the output signal such that a sequence of gate control pulses is included, wherein each gate control pulse of the sequence of gate control pulses is configured to cause a power transistor (238) to turn on and off according to a power transistor switching cycle, and wherein to provide the output signal, the power control circuit (120, 220, 320) is configured to provide the output signal to the gate driver circuit (136, 236) such that the gate driver circuit (136, 236) controls a gate terminal of the power transistor (238), so that the power transistor (238) turns off and turns on according to the sequence of gate control pulses.The power control circuit (120, 220, 320) of claim 2, wherein the power transistor (238) is connected to a node (142, 144, 242, 244) located between the power source (132, 232) and the load (134, 234), such that when the power control circuit (120, 220, 320) provides the output signal to the gate driver circuit (136, 236) to control the power transistor (238), the power control circuit (120, 220, 320) is configured to: cause at least a portion of the power signal to flow through the power transistor (238) in response to the power transistor (238) being turned on; and causing the power signal to flow from the power source (132, 232) to the load (134, 234) without flowing through the power transistor (238) in response to the power transistor (238) being turned off.The power control circuit (120, 220, 320) of any of claims 1-3, wherein the power control circuit (120, 220, 320) further comprises a signal sum unit (362), and wherein the power control circuit (120, 220, 320) is further configured to: cause the signal sum unit (362) to receive a first signal sum input (361) based on the power signal from the current sensor (126, 226, 326); cause the signal sum unit (362) to receive a second signal sum input (361') based on the control signal from the input connection (122, 219, 222, 322); using the signal sum unit (362), to generate a signal sum output (363) based on the first signal sum input (361) and the second signal sum input (361'), wherein the signal sum output (363) comprises a sum of the first signal sum input (361) and the second signal sum input (361'); and to generate the output signal based on the signal sum output (363).The power control circuit (120, 220, 320) of claim 4, wherein the power control circuit (120, 220, 320) further comprises a signal ramp unit, and wherein the power control circuit (120, 220, 320) is further configured to generate, using the signal ramp unit, the second signal sum input (361') based on the control signal from the input connection (122, 219, 222, 322), wherein the second signal sum input (361') comprises a sequence of ramp signal pulses corresponding to the sequence of control signal pulses occurring at the control signal frequency.The power control circuit (120, 220, 320) of any of claims 1-5, wherein the power control circuit (120, 220, 320) further comprises a comparator (366), and wherein to generate the output signal, the power control circuit (120, 220, 320) is configured to: cause the comparator (366) to receive a first comparator input (365) based on the control signal from the controller (110, 210) and the power signal from the current sensor (126, 226, 326); cause the comparator (366) to receive a second comparator input (365') based on the control signal from the controller (110, 210); and generating a comparator output (367) based on the first comparator input (365) and the second comparator input (365') using the comparator (366), wherein the comparator output (367) comprises the output signal provided to the gate driver circuit (136, 236).The power control circuit (120, 220, 320) of claim 6, wherein the power control circuit (120, 220, 320) further comprises a first signal ramp unit (368) and a second signal ramp unit (369), wherein to cause the comparator (366) to receive the first comparator input (365) based on the control signal from the controller (110, 210) and the power signal from the current sensor (126, 226, 326), the power control circuit (120, 220, 320) is configured to: generate, using the first signal ramp unit (368), a first sequence of ramp signal pulses corresponding to the sequence of control signal pulses occurring at the control signal frequency; generating the first comparator input (365) based on the first sequence of ramp signal pulses and the power signal from the current sensor (126, 226, 326), and wherein, to cause the comparator (366) to receive the second comparator input (365') based on the control signal from the controller (110, 210), the power control circuit (120, 220, 320) is configured to generate the second comparator input (365') using the second signal ramp unit (369) such that a second sequence of ramp signal pulses corresponding to the sequence of control signal pulses occurring at the control signal frequency is included.The power control circuit (120, 220, 320) of any of claims 1-7, wherein the control signal comprises an analog control signal, wherein by providing the output signal to the gate driver circuit (136, 236) to control the power signal provided from the power source (132, 232) to the load (134, 234), the power control circuit (120, 220, 320) is configured to cause the controller (110, 210) to receive an analog feedback signal, wherein the analog feedback signal is indicative of one or more parameters of the power signal provided from the power source (132, 232) to the load (134, 234), and wherein the analog control signal is based on the analog feedback signal.The power control circuit (120, 220, 320) of any of claims 1-8, wherein the control signal comprises a modulated digital signal.The power control circuit (120, 220, 320) according to any one of claims 1-9, wherein to provide the output signal for controlling the gate driver circuit (136, 236) for managing the power signal, the power control circuit (120, 220, 320) is configured to provide the output signal to the gate driver circuit (136, 236).The power control circuit (120, 220, 320) according to any one of claims 1-10, wherein to provide the output signal for controlling the gate driver circuit (136, 236) for managing the power signal, the power control circuit (120, 220, 320) is configured to provide the output signal to the controller (110, 210), thereby causing the controller (110, 210) to control the gate driver circuit (136, 236) for managing the power signal.The power control circuit (120, 220, 320) of any of claims 1-11, wherein the current sensor (126, 226, 326) comprises a Hall effect sensor configured to sense a magnetic field corresponding to a current of the power signal.A method comprising: generating a power signal by a current sensor (126, 226, 326) of a power control circuit (120, 220, 320), the power signal corresponding to an electrical signal provided from a power source (132, 232) to a load (134, 234); receiving a control signal by a power control circuit (120, 220, 320) from a controller (110, 210) via an input terminal (122, 219, 222, 322) of the power control circuit (120, 220, 320), the control signal comprising a sequence of control signal pulses occurring at a control signal frequency; generating an output signal by the power control circuit (120, 220, 320) based on the power signal, the sequence of control signal pulses, and the control signal frequency; and supplying the output signal through the power control circuit (120, 220, 320) via an output terminal (124, 218, 224, 324) to control a gate driver circuit (136, 236) to manage the power signal supplied from the power source (132, 232) to the load (134, 234).The method of claim 13, wherein generating the output signal comprises generating the output signal by the power control circuit (120, 220, 320) to include a sequence of gate control pulses, wherein each gate control pulse of the sequence of gate control pulses is configured to cause a power transistor (238) to turn on and off according to a power transistor switching cycle, and wherein supplying the output signal comprises supplying the output signal by the power control circuit (120, 220, 320) to the gate driver circuit (136, 236) such that the gate driver circuit (136, 236) controls a gate terminal of the power transistor (238) such that the power transistor (238) turns off and on according to the sequence of gate control pulses.The method of claim 14, wherein the power transistor (238) is connected to a node (142, 144, 242, 244) located between the power source (132, 232) and the load (134, 234), such that when the power control circuit (120, 220, 320) provides the output signal to the gate driver circuit (136, 236) to control the power transistor (238), the method comprises: causing, by the power control circuit (120, 220, 320), at least a portion of the power signal to flow through the power transistor (238) in response to the power transistor (238) being turned on; and causing, by the power control circuit (120, 220, 320), the power signal to flow from the power source (132, 232) to the load (134, 234) without flowing through the power transistor (238) in response to the power transistor (238) being turned off.The method of any of claims 13-15, wherein the power control circuit (120, 220, 320) further comprises a signal sum unit (362), and wherein the method further comprises: causing, by the power control circuit (120, 220, 320), the signal sum unit (362) to receive a first signal sum input (361) based on the power signal from the current sensor (126, 226, 326); causing, by the power control circuit (120, 220, 320), the signal sum unit (362) to receive a second signal sum input (361') based on the control signal from the input connection (122, 219, 222, 322); generating, by the power control circuit (120, 220, 320) using the signal sum unit (362), a signal sum output (363) based on the first signal sum input (361) and the second signal sum input (361'), wherein the signal sum output (363) comprises a sum of the first signal sum input (361) and the second signal sum input (361'); and generating, by the power control circuit (120, 220, 320), the output signal based on the signal sum output (363).The method of claim 16, wherein the power control circuit (120, 220, 320) further comprises a signal ramp unit, and wherein the method further comprises generating, by the power control circuit (120, 220, 320) using the signal ramp unit, the second signal sum input (361') based on the control signal from the input link (122, 219, 222, 322), wherein the second signal sum input (361') comprises a sequence of ramp signal pulses corresponding to the sequence of control signal pulses occurring at the control signal frequency.The method of any of claims 13-17, wherein the power control circuit (120, 220, 320) further comprises a comparator (366), and wherein generating the output signal comprises: causing, by the power control circuit (120, 220, 320), the comparator (366) to receive a first comparator input (365) based on the control signal from the controller (110, 210) and the power signal from the current sensor (126, 226, 326); causing, by the power control circuit (120, 220, 320), the comparator (366) to receive a second comparator input (365') based on the control signal from the controller (110, 210); and generating, by the power control circuit (120, 220, 320) using the comparator (366), a comparator output (367) based on the first comparator input (365) and the second comparator input (365'), the comparator output (367) comprising the output signal provided to the gate driver circuit (136, 236).The method of claim 18, wherein the power control circuit (120, 220, 320) further comprises a first signal ramp unit (368) and a second signal ramp unit (369), wherein causing the comparator (366) to receive the first comparator input (365) based on the control signal from the controller (110, 210) and the power signal from the current sensor (126, 226, 326) comprises: generating, by the power control circuit (120, 220, 320) using the first signal ramp unit (368), a first sequence of ramp signal pulses corresponding to the sequence of control signal pulses occurring at the control signal frequency; and generating, by the power control circuit (120, 220, 320), the first comparator input (365) based on the first sequence of ramp signal pulses and the power signal from the current sensor (126, 226, 326), and wherein causing the comparator (366) to receive the second comparator input (365') based on the control signal from the controller (110, 210) comprises: generating, by the power control circuit (120, 220, 320), the second comparator input (365') using the second signal ramp unit (369) so as to include a second sequence of ramp signal pulses corresponding to the sequence of control signal pulses occurring at the control signal frequency.A system (100, 200) comprising: a controller (110, 210); a gate driver circuit (136, 236); and a power control circuit (120, 220, 320) comprising: an input terminal (122, 219, 222, 322); an output terminal (124, 218, 224, 324); and a current sensor (126, 226, 326) configured to generate a power signal corresponding to an electrical signal provided from a power source (132, 232) to a load (134, 234), wherein the power control circuit (120, 220, 320) is configured to: receive from the controller (110, 210), via the input terminal (122, 219, 222, 322), a control signal comprising a sequence of control signal pulses occurring at a control signal frequency; generating an output signal based on the power signal, the sequence of control signal pulses, and the control signal frequency; and providing the output signal via the output terminal (124, 218, 224, 324) to control the gate driver circuit (136, 236) to manage the power signal provided from the power source (132, 232) to the load (134, 234).

Images