Integrated circuit with a test bus

Abstract

The invention relates to an application-specific integrated circuit comprising a test bus structure (2), wherein the test bus structure (2) comprises a first multiplexer circuit (3) with a first multiplexer (3.1), a test bus (5) and an output-side multiplexer (6), wherein the first multiplexer circuit (3) is configured to apply an input signal (E) from several input signals to the test bus (5), wherein the output-side multiplexer (6) is configured to transmit the signal transmitted on the test bus (5) as an output signal to an external contact point (7) of the integrated circuit (1), wherein a second multiplexer circuit (4) with a second multiplexer (4.1) is provided which is coupled on the input side to the test bus (5), wherein the second multiplexer circuit (4) is coupled on the output side to an analog-to-digital converter (8) which provides digital information on the output side for testing the functionality of the integrated circuit (1).

Description

[0001] The invention relates to an application-specific integrated circuit with a test bus.

[0002] It is generally known that application-specific integrated circuits, hereinafter also referred to as ASICs, have test bus structures. These test bus structures are currently used both during development, for example for characterizing or debugging the integrated circuit, and during production, for example in production tests.

[0003] In real-world operation of the integrated circuit, it is necessary, depending on the situation, to provide additional service functions, such as a monitoring function, fault detection, an integrated self-test, fail-safe functions and / or adjustment or adaptation measures.

[0004] Particularly for ASICs used in safety-critical applications, such as in the automotive, aerospace, or medical technology sectors, it is necessary to monitor the ASIC's functionality to ensure that it performs as specified. Currently, separate functional test structures are used for this purpose, operating independently and without any connection to the test bus.

[0005] The disadvantage is that these functional test structures require additional space, thus increasing the complexity and size of the ASIC, which also leads to higher costs for the ASIC.

[0006] DE 102 54 391 A1 discloses a circuit arrangement and an angle and length measuring device equipped with it, comprising multiple detector elements, in which a first circuit unit is located on a semiconductor chip and a second circuit unit is located on a separate substrate. The first circuit unit includes an amplifier circuit for amplifying measurement signals from the detector elements. Furthermore, the detector elements are also in electrical contact with a multiplexer of the first circuit unit. The multiplexer is electrically connected to a connection pad of the first circuit unit, which in turn is connected to a connection pad of the second circuit unit for transmitting test signals to the second circuit unit to verify the functionality of the detector elements.

[0007] Furthermore, DE 10 2024 200 161 A1 discloses a circuit arrangement for a radar sensor for measuring a sensor value, comprising a sensor which generates a DC voltage as a sensor signal proportional to the respective sensor value to be measured, at least one A / D converter via which the DC voltage is determined, and a polarity switch which is connected downstream of the sensor and via which the polarity of the DC voltage can be determined, wherein the polarity of the DC voltage is switched from a first measurement to a second measurement via the polarity switch, and a determination of the sensor value is carried out on the basis of the first measurement and the second measurement, preferably by subtracting the measurement result of the second measurement from the measurement result of the first measurement and halving the resulting difference.

[0008] Based on this, the object of the invention is to provide an application-specific integrated circuit that enables the implementation of additional functions with little additional effort and with a small footprint.

[0009] The problem is solved by an application-specific integrated circuit with the features of independent claim 1. Preferred embodiments are the subject of the dependent claims.

[0010] According to a first aspect, an application-specific integrated circuit is disclosed. The application-specific integrated circuit includes a test bus structure. The test bus structure comprises at least a first multiplexer circuit with a first multiplexer, a test bus, and an output-side multiplexer. The first multiplexer circuit is configured to select an input signal from several input signals and apply it to the test bus. The output-side multiplexer is configured to couple the test bus to an external interface of the integrated circuit. The test bus is configured to transmit test signals during development or production. A second multiplexer circuit with a second multiplexer is provided, which is coupled to the test bus on its input side.The second multiplexer circuit is coupled on its output side to an analog-to-digital converter, which provides digital information for testing the functionality of the integrated circuit. Together with the analog-to-digital converter, the second multiplexer circuit forms a signal path that is used, in particular, for at least one service function during the ASIC's intended operation.

[0011] The technical advantage of the application-specific integrated circuit lies in the fact that the test bus is not only used for testing during production and for characterization and debugging during ASIC development, but also enables service functions to be performed via the test bus structure during the ASIC's intended use. Such service functions can include, for example, monitoring values ​​that must be maintained during ASIC operation for proper function, fault detection, ASIC self-testing, configuration and tuning functions, or reliability tests. Through the second multiplexer circuit and the analog-to-digital converter, existing analog signals from the ASIC can be connected to the test bus and fed to the analog-to-digital converter during intended operation.The digital signals provided by the analog-to-digital converter are preferably evaluated by a processing unit of the ASIC. This allows for the provision of service functions during the ASIC's intended use with minimal additional effort and by reusing the existing test bus system.

[0012] According to one embodiment, the first multiplexer circuit and / or the second multiplexer circuit includes an amplifier. The input of the amplifier of the first multiplexer circuit is coupled to the output of the first multiplexer, and / or the input of the amplifier of the second multiplexer circuit is coupled to the output of the second multiplexer. The amplifier of the first multiplexer circuit acts as a driver and prevents the signals to be applied to the test bus, such as voltages, oscillator signals, etc., from being distorted by the load of the test bus structure. Another function of the amplifier of the first multiplexer circuit is to drive the input of an amplifier of the second multiplexer circuit.This amplifier in the second multiplexer circuit offers the advantage that no interfering effects resulting from the analog-to-digital converter affect the test bus, thus ensuring that the signals transmitted on the test bus are free of noise. Furthermore, the amplifier in the second multiplexer circuit also serves as a driver for the analog-to-digital converter.

[0013] According to one embodiment, a bypass branch is provided in the first and / or second multiplexer circuit, by means of which the amplifier of the first and / or second multiplexer circuit can be bypassed, thus enabling bidirectional signal flow past the amplifier through the first and / or second multiplexer circuit. An amplifier, in particular an operational amplifier, has the technical characteristic that signal transmission (possibly with corresponding amplification) occurs in a first transmission direction, whereas in a second transmission direction, which is opposite to the first direction, the high impedance of the amplifier prevents or at least inhibits signal transmission. To prevent this, the bypass branch forms a selectively activatable bridge that allows signal transmission in the second transmission direction, i.e., in the reverse direction via the amplifier.This ensures that bidirectional data transmission can still be guaranteed in the first and / or second multiplexer circuit despite the amplifier.

[0014] According to one embodiment, the amplifier's gain is adjustable. This adjustability is achieved, in particular, by applying a variable gain control signal to the amplifier. This has the advantage, for example, that the amplifier's gain factor can be adjusted so that when a reference voltage from the ASIC is transmitted via the test bus, the voltage value output at the external contact point and / or the analog-to-digital converter (ADC) has a desired value. This makes it possible to measure signals with low amplitudes using the ADC. Furthermore, the measurement accuracy at the ADC can be improved by reducing the measurement error and enhancing offset compensation.

[0015] According to one embodiment, a signal conditioning unit is provided whose input is coupled to the output-side multiplexer and whose output is coupled to the first multiplexer circuit. The signal conditioning unit is configured to receive a signal applied at an external contact point via the output-side multiplexer, condition it, and feed it to the first multiplexer circuit for transmission on the test bus. The signal conditioning unit enables the signal conditioning of a signal applied at the external contact point such that this signal can be transmitted via the test bus to the second multiplexer circuit, where it can be converted into a digital signal by the analog-to-digital converter and further processed. This makes it possible, for example, to measure the voltage of a signal applied at the external contact point and process it by the ASIC.

[0016] According to one embodiment, the signal conditioning unit is configured to convert a single-ended signal into a differential signal (so-called balanced-to-unbalanced conversion). Preferably, the second multiplexer circuit and the analog-to-digital converter are configured to process differential signals. This makes it possible to adapt the externally applied signal so that it can be transmitted to the second multiplexer circuit and processed by the analog-to-digital converter. It is understood that in an alternative embodiment, the analog-to-digital converter can also be configured to process single-ended signals, which would render the signal conditioning unit unnecessary.

[0017] According to one embodiment, the integrated circuit is configured to feed a signal applied to an external contact point via the signal conditioning unit, the first multiplexer circuit, and the test bus of the second multiplexer circuit, so that the signal can be converted into a digital signal by the analog-to-digital converter. This advantageously allows the voltage of a signal applied to the external contact point to be measured and processed by the ASIC.

[0018] According to one embodiment, a test component is provided at an input of the output-side multiplexer or on the signal line between the output-side multiplexer and an external contact point. The test component can thus be contacted from the external contact point in order to acquire parameters relating to this test structure.

[0019] According to one embodiment, the test component is a resistor or a sensor used to set and / or adjust operating parameters of the integrated circuit. According to an alternative embodiment, the test component is a test structure that enables the characterization of production processes. This test component can use any type of test structure suitable for characterizing circuit properties.

[0020] According to one embodiment, a switching unit is provided at the input of the first multiplexer circuit, allowing the assignment of the polarity-dissimilar partial signals of a differential signal to a line pair to be changed. In other words, the switching unit enables the inverse application of a differential signal to the test bus. This offers advantages with regard to offset compensation, as any existing offset and low-frequency noise (for example, caused by the use of MOSFET transistors) can be compensated for by differential calculation. This allows both the measurement accuracy and the sensitivity of the entire measurement process to be improved.

[0021] According to one embodiment, the integrated circuit is configured to control the switching unit such that the polarity-opposite partial signals of a differential signal are applied to the line pair in a first phase in a first assignment and in a second, reversed assignment in a second phase. This allows the switching unit to easily switch the assignment of the polarity-opposite partial signals of a differential signal to the input lines of the first multiplexer circuit.

[0022] According to another aspect, a method for providing a service function during the intended use of an integrated circuit is disclosed. The integrated circuit includes a test bus structure. The test bus structure comprises at least a first multiplexer circuit with a first multiplexer, a test bus, and an output multiplexer. A second multiplexer circuit with a second multiplexer is provided, which is coupled to the test bus on its input side. The second multiplexer circuit is coupled on its output side to an analog-to-digital converter, which provides digital information on its output side for performing a service function. The method comprises the following steps: - During the intended use of the integrated circuit, a signal is supplied to the first multiplexer of the first multiplexer circuit; - Transmitting the signal via the test bus to the second multiplexer circuit; - Using the analog-to-digital converter, the signal is converted into a digital signal; - Evaluating the digital signal to provide the service function.

[0023] This method offers the crucial advantage that a test bus structure, intended for testing purposes during the ASIC's development and production, can also be used during the ASIC's intended operation to fulfill service functions. This allows for significant space savings and the avoidance of redundant structures and components.

[0024] According to one embodiment of the method, at least one operating signal, available during the intended use of the integrated circuit, is transmitted via the first multiplexer circuit, the test bus, and the second multiplexer circuit to the analog-to-digital converter (ADC). This allows a functional test of the integrated circuit to be performed using the digital signal provided by the ADC based on the operating signal. This enables a built-in self-test (BIST) of the ASIC to be performed using the test bus structure, thereby increasing the ASIC's reliability or ensuring correct functionality.

[0025] According to one embodiment of the method, a signal applied to an external contact point of the integrated circuit is fed to the analog-to-digital converter via a signal conditioning unit, the first multiplexer circuit, the test bus, and the second multiplexer circuit. The analog-to-digital converter then converts the signal into a digital signal, which is subsequently evaluated in the integrated circuit. This makes it possible, for example, to use the test bus to measure the voltage of a signal applied to the external contact point and to evaluate this information in the ASIC.

[0026] According to one embodiment of the method, an amplifier in the first and / or second multiplexer circuit is bypassed by means of a bypass branch to enable bidirectional signal flow past the amplifier through the first and / or second multiplexer circuit. This makes it possible to ensure bidirectional signal flow through the test bus structure despite the presence of the amplifier.

[0027] For the purposes of this invention, an "input signal" is understood to be a single-ended signal or a differential signal.

[0028] For the purposes of this invention, "service function" means any function performed during the intended use of the ASIC to ensure its proper functioning. In particular, the following functions are considered service functions: - Functions for monitoring the ASIC's functionality; - Fault detection functions; - Functions for self-testing the ASIC (BIST functions); - Functions to ensure fail-safe requirements; - Functions for setting and / or adjusting operating parameters.

[0029] "Intended use" or "intended application" within the meaning of the present invention means that the ASIC is installed in a sensor or other system to perform application-specific tasks. When performing the service function, the ASIC can be in application-specific operation or operated in a test mode for the service function.

[0030] Further developments, advantages, and possible applications of the invention will also become apparent from the following description of exemplary embodiments and from the figures. All features described and / or illustrated are, individually or in any combination, fundamentally the subject matter of the invention, irrespective of their compilation in the claims or their cross-reference. The content of the claims is also incorporated into the description.

[0031] The invention will be explained in more detail below with reference to exemplary embodiments shown in the figures. The figures show: Fig. 1. An example is a schematic representation of an ASIC that has a test bus structure; Fig. 2. An example of a detailed diagram of the construction of a multiplexer circuit, which is shown in the Fig. The test bus structure shown in 1 can be used; Fig. 3 examples, one in comparison to the Fig. 1 alternative arrangement of the test component between the output of the output-side multiplexer and the external contact point; Fig. 4. Exemplary and schematic structure of the in Fig. 1 shown switching unit; Fig. 5. An example block diagram illustrates the steps of a procedure for providing a service function during the intended use of the ASIC.

[0032] Fig. Figure 1 schematically shows a section of an embodiment of an ASIC 1, which has a test bus structure 2. The test bus structure 2 is designed for multiple uses, firstly during the development of the ASIC, for example for characterization and debugging, and secondly during production, for example to perform tests regarding production quality. Furthermore, the test bus structure 2 is designed to provide functions during the intended use of the ASIC, by means of which functional monitoring, fault detection and / or self-tests are performed during operation of the ASIC, fail-safe requirements are met and / or adjustments and calibrations of operating parameters of the ASIC are made possible.

[0033] The ASIC can be, for example, a mixed-signal ASIC, especially one for safety-critical applications. Application areas include ASICs used in the automotive sector or medical technology. Specifically, the ASIC can be an ASIC used in the automotive sector to operate a radar sensor, also known as a radar ASIC.

[0034] The test bus structure 2 includes at least one first multiplexer circuit 3. The first multiplexer circuit 3 has several inputs E1 - En and one or more outputs A. Analog signals can be received at the inputs E1 - En, for example, a voltage representing the power of a radar sensor, a voltage from a sensor such as a temperature sensor, the operating voltage of the ASIC, a reference voltage, and / or other analog signals, such as an oscillator signal. It is understood that this list is purely exemplary and any other signals can also be applied to the inputs. The signals can be single-ended or differential signals.

[0035] The at least one output A of the first multiplexer circuit 3, which is preferably formed by a line pair for transmitting differential signals, is connected to a test bus 5. The test bus 5 is preferably configured for transmitting differential signals, as shown in Fig. 1 is indicated by the digits "2". It is understood that if the test bus 5 is designed for differential signals, a pair of external contact points 7 must also be present in order to be able to connect a differential signal to the test bus 5 or to receive such a signal from the test bus 5.

[0036] The first multiplexer circuit 3 can transmit signals bidirectionally, i.e., in the direction from a selected input E1 - En to the output A or in the reverse direction from output A to a selected input E1 - En, as indicated by the single and double arrows in Fig. 1 is indicated.

[0037] The test bus 5 is connected via an output-side multiplexer 6 to at least one external contact point 7, or, in the case of an ASIC, to a pair of external contact points 7 of the ASIC for transmitting differential signals. The output-side multiplexer 6, in turn, has several inputs and at least one output. It is configured to connect one of the inputs to the output. The external contact point 7 can be contacted with a suitable contact means to receive signals from the test bus structure 2 or to supply external signals to the test bus structure 2 from the outside; that is, an electrical signal can be transmitted from the at least one external contact point 7 via the output-side multiplexer 6, the test bus 5, and the first multiplexer circuit 3 to an internal electrical node of the ASIC (in Fig. 1: Transmission direction from right to left).

[0038] The test bus 5 has a tap through which a second multiplexer circuit 4 is coupled to the test bus 5. This allows the signals transmitted on the test bus 5 to be fed to the second multiplexer circuit 4.

[0039] The second multiplexer circuit 4 is coupled on its output side to an analog-to-digital converter 8. This analog-to-digital converter 8 converts the analog signal received by the second multiplexer circuit 4 into a digital signal to make it available for the respective service function on the ASIC. For example, the digital signal can be used for function monitoring, fault detection, or a self-test.

[0040] Fig. Figure 2 shows an exemplary setup of the first and / or second multiplexer circuit 3, 4. It should be noted that preferably both multiplexer circuits 3, 4 have the setup described below. Alternatively, only one of the two multiplexer circuits 3, 4 can be configured as described below.

[0041] The first and second multiplexer circuits 3, 4 each comprise a multiplexer 3.1, 4.1. The multiplexer is configured to selectively couple an input of the multiplexer 3.1, 4.1 with its output, depending on a switching signal S. The multiplexer 3.1, 4.1 can, in particular, be a passive multiplexer comprising a plurality of switching elements and gates. The output of the multiplexer 3.1, 4.1 is coupled to an amplifier 3.2, 4.2, which can also function as a driver. The gain of the amplifier 3.2, 4.2 can be varied via a control line V by means of a gain control signal.

[0042] Since amplifier 3.2, 4.2 only allows unidirectional operation (as indicated by the single arrows in Fig. (as indicated in Figure 2), the first and / or second multiplexer circuit 3, 4 has a bypass branch 3.3, 4.3. The amplifier 3.2, 4.2 can be bypassed via the bypass branch 3.3, 4.3, thus selectively establishing an electrically conductive connection from the output of the multiplexer 3.1, 4.1 to the output of the first and / or second multiplexer circuit 3, 4. The bypass branch 3.3, 4.3 has a switching device for activation or deactivation, allowing the bypass branch 3.3, 4.3 to be selectively opened or closed. The bypass branch 3.3, 4.3 is activated by closing the switching device, in particular, when signal transmission from the output of the first and / or second multiplexer circuit 3, 4 back to the multiplexer 3.1, 4.1 is desired (in the Fig. 2, from right to left).

[0043] Multiplexer circuits 3 and 4 offer the following technical advantages: - a high input impedance, so that the circuit components or sensors connected to the input of the multiplexer circuits 3, 4 are not loaded or only slightly loaded; - The amplifier 3.2 acts as a driver to ensure a stable signal is applied to the test bus despite the load of the entire test bus 5; - the amplifier 4.2 acts as a driver for the load of the analog-to-digital converter 8; - the amplifier 4.2 prevents feedback from the analog-to-digital converter 8 to the test bus 5; - A bidirectional data flow is enabled to allow any analog test modes to be executed via test bus 5; - Preventing leakage currents, noise or other interference effects on the test bus that could distort the results of tests.

[0044] The test bus structure 2 is, as in Fig. Figure 1 shows a device configured to apply a signal supplied to the ASIC 1 at the external contact point 7 to the test bus 5 and to feed it to the analog-to-digital converter 8 via the second multiplexer circuit 4. A feedback branch R is provided for this purpose, in which a signal conditioning unit 9 is included.

[0045] In the middle of the feedback branch R, it is possible to feed a signal applied to the external contact point 7 via the output-side multiplexer 6 and the feedback branch R to the input of the first multiplexer circuit 3. With appropriate control of the first multiplexer 3.1 of the first multiplexer circuit 3, the signal can then be applied to the test bus 5. In particular, an electrical signal applied to the external contact point 7 can be transmitted via the signal path described above to the analog-to-digital converter 8, and thus the electrical voltage of the signal can be measured.

[0046] The signal conditioning unit 9 is designed to condition the signal applied at the external contact point 7 so that it can be converted by the analog-to-digital converter 8. In particular, the signal conditioning unit 9 can be configured to convert the signal from a single-ended signal to a differential signal. Furthermore, the signal conditioning unit 9 can include an amplifier to prevent signal distortion due to loads.

[0047] The test bus structure 2 also includes a test component 10. The test component 10 can be a single "device under test", for example, a sensor, a resistor, or an arrangement of several electrical components. Alternatively, the test component 10 can be a test structure that characterizes at least part of the manufacturing process.

[0048] Test component 10 is in the Fig. In the embodiment shown in Figure 1, the test component 10 is coupled to an input of the output-side multiplexer 6. The connection can be bidirectional, meaning that electrical signals can be transmitted from the test component 10 to the output-side multiplexer 6 (and from there to the test bus 5) or via the output-side multiplexer 6 to the test component 10 (as indicated by the double arrow). The test component 10 can be used to characterize the production process (for example, using suitable test structures) or to adjust or calibrate operating parameters.

[0049] In an alternative embodiment, it is possible to connect the test component 10 to the connecting line between the output-side multiplexer 6 and the external contact point 7, as shown in Fig. Figure 3 shows this. This reduces the distance between the test component 10 and the external contact point 7 as much as possible, leading to a reduction in interference with other components of the ASIC, a reduction in noise input, a reduction in leakage currents and other interference effects.

[0050] Fig. Figure 4 shows a switching unit 11 which can be used on the input side before the first multiplexer circuit 3, as shown in Fig. Figure 1 shows the switching unit 11. It comprises a switch arrangement by means of which the assignment of the polarity-dissimilar partial signals of a differential signal to the lines of a power pair can be changed. In particular, the switching unit 11 can switch the first partial signal from the first signal line of the power pair to the second signal line and simultaneously switch the second partial signal from the second signal line of the power pair to the first signal line. Thus, the switching unit 11 can reverse the polarity of the differential input signal, which can be advantageously used to compensate for an offset. Specifically, an existing offset and low-frequency noise can be determined and thereby compensated by calculating the difference between the values ​​obtained at the respective switching positions of the switching unit 11.

[0051] Fig.Figure 5 shows a block diagram illustrating the process steps of a procedure for providing a service function during the intended use of an integrated circuit 1 with a test bus structure 2. The procedure comprises the following steps: Initially, during the intended use of the integrated circuit, a signal is fed to the first multiplexer of the first multiplexer circuit (S10).

[0052] This signal is then transmitted via the test bus to the second multiplexer circuit (S11).

[0053] The signal is then converted into a digital signal by means of the analog-to-digital converter, which is coupled to the second multiplexer circuit (S12).

[0054] Finally, the digital signal is evaluated in order to provide a service function based on it (S13). Reference symbol list 1 Application-specific integrated circuit 2 Test bus structure 3 first multiplexer circuit 3.1 First multiplexer 3.2 Amplifier 3.3 Bypass branch 4 second multiplexer circuit 4.1 Second multiplexer 4.2 Amplifier 4.3 Bypass branch 5 test buses 6 output-side multiplexers 7 external contact point 8 Analog-to-Digital Converters 9 Signal processing unit 10 Test components 11 Switching unit A Exit E1 - En Entrance R return branch V control line

Claims

[1] Application-specific integrated circuit comprising a test bus structure (2), wherein the test bus structure (2) comprises at least a first multiplexer circuit (3) with a first multiplexer (3.1), a test bus (5) and an output-side multiplexer (6), wherein the first multiplexer circuit (3) is configured to select an input signal (E) from several input signals and to connect it to the test bus (5), wherein the output-side multiplexer (6) is configured to selectively couple the test bus (5) to an external contact point (7) of the application-specific integrated circuit (1), characterized by, that a second multiplexer circuit (4) with a second multiplexer (4.1) is provided, which is coupled to the test bus (5) on the input side, wherein the second multiplexer circuit (4) is coupled to an analog-to-digital converter (8) on the output side, which provides digital information on the output side for testing the functionality of the application-specific integrated circuit (1). [2] Application-specific integrated circuit according to claim 1, characterized by , that the first multiplexer circuit (3) and / or the second multiplexer circuit (4) has an amplifier (3.2, 4.2) wherein the input of the amplifier (3.2) of the first multiplexer circuit is coupled to the output of the first multiplexer (3.1) and / or the input of the amplifier (4.2) of the second multiplexer circuit (4) is coupled to the output of the second multiplexer (4.1). [3] Application-specific integrated circuit according to claim 2, characterized by, that a bypass branch (3.3, 4.3) is provided by means of which the amplifier (3.2, 4.2) of the first and / or second multiplexer circuit (3, 4) can be bypassed, so that a bidirectional signal flow past the amplifier (3.2, 4.2) through the first and / or second multiplexer circuit (3, 4) is enabled. [4] Application-specific integrated circuit according to claim 2 or 3, characterized by , that the gain of the amplifier (3.2, 4.2) is adjustable. [5] Application-specific integrated circuit according to any one of the preceding claims, characterized by, that a signal conditioning unit (9) is provided, the input of which is coupled to the output-side multiplexer (6) and the output of which is coupled to the first multiplexer circuit (3), wherein the signal conditioning unit (9) is configured to receive a signal applied at an external contact point (7) via the output-side multiplexer (6), to condition it and to supply it to the first multiplexer circuit (3) for transmission on the test bus (5). [6] Application-specific integrated circuit according to claim 5, characterized by , that the signal conditioning unit (9) is designed to convert a single-ended signal into a differential signal. [7] Application-specific integrated circuit according to claim 5 or 6, characterized by, that the application-specific integrated circuit (1) is configured to supply a signal applied at an external contact point (7) via the signal conditioning unit (9), the first multiplexer circuit (3) and the test bus (4) to the second multiplexer circuit (4), so that the signal can be converted into a digital signal by the analog-to-digital converter (8). [8] Application-specific integrated circuit according to any one of the preceding claims, characterized by , that a test component (10) is provided at an input of the output-side multiplexer (6) or on the signal line between the output-side multiplexer (6) and an external contact point (7). [9] Application-specific integrated circuit according to claim 8, characterized by, that the test component (10) includes at least a resistor, a capacitor, an RC high-pass filter, an RC low-pass filter and / or a sensor used to adjust and / or calibrate parameters of the application-specific integrated circuit (1). [10] Application-specific integrated circuit according to any of the preceding claims, characterized by , that a switching unit (11) is provided on the input side of the first multiplexer circuit (3) by means of which the assignment of the polarity-different partial signals of a differential signal to a line pair can be changed. [11] Application-specific integrated circuit according to claim 10, characterized by, that the application-specific integrated circuit (1) is configured to control the switching unit (11) in such a way that the polarity-different partial signals of a differential signal are applied to the line pair in a first phase in a first assignment and in a second phase in a second, reverse assignment. [12] Method for providing a service function during the intended use of an application-specific integrated circuit (1) with a test bus structure (2), wherein the test bus structure (2) comprises at least a first multiplexer circuit (3) with a first multiplexer (3.1), a test bus (5) and an output multiplexer (6), wherein a second multiplexer circuit (4) with a second multiplexer (4.1) is provided, which is coupled to the test bus (5) on the input side, wherein the second multiplexer circuit (4) is coupled to an analog-to-digital converter (8) on the output side, which provides digital information on the output side for performing a service function, wherein the method comprises the following steps: - During the intended use of the application-specific integrated circuit (1), supplying a signal to the first multiplexer (3.1) of the first multiplexer circuit (3) (S10); - Transferring the signal via the test bus (5) to the second multiplexer circuit (4) (S11); - Using the analog-to-digital converter (8), converting the signal into a digital signal (S12); - Evaluating the digital signal to provide the service function (S13). [13] Method according to claim 12, characterized by , that at least one operating signal available during the intended use of the application-specific integrated circuit (1) is transmitted via the first multiplexer circuit (3), the test bus (5) and the second multiplexer circuit (4) to the analog-to-digital converter (8) in order to perform a functional test in the integrated circuit based on the digital signal provided by the analog-to-digital converter (8) based on the operating signal. [14] Method according to claim 12 or 13, characterized by, that a signal applied to an external contact point (7) of the application-specific integrated circuit (1) is fed to the analog-to-digital converter (8) via a signal conditioning unit (9), the first multiplexer circuit (3), the test bus (5) and the second multiplexer circuit (4), and that the signal is converted into a digital signal by the analog-to-digital converter (8) and that this digital signal is evaluated in the application-specific integrated circuit (1). [15] Method according to any one of claims 12 to 14, characterized by , that in the first and / or second multiplexer circuit (3, 4) an amplifier (3.2, 4.2) is bypassed by means of a bypass branch (3.3, 4.3) to allow a bidirectional signal flow past the amplifier (3.2, 4.2) through the first and / or second multiplexer circuit (3, 4).

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