DYNAMIC PROGRAM PULSE WIDTHS FOR DIFFERENT SUBBLOCKS IN A STORAGE DEVICE

Abstract

A storage device comprises a memory array with a plurality of blocks and control logic for initiating a program operation at one or more memory cells in a first subblock of one of the plurality of blocks of the memory array. The control logic further identifies a categorization of the first subblock, determines a corresponding program pulse width based on the categorization of the first subblock, and causes a program voltage pulse with the corresponding program pulse width to be applied to the one or more memory cells during the program operation.

Description

TECHNICAL AREA

[0001] Embodiments of the invention generally relate to memory subsystems and in particular to dynamic program pulse widths for different subblocks in a memory device of a memory subsystem. BACKGROUND

[0002] A storage subsystem can include one or more storage devices for storing data. These storage devices can be, for example, non-volatile or volatile. Generally, a host system can use a storage subsystem to store data in and read data from the storage devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The present invention will be better understood with reference to the detailed description below and the accompanying drawings of various embodiments of the invention. Fig. Figure 1A shows an exemplary computer system comprising a storage subsystem according to some embodiments of the present invention. Fig. Figure 1B is a block diagram of a storage device communicating with a storage subsystem controller of a storage subsystem, according to some embodiments of the present invention. Fig. 2 is a schematic representation of parts of an array of memory cells located in a memory of the system with reference to Fig. 1B can be used according to some embodiments of the present invention. Fig. Figure 3 is a representation illustrating a block of a memory array with multiple subblocks, according to some embodiments of the present invention. Fig. Figure 4 is a flowchart of an exemplary method for performing a program operation with dynamic program pulse widths for different subblocks in a storage device of a storage subsystem according to some embodiments of the present invention. Fig. Figure 5 is a representation illustrating waveforms with dynamic program pulse widths for different subblocks in a storage device, according to some embodiments of the present invention. Fig. Figure 6 is a block diagram of an exemplary computer system in which embodiments of the present invention can be implemented. DETAILED DESCRIPTION

[0004] Aspects of the present invention relate to dynamic program pulse widths for different subblocks in a storage device of a storage subsystem. A storage subsystem can be a storage device, a storage module, or a hybrid of a storage device and a storage module. Examples of storage devices and storage modules are given below in connection with Fig. As described in section 1A, a host system can generally use a storage subsystem, which comprises one or more components, such as storage devices, to store data. The host system can provide data to be stored in the storage subsystem and request data to be read from the storage subsystem.

[0005] A storage subsystem can include high-density non-volatile storage devices where data retention is desired even when the storage device is not powered. For example, NAND memory, such as 3D Flash NAND memory, provides storage in the form of compact, high-density configurations. A non-volatile storage device is a package of one or more chips, each with one or more layers. In some types of non-volatile storage devices (e.g., NAND memory), each layer contains a set of physical blocks. Each block contains a set of pages. Each page contains a set of memory cells (“cells”). A cell is an electronic circuit that stores information.Depending on the cell type, a cell can store one or more bits of binary information and have different logical states that correlate with the number of stored bits. These logical states can be represented by binary values, such as "0" and "1", or combinations of such values.

[0006] A storage device can be composed of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are formed on a silicon wafer in an array of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line can refer to one or more rows of memory cells of a storage device, which are used with one or more bit lines to generate the address of each of the memory cells. The address of the memory cell is formed by the intersection of a bit line with a word line. A block, hereinafter, refers to a unit of the storage device used to store data and can comprise a group of memory cells, a group of word lines, a single word line, or individual memory cells.

[0007] One or more blocks can be grouped together to form separate partitions (e.g., levels) of the storage device, enabling concurrent operations at each level. The storage device can include circuitry that performs concurrent memory page accesses on two or more memory levels. For example, the storage device can include multiple access line driver circuitry and power supply circuitry that can be shared by the levels of the storage device to facilitate concurrent access to pages from two or more memory levels, including different page types. Each data block can contain a number of subblocks, with each subblock defined by an associated column (e.g., a vertical conductive trace) extending from a common bit line. Because the subblocks can be accessed separately (e.g.,(To perform program or read operations), the data block can have a structure to selectively activate the column associated with a particular subblock while deactivating columns associated with other subblocks. In one embodiment, this structure includes one or more select-gate devices positioned at one or both ends of each column. Depending on an applied control signal, these select-gate devices can either enable or disable the transmission of signals through the columns. In one embodiment, the select-gate devices associated with each column in the data block are controlled separately. Newer memory architectures have an ever-increasing number of subblocks (e.g., 4, 6, 8, or more subblocks per block) to increase the potential for parallel memory access operations.However, the increased number of subblocks leads to an increase in the area (e.g. in the X and Y dimensions) of the storage device.

[0008] One solution to reduce the size of the storage device in the X and Y dimensions is to use deintegrated select-gate devices at the drain end of the columns (i.e., positioned in a region of the column that is formed as a separate processing step from the rest of the column, where the core memory cells are located). For example, these deintegrated select-gate devices can be formed in additional horizontal layers arranged above the rest of the storage array. Using such deintegrated select-gate devices can help reduce the size of the storage device in the X and Y dimensions because no physical cuts are required between the subblocks of a given block. However, adding additional horizontal layers can increase the overall height of the storage array (e.g., in the Z dimension).To accommodate the increased height, certain memory architectures reduce the height of each horizontal layer in the memory array (i.e., they reduce the thickness of the metal layers that form the access lines for the memory cells). However, the thinner metal layers have increased electrical resistance, making it more difficult for electrical signals, such as a program voltage signal, to flow through the access lines. Consequently, a longer program pulse width, which can be represented by a parameter T_pgm_pulse, may be required to ensure that a program operation succeeds and to reduce the error rate associated with the program operation. However, the longer program pulse width increases the overall program time and degrades the performance of the memory device.

[0009] As the number of subblocks per block of the storage device increases, fabrication challenges arise that can affect the device's performance. For example, the diffusion of metal layers to form the access lines generally begins at the edges of a given block and moves toward the center. Therefore, the thickness of the metal layers may become uneven across different subblocks. For instance, the outermost subblocks (i.e., those closer to the block's edges) may have thicker metal layers, while the innermost subblocks (i.e., those closer to the block's center) may have thinner metal layers. Furthermore, the previously described reduced scaling of the horizontal layers results in less uniform diffusion.The thinner metal layers and uneven thickness can lead to a number of problems during the operation of the storage device, such as worse read noise effects, worse cycles, erase saturation, higher resistance, etc. As described above, a longer program pulse width (i.e., T_pgm_pulse) can be used to improve the performance related to the program operation, but this comes at the cost of a longer overall program time.

[0010] Conventional storage devices use the same program pulse width for all subblocks within a given block. Since programming data in at least some subblocks in the storage device benefits from a longer program pulse width, this longer pulse width is used when programming all subblocks in the storage device. This includes certain subblocks that do not necessarily require a longer pulse width, such as those with thicker metal layers and those located closer to the block's edges. Consequently, the overall program time for these subblocks is unnecessarily increased.

[0011] Aspects of the present invention address the aforementioned and other shortcomings by implementing dynamic program pulse widths for different subblocks in a memory device of a memory subsystem. For example, when a program operation is performed on memory cells in a specific subblock of a block of the memory device, the control logic can identify a categorization of the subblock and determine a corresponding program pulse width. In one embodiment, the categorization can be based on the physical position of the subblock within the block (e.g., outermost, middle, innermost). In other embodiments, there can be any number of different categorizations, or the categorization can be based on different criteria.Each categorization can have a different corresponding program pulse width, which may be predefined according to the specific parameters of the storage device. For example, the outermost subblocks may have a shorter program pulse width than the middle subblocks, which in turn have a shorter program pulse width than the innermost subblocks. In various embodiments, two or more different categorizations may have the same corresponding program pulse width, or the relative widths may differ from those described in this example. Once the corresponding program pulse width is identified, the control logic can perform the program operation on the memory cells in the subblock using the identified program pulse width.

[0012] The advantages of this approach include, but are not limited to, improved performance in the memory subsystem. Dynamically selecting a program pulse width based on the categorization of the subblock being programmed ensures that unnecessarily long pulse widths are not used when required, while allowing the use of increased pulse widths with other subblocks to reduce the associated error rate. This can reduce overall programming times in the memory device and improve the overall quality of services provided to a host system.

[0013] Fig. Figure 1A shows an exemplary computer system 100 comprising a storage subsystem 110, according to some embodiments of the present invention. The storage subsystem 110 can comprise media such as one or more volatile storage devices (e.g., storage device 140), one or more non-volatile storage devices (e.g., storage device 130), or a combination thereof.

[0014] A Memory Subsystem 110 can be a storage device, a memory module, or a hybrid of both. Examples of storage devices include a solid-state drive (SSD), a flash drive, a universal serial bus flash drive (USB flash drive), an embedded multimedia controller drive (eMMC drive), a universal flash storage drive (UFS drive), a secure digital card (SD card), and a hard disk drive (HDD). Examples of memory modules include a dual in-line memory module (DIMM), a small-outline DIMM (SO-DIMM), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0015] The computer system 100 can be a computer device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or another means of transport), a device suitable for the Internet of Things (IoT), an embedded computer (e.g., one contained in a vehicle, an industrial plant, or a networked commercial device), or a computer device that includes a storage and processing unit.

[0016] The computer system 100 can comprise a host system 120 coupled with one or more storage subsystems 110. In some embodiments, the host system 120 is coupled with different types of storage subsystems 110. Fig. Figure 1A shows an example of a host system 120 coupled to a storage subsystem 110. As used here, "coupled to" or "coupled with" generally refers to a connection between components, which may be an indirect communication link or a direct communication link (e.g., without intermediary components), either wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0017] The Host System 120 can contain a processor chipset and a software stack that is executed by the processor chipset. The processor chipset can contain one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a memory protocol controller (e.g., a PCIe controller, a SATA controller, a CXL controller). The Host System 120 uses, for example, the Memory Subsystem 110 to write data to and read data from the Memory Subsystem 110.

[0018] The Host System 120 can be connected to the Storage Subsystem 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Compute Express Link (CXL) interface, a Peripheral Component Interconnect Express (PCLE) interface, a Universal Serial Bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-Line Memory Module (DIMM) interface (e.g., a DIMM socket interface that supports Double Data Rate (DDR)), etc. The physical host interface can be used to transfer data between the Host System 120 and the Storage Subsystem 110.The host system 120 can also use an NVM Express interface (NVMe interface) to access the storage components (e.g., storage devices 130) when the storage subsystem 110 is connected to the host system 120 via the physical host interface (e.g., PCIe or CXL interface). The physical host interface can provide an interface for transmitting control signals, address signals, data signals, and other signals between the storage subsystem 110 and the host system 120. Fig. Figure 1A shows a storage subsystem 110 as an example. In general, the host system 120 can access multiple storage subsystems via the same communication link, multiple separate communication links, and / or a combination of communication links.

[0019] The storage devices 130 and 140 can contain any combination of different types of non-volatile and / or volatile storage devices. The volatile storage devices (e.g., storage device 140) can be, but are not limited to, random access memory (RAM), such as DRAM and SDRAM.

[0020] Some examples of non-volatile storage devices (e.g., the Storage Device 130) include negative-AND-type flash memory (NAND) and write-in-place memory, such as three-dimensional cross-point memory (“3D cross-point memory”). A cross-point array of non-volatile memory can store bits based on a change in bulk resistance in conjunction with a stackable cross-gridded data access array. Furthermore, unlike many flash-based memories, cross-volatile memory can perform a write-in-place operation, in which a non-volatile memory cell can be programmed without first erasing the memory cell. NAND-type flash memory includes, for example, two-dimensional NAND memory (2D NAND) and three-dimensional NAND memory (3D NAND).

[0021] Each of the storage devices 130 can contain one or more arrays of memory cells. One type of memory cell, for example, single-level cells (SLCs), can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs), triple-level cells (TLCs), and quad-level cells (QLCs), can store multiple bits per cell. In some embodiments, each of the storage devices 130 can contain one or more arrays of memory cells, such as SLCs, MLCs, TLCs, QLCs, or any combination thereof. In some embodiments, a particular storage device can contain an SLC area and an MLC area, a TLC area, or a QLC area of ​​memory cells. The memory cells of the storage devices 130 can be grouped as pages that can reference a logical unit of the storage device used to store data. For some types of memory (e.g.,NAND) pages can be grouped to form blocks.

[0022] Although non-volatile memory components, such as a 3D cross-point array of non-volatile memory cells and NAND-type memory (e.g., 2D NAND, 3D NAND), are described, the memory device 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer-torque MRAM (STT-MRAM), conductive-bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), negative-OR flash memory (NOR flash memory), and electrically erasable programmable read-only memory (EEPROM).

[0023] A memory subsystem controller 115 (or controller 115 – for simplicity) can communicate with the memory devices 130 to perform operations such as reading, writing, or erasing data from the memory devices 130, as well as other such operations. The memory subsystem controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include a digital circuit with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 can be a microcontroller, a special logic circuit (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0024] The memory subsystem controller 115 can include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the example shown, the local memory 119 of the memory subsystem controller 115 comprises embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0025] In some embodiments, the local memory 119 can contain memory registers to store memory pointers, retrieved data, etc. The local memory 119 can also contain read-only memory (ROM) for storing microcode. Although the exemplary memory subsystem 110 in Fig. 1A is shown to contain the memory subsystem controller 115, in another embodiment of the present invention a memory subsystem 110 does not contain a memory subsystem controller 115 and can instead rely on external control (e.g. provided by an external host or by a processor or controller separate from the memory subsystem).

[0026] In general, the storage subsystem controller 115 can receive commands or operations from the host system 120 and translate these commands or operations into instructions or appropriate commands to achieve the desired access to the storage devices 130. The storage subsystem controller 115 can also be responsible for other operations, such as wear-leveling operations, garbage collection operations, error detection and correction (ECC) operations, encryption operations, caching operations, and address translations between a logical address (e.g., logical block address (LBA), namespace) and a physical address (e.g., physical block address) related to the storage devices 130.The storage subsystem controller 115 may further include a host interface circuit for communication with the host system 120 via the physical host interface. The host interface circuit can translate commands received from the host system into command instructions for accessing the storage devices 130 and translate responses related to the storage devices 130 into information for the host system 120.

[0027] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and addressing circuitry (e.g., a row decoder and a column decoder) that can receive an address from the memory subsystem controller 115 and decode the address to access the memory devices 130.

[0028] In some embodiments, the storage devices 130 comprise local media controllers 135 that work in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the storage devices 130. An external controller (e.g., the memory subsystem controller 115) can manage the storage device 130 externally (e.g., perform media management operations on the storage device 130). In some embodiments, a storage device 130 is a managed storage device, which is a raw storage device 130 with control logic (e.g., a local controller 135) on the chip and a controller (e.g., a memory subsystem controller 115) for media management within the same storage device package. An example of a managed storage device is a managed NAND device (MNAND).The storage device 130 can, for example, represent a single chip on which control logic (e.g., a local media controller 135) is implemented. In some embodiments, one or more components of the storage subsystem 110 can be omitted.

[0029] In one embodiment, the memory subsystem 110 includes a memory interface 113, which is responsible for handling interactions between the memory subsystem controller 115 and the memory devices of the memory subsystem 110, such as the memory device 130. For example, the memory interface 113 can send memory access commands to the memory device 130, corresponding to requests received from the host system 120, such as program commands, read commands, or other commands. Furthermore, the memory interface 113 can receive data from the memory device 130, such as data retrieved in response to a read command or confirmation that a program command was successfully executed. In some embodiments, the memory subsystem controller 115 includes at least a portion of the memory interface 113.For example, the memory subsystem controller 115 may have a processor 117 (processing device) configured to execute the instructions stored in the local memory 119 to perform the operations described herein.

[0030] In one embodiment, the local media controller 135 of the storage device 130 includes a program management component 150. The program management component 150 can implement dynamic program pulse widths for different subblocks in the memory array 104 of the storage device 130. For example, when a program operation is performed on memory cells in a specific subblock of a block of the storage device 130, the program management component 150 can identify a categorization of the subblock and determine a corresponding program pulse width. In one embodiment, the categorization can be based on the physical position of the subblock in the block (e.g., outermost, middle, innermost). Each categorization can have a different corresponding program pulse width, which can be predefined according to the specific parameters of the storage device 130.For example, the outermost subblocks may have a shorter program pulse width than the middle subblocks, which in turn may have a shorter program pulse width than the innermost subblocks. Once the appropriate program pulse width is identified, the program management component 150 can perform the program operation on the memory cells in the subblock using the identified program pulse width. Further details regarding the operations of the program management component 150 are described below.

[0031] Fig. Figure 1B is a simplified block diagram of a first device in the form of a storage device 130, which is connected to a second device in the form of a storage subsystem controller 115 of a storage subsystem (e.g., storage subsystem 110 from Fig. 1A) is connected, according to one embodiment. Examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, household appliances, vehicles, wireless devices, mobile phones, and the like. The memory subsystem controller 115 (e.g., a controller outside the memory device 130) can be a memory controller or another external host device. In one embodiment, the memory subsystem controller 115 includes a memory interface 113.

[0032] The storage device 130 comprises an array of memory cells 104, logically arranged in rows and columns. Memory cells of a logical row are typically connected to the same access line (e.g., a word line), while memory cells of a logical column are typically selectively connected to the same data line (e.g., a bit line). A single access line can be connected to more than one logical row of memory cells, and a single data line can be connected to more than one logical column. Memory cells (in Fig. (1B not shown) of at least one area of ​​the array of memory cells 104 can be programmed to one of at least two target data states.

[0033] A row decoder circuit 108 and a column decoder circuit 109 are provided to decode address signals. Address signals are received and decoded to access the array of memory cells 104. The storage device 130 further includes an input / output control circuit (I / O control circuit) 160 to manage the input of instructions, addresses, and data to the storage device 130, as well as the output of data and status information from the storage device 130. An address register 114 is connected to the I / O control circuit 160 and the row decoder circuit 108 and the column decoder circuit 109 to store the address signals before decoding. An instruction register 124 is connected to the I / O control circuit 160 and the local media controller 135 to store incoming instructions.

[0034] A controller (e.g., the local media controller 135 within the storage device 130) controls access to the array of memory cells 104 in response to instructions and generates status information for the external memory subsystem controller 115. That is, the local media controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on the array of memory cells 104. The local media controller 135 communicates with the row decoder circuit 108 and the column decoder circuit 109 to control the row decoder circuit 108 and the column decoder circuit 109 in response to addresses. In one embodiment, the local media controller 135 includes a program management component 150 that can implement dynamic program pulse widths for different subblocks in the memory array 104, as described here.

[0035] The local media controller 135 is also connected to a cache register 172. The cache register 172 stores incoming or outgoing data according to the instructions of the local media controller 135 to temporarily store data while the array of memory cells 104 is busy writing or reading other data. During a program operation (e.g., a write operation), data can be passed from the cache register 172 to the data register 170 for transfer to the array of memory cells 104; subsequently, new data can be temporarily stored in the cache register 172 by the I / O control circuit 160. During a read operation, data can be passed from the cache register 172 to the I / O control circuit 160 for output to the memory subsystem controller 115; subsequently, new data can be passed from the data register 170 to the cache register 172.The cache register 172 and / or the data register 170 can form a side buffer 162 of the storage device 130 (e.g., form a section thereof). The side buffer 162 can further contain measuring devices (in . Fig. (1B not shown), to capture a data state of a memory cell of the array of memory cells 104, e.g., by measuring a state of a data line connected to that memory cell. A status register 122 can be connected to the I / O control circuit 160 and the local memory controller 135 to store the status information for output to the memory subsystem controller 115.

[0036] The storage device 130 receives control signals at the storage subsystem control unit 115 from the local media controller 135 via a control link 182. These control signals can include, for example, a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protect signal WP#. Depending on the type of storage device 130, additional or alternative control signals (not shown) can be received via the control link 182. In one embodiment, the storage device 130 receives command signals (representing commands), address signals (representing addresses) and data signals (representing data) from the storage subsystem controller 115 via a multiplex input / output bus (I / O bus) 184 and outputs data to the storage subsystem controller 115 via the I / O bus 184.

[0037] For example, commands can be received via input / output pins (I / O pins) [7:0] of I / O bus 184 at I / O control circuit 160 and then written to command register 124. Addresses can be received via input / output pins (I / O pins) [7:0] of I / O bus 184 at I / O control circuit 160 and then written to address register 114. Data can be received via input / output pins (I / O pins) [7:0] for an 8-bit device or input / output pins (I / O pins) [15:0] for a 16-bit device at I / O control circuit 160 and then written to cache register 172. The data can then be written to data register 170 to program the array of memory cells 104.

[0038] In one embodiment, the cache register 172 can be omitted, and the data can be written directly to the data register 170. Data can also be output via input / output (I / O) pins [7:0] for an 8-bit device or input / output (I / O) pins [15:0] for a 16-bit device. Although reference can be made to I / O pins, these can include any conductive node that enables an electrical connection to the storage device 130 through an external device (e.g., the memory subsystem controller 115), such as conductive contacts or conductive bumps, as are commonly used.

[0039] Experts will recognize that additional circuits and signals may be provided, and that the storage device 130 consists of Fig. Figure 1B is simplified. It should be noted that the functionality of the various block components, which are referenced in Figure 1B, is not fully explained. Fig. The components described in 1B do not necessarily have to be divided among different components or component areas of an integrated circuit device. For example, a single component or component area of ​​an integrated circuit device could be designed to provide the functionality of more than one block component. Fig. 1B. Alternatively, one or more components or component areas of an integrated circuit device could be combined to provide the functionality of a single block component. Fig. 1B. It should also be noted that, although certain I / O pins are described according to common conventions for receiving and outputting the various signals, other combinations or numbers of I / O pins (or other I / O node structures) may be used in the various embodiments.

[0040] Fig. Figure 2 is a schematic representation of areas of an array of memory cells 104, for example a NAND memory array, as used in a memory of the with reference to Fig. The type described in 1B can be used according to one embodiment. The memory array 104 contains access lines, such as word lines 2020 to 202. N , and data lines, such as bit lines 2040 to 204 M The word lines 202 can be used with global access lines (e.g., global word lines) that are in Fig. 2, which are not shown, are connected in a many-to-one relationship. In some embodiments, the storage array 104 can be formed over a semiconductor, which may, for example, be conductively doped to have a certain type of conductivity, such as p-type conductivity to form, for example, a p-type well, or n-type conductivity to form, for example, an n-type well.

[0041] The memory array 104 can be arranged in rows (each corresponding to a word line 202) and in columns (each corresponding to a bit line 204). Each column can contain a string of serially connected memory cells (e.g., non-volatile memory cells), such as one of the NAND strings 2060 to 206. M Each NAND string 206 can be connected (e.g. selectively connected) to a common source (SRC) 216 and can represent memory cells 2080 to 208. N The memory cells 208 can represent non-volatile memory cells for storing data. The memory cells 208 of each NAND string 206 can be connected in series between a select gate 210 (e.g., a field-effect transistor), such as one of the select gates 2100 to 210. M(e.g., source-select transistors, commonly referred to as select-gate-source), and a select-gate 212 (e.g., a field-effect transistor), such as one of the select-gates 2120 to 212. M (e.g., drain-select transistors, commonly referred to as select-gate-drain). Select-gates 2100 to 210 M can be connected together with a Select line 214, for example a Source Select line (SGS), and the Select gates 2120 to 212 MThey can be connected together with a select line 215, for example, a drain select line (SGD). Although represented as conventional field-effect transistors, the select gates 210 and 212 can use a structure similar to (e.g., identical to) the memory cells 208. The select gates 210 and 212 can represent a number of select gates connected in series, with each select gate configured in series to receive an identical or independent control signal.

[0042] Each select gate 210 can have a source connected to a common source 216. Each select gate 210 can have a drain connected to a memory cell 2080 of the corresponding NAND string 206. For example, the drain of select gate 210 can be connected to memory cell 2080 of the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect a corresponding NAND string 206 to the common source 216. Each select gate 210 can have a control gate connected to the select line 214.

[0043] The drain of each select gate 212 can be connected to bit line 204 for the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to bit line 2040 for the corresponding NAND string 2060. The source of each select gate 212 can be connected to a memory cell 208. Nof the corresponding NAND string 206. For example, the source of the select gate 2120 can be connected to memory cell 208. N of the corresponding NAND string 2060. Therefore, each Select Gate 212 can be configured to selectively connect a corresponding NAND string 206 to the corresponding bit line 204. A Control Gate of each Select Gate 212 can be connected to the Select line 215.

[0044] The memory array 104 in Fig. 2 can be a quasi-two-dimensional memory array and can have a generally planar structure, where, for example, the common source 216, the NAND strings 206, and the bit lines 204 extend in essentially parallel planes. Alternatively, the memory array 104 can be in Fig. 2 a three-dimensional memory array wherein, for example, the NAND strings 206 can extend substantially perpendicular to a plane containing the common source 216, and can extend to a plane containing the bit lines 204, which can run substantially parallel to the plane containing the common source 216.

[0045] A typical design of memory cells 208 includes a data storage structure 234 (e.g., a floating gate, a charge trap, and the like) that can determine a data state of the memory cell (e.g., by changes in the threshold voltage), and a control gate 236, as shown in Fig. Figure 2 shows that the data storage structure 234 can comprise both conductive and dielectric structures, while the control gate 236 is generally formed from one or more conductive materials. In some cases, memory cells 208 can further have a defined source / drain (e.g., Source) 230 and a defined source / drain (e.g., Drain) 232. The memory cells 208 have their control gates 236 connected to (and in some cases form) a word line 202.

[0046] A column of memory cells 208 can be a NAND string 206 or a number of NAND strings 206 selectively connected to a particular bit line 204. A row of memory cells 208 can be memory cells 208 that are connected together to a particular word line 202. A row of memory cells 208 may, but need not, include all memory cells 208 that are connected together to a particular word line 202. Rows of memory cells 208 can often be subdivided into one or more groups of physical pages of memory cells 208, and physical pages of memory cells 208 often include every second memory cell 208 that is connected together to a particular word line 202. For example, the memory cells 208 that are connected together to word line 202 Nare connected and selectively connected to even-numbered bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.), be a physical side of the memory cells 208 (e.g., even-numbered memory cells), while memory cells 208, which are connected to the word line 202 N are connected and are selectively connected to odd-numbered bit lines 204 (e.g., bit lines 2041, 2043, 2045, etc.), and can be another physical side of the memory cells 208 (e.g., even-numbered memory cells).

[0047] Although the bit lines 2043-2045 in Fig. Although bit lines 2 are not explicitly shown, it can be seen from the figure that the bit lines 204 of the array of memory cells 104 run continuously from bit line 2040 to bit line 204. Mcan be numbered. Other groupings of memory cells 208 that are connected together to a particular word line 202 can also define a physical side of memory cells 208. In certain storage devices, all memory cells connected together to a particular word line can be considered a physical side of memory cells. The portion of a physical side of memory cells (which in some embodiments may still be the entire row) that is read during a single read operation or programmed during a single program operation (e.g., an upper or lower side of memory cells) can be considered a logical side of memory cells. A block of memory cells can include those memory cells that are configured to be erased together, such as all memory cells connected to word lines 2020-202. Nare connected (e.g., all NAND strings 206 that share common word lines 202). Unless explicitly stated otherwise, a reference to a page of memory cells here refers to the memory cells of a logical page of memory cells. Although the example in Fig. 2 in connection with NAND flash, the embodiments and concepts described here are not limited to a specific array architecture or array structure and can include other structures (e.g. SONOS, phase shift, ferroelectric, etc.) and other architectures (e.g. AND arrays, NOR arrays, etc.).

[0048] Fig. Figure 3 is a representation illustrating a block of a memory array with multiple subblocks, according to some embodiments of the present invention. Block 300 can be representative of any of the multiple blocks in the memory array 104. As shown, block 300 can comprise a number of subblocks (e.g., SB0-SB5). The number of subblocks can vary depending on the implementation, but may, for example, include 4 subblocks, 6 subblocks, 8 subblocks, or any other number of subblocks. Each subblock can include an associated control circuit that allows separate access to the subblocks, so that concurrent memory access operations can be performed in parallel on different subblocks.By including additional subblocks, the footprint of block 300 can be increased in the X-dimension, while by including additional bit lines, the footprint of block 300 can be increased in the Y-dimension. Although in . Fig. Block 300, not shown in Figure 3, also comprises a number of horizontal layers extending across the several subblocks SB0-SB5. Including these additional horizontal layers allows the height of Block 300 in the Z-dimension to be increased.

[0049] As described above, during the fabrication of the memory device, metal films can be diffused through the horizontal layers of block 300 to form access lines for the memory cells in the multiple subblocks SB0-SB5. In one implementation, the diffusion 310 generally begins at the edges of block 300 (i.e., first in contact with the outermost subblocks SB0 and SB5) and moves toward the center (i.e., through the middle subblocks SB1 and SB4 to the innermost subblocks SB2 and SB3). Therefore, the thickness of the metal layers may become uneven across the different subblocks. In one embodiment, the program management component 150 can use dynamic program pulse widths for the different subblocks to reduce the overall programming time and improve the performance of the memory device, as described in more detail below.

[0050] Fig. Figure 4 is a flowchart of an exemplary method for performing a program operation with dynamic program pulse widths for different subblocks in a storage device of a storage subsystem according to some embodiments of the present invention. The method 400 can be performed by processing logic that may include hardware (e.g., a processing device, circuits, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions executed or running on a processing device), or a combination thereof. In some embodiments, the method 400 is performed by the program management component 150. Fig. 1A and Fig. 1B. Although shown in a specific sequence or order, the order of the processes can be modified unless otherwise specified. Therefore, the embodiments shown are to be understood as examples only, and the processes shown can be carried out in a different order, with some processes being carried out in parallel. In addition, one or more processes can be omitted in different embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0051] Operation 405 initiates a program operation. For example, the processing logic (e.g., the program management component 150) can initiate a program operation with respect to one or more memory cells in a first subblock of a plurality of blocks in a memory array 104. In one embodiment, the memory array 104 comprises a plurality of memory cells located at the respective intersections of a plurality of word lines and a plurality of bit lines. These memory cells can be grouped into a number of subblocks, such as subblocks SB0-SB5, as shown in Fig. Figure 3 shows this. Depending on the embodiment, the program operation can be directed to memory cells in a single subblock or in several subblocks of a block, such as block 300.

[0052] Operation 410 identifies a subblock categorization. For example, the processing logic can identify a categorization of the first subblock or of the multiple subblocks targeted by the program operation. In one embodiment, block 300 comprises a number of subblocks, such as subblocks SB0-SB5, and each subblock has a corresponding associated categorization. In one embodiment, the categorization of the subblocks is based on a physical position of the subblocks within block 300. For example, the categorization can be an outermost subblock (e.g., SB0 or ​​SB5) located at an edge of block 300 (i.e., an edge where diffusion 310 begins), an innermost subblock (e.g., SB2 or SB3) located in the middle of block 300 (i.e., furthest from the edge), or a middle subblock (e.g.,SB1 or SB4) is located between the outermost subblock and the innermost subblock of block 300. In other embodiments, there may be a different number or different categorizations. For example, if a block had 8 subblocks, there could be several middle subblocks, each with its own categorization or grouped within the same categorization. In one embodiment, the subblocks are assigned a specific categorization during the manufacture of the storage device 130, and the categorizations are stored in local memory within the storage device 130, from which they can be retrieved by the program management component 150.

[0053] Operation 415 determines a corresponding program pulse width. For example, the processing logic can determine one or more corresponding program pulse widths for the subblock(s) based on the identified categorization(s). In one embodiment, each of the characterizations described above has a different corresponding program pulse width. In one embodiment, determining the corresponding program pulse width involves determining a predefined period, based on the categorization, for which a program voltage pulse is to remain at a peak voltage level (i.e., the plateau of the program voltage pulse that occurs after the signal has risen to the peak voltage level and before it falls back down). Fig. Figure 5 is a representation illustrating waveforms with dynamic program pulse widths for different subblocks in a storage device according to some embodiments of the present invention. In one embodiment, waveform 510 illustrates a short program pulse width (i.e., T_pgm_pulse_short), which may be related to the characterization of the outermost subblocks (e.g., SB0 and SB5), while waveform 520 illustrates a medium program pulse width (i.e., T_pgm_pulse_med), which may be related to the characterization of the middle subblocks (e.g., SB1 and SB4), and waveform 530 illustrates a long program pulse width (i.e., T_pgm_pulse_long), which may be related to the characterization of the innermost subblocks (e.g., SB2 and SB3).In one embodiment, the different program pulse widths are determined during the manufacture of the storage device 130 and stored in a local memory in the storage device 130, from where they can be retrieved by the program management component 150.

[0054] It will be revisited Fig. 4. Reference is made to step 420, in which a program voltage pulse is applied. For example, the processing logic can cause one or more program voltage pulses with the corresponding program pulse width(s) to be applied to one or more memory cells during the program operation. In one embodiment, each of the programming pulses is separated from the others by one or more verification operations and is applied to access lines (e.g., word lines) associated with selected memory cells in order to program the selected memory cells to respective target data states. After each programming pulse, one or more verification voltage levels are typically used to verify the programming of the selected memory cells.The programming typically uses many programming pulses in an incremental step-pulse programming (ISPP) scheme, where each programming pulse is a single-level pulse that shifts the limit voltage of the memory cell by a specified amount. In one embodiment, the processing logic can load a value specifying the corresponding program pulse width or pulse widths determined in Operation 415 into an associated register, thereby controlling the length of the predefined period for which the program voltage pulse is to remain at the peak voltage level (i.e., T_pgm_pulse length).The processing logic can repeat this process for any number of different program voltage pulses to be applied during the program operation, each pulse having a corresponding program pulse width based on the categorization of the subblock to which the program voltage pulse is applied.

[0055] Fig. Figure 6 shows an exemplary machine of a computer system 600 in which a set of instructions can be executed to cause the machine to perform one or more of the methodologies described herein. In some embodiments, the computer system 600 can be connected to a host system (e.g., the host system 120 from Fig. 1A) correspond to a memory subsystem (e.g., memory subsystem 110 from Fig. 1A) includes, is coupled to, or uses this, or can be used to perform operations of a controller (e.g., to run an operating system, to perform operations that are required by the program management component 150 or the local media controller 135) Fig. 1A). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine can function as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer network environment (or a distributed network environment), or as a server or client machine in a cloud computing infrastructure or environment.

[0056] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a web device, a server, a network router, a switch or bridge, or any other machine capable of executing a set of instructions (sequentially or otherwise) specifying actions to be performed by that machine. Furthermore, although a single machine is depicted, the term "machine" is to be understood as encompassing any grouping of machines that, individually or collectively, execute a set (or multiple sets) of instructions to perform one or more of the methodologies described herein.

[0057] The exemplary computer system 600 comprises a processing device 602, a main memory 604 (e.g., a read-only memory (ROM), a flash memory, a dynamic random-access memory (DRAM), such as a synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 606 (e.g., flash memory, static random-access memory (SRAM), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0058] The processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. In particular, the processing device may be a CISC (Complex Instruction Set Computing) microprocessor, a RISC (Reduced Instruction Set Computing) microprocessor, a VLIW (Very Long Instruction Word) microprocessor, or a processor implementing other sets of instructions, or processors implementing a combination of sets of instructions. The processing device 602 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like.The processing device 602 is configured to execute instructions 626 for performing the operations and steps described herein. The computer system 600 may also include a network interface device 608 for communication over the network 620.

[0059] The data storage system 618 may include a machine-readable storage medium 624 (also referred to as a computer-readable medium) on which one or more sets of instructions 626 or software embodying one or more of the methodologies or functions described herein are stored. The instructions 626 may also be stored, in whole or in part, in the main memory 604 and / or in the processing device 602 during their execution by the computer system 600, the main memory 604 and the processing device 602 also being machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 may be connected to the storage subsystem 110. Fig. 1A corresponds.

[0060] In one embodiment, the instructions comprise 626 instructions for implementing functionality that the program management component 150 provides. Fig.1A corresponds. Although the machine-readable storage medium 624 is shown in an exemplary embodiment as a single medium, the term “machine-readable storage medium” is to be understood as encompassing a single medium or multiple media that store the one or more sets of instructions. The term “machine-readable storage medium” is also to encompass any other medium capable of storing or encoding a set of instructions for execution by the machine and causing the machine to execute one or more of the methodologies described in the present disclosure. The term “machine-readable storage medium” is therefore to include, but not be limited to, solid-state storage media, optical media, and magnetic media.

[0061] Some parts of the preceding detailed descriptions have been presented in the form of algorithms and symbolic representations of operations concerning data bits in computer memory. These algorithmic descriptions and representations are those used by experts in the field of data processing to most effectively communicate the content of their work to other experts. An algorithm is understood here, and generally, as a consistent sequence of operations that leads to a desired result. The operations are those that require physical manipulations of physical quantities. Typically, though not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated.It has sometimes proven useful to refer to these signals as bits, values, elements, symbols, characters, terms, numbers or the like, mainly for reasons of general usage.

[0062] It should be noted, however, that all these and similar terms must be associated with the corresponding physical quantities and are merely simplified designations for these quantities. The present invention may relate to the actions and processes of a computer system or similar electronic computer device for manipulating data represented as physical (electronic) quantities in the registers and memories of the computer system and converting them into other data represented in a similar manner as physical quantities in the memories or registers of the computer system or in other such information storage systems.

[0063] The present invention also relates to a device for performing the operations described herein. This device may be specifically designed for the intended purposes or may contain a general-purpose computer that is selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of floppy disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROMs), random-access memory (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each being coupled to a computer system bus.

[0064] The algorithms and displays presented here are not inherently tied to any particular computer or other device. Various general-purpose systems can be used with programs according to the teachings contained herein, or it may prove advantageous to construct a more specialized device for carrying out the method. The structure for a multitude of such systems is presented in this description. Furthermore, the present invention is not described with reference to any particular programming language. It is understood that a multitude of programming languages ​​can be used to implement the teachings of the invention described herein.

[0065] The present invention can be provided as a computer program product or as software, which may include a machine-readable medium with instructions stored thereon that can be used to program a computer system (or other electronic devices) to perform a process according to the present invention. A machine-readable medium comprises any mechanism for storing information in a form that can be read by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium comprises a machine-readable (e.g., computer-readable) storage medium, such as read-only memory (“ROM”), random-access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory components, etc.

[0066] The preceding description describes embodiments of the invention with reference to specific exemplary embodiments. It is obvious that various modifications can be made to these without deviating from the general concept and scope of the embodiments of the invention, as set forth in the following claims. The description and the drawings should therefore be considered as illustrations rather than limitations.

Claims

[1] Storage device comprising: a memory array comprising a plurality of blocks; and a control logic that is functionally coupled to the memory array to perform operations, comprising: Initiating a program operation at one or more memory cells in a first subblock of one of the plurality of blocks of the memory array; Identifying a categorization of the first subblock; Determining an appropriate program pulse width based on the categorization of the first subblock; and To cause a program voltage pulse with the corresponding program pulse width to be applied to one or more memory cells during the program operation. [2] Storage device according to claim 1, wherein the categorization of the first subblock is based on a physical position of the first subblock within one of the plurality of blocks. [3] Storage device according to claim 1, wherein each of the plurality of blocks comprises a respective plurality of subblocks, and wherein each of the respective plurality of subblocks has a respective associated categorization. [4] Storage device according to claim 3, wherein each respective associated categorization has a different corresponding program pulse width. [5] Storage device according to claim 3, wherein each respective associated categorization comprises an outermost subblock located at an edge of one of the plurality of blocks, an innermost subblock located in the middle of one of the plurality of blocks, or a middle subblock located between the outermost subblock and the innermost subblock of one of the plurality of blocks. [6] Storage device according to claim 1, wherein determining the corresponding program pulse width comprises determining a predefined period based on the categorization of the first subblock for which the program voltage pulse is to remain at a peak voltage level. [7] Storage device according to claim 1, wherein causing the program voltage pulse with the corresponding program pulse width to be applied to one or more memory cells during the program operation comprises loading a value indicating the corresponding program pulse width into an associated register. [8] Procedures, comprehensive: Initiating a program operation at one or more memory cells in a first subblock of one of the plurality of blocks of a storage device; Identifying a categorization of the first subblock; Determining an appropriate program pulse width based on the categorization of the first subblock; and To cause a program voltage pulse with the corresponding program pulse width to be applied to one or more memory cells during the program operation. [9] Method according to claim 8, wherein the categorization of the first subblock is based on a physical position of the first subblock within one of the plurality of blocks. [10] Method according to claim 8, wherein each of the plurality of blocks comprises a respective plurality of subblocks, and wherein each of the respective plurality of subblocks has a respective associated categorization. [11] Method according to claim 10, wherein each respective associated categorization has a different corresponding program pulse width. [12] Method according to claim 10, wherein each respective associated categorization comprises an outermost subblock located at an edge of one of the plurality of blocks, an innermost subblock located in the middle of one of the plurality of blocks, or a middle subblock located between the outermost subblock and the innermost subblock of one of the plurality of blocks. [13] Method according to claim 8, wherein determining the corresponding program pulse width comprises determining a predefined period based on the categorization of the first subblock for which the program voltage pulse is to remain at a peak voltage level. [14] Method according to claim 8, wherein causing the program voltage pulse with the corresponding program pulse width to be applied to one or more memory cells during the program operation comprises loading a value indicating the corresponding program pulse width into an associated register. [15] Storage device comprising: a memory array comprising a plurality of blocks; and a control logic that is functionally coupled to the memory array to perform operations, comprising: Initiating a program operation at one or more memory cells in each of a plurality of subblocks of one of the plurality of blocks of the memory array; Identifying the respective categorizations of each of the majority of subblocks; Determining the respective program pulse widths for each of the majority of subblocks based on the respective categorizations; and Causing a plurality of program voltage pulses with the respective program pulse widths to be applied to one or more memory cells during the program operation. [16] Storage device according to claim 15, wherein the respective categorizations of each of the plurality of subblocks are based on physical positions of the plurality of subblocks within one of the plurality of blocks. [17] Storage device according to claim 15, wherein each respective categorization has a different corresponding program pulse width. [18] Storage device according to claim 15, wherein each categorization comprises an outermost subblock located at an edge of one of the plurality of blocks, an innermost subblock located in the middle of one of the plurality of blocks, or a middle subblock located between the outermost subblock and the innermost subblock of one of the plurality of blocks. [19] Storage device according to claim 15, wherein determining the corresponding program pulse widths for each of the plurality of subblocks comprises determining respective predefined periods based on the respective categorizations for which a corresponding program voltage pulse is to remain at a peak voltage level. [20] Storage device according to claim 15, wherein the plurality of program voltage pulses with the respective program pulse widths to be applied to the one or more memory cells comprises loading respective values ​​specifying the respective program pulse widths into an associated register.

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