Embedded power semiconductor package with sidewall contacts

Abstract

A method of forming a semiconductor package includes providing a lead frame including a metal frame at least partially surrounding a central opening and a plurality of connecting bars connected between the metal frame and an adjacent stabilizing metal section, disposing the lead frame on a temporary support, disposing a semiconductor die on the temporary support within the central opening, forming a dielectric material filling the central opening and encapsulating the semiconductor die, forming a first recess in the dielectric material over the semiconductor die to expose a first surface of the semiconductor die, electrically connecting terminals of the semiconductor die to the metal frame, and forming exposed external contacts of the semiconductor package from the connecting bars.

Description

background

[0001] Semiconductor power device packages are used in many applications, such as automotive and industrial applications. A semiconductor power device package may include one or more discrete power semiconductor devices rated to drive large voltages and / or currents, e.g., MOSFETs (metal-oxide-semiconductor field-effect transistors), IGBTs (insulated-gate bipolar transistors), diodes, etc., and in some cases may include driver devices configured to drive the discrete power semiconductor devices. Different types of package configurations are used for power applications. One type of package configuration used in power applications is an embedded package. An embedded package embeds a die in a PCB-like structure that both encapsulates the die and provides electrical connection to externally accessible bond pads.It is desirable to improve the performance, cost and manufacturability of embedded packages. Summary

[0002] A method of forming a semiconductor package is disclosed. According to one embodiment, the method comprises providing a lead frame comprising a metal frame at least partially surrounding a central opening and a plurality of tie bars connected between the metal frame and an adjacent stabilizing metal section; disposing the lead frame on a temporary support; disposing a semiconductor die on the temporary support within the central opening; forming a dielectric material filling the central opening and encapsulating the semiconductor die; forming a first recess in the dielectric material over the semiconductor die to expose a first surface of the semiconductor die; electrically connecting terminals of the semiconductor die to the metal frame; and forming exposed external contacts of the semiconductor package from the tie bars.

[0003] A semiconductor package is disclosed. According to one embodiment, the semiconductor package comprises a metal frame forming an at least partially enclosed shape around a central opening; severed connecting bars connected to the metal frame; a semiconductor die disposed within the central opening; and a dielectric material filling the central opening and encapsulating the semiconductor die, wherein terminals of the semiconductor die are electrically connected to the metal frame, and wherein the semiconductor package comprises exposed external contacts of the semiconductor package formed from the severed connecting bars. Short description of the characters

[0004] The elements of the drawings are not necessarily to scale relative to one another. Like reference numerals indicate corresponding similar parts. The features of the various illustrated embodiments may be combined, provided they are not mutually exclusive. Embodiments are illustrated in the drawings and are described in detail in the following description. Fig. 1, which the Fig. 1A and Fig. 1B illustrates a power semiconductor package according to one embodiment. Fig. 1A shows a cross-sectional view of the power semiconductor package and Fig. Figure 1B shows a side view perspective of the power semiconductor package. Fig. 2, which the Fig. 2A and Fig. 2B illustrates a power semiconductor package according to one embodiment. Fig. 2A shows a cross-sectional view of the power semiconductor package and Fig. Figure 2B shows a side view perspective of the power semiconductor package. Fig. 3, which the Fig. 3A and Fig. 3B illustrates a power semiconductor package according to one embodiment. Fig. Figure 3A shows a cross-sectional view of the power semiconductor package and Fig. Figure 3B shows a side view perspective of the power semiconductor package. Fig. 4 illustrates a lead frame used to form a power semiconductor package, according to one embodiment. Fig. 5, which the Fig. 5A, Fig. 5B, Fig. 5C, Fig. 5D, Fig. 5E, Fig. 5F, Fig. 5G, Fig. 5H and Fig. 5l illustrates selected process steps in a method of forming a semiconductor package according to one embodiment. Fig. 6 illustrates a power semiconductor package from a cross-sectional perspective according to one embodiment. Detailed description

[0005] Embodiments of a power semiconductor package with an advantageous contact configuration and corresponding methods for forming the power semiconductor package are disclosed herein. The power semiconductor package comprises one or more semiconductor dies embedded within the package and connected to externally accessible bond pads. The power semiconductor package is formed by providing a metal frame at least partially surrounding a central opening. One or more semiconductor dies are arranged within the central opening and encapsulated with a dielectric material. The metal frame provides a cost-effective solution for forming an embedded package structure.The metal frame may be configured as a vertical via structure providing electrical connection between a backside terminal of the semiconductor die and a bond pad disposed at a lower interface side of the semiconductor package. The metal frame is provided by a leadframe structure with connecting rods connected between the metal frame and an adjacent stabilizing structure. Advantageously, the connecting rods, which mechanically support the metal frame during package assembly, are integrated into the final package structure and form exposed external contacts of the power semiconductor package. The method advantageously reduces processing costs by eliminating the need to remove or otherwise isolate the connecting rods from the external environment.In addition, the exposed surfaces of the connecting rods can advantageously form so-called LTI (conductor tip inspection) features.

[0006] With reference to Fig. 1, a semiconductor package 100 includes a metal frame 102. The metal frame 102 may include an electrically conductive metal such as copper, aluminum, nickel, silver, palladium, gold, etc., and alloys thereof. The metal frame 102 may include a core metal region and one or more cladding layers used for protection, adhesion, corrosion protection, etc., formed on the core metal region. The metal frame 102 forms an at least partially enclosed shape around a central opening 104. From a top view perspective of the metal frame 102, the metal frame 102 defines a shape of the central opening 104. The description of the metal frame 102 forming an at least partially enclosed shape refers to the fact that there may be one or more interruptions in the continuity of the metal frame 102 such that the central opening 104 is not completely enclosed by the metal frame 102.For example, as in . Fig. 4, the metal frame 102 forms a partially enclosed shape around the central opening 104 with a discontinuity on one side of the metal frame 102. In other embodiments, there may be multiple discontinuities in the metal frame 102. In still other embodiments, there may be no discontinuities in the metal frame 102, i.e., the metal frame 102 forms a fully enclosed shape around the central opening 104. Provided that the metal frame 102 is adjacent to at least 50% of the overall diameter of the central opening 104, with the remaining diameter of the central opening 104 defined by intersecting planes along which inner edge sides of the metal frame 102 extend, the metal frame 102 forms a partially enclosed shape around a central opening 104 within the meaning of the present description.

[0007] With further reference to Fig. 1, the semiconductor package 100 includes a semiconductor die 106 disposed within the central opening 104 of the metal frame 102. Generally speaking, the semiconductor die 106 may be configured as any type of device. According to one embodiment, the semiconductor die 106 is configured as a power device, i.e., a device rated to receive voltages of 100 V (volts), 600 V, 1200 V, or more and / or rated to receive currents of at least 1 A (ampere), 10 A, 50 A, 100 A, or more. Examples of these power devices include MOSFETs (metal oxide semiconductor field-effect transistors), HEMTs (high electron mobility transistors), IGBTs (insulated gate bipolar transistors), JFETs (junction field-effect transistors), and diodes. The semiconductor die 106 may be formed in any device technology and may comprise IV semiconductor materials, e.g., silicon, silicon germanium, silicon carbide, etc., and / or Type III-V semiconductor materials, e.g., gallium nitride, gallium arsenide, etc. According to one embodiment, the semiconductor die 106 is configured as a vertical device configured to conduct a vertical current between a first load terminal 108 and a second load terminal 110. The first and second load terminals 108, 110 are the voltage-blocking terminals of the device. For example, the first and second load terminals 108, 110 may correspond, respectively, to the drain and source terminals (or vice versa) of a MOSFET, may correspond to the collector and emitter terminals (or vice versa) of an IGBT, and so on. As shown, the semiconductor die 106 has a first surface facing a top side 112 of the semiconductor package 100 and a second surface facing a bottom side 114 of the semiconductor package 100, i.e.a side of the semiconductor package 100 that mates with an external carrier, such as a PCB (printed circuit board). The first surface of the illustrated semiconductor die 106 corresponds to a back surface of the semiconductor die 106, which includes the second load terminal 110, and the second surface of the illustrated semiconductor die 106 corresponds to the main surface of the semiconductor die 106, which includes the first load terminal 108 and a gate terminal 116. The gate terminal 116 is configured to control a conductive connection between the first and second load terminals 108, 110 in a generally known manner.

[0008] The semiconductor package 100 may be configured to form a power switching device that is part of a power conversion circuit. For example, the semiconductor package 100 may be configured as the high-side switch or the low-side switch of a half-bridge circuit. A half-bridge circuit refers to a type of circuit topology used in a power conversion circuit, such as a DC-DC converter, DC-AC converter, etc. Instead of the single die configuration as shown, the semiconductor package 100 may have a multi-die configuration. For example, the semiconductor package 100 may include two power semiconductor device dies that form the high-side switch and the low-side switch of a half-bridge circuit, respectively. These semiconductor dies may be arranged within the opening or within different openings 104 of a metal frame.Separately or in combination, semiconductor package 100 may include additional semiconductor dies that are not configured as power dies, e.g., low-voltage and / or logic devices. For example, semiconductor package 100 may include a driver die disposed within another opening of metal frame 102 and encapsulated according to the technique described below, wherein the driver die is configured to control switching of semiconductor dies configured as power switching devices.

[0009] The semiconductor package 100 includes a dielectric material 118 that fills the central opening 104 and encapsulates the semiconductor die 106. The dielectric material 118 may comprise a resin material such as bismaleimidetrazine (BT) resin, a prepreg material such as FR-4, FR-5, CEM-4, or other types of encapsulation material. The dielectric material 118 may be formed as part of a lamination process, wherein multiple constituent laminate layers are stacked upon one another. An example of a lamination process is described below.

[0010] According to one embodiment, at least one of the terminals of the semiconductor die 106 is electrically connected to the metal frame 102. In this way, the metal frame 102 can serve as a via structure that provides electrical connectivity between the back surface of the semiconductor die 102 and the bottom side 114 of the semiconductor package 100. In the illustrated embodiment, the second load terminal 110 of the semiconductor die 106 is electrically connected to the metal frame 102 and is thus electrically accessible at the bottom side 114 of the semiconductor package 100. The semiconductor package 100 includes a first metallization layer 120 formed on the top side 112 of the semiconductor package 100 and forming the electrical connection between the second load terminal 110 and the metal frame 102. The electrical connection is enabled by the formation of recesses in the dielectric material 118.More specifically, a first recess 122 is formed in the dielectric material 118 over the back surface of the semiconductor die 106. The second load terminal 110 of the semiconductor die 106 is exposed through the first recess 122. Additionally, second recesses 124 are formed in the dielectric material 118 over the metal frame 102. Each of the second recesses 122 exposes a top surface of the metal frame 102, thereby enabling a metal connection thereto. The first metallization layer 120 is conformally deposited on the dielectric material 118, thereby forming the electrical connection to the second load terminal 110 and the metal frame 102. The semiconductor package 100 additionally includes a second metallization layer 126 formed on the bottom side 114 of the semiconductor package 100.The second metallization layer 126 is formed directly on the first load terminal 108, the gate terminal 116, and the metal frame 102 and forms separate and externally accessible bond pads of the semiconductor package 100. These bond pads can mate with an external carrier, such as a PCB or a power electronics substrate, e.g., an AMB (Active Metal Brazed) substrate, an IMS (Insulated Metal Substrate), etc., e.g., by soldering the bond pads to corresponding metal pads. The semiconductor package 100 additionally includes a solder mask 128 on the lower interface side of the semiconductor package 100 to electrically isolate each of the bond pads and facilitate direct board mounting of the semiconductor package 100. The solder mask 128 may comprise a solder resist material such as a varnish, an epoxy, a liquid photoimageable solder mask 128, a photoimageable dry film solder mask 128, etc.

[0011] The semiconductor package 100 is configured with exposed external contacts 130 arranged on the outer edge side of the semiconductor package 100. The exposed external contacts 130 extend transversely to the bottom side 114 of the semiconductor package 100. The exposed external contacts 130 can serve as LTI (Loop Tip Inspection) features. The LTI features enable optical inspection of a solder joint when the semiconductor package 100 is mounted on an external device, such as a printed circuit board, by exposing the metal solder interface on the outer edge side of the package. Separately or in combination, the exposed external contacts 130 can provide additional electrical contact points available for electrical contact with the external environment when the semiconductor package 100 is mounted on an external carrier.

[0012] According to one embodiment, the outer contacts 130 are formed by connecting rods 132. The connecting rods 132 are metal structures used to mechanically support the metal frame 102 during package construction and prior to encapsulation. As shown in Fig. 4, the semiconductor package 100 may be fabricated from a lead frame 200 having a plurality of metal frames 102, each defining one of the central openings 104. A plurality of connecting bars 132 extend between each of the metal frames 102 and an adjacent stabilizing metal section of the lead frame 200.

[0013] The embodiments disclosed herein configure the semiconductor package 100 such that at least portions of the connecting bars 132 remain intact, i.e., the connecting bars 132 are not trimmed or otherwise completely removed. The remaining portions of the connecting bars 132 are exposed at the outer edge side of the semiconductor package 100, thereby forming the exposed external contacts 130 that extend transversely to the bottom interface side of the semiconductor package 100. According to one embodiment, the exposed external contacts 130 comprise sidewall surfaces of the connecting bars 132. These sidewall surfaces may correspond to surfaces of the connecting bars 132 that are severed during a package singulation process, e.g., etching, laser ablation, mechanical drilling, etc., as described in more detail below.Alternatively, these sidewall surfaces may correspond to surfaces of the connecting bars 132, which are etched prior to package singulation, as described in more detail below. As shown in . Fig. 1B, the outer edge sides of the semiconductor package 100 may include a plurality of the outer contacts 130 provided by individual connecting bars 132, each of these individual structures of the connecting bars 132 forming a connection to the internally disposed metal frame 102.

[0014] According to one embodiment, the exposed outer contacts 130 additionally include bottom surfaces of the connecting bars 132 that intersect the sidewall surfaces of the connecting bars 132. As in Fig. For example, as shown in Figure 1A, bottom surfaces of the connecting bars 132 extend to the outer edge side of the semiconductor package 100 and intersect a sidewall surface of the connecting bar 132 extending transversely to the bottom side 114 of the semiconductor package 100. In this way, the connecting bars 132 may form a complete LTI feature of the semiconductor package 100, enabling inspection at the corner of the package terminal.

[0015] With reference to Fig. 2, a semiconductor package 100 according to one embodiment is shown. The semiconductor package 100 is similar to that of Fig. 1, except that the connecting rods 132 are thinner than the metal frame 102 surrounding the central opening 104. In this case, the lead frame 200 used to form the semiconductor package 100 has been processed to remove metal from the connecting rod portions of the lead frame 200. As a result, the exposed outer contacts 130 of the semiconductor package 100 formed by the connecting rods 132 have less vertical extension, such as in Fig. 2B. The dielectric material 118 is formed over the connecting rods 132 with a reduced thickness, thereby maintaining the shape of the semiconductor package 100.

[0016] With reference to Fig. 3, a semiconductor package 100 according to one embodiment is shown. The semiconductor package 100 is similar to that of Fig. 2, except that the connecting bars 132 were processed through an etching process prior to a package singulation step. As a result, the outer contacts 130 of the semiconductor package 100 formed by the connecting bars 132 correspond to the etched surfaces of the connecting bars 132. As shown, these etched surfaces may have a curved shape and create a depression at the lower outer corner of the etched semiconductor surfaces. This curved shape of the exposed outer contacts 130 may improve solderability and / or lead tip inspection.

[0017] With reference to Fig. 4, a lead frame 200 used to form a plurality of semiconductor packages 100 is shown according to one embodiment. The lead frame 200 may be provided from a sheet metal of electrically conductive metals such as copper, aluminum, nickel, silver, palladium, gold, etc., and alloys thereof. The lead frame 200 may include a core metal region and one or more plating layers on the core metal region used for protection, adhesion, corrosion protection, etc. The geometry of the lead frame 200 may be created by metal processing techniques, e.g., stamping, punching, cutting, etc. As shown, the lead frame 200 includes a plurality of metal frames 102, each defining one of the central openings 104. Each of the metal frames 102 is physically connected to an adjacent stabilizing metal section by the connecting bars 132.The adjacent stabilizing metal section may refer to an outer peripheral structure of the lead frame 200 that is adjacent to the outermost of the metal frames 102. The adjacent stabilizing metal section may also refer to adjacent ones of the metal frames 102 that are immediately adjacent to each other. The connecting rods 132 maintain the structural integrity of the lead frame 200 during processing and prior to package singulation.

[0018] With reference to Fig. 5, selected method steps for forming semiconductor packages 100 according to various embodiments are shown. Each of the figures shows a first package assembly 200 on the left side of the figure, a second package assembly 202 in the middle of the figure, and a third package assembly 204 on the right side of the figure. The method steps performed on the first package assembly 200 can be used to form the semiconductor package 100 described with reference to Fig. 1. The method steps performed on the second package assembly 202 can be used to manufacture the semiconductor package 100 described with reference to Fig. 2. The method steps performed on the third package assembly 204 can be used to manufacture the semiconductor package 100 described with reference to Fig. 3 to produce the semiconductor package 100 described.

[0019] With reference to Fig. 5A, a lead frame 200 is provided. The lead frame 200 may be similar to the one described with reference to Fig. 4. The first package assembly 200, the second package assembly 202, and the third package assembly 204 each represent a section of a package site of the lead frame 200, wherein one of the metal frames 102 and the corresponding connecting bars 132 are connected to the metal frame 102. In the case of the first package assembly 200, the lead frame 200 is provided with the connecting bars 132 and the metal frame 102 having the same thickness. In the case of the second package assembly 202 and the third package assembly 204, the lead frame 200 is provided such that the connecting bars 132 have a reduced thickness compared to the metal frame 102. For example, a half-etching step may be performed on the lead frame 200.Half-etching refers to a technique in which a metal structure, such as a lead frame, is partially etched to selectively reduce the thickness of the structure in certain features. Generally, the half-etching step may reduce the thickness of the lead frame 200 by at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, etc. Accordingly, the thickness of the connecting bars 132 may be at least 70%, at least 60%, at least 50%, at least 40%, at least 30%, etc. of the metal frame 102.

[0020] With reference to Fig. 5B, the lead frame 200 is placed on a temporary carrier 202. Generally speaking, the temporary carrier 202 can be any planar surface suitable for handling and transferring electronic components through various semiconductor processing tools. In one example, the temporary carrier 202 includes a thermal release tape.

[0021] With reference to Fig. 5C, a semiconductor die 106 is disposed on the temporary carrier 202. The semiconductor die 106 is positioned within the central opening 104 of the metal frame 102 and is spaced from the metal frame 102 in each direction. The semiconductor die 106 may have any of the device configurations described above.

[0022] With reference to Fig. 5D, a dielectric material 118 is formed to fill the metal central opening 104 and encapsulate the semiconductor die 106. As shown, the dielectric material 118 is formed to fill the lateral space between the semiconductor die 106 and the metal frame 102. Additionally, the dielectric material 118 is initially formed to completely cover the semiconductor die 106 and the metal frame 102. According to one embodiment, the dielectric material 118 is formed by a lamination technique. Lamination refers to a process in which multiple constituent layers of dielectric material 118 are sequentially formed. For example, the lamination technique may include forming a resin region, such as bismaleimidetrazine (BT) resin, that secures the central opening 104, which encapsulates and secures the semiconductor die 106 within the metal frame 102.One or more additional constituent layers of dielectric material 118 may be formed on this resin. These additional constituent layers may comprise a prepreg material such as FR-4, FR-5, CEM-4, etc.

[0023] With reference to Fig. 5E, recesses are formed in the dielectric material 118. More specifically, the first recess 122 is formed in the dielectric material 118 over the back surface of the semiconductor die 106, thereby exposing the second load terminal 110 of the semiconductor die 106 (in Fig. 5 (not shown). Additionally, the second recesses 124 are formed in the dielectric material 118 above the metal frame 102, thereby exposing the top surface of the metal frame 102. In general, the first and second recesses 122, 124 may be formed by a variety of techniques, e.g., etching, laser ablation, mechanical drilling, etc.

[0024] With reference to Fig. 5F, the temporary carrier 202 is removed from the bottom sides of the package assembly. Due to the cured dielectric material 118, each semiconductor assembly can remain intact in further processing steps without the need for the temporary carrier 202. In the case where the temporary carrier 202 is a thermal release tape, this removal may involve heating the assembly to the appropriate temperature and peeling the thermal release tape from the assembly.

[0025] With reference to Fig. 5G, an additional etching process is performed only on the third package assembly 204, which is shown on the right side of the figures. Thus, the additional etching process of Fig. 5G may be omitted from the process sequences performed on the first and second package assemblies 200, 202. The additional etch process removes material from the lead frame 200 near the connecting bars 132, thereby creating the recess and curved surfaces of the connecting bars 132 as described above. At this time, the adjacent package locations remain mechanically connected to each other by the dielectric material 118.

[0026] With reference to Fig. 5H, metallization processing steps are performed. These metallization processing steps form the first metallization layer 120 and the second metallization layer 126 of the semiconductor package 100, as described above. The first metallization layer 120 and the second metallization layer 126 may be formed by metal plating processes, such as electroplating and electroless plating. As shown, the first metallization layer 120 may be conformally deposited to contact the semiconductor die 106 and the metal frame 102 and extend along the surface of the dielectric material 118. On the bottom side 114 of the semiconductor package 100, the second metallization layer 126 may be patterned to form isolated bond pads. This may be done by selectively blocking the deposition of metal or by performing a subsequent etch of the deposited metal.

[0027] With reference to Fig. 5I, solder mask regions 128 are formed. The solder mask regions 128 are formed between the lateral spaces of the first and second metallization layers 120, 126 where these layers are not present. The solder mask regions 128 may be formed by screen printing a liquid solder mask material 128. After forming the solder mask 128, additional processing steps may be performed to complete the semiconductor package 100. These additional processing steps may include, for example, cleaning steps. Separately or in combination, additional processing steps may be performed to improve the surface qualities of the metallization, e.g., protection, solderability, etc. For example, an ENEPIG process (ENEPIG = Electroless Nickel Electroless Palladium Immersion Gold) may be performed to improve solderability and reduce oxidation.

[0028] After carrying out the procedure described with reference to Fig. 5A-5I, a package dicing step is performed to create individual semiconductor packages 100 from the first, second, and third package assemblies 200, 202, 204. The package dicing step includes a dicing process that divides the physically connected semiconductor package 100 assemblies into individual semiconductor packages 100. This dicing process may be performed by a variety of techniques, e.g., mechanical sawing, etching, laser ablation, etc. In the case of the first and second package assemblies 200, 202, the dicing process separates both the connecting bars 132 and the dielectric material 118 over the connecting bars 132, thereby creating outer sides of the package with planar exposed outer contacts 130 and dielectric material 118 that is planar coplanar with the exposed outer contacts 130.In the case of the third package assembly 204, the dicing process separates the dielectric material 118 between the sides of the semiconductor package 100, creating outer sides of the package with a planar surface of the dielectric material 118 and curved surfaces of the connecting rods 132, i.e., the previously etched surfaces that curve inward from the dielectric material 118.

[0029] With reference to Fig. 6, a semiconductor package 100 according to one embodiment is shown. The semiconductor package 100 is similar to that of Fig.1, except that it includes a metal interconnect 134 extending directly between the semiconductor die 106 and the metal frame 102. This metal interconnect 134 is disposed below a top surface of the metal frame 102. Thus, the metal interconnect 134 forms a direct metal path from the semiconductor die 106 to the metal frame 102, which is located below the top surface of the dielectric material 118. The metal interconnect 134 forms a thermally conductive path between the semiconductor die 106 and the metal frame 102, thereby improving the heat dissipation capability of the semiconductor package 100. The metal interconnect 134 may also form an electrically conductive connection between the semiconductor die 106 and the metal frame 102. For example, the second terminal 110 of the semiconductor die 106 may be electrically connected to the metal interconnect 134, e.g.by a metallization formed on the back surface of the semiconductor die 106 or by a sidewall connection of the semiconductor die 106. This creates a shorter distance and a lower electrical resistance path than the connection provided by the first metallization layer 120. Thus, the metal connection 134 can complement or replace the connection between the second load terminal 110 and the metal frame 102 provided by the first metallization layer 120.

[0030] The metal interconnect 134 may be provided by placing or forming metal between the semiconductor die 106 and the metal frame 102 prior to the formation of the dielectric material 118. For example, the metal interconnect may be provided by plated metal regions 134 formed on the side of the semiconductor die 106 and the lead frame 102. The metal interconnect 134, which extends directly between the semiconductor die 106 and the metal frame 102, may be integrated into one of the embodiments of the semiconductor package 100 disclosed herein. Optionally, the metal interconnect 134 may be provided between electrically insulating structures (as shown). These electrically insulating structures may correspond to solder mask material used to fill holes between the metal structures of the metal interconnect 134.

[0031] Although the present disclosure is not so limited, the following numbered examples illustrate one or more aspects of the disclosure.

[0032] Example 1. A method of forming a semiconductor package, the method comprising: providing a lead frame comprising a metal frame at least partially surrounding a central opening and a plurality of bonding bars connected between the metal frame and an adjacent stabilizing metal section; disposing the lead frame on a temporary support; disposing a semiconductor die on the temporary support within the central opening; forming a dielectric material filling the central opening and encapsulating the semiconductor die; forming a first recess in the dielectric material over the semiconductor die to expose a first surface of the semiconductor die; electrically connecting terminals of the semiconductor die to the metal frame; and forming exposed external contacts of the semiconductor package from the bonding bars.

[0033] Example 2. The method of Example 1, wherein the exposed outer contacts comprise sidewall surfaces of the connecting rods.

[0034] Example 3. The method of Example 2, wherein the exposed outer contacts further comprise bottom surfaces of the connecting bars that intersect the sidewall surfaces of the connecting bars.

[0035] Example 4. The method of Example 1, further comprising performing a package dicing process that separates the connecting bars from the adjacent stabilizing metal section, and wherein the exposed outer contacts are provided from severed surfaces of the connecting bars.

[0036] Example 5. The method of Example 1, further comprising performing an etching process that removes material from the connecting bars, and wherein the exposed external contacts are provided by surfaces of the connecting bars that are etched by the etching process.

[0037] Example 6. The method of Example 1, wherein the semiconductor die is configured as a vertical power transistor configured to conduct a vertical current between a first load terminal and a second load terminal, wherein the first surface of the semiconductor die is a back surface of the semiconductor die having the second load terminal, wherein electrically connecting terminals of the semiconductor die to the metal frame comprises forming a first metallization layer on a top side of the semiconductor package electrically connecting the second load terminal to the metal frame, and wherein the exposed external contacts form a conductor tip inspection feature electrically connected to the second load terminal of the semiconductor die.

[0038] Example 7. The method of example 1, wherein the lead frame is provided such that the connecting bars are thinner than the metal frame, and wherein forming the dielectric material fills a region between a top surface of the connecting bars and a top surface of the metal frame.

[0039] Example 8. The method of Example 1, further comprising forming a metal interconnect extending directly between the semiconductor die and the metal frame, wherein the metal interconnect is disposed below a top surface of the metal frame.

[0040] Example 9. The method of example 8, wherein the metal interconnect electrically connects a terminal from the first surface of the semiconductor die to the metal frame.

[0041] Example 10. A semiconductor package comprising: a metal frame forming an at least partially enclosed shape around a central opening; severed connecting bars connected to the metal frame; a semiconductor die disposed within the central opening; and a dielectric material filling the central opening and encapsulating the semiconductor die, wherein terminals of the semiconductor die are electrically connected to the metal frame, and wherein the semiconductor package has exposed external contacts of the semiconductor package formed from the severed connecting bars.

[0042] Example 11. The semiconductor package of Example 10, wherein the exposed outer contacts comprise sidewall surfaces of the severed connecting rods.

[0043] Example 12. The semiconductor package of Example 11, wherein the exposed external contacts further comprise bottom surfaces of the severed connecting bars that intersect the sidewall surfaces of the severed connecting bars.

[0044] Example 13. The semiconductor package of example 10, wherein a first recess is formed in the dielectric material over a first surface of the semiconductor die.

[0045] Example 14. The semiconductor package of example 13, wherein the semiconductor die is configured as a vertical power transistor configured to conduct a vertical current between a first load terminal and a second load terminal.

[0046] Example 15. The semiconductor package of example 14, wherein the first surface of the semiconductor die is a back surface of the semiconductor die having the second load terminal, the semiconductor package having a first metallization layer on a top side of the semiconductor package electrically connecting the second load terminal to the metal frame, and the exposed external contacts forming a conductor tip inspection feature electrically connected to the second load terminal of the semiconductor die.

[0047] Example 16. The semiconductor package of example 10, wherein the severed connecting bars are thinner than the metal frame, and wherein the dielectric material fills a region between a top surface of the severed connecting bars and a top surface of the metal frame.

[0048] Example 17. The semiconductor package of Example 10, further comprising a metal interconnect extending directly between the semiconductor die and the metal frame, the metal interconnect being disposed below a top surface of the metal frame.

[0049] Example 18. The semiconductor package of example 17, wherein the metal interconnect electrically connects a terminal from the first surface of the semiconductor die to the metal frame.

[0050] Spatially relative terms such as "below," "under," "lower," "above," "upper," and the like are used for convenience of description to explain the positioning of one element relative to a second element. These terms are intended to encompass various orientations of the device in addition to different orientations than those illustrated in the figures. Furthermore, terms such as "first," "second," and the like are also used to describe various elements, regions, sections, etc., and are also not intended to be limiting. Like terms refer to like elements throughout the description.

[0051] As used herein, the terms "having," "containing," "including," "comprising," and the like are open-ended terms that indicate the presence of specified elements or features but do not preclude additional elements or features. The articles "a," "an," and "the" are intended to include both the plural and singular unless the context clearly indicates otherwise.

[0052] Considering the above range of variations and applications, it is to be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.

Claims

[1] A method of forming a semiconductor package, the method comprising: Providing a lead frame comprising a metal frame at least partially surrounding a central opening and a plurality of connecting rods connected between the metal frame and an adjacent stabilizing metal section; Placing the ladder frame on a temporary support; Placing a semiconductor die on the temporary carrier within the central opening; Forming a dielectric material that fills the central opening and encapsulates the semiconductor die; Forming a first recess in the dielectric material over the semiconductor die to expose a first surface of the semiconductor die; electrically connecting terminals of the semiconductor die to the metal frame; and Forming exposed outer contacts of the semiconductor package from the connecting rods. [2] The method of claim 1, wherein the exposed outer contacts comprise sidewall surfaces of the connecting rods. [3] The method of claim 2, wherein the exposed outer contacts further comprise bottom surfaces of the connecting bars that intersect the sidewall surfaces of the connecting bars. [4] The method of any one of claims 1 to 3, further comprising performing a package dicing process that separates the connecting bars from the adjacent stabilizing metal section, and wherein the exposed outer contacts are provided from severed surfaces of the connecting bars. [5] The method of any one of claims 1 to 4, further comprising performing an etching process that removes material from the connecting bars, and wherein the exposed external contacts are provided by surfaces of the connecting bars that are etched by the etching process. [6] The method of any one of claims 1 to 5, wherein the semiconductor die is configured as a vertical power transistor configured to conduct a vertical current between a first load terminal and a second load terminal, wherein the first surface of the semiconductor die is a back surface of the semiconductor die having the second load terminal, wherein electrically connecting terminals of the semiconductor die to the metal frame comprises forming a first metallization layer on a top side of the semiconductor package electrically connecting the second load terminal to the metal frame, and wherein the exposed external contacts form a conductor tip inspection feature electrically connected to the second load terminal of the semiconductor die. [7] The method according to any one of claims 1 to 6, wherein the lead frame is provided such that the connecting bars are thinner than the metal frame, and wherein forming the dielectric material fills a region between an upper surface of the connecting bars and an upper surface of the metal frame. [8] The method of any one of claims 1 to 7, further comprising forming a metal interconnect extending directly between the semiconductor die and the metal frame, the metal interconnect being disposed below a top surface of the metal frame. [9] The method of claim 8, wherein the metal interconnect electrically connects a terminal from the first surface of the semiconductor die to the metal frame. [10] A semiconductor package comprising: a metal frame forming an at least partially enclosed shape around a central opening; severed connecting rods connected to the metal frame; a semiconductor die disposed within the central opening; and a dielectric material that fills the central opening and encapsulates the semiconductor die, wherein terminals of the semiconductor die are electrically connected to the metal frame, and wherein the semiconductor package has exposed outer contacts of the semiconductor package formed from the severed connecting rods. [11] The semiconductor package of claim 10, wherein the exposed outer contacts comprise sidewall surfaces of the severed connecting bars. [12] The semiconductor package of claim 11, wherein the exposed external contacts further comprise bottom surfaces of the severed connecting bars that intersect the sidewall surfaces of the severed connecting bars. [13] The semiconductor package of any one of claims 10 to 12, wherein a first recess is formed in the dielectric material over a first surface of the semiconductor die. [14] The semiconductor package of claim 13, wherein the semiconductor die is configured as a vertical power transistor configured to conduct a vertical current between a first load terminal and a second load terminal. [15] The semiconductor package of claim 14, wherein the first surface of the semiconductor die is a back surface of the semiconductor die having the second load terminal, the semiconductor package having a first metallization layer on a top side of the semiconductor package electrically connecting the second load terminal to the metal frame, and the exposed external contacts forming a conductor tip inspection feature electrically connected to the second load terminal of the semiconductor die. [16] The semiconductor package according to any one of claims 10 to 15, wherein the severed connecting bars are thinner than the metal frame, and wherein the dielectric material fills a region between an upper surface of the severed connecting bars and an upper surface of the metal frame. [17] The semiconductor package of any one of claims 10 to 16, further comprising a metal interconnect extending directly between the semiconductor die and the metal frame, the metal interconnect being disposed below a top surface of the metal frame. [18] The semiconductor package of claim 17, wherein the metal interconnect electrically connects a terminal from the first surface of the semiconductor die to the metal frame.

Images