SACRIFICE PAD DESIGN FOR SEMICONDUCTOR DEVICE

Abstract

A method for fabricating a semiconductor device comprises the following: fabricating a conductive pad over and in electrical connection with an interconnect structure, wherein the interconnect structure is arranged over a substrate and is electrically connected to electrical components fabricated on the substrate; fabricating a passivation layer over the conductive pad and the interconnect structure; and fabricating a sacrificial test structure over the passivation layer and in electrical connection with the conductive pad, wherein the sacrificial test structure comprises a sacrificial pad extending along a top surface of the passivation layer away from the substrate and a sacrificial via extending into the passivation layer and contacting the conductive pad.

Description

Priority claim and cross-reference

[0001] The present application claims priority from US patent application number 63 / 672.754, filed on July 18, 2024, entitled “Sacrificial Pad Design to Enhance SoIC Yield”, which is incorporated into the present application by reference. background

[0002] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, these improvements in integration density are attributable to repeated reductions in the smallest feature size, allowing more components to be integrated into a given area.

[0003] As the demand for miniaturized electronic devices has increased, there has been a need for faster and more innovative packaging methods for semiconductor dies. One example is SoIC (System on Integrated Chip) technology, a three-dimensional (3D) intermediate-chip stacking technology that integrates active and passive chips into a single SoC (System on Chip). The SoIC platform utilizes front-end technologies and precision methodologies from silicon microchip fabrication for the three-dimensional stacking of chips. The SoIC platform enables the integration of proven high-performance dies (KGDs) with varying chip sizes, functionalities, and wafer node technologies. The resulting structure allows for vertical ultra-high-density stacking to achieve high performance, low power consumption, and a low resistance-inductance-capacitance (RLC) ratio.These packaging technologies enable the production of semiconductor devices with improved functionalities and small footprints. Brief description of the drawings

[0004] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Rather, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. The Fig. 1, Fig. 2, Fig. 3A, Fig. 3B, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8 and Fig. Figure 9 shows different representations of a semiconductor device at different manufacturing stages according to one embodiment. Fig. Figure 10 shows a sectional view of a semiconductor device according to a further embodiment. The Fig. 11A and Fig. Figure 11B shows various representations of a semiconductor structure according to one embodiment. Fig. Figure 12 shows a flowchart of a method for manufacturing a semiconductor device according to some embodiments. Detailed description

[0005] The disclosure below provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element over or on top of a second element in the description below may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals may be repeated in the various examples in the present disclosure.Unless otherwise specified, throughout the description, identical or similar reference numerals in different figures denote the same or a similar component produced by the same or a similar process using one or more identical or similar materials.

[0006] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of one element or structural element to one or more other elements or structural elements depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90° or in a different orientation), and the spatially relative descriptors used here may be interpreted accordingly. In this discussion, figures with the same number but different letters (e.g., Fig. 3A and Fig. 3B) Different representations of the same structure at the same manufacturing stage.

[0007] In some embodiments, a sacrificial test structure is fabricated over a conductive pad of the semiconductor die during the manufacturing process and electrically connected to it. The sacrificial test structure can be fabricated, for example, using a solder material. During wafer testing, a test probe contacts the sacrificial test structure instead of the conductive pad of the die, thus preventing scratching of the conductive pad and the formation of a probe mark on it. After wafer testing, the sacrificial test structure is removed. If a probe mark is formed, it reduces the flatness (e.g., planarity) of the conductive pad surface and can increase the risk of delamination of a dielectric layer subsequently fabricated on the conductive pad.The present disclosure prevents the formation of a probe mark by using the sacrificial test structure for wafer testing, thereby reducing the risk of dielectric layer detachment.

[0008] The Fig. 1, Fig. 2, Fig. 3A, Fig. 3B, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8 and Fig. Figure 9 shows various representations (e.g., sectional views, top views) of a semiconductor device 100 at different manufacturing stages according to one embodiment. In the illustrated embodiment, the semiconductor device 100 is a semiconductor die, and it can therefore also be referred to as a semiconductor die 100 or a die 100.

[0009] Fig. Figure 1 shows a sectional view of the semiconductor device 100 at an early stage of fabrication. It should be noted that, for the sake of simplicity, not all structural elements of the semiconductor device 100 are shown. Fig. Figure 1 (and subsequent figures) may only show a part of the semiconductor device 100.

[0010] As in Fig. As shown in Figure 1, the semiconductor device 100 comprises a substrate 101, electrical components 103 manufactured on or in the substrate 101, and an interconnect structure 104 above the substrate 101. Furthermore, Figure 1 shows... Fig. 1 conductive pads 111 over the interconnect structure 104, a passivation layer 113 over the conductive pads 111 and the interconnect structure 104, and an etch stop layer (ESL) 115 over the passivation layer 113. Unless otherwise stated, in this discussion the word "conductive" as used in phrases such as "conductive pads", "conductive material", or "conductive structural elements" means electrically conductive (rather than, for example, thermally conductive).

[0011] The substrate 101 of die 100 can be a semiconductor substrate (e.g., a silicon substrate), either doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate contains a layer of a semiconductor material, such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof. Other substrates that can be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.

[0012] The electrical components 103 of the die 100 comprise a variety of active devices (e.g., transistors) and / or passive devices (e.g., capacitors, resistors, inductors), and the like. The electrical components 103 of the die 100 can be fabricated either in or on the substrate 101 of the die 100 by any suitable method.

[0013] The interconnect structure 104 of the die 100 contains one or more metallization layers (e.g., copper layers, such as conductive traces 107 and vias 109) embedded in one or more dielectric layers 105 (e.g., silicon oxide), and it is used to connect the various electrical components 103 to form functional circuits. The number of dielectric layers 105 and the number of metallization layers embedded in the die 100 are determined by the number of dielectric layers 105 and the number of metallization layers. Fig. The figures shown for Interconnect structure 104 are for illustrative purposes only and are not limiting.

[0014] In the example of Fig. 1. Conductive pads 111 (which can also be referred to as contact pads) are fabricated over the interconnect structure 104 and electrically connected to conductive structural elements (e.g., in the uppermost metallization layer) of the interconnect structure 104. The conductive pads 111 can be made of aluminum, but alternatively other materials, such as copper, can also be used.

[0015] The passivation layer 113 is fabricated over the conductive pads 111 and the interconnect structure 104 to provide some protection for the structures of the die 100. The passivation layer 113 can be made from one or more suitable dielectric materials such as silicon oxide, silicon nitride, low-k dielectrics such as carbon-doped oxides, extremely low-k dielectrics such as porous carbon-doped silicon dioxide, combinations thereof, or the like. The passivation layer 113 can be fabricated by a process such as chemical vapor deposition (CVD), but any suitable method can be used.

[0016] The ESL 115 is produced above the passivation layer 113. In some embodiments, the ESL 115 is produced from a suitable material such as silicon nitride (e.g., SiN), silicon carbide (e.g., SiC), silicon carbonitride (e.g., SiCN), silicon oxide nitride (SiON), or the like, and it can be produced using a suitable manufacturing process such as physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), or the like. In some embodiments, the ESL 115 can be used to protect underlying structures and to provide a control point for a subsequent etching process.

[0017] In the fabrication of semiconductor devices, multiple dies (e.g., 100) are typically produced on the same wafer (e.g., a silicon wafer). These multiple dies are then separated into individual dies using a subsequent singulation process. Therefore, the number of dies in the Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8 to Fig. The 9 dies shown correspond to one of the dies that are fabricated on a wafer. The substrate 101 can, for example, be part of a wafer (e.g., a silicon wafer).

[0018] Then in Fig. Two openings 112 are created that extend through the ESL 115 and the passivation layer 113 to expose the conductive pads 111. In some embodiments, an anisotropic etching process, such as a plasma etching process, is used to create the openings 112.

[0019] During the fabrication of the semiconductor device, after the conductive pads 111 of the semiconductor dies 100 have been fabricated, a wafer test, also known as a circuit probe test (CP test), is performed on the dies on the wafer to identify the proven good dies (KGDs). During the wafer test, the dies 100 on the wafer are checked for functional defects using test structures. The wafer test is typically performed with a test device called a wafer prober. A wafer prober is a machine used to verify integrated circuits against their designed functionality. In some embodiments, for electrical testing of the dies 100, a series of microscopic contacts or probes of the wafer prober are held in contact with the conductive pads 111 of the dies 100 during the wafer test.However, the probes can scratch the surfaces of the conductive pads 111 or cause probe marks (e.g., teeth) on the surfaces of the conductive pads 111. The depth of the probe marks can be greater than 2 µm. The probe marks reduce the flatness (e.g., planarity) of the surfaces of the conductive pads 111. During subsequent machining, the openings 112 are filled with a dielectric material. The reduced surface flatness of the conductive pads 111 can increase the risk of detachment of the dielectric material and can lead to device failure.

[0020] To prevent the conductive pads 111 from being scratched by the wafer probe probes during wafer testing, a sacrificial test structure 131, comprising a sacrificial pad 131P, is disclosed in the present disclosure. Each sacrificial pad 131P is electrically connected to a corresponding conductive pad 111. During wafer testing, the probes are held in contact with the sacrificial pads 131P instead of the conductive pads 111. Therefore, scratching of the conductive pads 111 is avoided. The sacrificial test structures 131 are removed after wafer testing. Details will be discussed later.

[0021] Then in Fig. 3A above the ESL 115 sacrificial test structures 131 are produced, which are then electrically connected to respective conductive pads 111. In the example of Fig. 3A Each sacrificial test structure 131 comprises the following: a sacrificial pad 131P extending along the top surface of the ESL 115; a sacrificial via 131V extending into the passivation layer 113 and contacting the conductive pad 111 below; and a sacrificial lead 131L extending along the top surface of the ESL 115 and connecting the sacrificial pad 131P to the sacrificial via 131V.

[0022] Fig. Figure 3B shows a top view of semiconductor device 100 of Fig. 3A. In Fig. In the top view of the sacrificial via 131V, the sacrificial pad 131P has a first circular shape with a radius R1, and the sacrificial pad 131P has a second circular shape with a radius R2, where R2 > R1. In other words, in the top view, the area (e.g., the surface area) of the sacrificial pad 131P is larger than the area of ​​the sacrificial via 131V. The larger area of ​​the sacrificial pad 131P facilitates the inspection of die 100. The shape of the sacrificial pad 131P and the shape of the sacrificial via 131V, which are shown in Fig. The examples shown in Figure 3B are merely non-limiting examples, and other shapes (e.g. an oval or rectangular shape or the like) are also possible and are intended to be entirely within the scope of protection of the present disclosure.

[0023] In some embodiments, the sacrificial test structures 131 are manufactured as follows: producing a solder material in the openings 112 and above the top of the ESL 115, wherein the solder material in the openings 112 forms the sacrificial vias 131V; and structuring the solder material arranged along the top of the ESL 115 to produce the sacrificial pads 131P and the sacrificial leads 131L.

[0024] Fig. Figure 4 shows the die 100 during wafer testing. During wafer testing, a probe 141 of the wafer prober is held in contact with the sacrificial pad 131P. The dies 100 that pass the wafer testing are identified as the proven good dies (KGDs). After a subsequent singulation process, the KGDs are used to fabricate semiconductor structures, such as SoIC devices.

[0025] Fig. Figure 5 shows the 100 after wafer inspection. As in Fig. As shown in Figure 5, scratching by the probe 141 creates a probe mark 133 on the upper surface of the sacrificial pad 131P. The probe mark 133 can have a tooth 133A and a projection 133B. The tooth 133A can be caused by the pressure of the probe 141 on the sacrificial pad 131P, and the projection 133B can be caused by a portion of the solder material being pushed away from its original position by the probe 141. The depth A of the probe mark 133, measured as the roughness depth of the probe mark 133, is greater than 2 µm in some embodiments.

[0026] Then in Fig. 6 the sacrificial test structures 131 are removed. In some embodiments, a wet etching process is carried out to remove the sacrificial test structures 131. The wet etching process can be carried out using an etchant containing, for example, H2SO4 and Fe2(SO4)3. In the example of Fig. 6. The wet etching process not only removes the sacrificial test structures 131 to create openings 114A in the passivation layer 113, but it also removes portions of the passivation layer 113 near the conductive pads 111 (e.g., in contact with them) to create undercuts 114B on the undersides of the openings 114A. Each opening 114A (which, for example, has straight sidewalls extending perpendicular to the top surface of the substrate 101) and the corresponding undercut 114B are collectively referred to as an opening 114. The width B of the undercut 114B can be greater than 0.01 µm. The height C of the undercut 114B can be 1 µm or less.

[0027] In the example of Fig. 6. Each opening 114 has an upper part with parallel side walls and a lower part with side walls that extend away from each other along the depth direction of the opening 114. In other words, the upper part of the opening 114 has a substantially uniform width, and the lower part of the opening 114 has a width that increases along the depth direction. It should be noted that the position of opening 114A is the position of opening 112 in Fig. 2 corresponds (e.g., is equal to this one).

[0028] Since probe 141 does not contact conductive pad 111, no probe mark is left on conductive pad 111. Therefore, the top surface of conductive pad 111 is considered flat within the limitations of the manufacturing process. The vertical distance between the highest and lowest points on the top surface of conductive pad 111 is less than 2 µm, for example, less than 1 µm or 0.5 µm.

[0029] In Fig. In 7, a dielectric layer 117 is then produced over the ESL 115. The dielectric layer 117 also fills the openings 114. The dielectric layer 117 can be produced using a suitable dielectric material such as silicon dioxide with a suitable fabrication process such as CVD. To achieve a planar top surface for the dielectric layer 117, a planarization process, such as chemical-mechanical planarization (CMP), can be performed. Since the dielectric layer 117 fills the openings 114, in some embodiments it has an upper part with a substantially uniform width and a lower part with a width that increases along the depth direction of the dielectric layer 117 in each opening 114.

[0030] Then, an ESL 119 is fabricated above the dielectric layer 117. In some embodiments, the ESL 119 is made from a suitable material such as silicon nitride (e.g., SiN), silicon carbide (e.g., SiC), silicon carbonitride (e.g., SiCN), silicon oxide nitride (SiON), or the like, and it can be fabricated using a suitable process such as PVD, CVD, PECVD, or the like. The ESL 119 serves to protect the underlying structures and, in some embodiments, can be used to provide a control point for a subsequent etching process.

[0031] A dielectric layer 121 is then fabricated over the ESL 119. The dielectric layer 121 can be produced using a suitable dielectric material such as silicon oxide and a suitable fabrication process such as CVD. To achieve a planar top surface for the dielectric layer 121, a planarization process, such as CMP, can be performed.

[0032] In Fig. In step 8, pad openings 122 and via openings 124 are created. The pad openings 122 are created to extend through the dielectric layer 121 and the ESL 119, and they are filled with one or more conductive materials after bond pads have been fabricated. The via openings 124 are created beneath the pad openings 122 to extend through the dielectric layer 117 and the ESL 115 and into the passivation layer 113 to expose the underlying conductive pads 111. The via openings 124 are then filled with one or more conductive materials to create vias. In some embodiments, a first structuring process is used to create the pad openings 122 (e.g. in front of the via openings 124) in the dielectric layer 121 and the ESL 119 in order to expose the dielectric layer 117.After the pad openings 122 have been created, a second structuring process is used to create the via openings 124 in the dielectric layer 117, the ESL 115 and the passivation layer 113 in order to expose the conductive pads 111.

[0033] In the example of Fig. 8 Each via opening 124 is generated such that it is laterally adjacent to the position of a respective opening 114 (e.g., spaced apart from it) (see Fig. 6) In some embodiments, a distance D between the via hole 124 and the respective hole 114 is greater than 2 µm. In some embodiments, parts of the passivation layer 113 above and around the undercuts 114B have lower structural integrity. The distance D ensures that the via holes 124 (and the vias that are subsequently produced) are not produced in the parts of the passivation layer 113 with lower structural integrity.

[0034] Then in Fig. 9 one or more conductive materials are deposited in the via holes 124 and the pad holes 122 to create vias 125 and bond pads 123 respectively.

[0035] In some embodiments, a barrier layer is fabricated to coat the sidewalls of the pad openings 122 and the sidewalls and bottom surfaces of the via openings 124 before a conductive material is fabricated to fill the via openings 124 and the pad openings 122. The barrier layer can contain an electrically conductive material such as titanium nitride, but alternatively, other materials such as tantalum nitride, titanium, tantalum, or the like can be used. The barrier layer can be fabricated using a CVD process, such as plasma-enhanced CVD (PECVD). Alternatively, other methods such as sputtering, metal-organic chemical vapor deposition (MOCVD), or atomic layer deposition (ALD) can be used.

[0036] A conductive material is then prepared to fill the via holes 124 and the pad holes. The conductive material can contain copper, but alternatively, other suitable materials can be used, such as aluminum, tungsten, alloys, combinations thereof, and the like. The conductive material can be prepared by depositing a seed layer and then plating the conductive material (e.g., copper) onto the seed layer, thereby filling or overfilling the via holes 124 and the pad holes 122. After the holes have been filled, excess barrier layer and excess conductive material outside the holes can be removed by a planarization process, such as CMP, but any suitable removal process can be used.The remaining conductive material in the via holes 124 and the pad holes 122 forms the vias 125 and the bond pads 123, respectively. The bond pads 123 can also be referred to as die connecting elements.

[0037] After the bond pads 123 have been manufactured, a singulation process can be carried out along singulation areas, which in Fig. 9, indicated by dashed arrows 151, is used to separate the dies 100 produced on the wafer into individual dies 100. The dies 100 that have passed the wafer inspection are used to manufacture various semiconductor devices. An example is given below with reference to the Fig. 11A and Fig. 11B is discussed.

[0038] Fig. Figure 10 shows a sectional view of a semiconductor device 100A according to a further embodiment. The semiconductor device 100A (e.g., a die 100A) is similar to the semiconductor device 100, but the vias 125 and the bond pads 123 are fabricated in different positions. In particular, each via 125 is fabricated such that it extends through the portion of the dielectric layer 117 that fills the opening 114. In other words, the via 125 is fabricated within the opening 114. Therefore, the via 125 is spaced apart from the passivation layer 113 and the ESL 115 (e.g., it does not contact these layers). As shown in Figure 10, the via 125 is fabricated in the opening 114. Fig. As shown in Figure 10, the via 125 extends from the top surface of the dielectric layer 117, which is away from the substrate 101, to a bottom surface of the dielectric layer 117 that contacts the conductive pad 111. The corresponding bond pad 123 is fabricated over (e.g., directly over and in contact with) the via 125 and extends through the dielectric layer 121 and the ESL 119.

[0039] With the embodiment of Fig. 10. Further advantages are achieved. For example, the etching process for creating the via hole can be simpler than the etching process for creating the via hole 124 in Fig. 8, since the via is 125 from Fig. 10 extends only through the dielectric layer 117. This is due to the fact that the etching process for creating the via opening 124 in Fig. Eight different materials (e.g., the dielectric layer 117, the ESL 115, and the passivation layer 113) must be etched through, and therefore more types of etchants and / or more etching steps may be required for the etching process. Furthermore, the portion of the dielectric layer 117 that fills the opening 114 has no structural integrity issues, and therefore the via 125 can be used in Fig. 10 without the condition that the minimum distance D (see Fig. 8) must be present between the via opening and the opening 114.

[0040] The Fig. 11A and Fig. Figure 11B shows a sectional view and a top view of a semiconductor structure 400 according to one embodiment. The semiconductor structure 400 can, for example, be a SoIC device produced by bonding the proven good dies to an interposer. As shown in the Fig. 11A and Fig. As shown in Figure 11B, the semiconductor structure 400 comprises: an interposer 200; dies 300A and 300B stacked vertically over the interposer 200; and a molding material 221 on the interposer 200 around the dies 300A and 300B.

[0041] In the illustrated embodiment, the interposer 200 has a substrate 201, vias 207 and conductive pads 205 and 215 on the top and bottom surfaces of the substrate 201, respectively. Fig. Figure 11A also shows passivation layers 203 and 209 of the interposer 200, located on the top and bottom surfaces of the substrate 201, respectively, and enclosing the conductive pads 205 and 215. The interposer 200 also has external terminals 211 (which can also be referred to as conductive contact bumps) that are formed on the conductive pads 215. Solder areas 213 can be created on the external terminals 211. The conductive pads 205 and 215 can also be referred to as bond pads of the interposer 200.

[0042] Substrate 201 can be, for example, a silicon substrate, either doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. Alternatively, substrate 201 can be a glass substrate, a ceramic substrate, a polymer substrate, or any other substrate that can provide suitable protection and / or interconnect functionality.

[0043] In some embodiments, the substrate 201 may contain electrical components, such as resistors, capacitors, combinations thereof, or the like. These electrical components may be active, passive, or a combination thereof. In other embodiments, the substrate 201 contains no active or passive electrical components. All such combinations are intended to be entirely within the scope of protection of this disclosure.

[0044] The vias 207 extend from the top of the substrate 201 to its bottom and establish electrical connections between the conductive pads 205 and 215. The vias 207 can be made of a suitable conductive material, such as copper, tungsten, aluminum, alloys thereof, combinations thereof, and the like. A barrier layer can be provided between the vias 207 and the substrate 201. The barrier layer can contain a suitable material such as titanium nitride, but alternatively, other materials such as tantalum nitride, titanium, or the like can also be used.

[0045] Although not shown, a redistribution structure (RDS) can be fabricated on the top side of the substrate 201 between the substrate 201 and a passivation layer 203. The RDS is electrically connected to the vias 207 and the conductive pads 205 and redistributes electrical signals along the top side of the substrate 201. The RDS can have one or more dielectric layers (e.g., silicon oxide) and conductive structural elements (e.g., conductive traces and vias) fabricated in the one or more dielectric layers. Furthermore, another RDS can be fabricated on the bottom side of the substrate 201 between the substrate 201 and a passivation layer 209.

[0046] The passivation layers 203 and 209 can be made from a suitable material, such as silicon oxide, silicon nitride, combinations thereof, or the like. In some embodiments, a polymer material, such as a polyimide, can be used to produce the passivation layers 203 and 209. A suitable manufacturing process, such as CVD, PECVD, spin coating, or the like, can be used to produce the passivation layers 203 and 209.

[0047] The external contacts 211 are fabricated on the conductive pads 215 and extend through the passivation layer 209 to be electrically connected to the conductive pads 215. The external contacts 211 can be any suitable type of external contact, such as microbumps, copper pillars, a copper layer, a nickel layer, a lead-free layer (LF layer), an ENEPIG layer (ENEPIG: Electroless Nickel Electroless Palladium Immersion Gold), a Cu / LF layer, a Sn / Ag layer, a Sn / Pb layer, a combination thereof, or the like.

[0048] The 300A and 300B dies may be identical or similar to the 100 die, and they are proven good dies (KGDs) that have passed wafer testing. For simplicity, the following applies to the 300A and 300B dies in Fig. 11A not all structural elements of the die 100 of Fig. 9 or Fig. 10 is shown. For example, the 300B in Fig. 11A only the substrates 101, the bond pads 123 and the dielectric layer 121. It should be noted that the die 300A has bond pads 123 and dielectric layers 121 on the top and bottom of the substrate 101 as well as substrate vias (TSVs) 127 which electrically connect the bond pads 123 on the top and bottom of the substrate 101.

[0049] In some embodiments, the die 300A is bonded to the conductive pads 205 by direct bonding (e.g., metal-to-metal direct bonding or dielectric-to-dielectric direct bonding) without the use of an adhesive (e.g., solder). The direct bonding process may include: cleaning the surfaces of the die 300A and the interposer 200; aligning the bond pads 123 of the die 300A with the respective conductive pads 205 of the interposer 200; and pressing the die 300A and the interposer 200 together. Heat treatment may be performed to support the direct bonding process. The resulting bond connections between the die 300A and the interposer 200 include dielectric-dielectric bond connections (e.g. connections of dielectric layers 121 with the passivation layer 203) and metal-metal bond connections (e.g. connections of bond pads 123 with conductive pads 205).The die 300B can also be bonded directly to the bond pads 123 on the top side of the die 300A. In other embodiments, the dies 300A and 300B are bonded using a solder material.

[0050] Then, a molding material 221 is produced on the interposer 200 around dies 300A and 300B. The molding material 221 can, for example, comprise an epoxy, an organic polymer, a polymer with or without the addition of a silicon dioxide-based or glass filler, or other materials. In some embodiments, the molding material 221 comprises a liquid molding compound (LMC) that is a gel-like liquid when applied. The molding material 221 can also comprise a liquid or a solid when applied. Alternatively, the molding material 221 can comprise other insulating and / or encapsulating materials. In some embodiments, the molding material 221 is applied using a wafer-level forming process. The molding material 221 can be formed, for example, by compression molding, injection molding, mold underfill (MUF), or other methods.

[0051] In some embodiments, the mold material 221 is then cured by a curing process. This curing process may involve heating the mold material 221 to a specified temperature for a specified duration using a tempering process or another curing process. The curing process may also include irradiation with ultraviolet (UV) light, irradiation with infrared (IR) energy, combinations thereof, or a combination with a heating process. Alternatively, the mold material 221 may be cured by other methods. In some embodiments, no curing process is used.

[0052] After the mold material 221 has been produced, a planarization process, such as CMP, can be performed to achieve a planar top surface for the mold material 221. In the illustrated embodiments, the mold material 221 extends further from the interposer 200 than the dies 300A and 300B, thus covering the top surface of the die 300B. In some embodiments, the mold material 221 and the die 300B have a coplanar top surface. In the illustrated embodiment, the sidewalls of the mold material 221 are aligned with the respective sidewalls of the interposer 200 along the same vertical lines.

[0053] Embodiments can offer advantages. For example, the disclosed sacrificial test structure 131 prevents probe marks from forming on the conductive pads 111 of the die 100, thus maintaining the flatness of the top surface of the conductive pads 111 and reducing the risk of detachment of the dielectric layer 117. When the die 100 is used to fabricate further semiconductor structures (e.g., 400), the dielectric layer 117 undergoes subsequent high-temperature processes, such as the bonding process for the dies 300A / 300B and the forming process for producing the mold material 221. These high-temperature processes, together with the discrepancy in the coefficients of thermal expansion (CTE) between the mold material 221 and the dies 300A / 300B, can lead to high mechanical stress in the dies 300A / 300B and to detachment of the dielectric layer 117. The detachment of the dielectric layer 117 can lead to a device failure of the semiconductor structure (e.g. 400).The disclosed sacrificial test structure 131 reduces the risk of detachment, thereby also reducing the risk of device failure in the semiconductor structure (e.g. 400) and increasing the production yield.

[0054] Fig. Figure 12 shows a flowchart of a method 1000 for manufacturing a semiconductor device according to some embodiments. It is understood that the in Fig. The process implementation shown in Figure 12 is merely one example of numerous possible process implementations. An average person skilled in the art would likely recognize numerous variations, alternatives, and modifications. For example, various steps that are described in Figure 12 can be modified. Fig. The 12 items listed can be added, omitted, replaced, rearranged, and repeated.

[0055] In Fig.In block 1010, a conductive pad is fabricated over an interconnect structure and electrically connected to it. The interconnect structure is arranged over a substrate and electrically connected to electrical components fabricated on the substrate. In block 1020, a passivation layer is fabricated over the conductive pad and the interconnect structure. In block 1030, a sacrificial test structure is fabricated over the passivation layer and electrically connected to the conductive pad. The sacrificial test structure comprises a sacrificial pad extending along a top surface of the passivation layer away from the substrate and a sacrificial via extending into the passivation layer and contacting the conductive pad.

[0056] According to one embodiment, a method for manufacturing a semiconductor device comprises: manufacturing a conductive pad over and in electrical connection with an interconnect structure, wherein the interconnect structure is arranged over a substrate and is electrically connected to electrical components manufactured on the substrate; manufacturing a passivation layer over the conductive pad and the interconnect structure; and manufacturing a sacrificial test structure over the passivation layer and in electrical connection with the conductive pad, wherein the sacrificial test structure comprises a sacrificial pad extending along a top surface of the passivation layer away from the substrate and a sacrificial via extending into the passivation layer and contacting the conductive pad.In one embodiment, the method further comprises: testing the sacrificial pad with a probe; after testing, removing the sacrificial test structure, wherein the removal of the sacrificial test structure creates a first opening in the passivation layer; producing a first dielectric layer over the passivation layer, wherein a first part of the first dielectric layer fills the first opening; producing a second dielectric layer over the first dielectric layer; producing a via extending through the first dielectric layer and electrically connected to the conductive pad; and producing a bond pad extending through the second dielectric layer and electrically connected to the via.In one embodiment, fabricating the sacrificial test structure comprises: creating a second opening in the passivation layer to expose the conductive pad; depositing solder material in the second opening and along the top surface of the passivation layer, the solder material in the second opening forming the sacrificial via; and structuring the solder material arranged along the top surface of the passivation layer, the remaining portion of the solder material along the top surface of the passivation layer forming the sacrificial pad after structuring. In one embodiment, in a top view, the sacrificial pad has a larger area than the sacrificial via. In one embodiment, removing the sacrificial test structure comprises performing a wet etching process.In one embodiment, the wet etching process removes the solder material in the second opening, and furthermore removes a portion of the passivation layer that contacts the conductive pad to create an undercut beneath the passivation layer. In one embodiment, the conductive pad is made of a first conductive material, while the via and the bond pad are made of a second conductive material that is different from the first conductive material. In one embodiment, the first conductive material is aluminum, and the second conductive material is copper. In one embodiment, the via is spaced apart from the first portion of the first dielectric layer.In one embodiment, an upper part of the via extends through the first dielectric layer, and a lower part of the via extends into the passivation layer and contacts the conductive pad. In another embodiment, the via is fabricated such that it is embedded in the first part of the first dielectric layer.

[0057] According to one embodiment, a method for fabricating a semiconductor device comprises the following: fabricating a conductive pad over and in electrical connection with an interconnect structure, wherein the interconnect structure is fabricated over a substrate and electrically connects electrical components fabricated on the substrate to form a functional circuit; fabricating a passivation layer over the conductive pad and the interconnect structure; fabricating a sacrificial test structure that is electrically connected to the conductive pad, wherein the sacrificial test structure is fabricated to have a sacrificial pad along a top surface of the passivation layer and a sacrificial via extending into the passivation layer and electrically connected to the conductive pad; testing the functional circuit by testing the sacrificial pad with a probe; and removing the sacrificial test structure after testing.In one embodiment, removing the sacrificial test structure creates an opening in the passivation layer, wherein the method after removing the sacrificial test structure further comprises: producing a first dielectric material over the passivation layer and in the opening; producing a second dielectric material over the first dielectric material; producing a via extending through the first dielectric material and contacting the conductive pad; and producing a bond pad extending through the second dielectric material and contacting the via.In one embodiment, fabricating the sacrificial test structure comprises: creating a recess in the passivation layer to expose the conductive pad; depositing solder material in the recess and along the top surface of the passivation layer; and structuring the solder material arranged along the top surface of the passivation layer. In another embodiment, removing the sacrificial test structure comprises performing a wet etching process to remove the solder material, wherein the wet etching process further removes a portion of the passivation layer adjacent to the conductive pad to create an undercut, the opening comprising the recess and the undercut.In one embodiment, the via is produced laterally adjacent to a position of the opening, with an upper part of the via being embedded in the first dielectric material and a lower part of the via being embedded in the passivation layer. In another embodiment, part of the first dielectric material fills the opening, with the via being produced such that it is embedded in this part of the first dielectric material.

[0058] According to one embodiment, a method for fabricating a semiconductor device comprises the following: fabricating an interconnect structure over a substrate, wherein the interconnect structure connects electrical components fabricated on the substrate to form a functional circuit; fabricating a conductive pad over and electrically connected to the interconnect structure; fabricating a passivation layer over the conductive pad and the interconnect structure; fabricating a sacrificial test structure extending through the passivation layer and electrically connected to the conductive pad; testing the functional circuit by probing the sacrificial test structure with a probe; removing the sacrificial test structure after testing; and, after removing the sacrificial test structure, fabricating a via and a bond pad that are placed over the conductive pad and electrically connected to it.In one embodiment, removing the sacrificial test structure creates an opening in the passivation layer, wherein the creation of the via and the bond pad comprises: creating a first dielectric material in the opening and along the top of the passivation layer; creating a second dielectric material over the first dielectric material; creating the via in the first dielectric material, wherein the via contacts the conductive pad; and creating the bond pad in the second dielectric material, wherein the bond pad is positioned over and contacts the via.In one embodiment, the fabrication of the sacrificial test structure comprises: creating a recess in the passivation layer to expose the conductive pad; depositing a solder material in the recess and along the top surface of the passivation layer; and structuring the solder material arranged along the top surface of the passivation layer.

[0059] Features of various embodiments have been described above so that those skilled in the art can better understand the aspects of the present disclosure. It should be clear to those skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other methods and structures to achieve the same objectives and / or to obtain the same advantages as in the embodiments presented here. Those skilled in the art should also recognize that such equivalent interpretations do not deviate from the fundamental concept and scope of protection of the present disclosure and that they can make various changes, substitutions, and modifications without deviating from the fundamental concept and scope of protection of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 672.754

[0001]

Claims

[1] Method for manufacturing a semiconductor device, comprising: Manufacturing a conductive pad over and in electrical connection with an interconnect structure, wherein the interconnect structure is arranged over a substrate and is electrically connected to electrical components manufactured on the substrate; Creating a passivation layer over the conductive pad and the interconnect structure; and Providing a sacrificial test structure above the passivation layer and in electrical contact with the conductive pad, wherein the sacrificial test structure comprises a sacrificial pad extending along a top surface of the passivation layer away from the substrate and a sacrificial via extending into the passivation layer and contacting the conductive pad. [2] The method of claim 1, further comprising: Checking the sacrificial pad with a probe; After testing, the sacrificial test structure is removed, whereby the removal of the sacrificial test structure creates an initial opening in the passivation layer; Forming a first dielectric layer over the passivation layer, wherein a first part of the first dielectric layer fills the first opening; Creating a second dielectric layer over the first dielectric layer; Creating a via that extends through the first dielectric layer and is electrically connected to the conductive pad; and Creating a bond pad that extends through the second dielectric layer and is electrically connected to the via. [3] Method according to claim 2, wherein the production of the sacrificial test structure comprises: Creating a second opening in the passivation layer to expose the conductive pad; Deposition of a solder material in the second opening and along the top surface of the passivation layer, wherein the solder material in the second opening forms the sacrificial via; and Structuring the solder material arranged along the top of the passivation layer, wherein after structuring a remaining portion of the solder material along the top of the passivation layer forms the sacrificial pad. [4] Method according to claim 2 or 3, wherein in a top view the sacrificial pad has a larger area than the sacrificial via. [5] Method according to any one of claims 2 to 4, wherein the removal of the sacrificial test structure comprises performing a wet etching process. [6] Method according to claim 5, wherein The wet etching process removes the solder material from the second opening, and The wet etching process continues to remove part of the passivation layer that contacts the conductive pad, creating an undercut beneath the passivation layer. [7] Method according to any one of claims 2 to 6, wherein the conductive pad is made from a first conductive material, and The via and the bond pad are made from a second conductive material that is different from the first conductive material. [8] Method according to claim 7, wherein the first conductive material is aluminium, and the second conductive material is copper. [9] Method according to any one of claims 2 to 8, wherein the via is spaced apart from the first part of the first dielectric layer. [10] Method according to any one of claims 2 to 9, wherein an upper part of the via extends through the first dielectric layer, and a lower part of the via extends into the passivation layer and contacts the conductive pad. [11] Method according to any one of claims 2 to 10, wherein the via is produced such that it is embedded in the first part of the first dielectric layer. [12] Method for manufacturing a semiconductor device, comprising: Manufacturing a conductive pad over and in electrical connection with an interconnect structure, wherein the interconnect structure is manufactured over a substrate and electrically connects electrical components manufactured on the substrate to form a functional circuit; Creating a passivation layer over the conductive pad and the interconnect structure; Fabricating a sacrificial test structure that is electrically connected to the conductive pad, wherein the sacrificial test structure is fabricated to have a sacrificial pad along a top surface of the passivation layer and a sacrificial via extending into the passivation layer and electrically connected to the conductive pad; Verifying the functional circuit by testing the sacrificial pad with a probe; and Remove the victim test structure after testing. [13] Method according to claim 12, wherein Removing the sacrificial test structure creates an opening in the passivation layer, and The procedure after removing the victim verification structure still includes the following: Creating an initial dielectric material above the passivation layer and in the opening; Creating a second dielectric material over the first dielectric material; Creating a via that extends through the first dielectric material and contacts the conductive pad; and Creating a bond pad that extends through the second dielectric material and contacts the via. [14] Method according to claim 13, wherein the production of the sacrificial test structure comprises: Creating a recess in the passivation layer to expose the conductive pad; Deposition of a solder material in the recess and along the top surface of the passivation layer; and Structuring the solder material that is arranged along the top surface of the passivation layer. [15] Method according to claim 13 or 14, wherein the removal of the sacrificial test structure comprises performing a wet etching process to remove the solder material, wherein the wet etching process further removes a portion of the passivation layer adjacent to the conductive pad to create an undercut, the opening comprising the recess and the undercut. [16] Method according to any one of claims 13 to 15, wherein the via is produced laterally adjacent to a position of the opening, wherein an upper part of the via is embedded in the first dielectric material and a lower part of the via is embedded in the passivation layer. [17] Method according to any one of claims 13 to 16, wherein a portion of the first dielectric material fills the opening, and The via is produced in such a way that it is embedded in the part of the first dielectric material. [18] Method for manufacturing a semiconductor device, comprising: Fabricating an interconnect structure over a substrate, wherein the interconnect structure connects electrical components fabricated on the substrate to form a functional circuit; Creating a conductive pad over and in electrical connection with the interconnect structure; Creating a passivation layer over the conductive pad and the interconnect structure; Creating a sacrificial test structure that extends through the passivation layer and is electrically connected to the conductive pad; Testing the functional circuit by testing the sacrificial test structure with a probe; Removing the victim test structure after testing; and After removing the sacrificial test structure, a via and a bond pad are created, which are placed over the conductive pad and electrically connected to it. [19] Method according to claim 18, wherein Removing the sacrificial test structure creates an opening in the passivation layer, and Creating the via and bond pad includes the following: Establishing an initial dielectric material in the opening and along the top surface of the passivation layer; Creating a second dielectric material over the first dielectric material; Creating the via in the first dielectric material, wherein the via contacts the conductive pad; and Fabricating the bond pad in the second dielectric material, wherein the bond pad is positioned over the via and contacts it. [20] Method according to claim 18 or 19, wherein the manufacture of the sacrificial test structure comprises: Creating a recess in the passivation layer to expose the conductive pad; Deposition of a solder material in the recess and along the top surface of the passivation layer; and Structuring the solder material that is arranged along the top surface of the passivation layer.

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