CIRCUIT AND PROCEDURE FOR INTERCONNECT TEST

Abstract

A circuit comprises a first die having a first and second interface circuit, a second die having a third and fourth interface circuit, and a first interconnect configured to operationally couple the first die to the second die through the third and fourth interface circuits via the first and second interface circuits. During a first operating phase, the first through fourth interface circuits are each configured to receive control data based on a first frequency, the control data containing a series of sample data bits for testing the first interconnect.During a second operating phase, following the first, interface circuits one through four are each configured to receive test data based on a second frequency. This test data includes a series of acquisition data bits for testing the first interconnect. The second frequency is essentially higher than the first.

Description

CROSS-REFERENCE TO RELATED REGISTRATION

[0001] This application claims the priority and benefit of the preliminary US patent application No. 63 / 681,447, filed on August 9, 2024, entitled “Design-for-Test Method for Die-to-Die Interconnect Delay Test”, which is incorporated by reference into the present application. BACKGROUND

[0002] Integrated circuits (ICs) with a multi-die design (e.g., 3-dimensional (3D) ICs) can contain stacks of multiple dies or chiplets in a single package. The dies can be connected by die-to-die interconnects (D2D interconnects). BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 is a block diagram of an exemplary circuit according to some embodiments. Fig. Figure 2 is a block diagram of an exemplary circuit according to some embodiments. Fig. Figure 3 is a block diagram of an exemplary circuit according to some embodiments. Fig. 4A and Fig. Figure 4B shows schematic representations of an exemplary circuit according to some embodiments. Fig. 5A is a table showing an exemplary implementation of a circuit according to some embodiments. Fig. 5B is a table showing an exemplary implementation of a circuit according to some embodiments. Fig. 6A, Fig. 6B, Fig. 6C and Fig. Figure 6D shows block diagrams of an exemplary circuit according to some embodiments. Fig. 7A and Fig. Figure 7B shows block diagrams of an exemplary circuit according to some embodiments. Fig. 8A, Fig. 8B and Fig. Figure 8C are schematic representations of exemplary circuits according to some embodiments. Fig. 9A, Fig. 9B, Fig. Figures 9C are schematic representations of an exemplary circuit according to some embodiments. Fig. 10A and Fig. Figure 10B shows block diagrams of an exemplary circuit according to some embodiments. Fig. Figure 11 is a flowchart of an exemplary method for operating a circuit according to some embodiments. Fig. Figure 12 is a flowchart of an exemplary method for operating a circuit according to some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments, or examples, for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first structural element over or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, such that the first and second structural elements might not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition serves the purpose of simplification and clarity and does not itself imply any relationship between the different embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative terms such as "underlying", "below", "under", "overlying", "above", "above", "below", and the like may be used herein to facilitate description and to describe the relationship of one element or structural element to another element(s) or structural element(s), as illustrated in the figures. These spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0006] In general, an IC can have multiple dies connected by D2D interconnects. These interconnects must be tested for various types of defects, such as delay tests between the dies. For example, a delay test might involve a first die (Die 1) and a second die (Die 2), and the test can be performed based on a test clock frequency ranging from 10 to 100 MHz. These frequencies are typically lower than the IC's operating frequency, so they do not specify the operating conditions of the D2D interconnects.

[0007] The present disclosure can provide techniques for D2D interconnect testing. During an initial operating phase, a first die can be configured to provide a second die with control data specifying a test type, based on a first frequency. During a second operating phase following the first, the first die can be configured to provide the second die with test data based on a second frequency that is significantly higher than the first frequency. The lower frequency of the first clock reduces the risk of errors or failed control data transmission, while the higher frequency of the second clock speeds up the delay test. Additionally, source-synchronous clocking mitigates timing control problems related to clock synchronization between the two dies.Moreover, if the second frequency is similar to or equal to the operating frequency of the IC, the delay test can more accurately reflect the real operating conditions of the D2D interconnects.

[0008] Fig. Figure 1 is a block diagram of an exemplary circuit 100 according to some embodiments. The circuit 100 may be or have an IC D2D interface. For example, the circuit 100 may have a 3D or 2.5D IC interface. The circuit 100 may have a first die 110, a second die 120, and an interconnect 130. Fig. Figure 1 is a non-restrictive example shown, and circuit 100 may have more, fewer, or different components than those shown in relation to Fig. 1 are shown or described.

[0009] In some embodiments, the first die 110 may have a first interface circuit and a second interface circuit. The first interface circuit may be RX / TX1 and the second interface circuit may be TX / RX1. The second die 120 may have a third interface circuit and a fourth interface circuit. The third interface circuit may be TX / RX2 and the fourth interface circuit may be RX / TX2.

[0010] In some embodiments, a first interconnect of the interconnect 130 can be configured to operationally couple the first die 110 to the second die 120. The first interconnect of the interconnect 130 can operationally couple the first die 110 to the second die 120 via the first and second interface circuits and the third and fourth interface circuits. In some embodiments, the first interconnect of the interconnect 130 can be configured solely for the connection between the first and second interface circuits of the first die 110 and the third and fourth interface circuits of the second die 120.

[0011] The first Die 110 can be configured to perform a delay test with the second Die 120, for example, based on the first interconnect of Interconnect 130. In some examples, the delay test can include a first operating phase and a second operating phase. During the first operating phase, each of the first through fourth interfaces can be configured to receive control data based on a first frequency (e.g., a first clock). The control data can include a series of sample data bits for testing the first interconnect of Interconnect 130. During the second operating phase, which follows the first operating phase, each of the first through fourth interfaces can be configured to receive test data based on a second frequency (e.g., a second clock) that is significantly higher than the first frequency.In some embodiments, the test data may include a series of acquisition data bits for testing the first interconnect. In some embodiments, the first frequency ranges, for example, from 10 to 100 MHz. The second frequency ranges from 1 to 5 GHz and / or is substantially similar to or equal to the operating frequency of the IC. Because the first clock frequency can be lower than the second clock frequency, the risk of errors or failed control data transmission can be reduced. Additionally, the higher frequency of the second clock can speed up the delay test.

[0012] In some embodiments, the delay test can include a third operating phase. During the third operating phase, the second die 120 can provide the first die 110 with a test result based on the first clock signal. The second die 120 can then provide the test result according to the type of delay test based on the control data and a test signal.

[0013] In some embodiments, during the initial operating phase, the first interface circuit may be configured to receive control data based on the first frequency. The second interface circuit may be configured to receive control data from the first interface circuit based on the first frequency. The fourth interface circuit may be configured to receive control data from the second interface circuit via a second interconnect, based on the first frequency. The third interface circuit may be configured to receive control data from the fourth interface circuit based on the first frequency.

[0014] In some embodiments, during the second operating phase, the first interface circuit can be configured to receive test data based on the second frequency. The second interface circuit can be configured to receive test data through the first interface circuit based on the second frequency. The fourth interface circuit can be configured to receive test data through a second interconnect from the second interface circuit based on the second frequency. The third interface circuit can be configured to receive test data through the fourth interface circuit based on the second frequency.

[0015] In some embodiments, the first die 110 (and / or the second die 120) can be configured to determine, based on result data, whether the interconnect is malfunctioning. The result data can be provided by the second die 120 (and / or the first die 110) in response to receiving the test data. In some embodiments, at least one of the first die 110 and the second die 120 includes a die wrapper register (DWR) circuit to provide the result data and determine whether a particular interconnect is malfunctioning.

[0016] Fig. Figure 2 is a block diagram of an exemplary circuit 200 according to some embodiments. In some embodiments, the circuit 200 may be substantially similar to the circuit 100 and / or include structural elements of the same. For example, the circuit 200 may have the first die 110, the second die 120, the interconnect 130, etc., configured to test a first defect (resistive open (high-resistance)) 231A and a second defect (resistive bridge (high-resistance)) 231B. Fig. Figure 2 is a non-restrictive example shown, and circuit 200 may have more, fewer, or different components than those shown in relation to Fig. 2 are shown or described.

[0017] In some embodiments, the type of delay test can be one of two defect types, including the first defect, Resistive Open (High-R Delay), 231A, and the second defect, Resistive Bridge (High-R Delay), 231B. To test the first defect 231A, a high-speed transition from 0 → 1 and from 1 → 0 can be generated on each mesh. To test the second defect 231B, a high-speed transition from 0 → 1 and from 1 → 0 can be generated on each mesh, while other meshes can be held at an opposite constant value.

[0018] Fig. Figure 3 is a block diagram of an exemplary circuit 300 according to some embodiments. In some embodiments, the circuit 300 may be substantially similar to the circuit 100 and / or include structural elements of the same. For example, the circuit 300 may have the first die 110, the second die 120, the interconnect 130, etc., configured to test a third defect (locked-at-0 / 1) 331C and a fourth defect (hard-bridge defect) 331D. Fig. Figure 3 is a non-restrictive example shown, and circuit 200 may have more, fewer, or different components than those shown in relation to Fig. 3 are shown or described. In some embodiments, the type of delay test may be one of defect types that include the third defect, Locked-at-0 / 1, 331C and the fourth defect, Hard Bridge Defect, 331D.

[0019] Fig. 4A and Fig. Figure 4B shows schematic representations of an exemplary circuit 400 according to some embodiments. In some embodiments, the circuit 400 may be substantially similar to the circuit 100 and / or include structural elements of the same. For example, the circuit 400 may have the first die 110, the second die 120, the interconnect 130, etc., while these are arranged in various ways, as shown in Figure 4B. Fig. 4A and Fig. 4B shown. Fig. 4A and Fig. Figure 4B shows non-restrictive examples and the circuit 400 may have more, fewer or different components than those shown in the figures or described in relation to them.

[0020] As in Fig. As shown in Figure 4A, in some embodiments the circuit 400 can be configured such that the first die 110 and the second die 120 can be arranged laterally relative to each other (2.5D integration). The circuit 400 can have various structural elements to enable the 2.5D configuration. For example, as shown in Fig. As shown in Figure 4A, the interconnect 130 can be formed within an interposer layer that can be arranged over a substrate.

[0021] As in Fig. As shown in Figure 4B, in some embodiments the circuit 400 can be configured such that the first die 110 and the second die 120 can be arranged vertically relative to each other (3D integration). The circuit 400 can have various structural elements to enable the 3D configuration. For example, as shown in Fig. As shown in Figure 4B, the interconnect 130 can be formed between the first die 110 and the second die 120, while the first die 110 and the second die 120 can be formed on the substrate.

[0022] Fig. Table 500A is an exemplary implementation of a circuit according to some embodiments. In some embodiments, Table 500A shows an exemplary implementation of circuit 100. Fig. Figure 5A is a non-restrictive example shown and the implementation in Table 500A may have more, fewer or different implementations than those shown in the figure or described in relation to it.

[0023] In some embodiments, the circuit 100 can perform a "slow-rise: 0 → 1 delay test". The first die 110 can provide control data corresponding to the delay test to the second die 120 during the first operating phase. This can sometimes be referred to as a "sample load" or "shift" operation. The second die 120 can receive the control data from the first die 110 and identify that the type of delay test is the "slow-rise: 0 → 1 delay test". In response to the identification of the delay type, the second die 120 can set an RX value to "1" in clock cycle o during the second operating phase.

[0024] During the second operating phase, the first die 110 can provide a test signal "0" as a TX value in clock cycle 0. The first die 110 can provide the test signal "1" in clock cycle 1. The first die 110 can provide the test signal "0" in clock cycle 2.

[0025] In response to the RX value being "0" in clock cycle 1 and "1" in clock cycle 2, the second die 120 can determine that the interconnect 130 passes the delay test. In some embodiments, the second die 120 can provide a "pass" test result during a third operating phase (sometimes called "sampling discharge") based on the first clock. In response to the RX value being "1" in clock cycle 1 or "0" in clock cycle 2, the second die 120 can determine that the interconnect 130 fails the delay test. In some embodiments, the second die 120 can provide a "fail" test result during the third operating phase based on the first clock.

[0026] Fig. Table 500B is an exemplary implementation of a circuit according to some embodiments. In some embodiments, Table 500B shows an exemplary implementation of circuit 100. Fig. Figure 5B shows a non-restrictive example and the implementation in Table 500B may contain more, fewer or different implementations than those shown in the figure or described in relation to it.

[0027] In some embodiments, the circuit 100 can perform a "slow-decrease: 1 → 0 delay test". The first die 110 can provide control data corresponding to the delay test to the second die 120 during the first operating phase. The second die 120 can receive the control data from the first die 110 and identify that the type of delay test is the "slow-decrease: 0 → 1 delay test". In response to identifying the type of delay, the second die 120 can set an RX value to "0" in clock cycle o during the second operating phase.

[0028] During the second operating phase, the first Die 110 can provide a test signal "1" as a TX value in clock cycle 0. The first Die 110 can provide the test signal "0" in clock cycle 1. The first Die 110 can provide the test signal "1" in clock cycle 2.

[0029] In response to the RX value being "1" in clock cycle 1 and "0" in clock cycle 2, the second die 120 can determine that the interconnect 130 passes the delay test. In some embodiments, the second die 120 can provide a "Pass" test result during the third operating phase based on the first clock. In response to the RX value being "0" in clock cycle 1 or "1" in clock cycle 2, the second die 120 can determine that the interconnect 130 fails the delay test. In some embodiments, the second die 120 can provide a "Fail" test result during the third operating phase based on the first clock.

[0030] Fig. 6A, Fig. 6B, Fig. 6C and Fig. Figures 6D are block diagrams of an exemplary circuit 600 according to some embodiments. In particular, the figures show the circuit 600 during various operating phases. In some embodiments, the circuit 600 may be substantially similar to the circuit 100 and / or include structural elements of the same. For example, the circuit 600 may have a first die 610, a second die 620, and an interconnect 630, which may be substantially similar to the first die 110, the second die 120, and the interconnect 130, respectively, and / or include structural elements of these. Fig. 6A, Fig. 6B, Fig. 6C and Fig. The 6D examples shown are non-restrictive and the 600 circuit may have more, fewer, or different components than those shown in relation to Fig. 6A, Fig. 6B, Fig. 6C and Fig. 6D are shown or described. In some embodiments, the first die 610 may include a first functional logic (or sometimes called a "functional core") 614, a first clock circuit 616, and a first test signal transfer circuit 618, etc. In some embodiments, the second die 620 may include a second functional logic 624, a second clock circuit 626, and a second test signal transfer circuit 628, etc.

[0031] In some embodiments, the first die 610 may have a first interface circuit 612A and a second interface circuit 612B. As shown, the first interface circuit 612A may be RX / TX1 and the second interface circuit 612B may be TX / RX1. The second die 620 may have a third interface circuit 622A and a fourth interface circuit 622B. The third interface circuit 622A may be TX / RX2 and the fourth interface circuit 622B may be RX / TX2.

[0032] In some embodiments, a first interconnect of the interconnect 630 can be configured to operationally couple the first die 610 to the second die 620. The first interconnect of the interconnect 630 can operationally couple the first die 610 to the second die 620 via the first and second interface circuits 612A, 612B, and via the third and fourth interface circuits 622A, 622B. In some embodiments, the first interconnect of the interconnect 630 can be directed only to the intermediate connection between the first interface circuit 612A and the second interface circuit 612B of the first die 610 and the third interface circuit 622A and the fourth interface circuit 622B of the second die 620.

[0033] As shown, the first clock circuit 616 can be operationally coupled with the first functional logic 614, the first and second interface circuits 612A, 612B, etc. In some embodiments, the first clock circuit 616 can be operationally coupled with the first test signal transmission circuit 618. In some embodiments, the first clock circuit 616 can be operationally coupled with the second clock circuit 626. The first functional logic 614 can be operationally coupled with the first and second interface circuits 612A, 612B. The first and second interface circuits 612A, 612B can be operationally coupled with the first test signal transmission circuit 618.

[0034] The second clock circuit 626 can be operationally coupled with the second functional logic 624, the third and fourth interface circuits 622A, 622B, etc. In some embodiments, the second clock circuit 626 can be operationally coupled with the second test signal transmission circuit 628. The second functional logic 624 can be operationally coupled with the third and fourth interface circuits 622A, 622B. The third and fourth interface circuits 622A, 622B can be operationally coupled with the second test signal transmission circuit 628.

[0035] With reference to Fig. During an initial operating phase (referred to as a "sampling load" or "shift" operation), the first clock circuit 616 can provide an initial clock (CLK1) at a first frequency (e.g., a lower frequency). The first die 610 and the second die 620 can transmit the first clock CLK1, as shown in the figure. The first clock circuit 616 can provide the first clock CLK1 to the first interface circuit 612A, the second interface circuit 612B, and the second clock circuit 626. The second clock circuit 626 can provide the first clock CLK1 to the third interface circuit 622A and the fourth interface circuit 622B. This allows each of the TX / RX interfaces (e.g., the first through fourth interface circuits 612A, 612B, 622A, 622B) to operate based on the first frequency.

[0036] With reference to Fig. During the initial operating phase, the first Die 610 and the second Die 620 can transmit control data (SI) through the TX / RX interfaces (e.g., the first through fourth interface circuits 612A, 612B, 622A, 622B, etc.). For example, the first test signal transmission circuit 618 can receive the control data SI and send it to the first interface circuit 612A. The first interface circuit 612A can send the control data SI to the second interface circuit 612B, which can then send the control data SI back to the first test signal transmission circuit 618. The first test signal transmission circuit 618 can then send the control data SI to the second test signal transmission circuit 628, which can then send the control data SI to the fourth interface circuit 622B. The fourth interface circuit 622B can receive the control data SI and send it to the third interface circuit 622A, which can send the control data SI to the second test signal transmission circuit 628.The second test signal transmission circuit 628 can send the control data SI to the first test signal transmission circuit 618. This allows the second die 620 to receive the control data SI based on the first frequency and to perform the type of delay test based on the control data SI.

[0037] With further reference to Fig. During a second operating phase (or sometimes referred to as the "capture" operation), the first clock circuit 616 can provide a second clock (CLK2) with a second frequency (e.g., a higher frequency). The first die 610 and the second die 620 can transmit the second clock CLK2, as shown in the figure. The first clock circuit 616 can provide the second clock CLK2 to the first interface circuit 612A, the second interface circuit 612B, and the second clock circuit 626. The second clock circuit 626 can provide the second clock CLK2 to the third interface circuit 622A and the fourth interface circuit 622B. In some embodiments, the first clock circuit 616 and the second clock circuit 626 can be configured to send the second clock CLK2 to the second clock circuit 626 and the first clock signal 616, respectively.In some embodiments, during the second phase, one of the first clock circuits 616 and the second clock circuit 626 can send the second clock signal CLK2 to the other clock circuit. For example, during the second phase, the first clock circuit 616 can send the second clock signal CLK2 to the second clock circuit 626. Conversely, during the second phase, the second clock circuit 626 can send the second clock signal CLK2 to the first clock circuit 616. This allows each of the TX / RX interfaces (e.g., the first through fourth interface circuits 612A, 612B, 622A, 622B) to operate based on the second frequency.

[0038] With reference to Fig. 6D, the TX / RX interfaces (e.g., the first to fourth interface circuits 612A, 612B, 622A, 622B) can generate the test signal based on the second clock CLK2 during the second operating phase in response to the first clock circuit 616 providing the second clock CLK2 at the second frequency, as for example in relation to Fig. 5A and Fig. 5B has been discussed.

[0039] Fig. 7A and Fig. Figures 7B are block diagrams of an exemplary circuit 700 according to some embodiments. In particular, the figures show the circuit 700 during various operating phases. In some embodiments, the circuit 700 may be substantially similar to the circuit 100 and / or include structural elements of the same. For example, the circuit 700 may have a first die 710, a second die 720, and an interconnect 730, which may be substantially similar to the first die 110, the second die 120, and the interconnect 130, respectively, and / or include structural elements of these. Fig. 7A and Fig. The examples shown in Figure 7B are non-restrictive and the circuit 700 may have more, fewer, or different components than those shown in relation to Fig. 7A and Fig. 7B are shown or described. In some embodiments, the first die 710 may include a first functional logic 714, a first clock circuit 716, a first control circuit 717, and a first test signal transmission circuit 718, etc. In some embodiments, the second die 720 may include a second functional logic 724, a second clock circuit 726, a second control circuit 727, and a second test signal transmission circuit 728, etc.

[0040] In some embodiments, the first die 710 may have a first interface circuit 712A and a second interface circuit 712B. As shown, the first interface circuit 712A may be RX / TX1 and the second interface circuit 712B may be TX / RX1. The second die 720 may have a third interface circuit 722A and a fourth interface circuit 722B. The third interface circuit 722A may be TX / RX2 and the fourth interface circuit 722B may be RX / TX2.

[0041] In some embodiments, the first clock circuit 716 may comprise the first control circuit 717, a first multiplexer (MUX1), a second multiplexer (MUX2), a first phase-locked loop (PLL1), a first open-loop control (OCC1), and a first clock transfer circuit (CTC1). The second clock circuit 726 may comprise the second control circuit 727, a third multiplexer (MUX3), a fourth multiplexer (MUX4), a second phase-locked loop (PLL2), a second open-loop control (OCC2), and a clock transfer circuit (CTC2).

[0042] In some embodiments, during an initial operating phase, MUX1 and MUX2 can be configured to select a first clock with a first clock frequency and provide the first clock to the first interface circuit 712A and the second interface circuit 712B, respectively. MUX3 and MUX4 can be configured to select the first clock with the first clock frequency and provide the first clock to the third interface circuit 722A and the fourth interface circuit 722B, respectively.

[0043] In some embodiments, MUX2 can be configured during the second operating phase to select a second clock with a second clock frequency and provide the second clock to the second interface circuit 712B, then to the fourth interface circuit 722B (e.g., via a first interconnect of the 730). MUX3 can be configured to select the second clock received (e.g., via a second interconnect of the 730) and provide the second clock to the third interface circuit 722A, then to the first interface circuit 712A (e.g., via the first interconnect). MUX4 can be configured to select the second clock received (e.g., via the second interconnect) and provide the second clock to the fourth interface circuit 722B.

[0044] In some embodiments, MUX1 and MUX2 can be configured to select the first clock signal based on a first control signal established in a first logic state, and MUX3 and MUX4 can be configured to select the first clock signal based on a second control signal established in the first logic state. In some embodiments, MUX1 and MUX2 can be configured to select the second clock signal based on the first control signal established in a second logic state, and MUX3 and MUX4 can be configured to select the second clock signal based on the second control signal established in the second logic state.

[0045] For example, with reference to Fig. During the first phase, PLL1, PLL2, CTC1, and CTC2 are locked. OCC1 can receive a first clock signal (CLK1), and the first clock circuit 716 can receive a signal SE of "1". The first control circuit 716 can control MUX1 to output the first clock signal (CLK1) to the first interface circuit 712A (e.g., RX / TX1) and control MUX2 to output the first clock signal (CLK1) to the second interface circuit 712B (e.g., TX / RX1) in response to receiving at least a signal SE of "1". During the first phase, OCC2 can receive the first clock signal (CLK1). The second clock circuit 726 can receive a signal SE of "1". The second control circuit 726 can control the MUX3 to output the first clock signal (CLK1) to the third interface circuit 722A (e.g. TX / RX2), and control the MUX4 to output the first clock signal (CLK1) to the fourth interface circuit 722B (e.g. RX / TX2) in response to receiving at least the SE signal of “1”.

[0046] For example, with reference to Fig. 7B, during a second phase of PLL1, is released to generate a second clock (CLK2). OCC1 can receive the second clock (CLK2). The first clock circuit 716 can receive a signal SE of "0". The first control circuit 717 can control MUX2 to output the second clock (CLK2) to the first and second interface circuits 712A, 712B, and to CTC1 in response to receiving at least the signal SE of "0". In some embodiments, CTC1 can be released during the second phase to transmit the second clock (CLK2) to MUX3 and MUX4. The second control circuit 727 can control the MUX3 to output the second clock (CLK2) to the first and third interface circuits 712A, 722A and to the CTC2, and can control the MUX4 to output the second clock (CLK2) to the fourth interface circuit 722B in response to receiving at least the SE signal of “0”.In some embodiments, CTC1 can be released during the second phase to transmit the second clock (CLK2) to MUX1. The first control circuit 717 can control MUX1 to output the second clock (CLK2) to the first interface circuit 712A in response to receiving at least the SE signal of "0". Therefore, each of the first through fourth interface circuits 712A, 712B, 722A, and 722B can receive the second clock (CLK2). This can mitigate timing control problems with clock synchronization between two dies.

[0047] Fig. 8A, Fig. 8B and Fig. 8C are schematic representations of exemplary circuits 800A, 800B, 800C according to some embodiments. In some embodiments, the circuits 800A, 800B, 800C may be part of circuits 100, 600, 700, etc. For example, the circuits 800A, 800B, 800C may be included in an interface circuit (e.g., the interface circuits RX / TX, TX / RX, etc.). In some embodiments, the circuits 800A, 800B, 800C may be a die-wrapper register circuit (DWR circuit). Fig. 8A, Fig. 8B and Fig. The examples shown in Figure 8C are non-restrictive and the circuits 800A, 800B, 800C may have more, fewer or different components than those shown in the figures or described in relation to them.

[0048] With reference to Fig. In the 8A, a first multiplexer (MUX1) can receive a signal c1 of "0" during a second phase, and a second multiplexer (MUX2) can receive a signal c0 of "1". The 800A circuit can generate test data in response to receiving sample data and a clock CLK1 / CLK2. In some embodiments, the 800A circuit can generate the test data in response to receiving function data. With reference to Fig. In the 8B version, the 800B circuit can additionally include a third multiplexer (MUX3). During the second phase, MUX1 can receive the signal c1 from "0", MUX2 can receive the signal c0 from "1", and MUX3 can receive a signal c2 from "1". The 800B circuit can generate the test data and output it to an interface circuit (e.g., RX / TX, TX / RX, etc.) in response to receiving the sample data and the clock signal CLK1 / CLK2. In some embodiments, the 800B circuit can generate the test data in response to receiving function data. With reference to Fig. During the second phase, the 800C circuit can generate the test data and output it to the interface circuit (e.g., RX / TX, TX / RX, etc.) in response to receiving the sample data and the second clock signal CLK2.

[0049] Fig. 9A, Fig. 9B, Fig. Figures 9C are schematic representations of an exemplary circuit 900 according to some embodiments. In some embodiments, the circuit 900 may be substantially similar to the circuit 100 and / or include structural elements of the same. For example, the circuit 900 may have a first die 910, a second die 920, etc., which are substantially similar to the first die 110, the second die 120, etc., and / or include structural elements of the same. Fig. 9A, Fig. 9B, Fig. Figure 9C shows non-limiting examples, and the circuit 900 may have more, fewer, or different components than those shown in or described in the figures. In some embodiments, the first die 910 may have a first control circuit 917, a first multiplexer (MUX1), and a second multiplexer (MUX2). The second die 920 may have a second control circuit 927, a third multiplexer (MUX3), and a fourth multiplexer (MUX4).

[0050] In some embodiments, with reference to Fig. 9A, state data (e.g., S, CRX, CTX, M) can be external data. The state data (e.g., S, CRX, CTX, M) can be applied in various ways. In some embodiments, the state data can be control values ​​used to apply correct selection signals to MUX1, MUX2, MUX3, and MUX4. These control values ​​can be applied based on primary inputs (Pis), test data registers (TDRs), a finite state machine capable of generating these signals, and so on. This allows the first and second operating phases of a delay test of circuit 400 to be performed by a "primary input control" (PI control). The state data can be used to control the multiplexers MUX1, MUX2, MUX3, and MUX4. With reference to Fig. In some embodiments of 9B, the state data and signal SE can be provided by a finite state machine (FSM). For example, unlike circuit 900, which is described in Fig. As shown in 9A, the circuit 900, which is in Fig. Figure 9B shows the FSMs. The first die 910 can have a first FSM 919. The second die 920 can have a second FSM 929. The first and second FSM 919 and 929 can provide the status data and signal SE. (Referring to...) Fig. In the first die 910 of circuit 900, the second die 920 of circuit 900 can additionally include a first test data register (TDR) 919. For example, the first control circuit 917 can include the first TDR 919, and the second control circuit 927 can include the second TDR 929. In some embodiments, each of the first TDR 919 and the second TDR 929 can contain the state data. In some embodiments, the first TDR 919 and the second TDR 929 can be omitted.

[0051] Further with reference to Fig. In some embodiments of the 9C, the state data can be used to control the multiplexers MUX1, MUX2, MUX3, and MUX4. In the first TDR 919, state data S can be set to "0", state data CRX can be set to "1", state data CTX can be set to "0", and state data M can be set to "1". In the second TDR 929, state data S can be set to "0", state data CRX can be set to "1", state data CTX can be set to "1", and state data M can be set to "1".

[0052] Fig. 10A and Fig. Figures 10B are block diagrams of an exemplary circuit 1000 according to some embodiments. In particular, the figures show the circuit 1000 during various operating phases. In some embodiments, the circuit 1000 may be substantially similar to the circuit 100 and / or include structural elements of the same. For example, the circuit 1000 may have a first die 1010, a second die 1020, and an interconnect 1030, which may be substantially similar to the first die 110, the second die 120, and the interconnect 130, respectively, and / or may include structural elements of these. Fig. 10A and Fig. The examples shown in Figure 10B are non-restrictive and the circuit in Figure 1000 may have more, fewer, or different components than those shown in Figure 10B. Fig. 10A and Fig. 10B shown or described with reference to it. In some embodiments, the first die 1010 may include a first clock circuit 1016, a first TDR 1019, and a first test signal transmission circuit 1018, etc. In some embodiments, the second die 1020 may include a second clock circuit 1026, a second TDR 1029, and a second test signal transmission circuit 1028, etc.

[0053] In some embodiments, the first die 1010 may have a first interface circuit 1012A and a second interface circuit 1012B. As shown, the first interface circuit 1012A may be RX / TX1 and the second interface circuit 1012B may be TX / RX1. The second die 1020 may have a third interface circuit 1022A and a fourth interface circuit 1022B. The third interface circuit 1022A may be TX / RX2 and the fourth interface circuit 1022B may be RX / TX2.

[0054] As shown, the circuit 1000 can operate based on the first and second TDRs 1019 and 1029. In some embodiments, with reference to Fig. 10A, the first control circuit (CN1) 1016, during a first phase, based on a signal SE of "1" and state data M of "1", can control MUX1 to output a first clock signal (CLK1) to the first interface circuit 1012A (e.g., RX / TX1) and control MUX2 to output the first clock signal (CLK1) to the second interface circuit 1012B (e.g., TX / RX1). The second control circuit 1026 can control MUX3 to output the first clock signal (CLK1) to the third interface circuit 1022A (e.g., TX / RX2) and control MUX4 to output the first clock signal (CLK1) to the fourth interface 1022B (e.g., RX / TX2). With reference to Fig. 10B can control the first control circuit 1016 during a second phase, based on the signal SE of “0” and the state data M of “1”, to control the MUX2 to output the second clock (CLK2) to the second and fourth interface circuits 1012B, 1022B (e.g. TX / RX1, RX / TX2) and a first clock transfer circuit (CTC1), and to control the MUX1 to output the second clock (CLK2) to the first interface circuit 1012A (e.g. RX / TX1). The second control circuit 1026 can control the MUX3 to output the second clock (CLK2) to the first and third interface circuits 1012A, 1022A (e.g. TX / RX2, RX / TX1) and a second clock transfer circuit (CTC2), and control the MUX4 to output the second clock (CLK2) to the fourth interface circuit (e.g. RX / TX2).

[0055] Fig. Figure 11 is a flowchart of an exemplary method 1100 for operating a circuit according to some embodiments. The method 1100 can be carried out by one or more components of the circuits 100, 600, 700, 1000, etc. In some embodiments, the method 1100 can be carried out by other units. In some embodiments, the method 1100 includes more, fewer, or different operations than in Figure 11. Fig. 11 shown.

[0056] In brief, procedure 1100 can start with operation 1110 to load, based on a first frequency, a first logical value, and a second logical value, into a first interface circuit of a first die or a second interface circuit of a second die. Procedure 1100 can continue with operation 1120 to detect, during a first pulse with a second frequency, a third logical value represented by the second die. Procedure 1100 can continue with operation 1120 to detect, during a second pulse with a second frequency, a fourth logical value represented by the second die. Procedure 1100 can continue with operation 1120 to determine, based on the fourth logical value, whether an interconnect coupling the first interface circuit to the second interface circuit is malfunctioning.

[0057] In Operation 1110, a first logical value and a second logical value can be loaded into a first interface circuit (e.g., the first interface circuit 612A, etc.) of a first die (e.g., the first die 610, etc.) and a second interface circuit (e.g., the third interface circuit 622A, etc.) of a second die (e.g., the second die 620, etc.) based on a first frequency. In some embodiments, the first die and the second die can be arranged laterally relative to each other. For example, the first die and the second die can be arranged in a 2.5D configuration. In some embodiments, the first die and the second die can be arranged vertically relative to each other. For example, the first die and the second die can be arranged in a 3D configuration. In Operation 1120, a third logical value, represented by the second die, can be captured during a first pulse at a second frequency.In Operation 1130, a fourth logical value, represented by the second die, can be detected during a second pulse at the second frequency. In Operation 1140, based on this fourth logical value, it can be determined whether an interconnect (e.g., Interconnect 130) that couples the first interface circuit to the second interface circuit is malfunctioning.

[0058] Fig. Figure 12 is a flowchart of an exemplary method 1200 for operating a circuit according to some embodiments. The method 1200 can be carried out by one or more components of the circuits 100, 600, 700, 1000, etc. In some embodiments, the method 1200 can be carried out by other units. In some embodiments, the method 1200 includes more, fewer, or different operations than in Figure 12. Fig. 12 shown.

[0059] In brief, procedure 1200 can start with operation 1210 to insert the die wrapper register (DWR). Procedure 1200 can continue with operation 1220 to establish a wrapper sampling chain. Procedure 1200 can continue with operation 1230 to insert testable design rules (DFT, Design for Testability) for clock control.

[0060] Method 1200 can continue with operation 1240 to perform a sample chain load (shift) operation. Method 1200 can continue with operation 1250 to perform a capture operation. Method 1200 can continue with operation 1260 to perform a sample chain discharge (shift) operation. Method 1200 can continue with operation 1270 to perform fault detection. In some embodiments, operations 1230 to 1240 can be performed during a first operating phase of a circuit. In some embodiments, operation 1250 can be performed during a second operating phase of the circuit. In some embodiments, operations 1260 to 1270 can be performed during a third operating phase of the circuit.

[0061] Operation 1210 allows DWR insertion. The TX / RX DWR can be used with a toggle function to drive interface circuits (e.g., the first through fourth interface circuits 612A, 612B, 622A, 622B) in dies (e.g., the first and second dies 610, 620). Operation 1220 allows the wrapper sampling chain to be set up by connecting the DWR in each die to sample the chain. Operation 1230 allows the DFT to be used for clock control, and an initial clock (e.g., at a lower frequency) can be applied. Operation 1240 allows the sampling chain loading (shift) operation to be performed. The DWR in the sampling chain can be driven by the initial clock by applying the DFT clock control signals. The wrapper sampling chain can then be loaded. For a slow-rise delay test, a logical state of "0" can be loaded into TX DWR.For a slow-decrease delay test, a logical state of "1" can be loaded into the TW DWR. In Operation 1250, the acquisition operation can be performed. The DWR in the sampling chain can be driven by a second clock (e.g., at a higher frequency) by applying the DFT control signals. In some embodiments, two clock pulses at the higher frequency can be applied to generate a 0 → 1 or 1 → 0 transition at the interconnect, and the transition value can be acquired on an RX cell. In Operation 1260, the sampling chain discharge (shift) operation can be performed. The DWR in the sampling chains can be driven by the first clock (e.g., at the lower frequency) by applying the DFT control signals. The sampling chains can be discharged to observe the values ​​acquired on the RX cells. In Operation 1270, fault detection can be performed.In some embodiments, a slow-rise delay error can be detected when the RX cell detects "0". In some embodiments, a slow-decrease delay error can be detected when the RX cell detects "1".

[0062] In one aspect of the present disclosure, a circuit is disclosed. The circuit comprises a first die having a first interface circuit and a second interface circuit, a second die having a third interface circuit and a fourth interface circuit, and a first interconnect configured to operationally couple the first die to the second die through the third and fourth interface circuits via the first and second interface circuits. During a first operating phase, the first through fourth interface circuits are each configured to receive control data based on a first frequency, the control data containing a series of sample data bits for testing the first interconnect.During a second operating phase, following the first, interface circuits one through four are each configured to receive test data based on a second frequency. This test data includes a series of acquisition data bits for testing the first interconnect. The second frequency is substantially higher than the first.

[0063] In another aspect of the present disclosure, a circuit is disclosed. The circuit comprises a first die, a second die, and at least one interconnect configured to operationally couple the first die to the second die. During a first operating phase, the first die is configured to provide control data specifying a type of test to the second die based on a first frequency. During a second operating phase following the first operating phase, the first die is configured to provide test data to the second die based on a second frequency, the second frequency being substantially higher than the first frequency.

[0064] In a further aspect of the present disclosure, a method is disclosed. The method comprises loading, based on a first frequency, a first logical value, and a second logical value, into a first interface circuit of a first die and a second interface circuit of a second die, respectively; detecting, during a first pulse at a second frequency, a third logical value represented by the second die; detecting, during a second pulse at the second frequency, a fourth logical value represented by the second die; and determining, based on the fourth logical value, whether an interconnect coupling the first interface circuit to the second interface circuit is malfunctioning. The second frequency is essentially higher than the first frequency.

[0065] As used here, the terms "approximately" and "about" generally indicate the value of a given quantity, which may vary based on a specific technology node associated with the semiconductor device in question. Based on that specific technology node, the term "approximately" can indicate a value of a given quantity that varies within, for example, 10-30% of the value (e.g., +10%, ±20%, or ±30% of the value).

[0066] The foregoing outlines features of some embodiments so that those skilled in the art will better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can already use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or obtain the same advantages as the embodiments presented herein. Those skilled in the art should also recognize that such equivalent designs do not deviate from the nature and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without deviating from the nature and scope of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 681,447

[0001]

Claims

[1] Circuit comprising: a first die having a first interface circuit and a second interface circuit; a second die having a third interface circuit and a fourth interface circuit; and a first interconnect that is set up to operationally couple the first die to the second die via the third and fourth interface circuits; wherein during a first operating phase the first to fourth interface circuits are each set up to receive control data based on a first frequency, the control data containing a series of sample data bits for testing the first interconnect; wherein, during a second operating phase following the first operating phase, the first to fourth interface circuits are each configured to receive test data based on a second frequency, the test data containing a series of acquisition data bits for testing the first interconnect; and where the second frequency is essentially higher than the first frequency. [2] Circuit according to claim 1, wherein during the first operating phase the first interface circuit is configured to receive the control data based on the first frequency, the second interface circuit is configured to receive the control data through the first interface circuit based on the first frequency, the fourth interface circuit is configured to receive the control data through a second interconnect from the second interface circuit based on the first frequency, and the third interface circuit is configured to receive the control data through the fourth interface circuit based on the first frequency. [3] Circuit according to claim 1, wherein during the second operating phase the first interface circuit is configured to receive the test data based on the second frequency, the second interface circuit is configured to receive the test data through the first interface circuit based on the second frequency, the fourth interface circuit is configured to receive the test data through a second interconnect from the second interface circuit based on the second frequency, and the third interface circuit is configured to receive the test data through the fourth interface circuit based on the second frequency. [4] Circuit according to any one of claims 1 to 3, wherein the first die is configured to determine, based on result data, whether the interconnect has a malfunction, and wherein the result data is provided by the second die in response to receiving the test data. [5] Circuit according to any one of claims 1 to 4, wherein the first die comprises a first multiplexer and a second multiplexer and the second die comprises a third multiplexer and a fourth multiplexer. [6] Circuit according to claim 5, wherein during the first operating phase the first multiplexer and the second multiplexer are configured to select a first clock with the first clock frequency and to provide the first clock to the first interface circuit and the second interface circuit respectively, and the third multiplexer and the fourth multiplexer are configured to select the first clock with the first clock frequency and to provide the first clock to the third interface circuit and the fourth interface circuit respectively. [7] Circuit according to claim 6, wherein during the second operating phase the second multiplexer is configured to select a second clock with the second clock frequency and to provide the second clock to the second interface circuit, then to the fourth interface circuit through the first interconnect, the third multiplexer is configured to select the second clock received through a second interconnect and to provide the second clock to the third interface circuit, then to the first interface circuit through the first interconnect, and the fourth multiplexer is configured to select the second clock also received through the second interconnect and to provide the second clock to the fourth interface circuit. [8] Circuit according to claim 7, wherein the first multiplexer and the second multiplexer are configured to select the first clock signal based on a first control signal that is set up in a first logical state, and the third multiplexer and the fourth multiplexer are configured to select the first clock signal based on a second control signal that is set up in the first logical state. [9] Circuit according to claim 8, wherein the first multiplexer and the second multiplexer are configured to select the second clock signal based on the first control signal which is configured in a second logical state, and the third multiplexer and the fourth multiplexer are configured to select the second clock signal based on the second control signal which is configured in the second logical state. [10] Circuit according to any one of claims 1 to 9, wherein the first die and the second die are arranged laterally in relation to each other. [11] Circuit according to any one of claims 1 to 9, wherein the first die and the second die are arranged vertically in relation to each other. [12] Circuit comprising: a first The; a second Die; and at least one interconnect is set up to operationally couple the first die to the second die; wherein, during an initial operating phase, the first die is set up to provide control data specifying a type of test to the second die based on a first frequency; wherein during a second operating phase following the first operating phase, the first die is set up to provide the second die with test data based on a second frequency, the second frequency being substantially higher than the first frequency. [13] Circuit according to claim 12, wherein the first die is configured to determine, based on result data, whether the at least one interconnect has a malfunction, and wherein the result data is provided by the second die in response to receiving the test data. [14] Circuit according to claim 12 or 13, wherein the first die comprises a first multiplexer and a second multiplexer and the second die comprises a third multiplexer and a fourth multiplexer. [15] Circuit according to claim 14, wherein during the first operating phase the first multiplexer and the second multiplexer are configured to select a first clock and provide the first clock to a first interface circuit and a second interface circuit respectively, and the third multiplexer and the fourth multiplexer are configured to select the first clock and provide the first clock to a third interface circuit and a fourth interface circuit respectively. [16] Circuit according to claim 15, wherein during the second operating phase the second multiplexer is configured to select a second clock and to provide the second clock to the second interface circuit, then to the fourth interface circuit through a first interconnect of the at least one interconnect, the third multiplexer is configured to select the second clock received through a second interconnect of the at least one interconnect and to provide the second clock to the third interface circuit, then to the first interface circuit through the first interconnect, and the fourth multiplexer is configured to select the second clock also received through the second interconnect and to provide the second clock to the fourth interface circuit. [17] Circuit according to any one of claims 12 to 16, wherein the first die and the second die are arranged laterally or vertically in relation to each other. [18] Procedures, including: Loading, based on a first frequency, a first logical value and a second logical value, into a first interface circuit of a first die or a second interface circuit of a second die; Capture, during a first pulse with a second frequency, a third logical value represented by the second die; Capture, during a second pulse with the second frequency, a fourth logical value represented by the second die; and Determine whether an interconnect coupling the first interface circuit to the second interface circuit is malfunctioning, based on the fourth logical value; where the second frequency is essentially higher than the first frequency. [19] Method according to claim 18, wherein the first die and the second die are arranged laterally in relation to each other. [20] Method according to claim 18, wherein the first die and the second die are arranged vertically in relation to each other.

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