semiconductor device
A semiconductor device with a zigzag or U-shaped lead frame design addresses thermal stress and machining challenges, enhancing reliability and efficiency through stress relief and improved heat dissipation.
Patent Information
- Application Number
- DE102025101810
- Authority / Receiving Office
- DE · DE
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-02-09
- Filing Date
- 2025-01-20
- Publication Date
- 2025-08-14
AI Technical Summary
Existing semiconductor devices face issues with thermal expansion/contraction differences between components due to heat application, leading to bending and stress, which requires significant machining force for lead frame formation.
The semiconductor device incorporates a plate-like lead frame with a zigzag or U-shaped loop configuration, allowing for stress relief and reduced machining force by folding adjacent straight parts at angles less than 180 degrees, and using materials with high thermal conductivity for improved heat dissipation.
This design reduces manufacturing costs and electric resistance while enhancing the reliability and efficiency of the semiconductor device by minimizing stress and improving heat dissipation.
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Abstract
Description
Background of the inventionArea
[0001] The present disclosure relates to a semiconductor device. background
[0002] A technique for using a plate-like lead frame as a wiring connected to a surface electrode of a semiconductor device to realize a large area is known. Compared with a conventionally used wire, the connection strength to the semiconductor device can be improved, and heat dissipation can also be improved. Thus, it is possible to extend the power cycle life of the semiconductor device.
[0003] However, a thermal expansion / contraction difference may occur between parts such as a substrate, the semiconductor device, the lead frame, and a sealing material due to heat applied during manufacturing, and these parts may be bent due to generation of residual stress.
[0004] JP 2017-174927 A discloses a structure that, in order to relieve stress, includes a spring member having a wave shape formed by vertically bending a lead frame by 180 degrees. Expansion / contraction of the spring member can compensate for the thermal expansion / contraction difference between the members. This makes it possible to suppress the occurrence of bending.
[0005] However, in the process described above, it is necessary to bend the lead frame 180 degrees to form the waveform. Therefore, a machining force is required. Summary
[0006] In order to solve the above-described problem, an object of the present disclosure is to provide a semiconductor device which has a lead frame having a shape for relaxing stress and can reduce a force applied during formation of the lead frame.
[0007] The features and advantages of the present disclosure can be summarized as follows.
[0008] According to one aspect of the present disclosure, a semiconductor device comprises a substrate having an electrode surface; a semiconductor component mounted on the substrate and connected to the electrode surface; a plate-like lead frame having one end connected to the semiconductor component or the electrode surface; and a sealing material configured to seal the semiconductor component, the substrate, and the lead frame, wherein, within the sealing material, adjacent straight portions of the lead frame, which form elevations and depressions in a side view, are folded over by an angle that is smaller than 180 degrees.
[0009] According to another aspect of the present disclosure, a semiconductor device includes a substrate having an electrode pad; a semiconductor component mounted on the substrate and connected to the electrode pad; a plate-like lead frame having one end connected to the semiconductor component or the electrode pad; and a sealing material configured to seal the semiconductor component, the substrate, and the lead frame, wherein, within the sealing material, the lead frame has a U-shaped loop part in a plan view, or has a zigzag shape or a step shape in a plan view.
[0010] Other and further objects, features and advantages of the invention will become more apparent from the following description. Brief description of the drawings Fig. 1 is a side view of a semiconductor device according to a first embodiment of the present disclosure. Fig. 2 is a side view of the lead frame according to the first embodiment. Fig. 3 illustrates a modification of the semiconductor device according to the first embodiment. Fig. 4 illustrates another modification of the semiconductor device according to the first embodiment. Fig. 5 is a plan view of the semiconductor device according to the second embodiment of the present disclosure. Fig. 6 is a side view of the semiconductor device according to the second embodiment of the present disclosure. Fig. 7 is a plan view of the semiconductor device according to a third embodiment of the present disclosure. Fig. 8 is a mold structure of the lead frame according to the third embodiment. Fig. 9 is a mold structure of the lead frame according to the third embodiment. Fig. 10 is a mold structure of the lead frame according to the third embodiment. Fig. 11 is a mold structure of the lead frame according to the third embodiment. Fig. 12 is a plan view of the semiconductor device obtained by combining the first to third embodiments. Description of the embodiments
[0011] A semiconductor device according to embodiments of the present disclosure will be described with reference to the drawings. The same components are denoted by the same reference numerals, and repeated descriptions thereof may be omitted. First embodiment
[0012] Fig. 1 is a side view of a semiconductor device 100 according to a first embodiment of the present disclosure. The semiconductor device 100 includes a semiconductor component 1, a substrate 3 on which the semiconductor component 1 is mounted, a plate-like lead frame 4, interconnecting materials 5 and 6, and a sealing material 9 that seals these components.
[0013] The substrate 3 includes an electrode surface 31, an insulation layer 32, and a substrate heat dissipation layer 33, and performs switching control of the semiconductor device 1. The electrode surface 31 is an electrode layer of the substrate 3. If a metal material having high thermal conductivity is used as the electrode surface 31, heat dissipation can be improved.
[0014] The insulation layer 32 is disposed between the electrode surface 31 and the substrate heat dissipation layer 33, insulating the electrode surface 31 and the substrate heat dissipation layer 33 from each other. When a deformation-resistant resin is used as the insulation layer 32, it is possible to prevent cracks from occurring even when a small deformation occurs in a component due to a power cycle or the like. The material of the insulation layer 32 is not limited to the resin, and AlN, Al2O3, Si3N4, or other materials can be used.
[0015] When a material having high thermal conductivity is used for the substrate heat dissipation layer 33, heat dissipation of the electrode surface 31 through the insulation layer 32 can be improved, and a temperature rise of the semiconductor device 100 can be suppressed.
[0016] The semiconductor component 1 is electrically connected to the electrode surface 31 by the connecting material 5. The semiconductor component 1 is, for example, a reverse-conducting insulated-gate bipolar transistor (RC-IGBT) made of Si or a metal-oxide-semiconductor field-effect transistor (MOSFET) made of SiC.
[0017] The bonding material 5 is arranged between the semiconductor device 1 and the electrode pad 31. The bonding material 6 is arranged between the semiconductor device 1 and the lead frame 4. The bonding materials 5 and 6 are preferably components with high electrical conductivity and thermal conductivity, and a solder, silver, or the like is used. A lead-free solder has a buffer role that reduces stress in addition to the properties described above, and using the lead-free solder makes it possible to improve the reliability of the semiconductor device 100. Alternatively, sintered silver can be used.
[0018] The sealing material 9 seals the semiconductor device 1, the substrate 3, the lead frame 4, and the like. The material of the sealing material 9 is desirably one that can improve the reliability of the semiconductor device 100. For example, a curable epoxy resin mixed with an SiO2 filler is used. As a sealing method, an injection molding method, for example, is used.
[0019] The lead frame 4 is a plate-like metal, and one end thereof is electrically connected to a control electrode, such as a gate electrode of the semiconductor device 1, an emitter electrode, or a collector electrode. Alternatively, one end is electrically connected to the electrode pad 31.
[0020] The other end of the lead frame 4, which is neither connected to the semiconductor device 1 nor to the electrode surface 31, extends outside the sealing material 9. In order to relieve stress, the lead frame 4 has a spring part 41 having a zigzag shape within the sealing material 9.
[0021] More specifically, at the spring part 41 having the zigzag shape, the lead frame 4 is folded to form protrusions and depressions in a side view, and a folding angle θ between adjacent straight portions forming a protrusion or depression is less than 180 degrees. In order to reduce folding force, the angle θ is more preferably 90 degrees or less, as shown in the drawing.
[0022] As the machining for the spring part 41, bending processing of a metal plate is common, but press processing using a cutting tool or the like may be used.
[0023] As described above, in the existing technology, the spring member has a wave shape, and a force is required during machining because it is necessary to bend the lead frame 4 by 180 degrees. On the other hand, when the spring member 41 is formed into a zigzag shape as in the present disclosure, a force applied during machining can be reduced. When the number of repetitions, which is the number of coils of the spring, is the same, a volume of the metal as a base material can be reduced in the case of the zigzag shape compared to the case of the wave shape. This makes it possible to reduce an electrical resistance of the lead frame and reduce manufacturing costs.
[0024] Fig. 2 is a side view of the lead frame 4 according to the first embodiment. To increase the deflection of the spring, the height W1 of the protrusion is preferably ensured to be equal to or greater than one plate thickness. The function as the spring can be performed by providing one or more protrusions and one or more depressions.
[0025] As described above, the lead frame 4 according to the present embodiment includes the spring part 41 having a zigzag shape. The lead frame 4 is folded at the spring part 41 to form protrusions and depressions in a side view, and the folding angle θ between adjacent straight portions forming a protrusion or depression is less than 180 degrees. This makes it possible to reduce the force applied during machining.
[0026] The semiconductor device 1 is not limited to a semiconductor device made of silicon and may be formed of a wide-bandgap semiconductor having a bandgap larger than that of silicon. Examples of the wide-bandgap semiconductor include silicon carbide, a gallium nitride material, and diamond. The semiconductor device 1 formed of such a wide-bandgap semiconductor can be downsized due to a high breakdown voltage and a high allowable current density. Using the downsized semiconductor device 1 makes it possible to downsize and highly integrate the semiconductor device 100 in which the semiconductor device 1 is incorporated. Furthermore, since the semiconductor device 1 has high thermal resistance, a heat dissipation fin of a heat sink can be downsized, and a water cooling unit can be replaced with an air cooling unit.This makes it possible to further downsize the semiconductor device 100. The semiconductor device 1 has low power loss and high efficiency. Thus, the semiconductor device 100 can be improved in efficiency. Note that the entire semiconductor device 1 is desirably formed from the wide band gap semiconductor; however, the semiconductor device 1 may be partially formed from the wide band gap semiconductor, and the effects described in the present embodiment are available. This applies to all the embodiments described below. [First modification]
[0027] Fig. 3 illustrates a modification of the semiconductor device 100 according to the first embodiment. One end of the lead frame 4 not connected to the semiconductor device 1 is connected to another semiconductor device 2 within the sealing material 9. The lead frame 4, which connects the two semiconductor devices 1 and 2 as shown, may include the spring member 41 having a zigzag shape. As a result, effects similar to those of the first embodiment are available. [Second modification]
[0028] Fig. 4 illustrates another modification of the semiconductor device 100 according to the first embodiment. One end of the lead frame 4, which is not connected to the semiconductor device 1, is connected to another electrode pad 312 on the substrate 3, on which the semiconductor device 1 is not mounted. The lead frame 4, which connects the semiconductor device 1 and the substrate 3 in the manner described above, may include the spring member 41 having a zigzag shape. As a result, effects similar to those of the first embodiment are available. Second embodiment
[0029] In the present embodiment, a through-hole 43, into which the bonding material 6 is filled, is provided at the front end of the lead frame 4 connected to the semiconductor device 1. Areas that are different from the first embodiment will be described below.
[0030] Fig. 5 is a plan view of the semiconductor device 100 according to the second embodiment of the present disclosure. The lead frame 4 has the through-hole 43 penetrating from a top surface of the lead frame 4 to a surface connected to the semiconductor device 1. During bonding, the bonding material 6 is filled into the through-hole 43. When bonding the semiconductor device 1 and the lead frame 4, a method is generally used in which a solder foil is inserted between the semiconductor device 1 and the lead frame 4, and the semiconductor device 1 and the lead frame 4 are soldered while being positioned.When the bonding material 6 is filled into the through hole 43 as in the present disclosure, it is not necessary to simultaneously position three components, namely the semiconductor device 1, the solder foil and the lead frame 4, and the bonding can be easily performed.
[0031] Fig. 6 is a side view of the semiconductor device 100 according to the second embodiment of the present disclosure. The bonding material 6 between the lead frame 4 and the semiconductor device 1 passes through the through-hole 43 and swells on the upper surface of the lead frame 4. Increasing a contact area between the bonding material 6 and the lead frame 4 as described above makes it possible to firmly fix the semiconductor device 1 and the lead frame 4 compared to a conventional lead frame that does not have the through-hole 43. Third embodiment
[0032] Fig. 7 is a plan view of the semiconductor device 100 according to a third embodiment of the present disclosure. In order to relax stress, the lead frame 4 according to the present embodiment includes a spring member 42 having a zigzag shape in a plan view. In other words, in the spring member 42, ridges and depressions each having a V-shape are repeatedly provided in a plan view. To form the spring member 42 according to the present embodiment, it is not necessary to fold the lead frame 4, unlike the lead frame 4 according to the first embodiment. Therefore, the spring member 42 can be machined by punching with a cutting tool or the like, and a force applied in machining can be reduced.
[0033] The spring member 42 according to the present embodiment has a large cross-sectional secondary moment compared to the first embodiment. Therefore, the expansion / contraction effect is small. To increase the deflection of the spring, the deformation amount W2 is desirably a value sufficiently larger than the plate width W3.
[0034] Fig. 8 to 11 are plan views of the lead frame 4, each illustrating a mold structure of the lead frame 4 according to the third embodiment. Fig. 8 represents the same zigzag shape as in Fig. 7. Therefore, a description of the shape is omitted. The lead frame 4 may be bent into a step shape in a plan view, as shown in Fig. 9. Note that the number of stages is not limited.
[0035] The lead frame 4 may have a U-shaped loop part in a plan view, as in Fig. 10. A corner as a folded part of the U-shape is formed with a curved line. Therefore, compared to the Fig. 8, a stress concentrated at the corner can be relieved. The spring part 42, which has a wave shape, can be formed by continuously arranging loops.
[0036] In Fig. 11, the ladder frame 4 has a step shape in a plan view as in Fig. 9, but a curved part of the step is formed with a curved line. In other words, the curved part of the step is subjected to rounding, R-beveling, and the like. Compared to Fig. 9, an effect of relaxing a stress at the corner is expected. Even in the Fig. In the zigzag shape shown in Figure 8, the folded parts of the zigzag shape can be formed with a curved line.
[0037] As described above, in the present embodiment, the spring part 42 is provided, which has a zigzag shape, a step shape, or a U-shaped loop in plan view. Therefore, stress can be relieved as in the first embodiment. Furthermore, the force applied during machining of the spring part 42 can be further reduced compared to the first embodiment.
[0038] As described above, according to the present disclosure, it is possible to provide the semiconductor device having the lead frame having the shape for relaxing stress and capable of reducing a force applied during formation of the lead frame.
[0039] The present disclosure is not limited to the above-described embodiments and may be variously modified without departing from the spirit of implementation. Furthermore, the embodiments may be appropriately implemented in combination. In this case, combined effects can be achieved. For example, Fig. 12 is a plan view of the semiconductor device 100 obtained by combining the first to third embodiments. As a result, the combined effects of the first to third embodiments are achievable.
[0040] Below, various aspects of the present disclosure are described collectively as appendices. (Appendix 1)
[0041] Semiconductor device comprising: a substrate having an electrode surface; a semiconductor device mounted on the substrate and connected to the electrode surface; a plate-like lead frame having one end connected to the semiconductor device or the electrode surface; and a sealing material configured to seal the semiconductor device, the substrate and the lead frame, wherein Within the sealing material, adjacent straight portions of the lead frame, which form elevations and depressions in a side view, are folded over by an angle that is less than 180 degrees. (Appendix 2)
[0042] Semiconductor device according to Appendix 1, wherein within the sealing material the adjacent straight portions of the lead frame are folded over by an angle which is less than 90 degrees. (Appendix 3)
[0043] Semiconductor device comprising: a substrate having an electrode surface; a semiconductor device mounted on the substrate and connected to the electrode surface; a plate-like lead frame having one end connected to the semiconductor device or the electrode surface; and a sealing material configured to seal the semiconductor device, the substrate and the lead frame, wherein within the sealing material of the lead frame has a U-shaped loop in a plan view, or has a zigzag shape or a step shape in a plan view. (Appendix 4)
[0044] Semiconductor device according to one of Appendices 1 to 3, wherein one end of the lead frame is connected to the semiconductor component, and another end of the lead frame is connected to another semiconductor device or another electrode surface within the sealing material or extends outside the sealing material. (Appendix 5)
[0045] Semiconductor device according to one of Appendices 1 to 4, wherein one end of the lead frame is connected to the semiconductor component, the other end of the lead frame has a through-hole penetrating from a top surface through the lead frame to a surface connected to the semiconductor device, and a bonding material that connects one end of the lead frame and the semiconductor device, passes through the through-hole, and swells on the top surface. (Appendix 6)
[0046] A semiconductor device according to any one of appendices 1 to 5, wherein the semiconductor component is formed by a wide band gap semiconductor. (Appendix 7)
[0047] A semiconductor device according to any one of appendices 3 to 6, wherein the lead frame has a step shape in a plan view and a bent part of the step is formed with a curved line. (Appendix 8)
[0048] A semiconductor device according to any one of appendices 3 to 6, wherein the lead frame has a zigzag shape in a plan view and a folded part of the zigzag shape is formed with a curved line.
[0049] Obviously, many modifications and variations of the present disclosure are possible in light of the above teachings. It is therefore to be understood that, within the scope of the appended claims, the invention may be practiced otherwise than as specifically described.
[0050] The entire disclosure of Japanese Patent Application No. 2024-18818, filed on February 9, 2024, including specification, claims, drawings and abstract, on which the priority of the present application is based, is incorporated herein by reference in its entirety. QUOTES CONTAINED IN THE DESCRIPTION
[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature
[0000] JP 2017-174927 A
[0004] JP 2024-18818
[0050]
Claims
[1] A semiconductor device (100) comprising: a substrate (3) having an electrode surface (31); a semiconductor component (1) mounted on the substrate (3) and connected to the electrode surface (31); a plate-like lead frame (4) having one end connected to the semiconductor component (1) or the electrode surface (31); and a sealing material (9) designed to seal the semiconductor component (1), the substrate (3) and the lead frame (4), wherein within the sealing material (9), adjacent straight partial regions of the lead frame (4), which form elevations and depressions in a side view, are folded over by an angle which is less than 180 degrees. [2] A semiconductor device (100) according to claim 1, wherein within the sealing material (9) the adjacent straight portions of the lead frame (4) are folded over by an angle which is smaller than 90 degrees. [3] A semiconductor device (100) comprising: a substrate (3) having an electrode surface (31); a semiconductor component (1) mounted on the substrate (3) and connected to the electrode surface (31); a plate-like lead frame (4) having one end connected to the semiconductor component (1) or the electrode surface (31); and a sealing material (9) designed to seal the semiconductor component (1), the substrate (3) and the lead frame (4), wherein within the sealing material (9) of the lead frame (4) has a U-shaped loop in a plan view, or has a zigzag shape or a step shape in a plan view. [4] Semiconductor device (100) according to one of claims 1 to 3, wherein one end of the lead frame (4) is connected to the semiconductor component (1), and another end of the lead frame (4) is connected to another semiconductor component (2) or another electrode surface (312) within the sealing material (9) or extends outside the sealing material (9). [5] Semiconductor device (100) according to one of claims 1 to 4, wherein one end of the lead frame (4) is connected to the semiconductor component (1), the other end of the lead frame (4) has a through-hole (43) penetrating from an upper surface through the lead frame (4) to a surface connected to the semiconductor component (1), and a connecting material (6) connecting one end of the lead frame (4) and the semiconductor device (1), passing through the through-hole (43) and swelling on the upper surface. [6] A semiconductor device (100) according to any one of claims 1 to 5, wherein the semiconductor component (1) is formed by a wide band gap semiconductor. [7] The semiconductor device (100) according to any one of claims 3 to 6, wherein the lead frame (4) has a step shape in a plan view and a bent part of the step is formed with a curved line. [8] The semiconductor device (100) according to any one of claims 3 to 6, wherein the lead frame (4) has a zigzag shape in a plan view, and a folded part of the zigzag shape is formed with a curved line.
Citation Information
Patent Citations
JAPANISCHENPATENTANMELDUNGNR.2024-18818
Power module and manufacturing method thereof
JP2017174927A