Throttle filters using substrate materials

Abstract

Novel tools and techniques for implementing a semiconductor package or a chip package are provided, and more particularly, methods, systems, and devices for implementing a semiconductor package or a chip package with an inductor are provided. In one embodiment, a semiconductor device may include an inductor comprising a first layer having a first inductor and a second inductor. A first path of the first inductor may alternate with a second path of the second inductor. The inductor may also include a second layer comprising a first capacitor having a first plate and a second capacitor having a second plate. The first capacitor plate may be coupled in parallel to at least one of the first inductor and the second inductor, and the second capacitor may be coupled in parallel to at least one of the first inductor and the second inductor.

Description

Statement on copyrightA portion of the disclosure of this specification includes material subject to copyright. The copyright owner has no objection to the facsimile reproduction of the patent document or patent disclosure as it appears in the Patent and Trademark Office Patent Record or Registry, but otherwise reserves all copyright rights whatsoever.Field of InterestThe present disclosure relates generally to methods, systems, and apparatuses for implementing a semiconductor device having a choke and capacitive features.BackgroundConductive tracks which transmit electronic signals have the potential to radiate energy at different frequencies. As serializer / deserializer (SerDes) bus speeds increase over time with future generations of semiconductor devices, energy dissipation becomes worse because many of the emitted frequencies are not only harmonics of clock and data, but fundamental operating frequencies. Therefore, the energy radiation interferes with other electrical devices or signals in the vicinity of the radiation source.Thus, there is a need for more robust and scalable solutions for implementing semiconductor packages and die packages with chokes. Therefore, methods, systems, and apparatus for implementing semiconductor or die packages with inductors are provided.Brief Description of the DrawingsFurther understanding of the nature and advantages of certain embodiments may be obtained by reference to the remaining portions of the specification and the drawings, in which the same reference numerals are used to refer to similar components. In some cases, a sub-label is associated with a reference sign to identify one of several similar components. When reference is made to a reference number without indicating an existing sub-label, this is intended to refer to all of these multiple similar components. FIG. 1 is a perspective view of an embodiment of a semiconductor device having a choke and capacitive features according to various embodiments; FIGS. 2A to 2D are perspective plan views of different layers of the semiconductor device of FIG. 1 ; FIGS. 3A and 3B are schematic cross-sectional views of the semiconductor device taken along line A-A of FIG. 1 ; FIG. 4 is a graph showing the frequencies filtered by the choke of the semiconductor device of FIG. 1 ; FIGS. 5A to 5C are top views of layers of a choke and capacitive features of another semiconductor device according to various embodiments; FIG. 6 is a graph showing the frequencies filtered by the choke of the semiconductor device of FIG. 5 ; FIGS. 7A and 7B are plan views of layers of a first inductor and a second inductor, as well as capacitive features of the first inductor and the second inductor, according to various embodiments; FIG. 8 is a graph showing the frequencies filtered by the chokes of FIG. 7; FIG. 9 is a top view of a capacitive feature of a choke integrated with a signal path, according to various embodiments; FIG. 10 is a top view of a capacitive feature of a choke, according to various embodiments; FIG. 11 is a top view of an inductive feature of a reactor, according to various embodiments; and FIG. 12 is a flow diagram of a method of manufacturing a semiconductor device having a choke and capacitive features, according to various embodiments.Detailed Description of EmbodimentsVarious embodiments provide tools and techniques for implementing semiconductor or chip packages that include one or more chokes and capacitive characteristics described herein.In a first aspect, a semiconductor device includes a reactor having a first layer including a first inductor and a second inductor, a first path of the first inductor alternating with a second path of the second inductor, and a second layer including a first capacitor having a first plate and a second capacitor having a second plate. The first plate may be coupled in parallel with the first inductor and / or the second inductor, and the second plate may be coupled in parallel with the first inductor and / or the second inductor.In some cases, the semiconductor device includes a printed circuit board, the printed circuit board including the inductor. In various examples, the semiconductor device includes a multichip module and the multichip module includes the reactor.In various embodiments, the first capacitor does not include a first parallel plate disposed parallel to the first plate, and the second capacitor does not include a second parallel plate disposed parallel to the first plate.In some examples, the first path includes two or more first coils and the second path includes two or more second coils, wherein at least one coil of the two or more first coils alternates with a corresponding coil of the two or more second coils.In various cases, the first plate is coupled to a first terminal of the first inductor and the second plate is coupled to a second terminal of the second inductor. The first plate may be coupled to the first path of the first inductor and the second path of the second inductor, and the second plate may be coupled to the first path of the first inductor and the second path of the second inductor. In some examples, the first plate extends in a first direction along the first path of the first inductor and the second path of the second inductor, and the second plate extends in a second direction opposite the first direction along the first path of the first inductor and the second path of the second inductor. In some embodiments, a first protrusion of the first plate is coupled to the first path of the first inductor and a second protrusion of the second plate is coupled to the second path of the second inductor. In various cases, the first plate of the first terminal is coupled to a third terminal of the first inductor and the second plate of the second terminal is coupled to a fourth terminal of the second inductor.In some embodiments, the semiconductor device further comprises a third layer comprising a first conductive trace and a second conductive trace, wherein the first conductive trace is coupled to the first inductor and / or the first plate and the second conductive trace is coupled to the second inductor and / or the second plate. The first conductive path may be configured to transmit a first high definition multimedia interface (HDMI) signal and the second conductive path may be configured to transmit a second HDMI signal.In various embodiments, the choke is configured to filter signals at at least 2.4 gigahertz (GHz) or 5 GHz.In another aspect, a substrate includes a first layer including a first inductor and a second inductor, the first inductor alternating with the second inductor; a second layer including a first capacitor including a first plate; and the second layer and / or a third layer including a second capacitor including a second plate. The first plate may be coupled to the first inductor and the second plate may be coupled to the second inductor.In some cases, the substrate may be formed as part of a printed circuit board or a multi-chip module.In various embodiments, the first plate of a first terminal is coupled to a third terminal of the first inductor and the second plate of a second terminal is coupled to a fourth terminal of the second inductor.In some examples, the first layer further includes a third inductor and a fourth inductor. The third inductor may alternate with the fourth inductor and may be spaced apart from the first inductor and the second inductor. The second layer also includes a third capacitor including a third plate, and the second layer and / or the third layer includes a fourth capacitor having a fourth plate. In various cases, the third plate is coupled to the third inductor and the fourth plate is coupled to the fourth inductor. In some examples, the first inductor, the second inductor, the first capacitor, and the second capacitor form a first inductor configured to filter a first frequency, and the third inductor, the fourth inductor, the third capacitor, and the fourth capacitor form a second inductor configured to filter a second frequency.In another aspect, a method of manufacturing a semiconductor device having a reactor includes forming a first layer having a first inductor and a second inductor. The first inductor may be interdigitated with the second inductor. The method may further include: forming a second layer having a first capacitor including a first plate and a second capacitor including a second plate; coupling the first plate in parallel with the first inductor and / or the second inductor; and coupling the second plate in parallel with the first inductor and / or the second inductor.In various cases, the method further includes forming a dielectric layer between the first layer and the second layer.In the following description, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the described embodiments. However, it will be understood by one of ordinary skill in the art that other embodiments may be practiced without some of these details. Several embodiments are described herein, wherein although different features are attributed to different embodiments, it is understood that the features described with respect to an embodiment may also be included in other embodiments. Conversely, however, no single feature or features of a described embodiment should be considered as essential for each embodiment of the invention, since such features can be dispensed with in other embodiments of the invention.When an element is referred to herein as being "connected," "coupled," or "attached" to / to another element (such as by an electrical or communicative connection or coupling), it is understood that the elements may be directly connected to the other element, or intervening elements may be present between the elements. On the other hand, when an element is referred to as being "directly connected", "directly coupled", or "directly attached" to / to another element, it is understood that no intervening elements are present in the "direct" connection between the elements. However, the presence of a direct connection does not exclude other connections in which intermediate elements may be present.When reference is made herein to an element that is "arranged" or "positioned" in any manner relative to another element (such as disposed on, between, under, adjacent, or in another relative manner), the elements may be directly arranged or positioned relative to the other element (such as directly on another element) or may have intermediate elements between the elements. On the other hand, when an element is referred to as being "directly disposed" or "directly positioned" with respect to another element, it is understood that there are no intervening elements present in the "direct" example. However, the presence of a direct arrangement does not exclude other examples in which intermediate elements may be present.When an element is referred to herein as a "layer", the layer may be a single layer or may comprise multiple layers. For example, a conductive layer may comprise multiple different conductive materials or multiple layers of different conductive materials and a dielectric layer may comprise multiple dielectric materials or multiple layers of dielectric materials. When a layer is described as being coupled or connected to another layer, this means that the coupled or connected layers may include intervening elements between the coupled or connected layers. By contrast, if a layer is referred to as being "directly" connected or coupled to another layer, it is to be understood that no intervening elements are present between the layers. However, the presence of directly coupled or connected layers does not exclude other connections where intermediate elements may be present.Moreover, the terms left, right, front, rear, top, bottom, forward, rearward, clockwise and counterclockwise are used for explanatory purposes only and are not limited to any particular direction or orientation. Rather, they are used only to indicate relative positions and / or directions between different parts of an object and / or components. Moreover, terms such as "first", "second", "third" are used only to distinguish elements and components from each other, and are not intended to imply an order unless expressly stated otherwise.In addition, the methods and operations described herein may be described in a particular order for simplicity. However, it should be appreciated that unless the context dictates otherwise, intervening operations may occur before and / or after each portion of the described operation, and that other various methods may be rearranged, added, and / or omitted according to various embodiments.Unless otherwise indicated, all numbers used herein to indicate amounts, dimensions, etc. are to be understood as being modified in all instances by the term "about.". As used herein, the term "about" refers to deviations from the reference value or ratio of ±10% or less (e.g., ±10%, ± 5%, etc.), including the endpoints of the range.In this application, the use of the singular includes the plural, unless expressly stated otherwise, and the use of the terms "and" and "or" means "and / or" unless otherwise stated. Moreover, the use of the terms "including" and "having", as well as other forms such as "comprises", "included", "has", "have", and "had", is not to be considered exclusive. Also, terms such as "element" or "component" include both elements and components that form a unit and elements and components that form more than one unit, unless expressly stated otherwise.The phrase "at least one of" preceding a series of items, where the term "and" or "or" separates each of the items, refers to the list as a whole and not to each individual element of the list (i.e., each item). The phrase "at least one of" does not require the selection of at least one of the listed items; rather, the phrase allows a meaning that includes at least one of the items and / or at least any combination of the items. For example, the terms "at least one of A, B, and C" or "at least one of A, B, or C" refer to only A, only B, or only C, respectively, and / or any combination of A, B, and C. In cases where a selection of "at least one of each of A, B, and C" or, alternatively, "at least one of A, at least one of B, and at least one of C" is intended, it is expressly described as such.In existing semiconductor or chip packages, conductive traces that conduct electronic signals have the potential to radiate energy at various frequencies. In a non-limiting example, conductive traces that route high-definition multimedia interface (HDMI) signals may radiate energy when the HDMI signals are transmitted through the conductive traces. The energy radiated from the conductive traces with HDMI signals may interfere with, for example, other signals of a semiconductor device, such as WiFi signals, Bluetooth signals, cellular signals, or the like. In some cases, chokes may be used to reduce the radiation of the energy of the HDMI signals. However, commonly, reactors are separately inserted from the chip, the integrated circuit (IC), the printed circuit board (PCB), the multi-chip module (MCM), the substrate, or the like, and installed as a separate auxiliary device after the chip, the IC, the printed circuit board, the MCM, the substrate, or the like is manufactured.The subject technique includes a semiconductor device (such as chip, IC, PCB, MCM, substrate, or other semiconductor device or module) having an integrated inductor formed from one or more materials of the semiconductor device and fabricated as part of the semiconductor device. In various cases, the inductor may be comprised of one or more conductive layers comprising one or more conductive traces integrated into the semiconductor device. The one or more conductive layers or traces may be made of copper, aluminum, another conductive material, or other combinations of conductive materials, or the like. The choke may be configured to pass some types of signals (such as HDMI signals or the like), but attenuate or prevent other types of signals or energy (such as 2.4 gigahertz (GHz) frequencies, 5GHz frequencies, or the like) from radiating from the traces that conduct the signals after the signals have passed through the choke. This functionality enables implementing complex chokes on the semiconductor device while using only the material used to fabricate the semiconductor device. In some cases, significant product cost savings may be achieved because the chokes may be printed or manufactured with the semiconductor device and take the place of a purchased discrete choke or filter that would otherwise have to be separated from the semiconductor device and incorporated into the semiconductor device after the manufacture of the semiconductor device.FIG. 1 is a perspective view of an embodiment of a semiconductor device 100 (collectively semiconductor device 100) having transparent layers according to various embodiments. Although the layers of the semiconductor device 100 are depicted as transparent in FIG. 1, it will be understood by those skilled in the art that the layers need not be transparent and that the layers in FIG. 1 are transparent to more easily recognize the components of the semiconductor device 100. FIGS. 2A to 2D are top perspective views of various layers of the semiconductor device 100 of FIG. 1, FIGS. 3A and 3B are schematic cross-sectional views of the semiconductor device 100 taken along line A-A of FIG. 1, and one of ordinary skill in the art will understand that the semiconductor device 100 may have more or fewer components or layers than shown in FIGS. 1 to 3.In some cases, the semiconductor device 100 may be at least one of a chip, an IC, a PCB, an MCM, a substrate or other semiconductor device or module that provides a choke (such as the choke 118) made of one or more materials of the semiconductor device 100. In various cases, the semiconductor device 100 may be coupled to a device such as a set-top box, a phone, a game console, a laptop, a computer, an access point, a router, a modem, a gateway, or other device that may transmit or receive signals, or the like. In various cases, the device may be configured to receive or transmit one or more signals such as HDMI signals, WiFi signals, Bluetooth signals, cellular signals, other signals, or the like.The semiconductor device 100 may include one or more layers. The one or more layers may / may include, without limitation, one or more dielectric layers, one or more device layers, one or more conductive layers, one or more metal layers, one or more insulating layers, one or more redistribution layers, and / or the like. In some cases, the semiconductor device 100 may include a first layer 102 and a second layer 104. In some cases, the semiconductor device 100 may include one or more optional layers (such as a third layer 106, a fourth layer 108, or the like). The first layer 102, the second layer 104, the third layer 106, the fourth layer 108, or the like may be one or more metal layers comprising one or more conductive traces, ground planes, or the like. In various cases, one or more optional dielectric layers 109 a- cmay be formed between each layer or between one or more of the first layer 102, the second layer 104, the third layer 106, the fourth layer 108, or the like, as shown in FIGS. 3A and 3B.In various embodiments, the first layer 102 of the semiconductor device 100 includes a first inductor 110 and a second inductor 112. In some cases, the first inductor 110 and the second inductor 112 may be formed on the same first layer 102 such that the first inductor 110 and the second inductor 112 are in close proximity to each other. The first inductor 110 and the second inductor 112 may be formed from one or more metallizations or traces 114 and 116, respectively (such as one or more wires, one or more lines, one or more interconnects, or the like). In various cases, the one or more first conductive traces 114 of the first inductor 110 and the one or more second conductive traces 116 of the second inductor 112 may be made of copper, aluminum, or other conductive material or the like.In various cases, the conductive traces 114 and 116 may be configured to transmit / transmit (such as transmit / transmit or the like) one or more signals (such as differential signals, HDMI signals, or the like). In some cases, the one or more first conductive traces 114 may / may be configured to transmit / transmit one or more first signals having a first polarity (such as a positive polarity, a negative polarity, or the like) and the one or more second conductive traces 116 may / may be configured to transmit / transmit one or more second signals having an opposite polarity of the one or more first signals. In some cases, the one or more first signals and the one or more second signals may have the same magnitude and an opposite polarity.In various cases, a choke 118 may include at least a portion of the first layer 102 that includes the first inductor and the second inductor. The inductor 118 may be used to prevent (e.g., attenuate, filter, block, impede, prevent, limit, or the like) one or more first signals, first frequency ACs, or common mode energy from radiating from the inductor 118 while passing one or more second signals, DC (direct current) or second frequency AC currents through the traces 114 and 116 in the semiconductor device 100. Common mode energy refers to signal energy that may radiate from one or more conductive traces and interfere with or interfere with other components (such as WiFi components, Bluetooth components, cellular components, or the like) in the semiconductor device 100.In a non-limiting example, when one or more HDMI signals pass through the conductive traces 114 or 116, energy at one or more frequencies may be radiated from the one or more conductive traces 114 or 116 and interfere with one or more WiFi signals, Bluetooth signals, cellular signals, or the like. Forming the choke 118 may be used to prevent the energy of the HDMI signals passing through the conductive traces 114 or 116 from radiating at certain frequencies after the signals pass through the choke 118 and interfere with one or more WiFi signals, Bluetooth signals, cellular signals, or the like of the semiconductor device 100.The choke 118 may be formed by alternating a first path 120 of the one or more first conductive traces 114 with a second path 122 of the one or more second conductive traces 116. Alternating the first path 120 with the second path 122 may include intertwining or twisting the first path 120 with the second path 122. Interdigitating the first path 120 and the second path 122 may include forming the second path 122 between each turn of the first path 120 such that one turn of the first path 120 is not immediately adjacent to a next turn of the first path 120. In some cases, as shown in FIGS. 1 and 2A, the conductive traces 114 and 116 of the inductors 110 and 112 may be formed in an alternating circular pattern, one or more alternating turns, a spiral pattern, or the like. Alternatively, the alternating pattern may be triangular, square, rectangular or similar. Alternating paths 120 and 122 may increase the magnetic flux generated by the current flowing through inductors 110 and 112, and thus increase the induction of conductive traces 114 and 116, thereby preventing energy at certain frequencies from radiating from the conductive traces after the signals pass through inductor 118.In some cases, the first inductor 110 may have a first terminal 124 and a third terminal 126, and the second inductor 112 may have a second terminal 128 and a fourth terminal 130. In some cases, the first port 124, the third port 126, the second port 128, or the fourth port 130 may be one or more input ports or output ports configured to receive or transmit one or more signals (such as HDMI signals, or the like).In some examples, the first layer 102 may also include a ground plane 131 surrounding the first inductor 110 and the second inductor 112. The ground plane 131 may be used to reduce interference or noise between one or more signals (such as HDMI signals, WiFi signals, Bluetooth signals, cellular signals, or the like) of the semiconductor device 100. The ground plane 131 may also be used as a return path for the current of one or more signals from different components of the semiconductor device 100.In various embodiments, the semiconductor device 100 or the inductor 118 may further include a first capacitor 132 and a second capacitor 134 on the second layer 104 of the semiconductor device 100. In some cases, the second layer 104 may be over or under the first layer 102. Capacitor 132 may include a first plate 136 and second capacitor 134 may include a second plate 138. The first plate 136 and the second plate 138 may be coupled (such as electrically coupled or the like) to the first inductor 110 and / or the second inductor 112. The combination of inductors 110 and 112 and capacitors 132 and 134 may form common mode resonant circuits that more strongly inhibit particular frequencies than chokes without capacitive coupling. In various cases, the size and / or shape of the inductors 110 and 112 and the capacitors 132 and 134, the number of turns of the inductors 110 and 112, the amount of coupling between the inductors 110 and 112 and the capacitors 132 and 134, or the like, may be varied or adjusted to prevent particular or selected frequencies.In some examples, the first plate 136 may be a first single capacitor plate 136 and the second plate 138 may be a second single capacitor plate 138. The capacitor 132 with the first single capacitor plate 136 and the second capacitor 134 with the second single capacitor plate 138 are different from other types of capacitors having two parallel plates or interdigitated "fingers.". The first capacitor 132 and the second capacitor 134 each have only one or a single capacitor plate 136 and 138 without a corresponding second parallel plate. In other words, the first capacitor does not include a first parallel plate disposed parallel to the first plate, and the second capacitor does not include a second parallel plate disposed parallel to the first plate. Significantly smaller circuit layouts can be formed by coupling a single capacitor plate 136 from the first terminal 124 to or with the third terminal 126 of the first inductor 110 and a single capacitor plate 138 from the second terminal 128 to or with the fourth terminal 130 of the second inductor 112. In some cases, the circuit layouts or the semiconductor device 100 may have fewer layers, since two parallel capacitor plates may not need to be formed on different layers of the circuit or the semiconductor device 100. These smaller layouts may help avoid unnecessary copper features leading to parasitic effects that degrade the performance of the semiconductor device 100.Depending on the size and shape of the first single capacitor plate 136 and the second single capacitor plate 138, each plate may be coupled to all turns of the first inductor 110 or the second inductor 112 or to certain turns or portions of the first inductor 110 or the second inductor 112. In some cases, the first single capacitor plate 136 and the second single capacitor plate 138 may be coupled to both the first inductor 110 and the second inductor 112. Alternatively, in other cases, the first single capacitor plate 136 may be coupled to the first inductor 110 and the second single capacitor plate 138 may be coupled to the second inductor 112. In some cases, the first single capacitor plate 136 may be coupled to the first inductor 110 without coupling to the second inductor 112 and the second single capacitor plate 138 may be coupled to the second inductor 112 without coupling to the first inductor 110.To ensure that the first single capacitor plate 136 is not coupled to the second inductor 112, the first single capacitor plate 136 may be etched at locations where the second inductor could contact the first single capacitor plate 136. A similar process could be performed for the second single capacitor plate 138. In some cases, the first single capacitor plate 136 may be connected to the first terminal 124 of the first inductor 110 via a first via 140, and the second single capacitor plate 138 may be coupled to the second terminal 128 of the second inductor 112 via a second via 142.In various cases, the first single capacitor plate 136 or the second single capacitor plate 138 may be electrically parallel to the first inductor 110 and / or the second inductor 112. In some cases, the first single capacitor plate 136 extends in a first direction D 1 and is coupled to both the first path 120 of the first inductor 110 and the second path 122 of the second inductor 112, and the second single capacitor plate 138 extends in a second direction D 2 opposite the first direction D 1 and is coupled to both the first path 120 of the first inductor 110 and the second path 122 of the second inductor 112. Alternatively, in other cases, the first single capacitor plate 136 extends in the first direction D 1 and is coupled to the first path 120 of the first inductor 110, and the second single capacitor plate 138 extends in the second direction D 2 opposite to the first direction D 1 and is coupled to the second path 122 of the second inductor 112.In some cases, the second layer 104 may also include a ground plane 144 surrounding the first capacitor 132 and the second capacitor 134. Ground plane 144 may function in a similar manner to ground plane 131.In some embodiments, the semiconductor device 100 may also include a first signal path 146 and a second signal path 148. The first signal path 146 and the second signal path 148 may be formed or formed on a third layer 106 of the semiconductor device 100. The third layer 106 may be formed over or under the layers 102 and 104. Alternatively, in other cases, the first signal path 146 and the second signal path 148 may be embodied on the first layer 102 or the second layer 104. In some cases, the first signal trace 146 may be coupled to the first inductor 110 or the first capacitor 132 via the first via 140, and the second signal trace 148 may be coupled to the second inductor 112 or the second capacitor 134 via the second via 142. In various cases, the first signal path 146 may be configured to transmit or receive one or more signals (such as HDMI signals or the like) to or from the one or more first conductive paths 114, and the second signal path 148 may be configured to transmit or receive one or more signals (such as HDMI signals or the like) to or from the one or more second conductive paths 116. In some cases, the third layer 106 may also include a ground plane 150 surrounding the first signal path 146 and the second signal path 148. Ground plane 150 may function in a similar manner to ground plane 131.In some cases, the semiconductor device 100 may also include one or more optional ground planes 152 above or below the first signal path 146 and the second signal path 148. For example, the ground plane 152 may be on the fourth layer 108 below the third layer 106, as shown in FIGS. 1 and 3. Ground plane 152 may function in a similar manner to ground plane 131.In various examples, the semiconductor device 100 may also include one or more vias 154 coupling one or more of the ground planes 131, 144, 150, 152 or the like. The one or more vias 154 may be configured to reduce interference or noise between one or more signals (such as HDMI signals, WiFi signals, Bluetooth signals, cellular signals, or the like) of the semiconductor device 100. The one or more vias 154 may also be used as a return path for the current of one or more signals from various components on the semiconductor device 100.In various cases, as described above and below, the first inductor 110, the second inductor 112, the first capacitor 132, and the second capacitor 134 may be adjusted or modified to filter out or prevent certain frequencies from radiating from the traces after the signals pass through the inductor 118. Various embodiments of the choke 118 that prevent different frequencies are shown below with reference to FIGS. 1-8.In the embodiment shown in FIGS. 1-3, the choke 118 may be configured to filter out 2.4 GHz and some other frequencies, as shown in the diagram 400 of FIG. 4. To filter 2.4 GHz, the first single capacitor plate 136 is coupled (such as electrically coupled or the like) to the first terminal 124 of the first inductor 112 via a first line 140 and is electrically parallel to both the first inductor 110 and the second inductor 112, and the second single capacitor plate 138 is coupled to the second terminal 128 of the second inductor 112 via the second via 142 and is electrically parallel to both the first inductor 110 and the second inductor 112. In other words, the first single capacitor plate 136 is coupled to the first terminal 124 of the first inductor 110 via the first via 140 and is coupled to one or more conductive traces 114 and 116 of both the first inductor 110 and the second inductor 112, and the second single capacitor plate 138 is coupled to the second terminal 128 of the second inductor 112 via the second via 142 and is coupled to one or more conductive traces 114 and 116 of both the first inductor 110 and the second inductor 112. FIG. 4 shows the performance of the choke of FIGS. 1 to 3 when 2.4 GHz is filtered out. As can be seen from curve 400 in FIG. 4, 2.4 GHz has the greatest suppression of all frequencies and is prevented from radiating from the traces after the signals have passed through the choke 118.In the embodiment shown in FIGS. 5A to 5C, the reactor 502 shown in FIG. 5C may be configured to filter out 5 GHz. The inductor 502 of FIG. 5 may be used in or in addition to the semiconductor device 100 or another semiconductor device instead of the inductor 118 of FIGS. 1-3. The inductor 502 may include a first layer 504 having a first inductor 506 and a second inductor 508. The inductors 506 and 508 may be similar to the inductors 110 and 112 described with respect to FIGS. 1-3. The inductor 502 may further include a second layer 510 having a first capacitor 512 with a first single capacitor plate 514 and a second capacitor 516 with a second single capacitor plate 518.In some cases, the first single capacitor plate 514 may include one or more first protrusions or fingers 520 aand 520 b(collectively first protrusions 520) and the second single capacitor plate 518 may include one or more second protrusions or fingers 522 aand 522 b(collectively second protrusions 522). The one or more first protrusions 520 may be configured to be coupled to one or more turns or portions of the first inductor 506 without being coupled to one or more turns of the second inductor 508, while the one or more second protrusions 522 may be configured to be coupled to one or more turns or portions of the second inductor 508 without being coupled to one or more turns of the first inductor 508. The coupling of the first single capacitor plate 514 to the first inductor 506 and the coupling of the second single capacitor plate 518 to the second inductor 508 is illustrated in the inductor 502 of FIG. 5C. In various cases, the one or more first protrusions 520 may be sized and shaped to follow a path of the first inductor 506, while the one or more second protrusions 522 may be sized and shaped to follow a path of the second inductor 508.To filter 5 GHz, the first single capacitor plate 514 may be coupled (such as electrically coupled or the like) to a first terminal 524 of the first inductor 506 and electrically parallel to the first inductor 506. In other words, the first single capacitor plate 514 is coupled to the first terminal 524 of the first inductor 506, and one or more first protrusions 520 of the first single capacitor plate 514 are coupled to one or more turns or portions of the one or more conductive traces 528 of the first inductor 506. The second single capacitor plate 518 may be coupled to a second terminal 526 of the second inductor 508 and electrically parallel to the second inductor 508. In other words, the second single capacitor plate 518 is coupled to the second terminal 526 of the second inductor 508, and one or more first protrusions 520 of the second single capacitor plate 518 are coupled to one or more turns or portions of the one or more conductive traces 530 of the second inductor 508. As is apparent from the curve 600 in FIG. 6, although 5.5 GHz of all frequencies is suppressed most, the radiation of 5 GHz from the conductive lines is also inhibited after the signals pass through the choke 502.In some cases, a plurality of chokes may be used in the semiconductor device 100 instead of or in addition to the choke 118 of FIGS. 1 to 3, as shown in FIG. 7. Each choke may be configured to filter a different frequency (such as 2.4 GHz, 5 GHz, or the like). In FIG. 7, two chokes may be formed with four inductors and four capacitors. The first inductor may include a first layer 702 shown in FIG. 7B and having a first inductor 704 and a second inductor 706. The second inductor may include the first layer 702 and include a third inductor 708 and a fourth inductor 710. The third inductor 708 and the fourth inductor 710 may be spaced apart from the first inductor 704 and the second inductor 706. The inductors 704- 710 may be similar to the inductors 110 and 112 described in FIGS. 1-3.The first inductor may also include a second layer 712 shown in FIG. 7A that includes a first capacitor 714 having a first single capacitor plate 716 and a second capacitor 718 having a second single capacitor plate 720. The second inductor may also include the second layer 712 and include a third capacitor 722 with a third single capacitor plate 724. The second inductor may also include a third layer 726 illustrated in FIG. 7C, which includes a fourth capacitor 728 and a fourth single capacitor plate 730. In various cases, the first layer 702 may be coupled between the second layer 712 and the third layer 726. In some examples, the first, second, third, and fourth capacitors may all be formed on the second layer 712, or various variations or configurations of the first, second, third, and fourth capacitors may be formed on the second layer 712 and the third layer 726. In a non-limiting example, the first and third capacitors could be embodied on the second layer 712 while the second and fourth capacitors could be embodied on the third layer 726.The first throttle of FIG. 7 may be configured to filter 5 GHz. To filter 5 GHz, the first single capacitor plate 716 may be coupled (such as electrically coupled or the like) to the first inductor 704 and electrically connected in parallel with the first inductor 704. In some cases, the first single capacitor plate 716 may be coupled to one or more turns or portions of the one or more turns of the first inductor 704 in a similar manner as described above with respect to FIG. 5. In some cases, the first single capacitor plate 716 may be selectively etched to ensure that only selected portions of the first single capacitor plate 716 are coupled to the first inductor 704 or the second inductor 706. The second single capacitor plate 720 may be coupled to the second inductor 706 and electrically parallel to the second inductor 706. In some cases, the second single capacitor plate 720 may be coupled to one or more turns or portions of the one or more turns of the second inductor 706 in a similar manner as described above with respect to FIG. 5. In some cases, the second single capacitor plate 720 may be selectively etched to ensure that only selected portions of the second single capacitor plate 720 are connected to the first inductor 704 or the second inductor 706.The second choke may be configured to filter 2.4 GHz. To filter 2.4 GHz, the third single capacitor plate 724 may be coupled to the third inductor 708 and is electrically parallel to the third inductor 708 and / or the fourth inductor 710. In some cases, the third single capacitor plate 724 may be coupled to one or more turns or portions of the one or more turns of the third inductor 708 in a similar manner as described above with respect to FIG. 5. In some cases, the third single capacitor plate 724 may be selectively etched to ensure that only selected portions of the third single capacitor plate 724 are coupled to the third inductor 708 or the fourth inductor 710. The fourth single capacitor plate 730 may be coupled to the fourth inductor 710 and electrically parallel to the third inductor 708 and / or the fourth inductor 710. In some cases, the fourth single capacitor plate 730 may be coupled to one or more turns or portions of the one or more turns of the fourth inductor 710 in a similar manner as described above with respect to FIG. 5. In some cases, the fourth single capacitor plate 730 may be selectively etched to ensure that only selected portions of the fourth single capacitor plate 730 are connected to the third inductor 708 or the fourth inductor 710.Curve 800 in FIG. 8 shows that both 2.4 GHz and 5 GHz are prevented from radiating from the traces after the signals pass through the chokes of FIG. 7.In some embodiments, as shown in FIG. 9, a first single capacitor plate 902 may be integrated with and extend from a first signal trace 904 and the second single capacitor plate 906 may be integrated with and extend from a second signal trace 908. The first and second individual capacitor plates may operate in a manner similar to the capacitor plates described in Figures 1 to 8, while the first signal path and the second signal path may operate in a manner similar to the signal paths described in Figures 1 to 3. The first signal trace 904 and the second signal trace 908 may be used to transmit or receive one or more signals from the traces of the one or more inductors described above with respect to FIGS. 1-8. The first single capacitor plate 902 or the second single capacitor plate 906 may be configured to contact the first inductor and / or the second inductor in different ways, as described in FIGS. 1-8, to filter out different frequencies.In some cases, as shown in FIG. 10, a first single capacitor plate 1002 and a second single capacitor plate 1004 may be tapered to couple energy into one or more selected portions of the one or more inductors. In FIG. 10, the first and second individual capacitor plates 1002 and 1004 are wider near an outer portion 1006 of the capacitor plates. Therefore, more energy may be coupled into the outermost portion of the one or more inductors.In various examples, as shown in FIG. 11, a first inductor 1102 and a second inductor 1104 may be more symmetrical and uniform than the inductors shown in FIGS. 1-3. In the embodiment shown in FIG. 11, the path of the first inductor 1102 aligns with the path of the second inductor 1104 and merges with the path of the second inductor 1104.FIG. 12 is a flow diagram of a method of manufacturing a semiconductor device according to various embodiments. The method described in Figure 12 is one way in which the components of Figures 1-11 may be made. However, other methods of making the components of Figures 1-11 may be used.The method 1200 may begin at block 1205 by forming a first layer comprising a first inductor and a second inductor. The first inductor may alternate with the second inductor in a manner similar to that described in FIGS. 1-3.Next, in block 1210, the method 1200 may include forming a second layer having a first capacitor comprising a first single capacitor plate and a second capacitor comprising a second single capacitor plate. In some cases, one or more dielectric layers may be formed between the two or more layers of the semiconductor device formed by the method 1200. In various cases, a choke (such as choke 118 or the like) may be formed by forming the first layer with the first inductor and the second inductor and forming the second layer with the first capacitor and the second capacitor.In various cases, the inductor, the first layer, the second layer, or the dielectric layer may be formed as one or more layers of a semiconductor device (such as a chip, ICs, PCBs, MCMs, substrate, or other semiconductor device or module). In other words, the inductor, the first layer, the second layer or the dielectric layer may be manufactured or manufactured together with the semiconductor device and may be included or integrated in the semiconductor device. In a non-limiting example, the inductor, the first layer, the second layer, or the dielectric layer may be formed as one or more layers of a PCB and integrated into the structure of the PCB. In this way, the choke is integrated into the structure of the PCB and not a separate, discrete component that can be coupled to the PCB after the manufacture of the PCB.The method 1200 may then proceed to optional block 1215 and couple the first single capacitor plate in parallel with the first inductor and / or the second inductor. In optional block 1220, the method may include connecting the second capacitor in parallel with the first inductor and / or the second inductor. Coupling the first single capacitor plate or the second single capacitor plate to the first inductor and / or the second inductor may be similar to the operations described in FIGS. 1-11. In some cases, to couple the first single capacitor plate or the second single capacitor plate to the first inductor and / or the second inductor, the first single capacitor plate or the second single capacitor plate may be etched to ensure that selected portions of the first single capacitor plate or the second single capacitor plate are coupled to the first inductor and / or the second inductor. In some cases, the first single capacitor plate or the second single capacitor plate may be etched to ensure that selected portions of the first single capacitor plate or the second single capacitor plate are not coupled to or contact selected portions of the first inductor or the second inductor.The techniques and processes described above with respect to various embodiments may be used to manufacture the semiconductor devices or components of FIGS. 1-11 and / or components thereof as described herein.Moreover, while the operations of the methods and operations described herein are described in a particular order to simplify the description, unless the context dictates otherwise, various operations may be reordered, added, and / or omitted according to various embodiments. Moreover, the methods described with respect to a method or operation may be incorporated into other described methods or operations. Likewise, system components described according to a particular structural architecture and / or with respect to a system may be organized into alternative structural architectures and / or incorporated into other described systems. While various embodiments are described with or without particular features to simplify the description and illustrate aspects of these embodiments, the various components and / or features described herein with respect to a particular embodiment may be replaced, added, and / or removed from other described embodiments unless the context dictates otherwise. Thus, although several embodiments are described above, the invention is to be understood as including all modifications and equivalents within the scope of the following claims.

Claims

A semiconductor device, comprising: a choke comprising: a first layer having a first inductor and a second inductor, wherein a first path of the first inductor alternates with a second path of the second inductor; and a second layer having a first capacitor comprising a first plate and a second capacitor comprising a second plate, wherein the first plate is coupled in parallel to the first inductor and / or the second inductor and the second plate is coupled in parallel to the first inductor and / or the second inductor.The semiconductor device of claim 1, wherein the semiconductor device comprises a printed circuit board and the printed circuit board comprises the choke.The semiconductor device of claim 1, wherein the semiconductor device comprises a multichip module and the multichip module comprises the choke.The semiconductor device of claim 1, wherein the first capacitor does not include a first parallel plate disposed parallel to the first plate, and the second capacitor does not include a second parallel plate disposed parallel to the first plate.The semiconductor device of claim 1, wherein the first path comprises two or more first coils and the second path comprises two or more second coils, and at least one coil of the two or more first coils alternates with a corresponding coil of the two or more second coils.The semiconductor device of claim 1, wherein the first plate is coupled to a first terminal of the first inductor and the second plate is coupled to a second terminal of the second inductor.The semiconductor device of claim 6, wherein the first plate is coupled to the first path of the first inductor and the second path of the second inductor, and the second plate is coupled to the first path of the first inductor and the second path of the second inductor.The semiconductor device of claim 7, wherein the first plate extends in a first direction along the first path of the first inductor and the second path of the second inductor, and the second plate extends in a second direction opposite to the first direction along the first path of the first inductor and the second path of the second inductor.The semiconductor device of claim 6, wherein a first protrusion of the first plate is coupled to the first path of the first inductor and a second protrusion of the second plate is coupled to the second path of the second inductor.The semiconductor device of claim 6, wherein the first plate of the first terminal is coupled to a third terminal of the first inductor and the second plate of the second terminal is coupled to a fourth terminal of the second inductor.The semiconductor device of claim 1, wherein the semiconductor device further comprises: a third layer comprising a first conductive trace and a second conductive trace, wherein the first conductive trace is coupled to the first inductor and / or the first plate and the second conductive trace is coupled to the second inductor and / or the second plate.The semiconductor device of claim 11, wherein the first path is configured to transmit a first high definition multimedia interface (HDMI) signal and the second path is configured to transmit a second HDMI signal.The semiconductor device of claim 1, wherein the choke is configured to filter signals at 2.4 gigahertz (GHz) and / or 5 GHz.A substrate comprising: a first layer comprising a first inductor and a second inductor, wherein the first inductor alternates with the second inductor; a second layer comprising a first capacitor having a first plate; and the second layer and / or a third layer comprising a second capacitor having a second plate, wherein the first plate is coupled to the first inductor and the second plate is coupled to the second inductor.The substrate of claim 14, wherein the substrate is formed as part of a printed circuit board or a multi-chip module.The substrate of claim 14, wherein the first plate is coupled from a first terminal to a third terminal of the first inductor and the second plate is coupled from a second terminal to a fourth terminal of the second inductor.The substrate of claim 14, wherein the first layer further comprises a third inductor and a fourth inductor, the third inductor alternating with the fourth inductor and spaced apart from the first inductor and the second inductor, the second layer further comprises a third capacitor having a third plate; and the second layer and / or the third layer comprises a fourth capacitor having a fourth plate, the third plate coupled to the third inductor and the fourth plate coupled to the fourth inductor.The substrate of claim 17, wherein the first inductor, the second inductor, the first capacitor, and the second capacitor form a first inductor configured to filter a first frequency, and the third inductor, the fourth inductor, the third capacitor, and the fourth capacitor form a second inductor configured to filter a second frequency.A method of manufacturing a semiconductor device comprising a reactor, the method comprising: forming a first layer comprising a first inductor and a second inductor, wherein the first inductor is interlaced with the second inductor; forming a second layer comprising a first capacitor having a first plate and a second capacitor having a second plate; coupling the first plate in parallel with the first inductor and / or the second inductor; and coupling the second plate in parallel with the first and / or second inductor.The method of claim 19, further comprising: forming a dielectric layer between the first layer and the second layer.

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