Neural networks for language generation

Abstract

Apparatus, systems, and techniques for generating speech signal tones. In at least one embodiment, a processor uses one or more neural networks to generate a first speech signal tone based at least in part on a second speech signal tone and a reference tone.

Description

TECHNICAL FIELDAt least one embodiment relates to processing resources used to perform and facilitate artificial intelligence. For example, at least one embodiment relates to processors or computer systems used to improve speech quality of audio data of speech using neural networks according to various novel techniques described herein.BACKGROUNDAudio data of speech signal tones often contain noise and distortions due to poor pick-ups or environmental factors, making it difficult for listeners to understand speech. The quality of speech signal tones can be improved by means of neural networks.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 illustrates an example system for generating high-quality speech signals using one or more neural networks, according to at least one embodiment; FIG. 2 illustrates an example system for generating features from audio data using one or more neural networks, according to at least one embodiment; FIG. 3 illustrates an example system that generates contextual information from reference tones using one or more neural networks, according to at least one embodiment; FIG. 4 illustrates an example system that generates high-quality speech signals using one or more neural networks, according to at least one embodiment; FIG. 5 illustrates an example method for generating high-quality speech signals using one or more neural networks, according to at least one embodiment; FIG. 6 illustrates an example method for generating context information from reference tone data using one or more neural networks, according to at least one embodiment; FIG. 7 illustrates an example method for generating high-quality speech signals using one or more neural networks, according to at least one embodiment; FIG. 8 shows an example of audio data with improved speech quality, according to at least one embodiment; FIG. 9 illustrates an example system that generates high quality speech signals using one or more neural networks, according to at least one embodiment; FIG. 10 illustrates an example system that generates high quality voice signals using one or more application programming interfaces (APIs), according to at least one embodiment; FIG. 11A illustrates logic in accordance with at least one embodiment; FIG. 11B illustrates logic in accordance with at least one embodiment; FIG. 12 illustrates training and deployment of a neural network, according to at least one embodiment; FIG. 13 illustrates an example of a system for data centers, according to at least one embodiment; FIG. 14A shows an example of an autonomous vehicle, according to at least one embodiment; FIG. 14B shows an example of camera locations and fields of view for the autonomous vehicle of FIG. 14A, according to at least one embodiment; FIG. 14C is a block diagram illustrating an example system architecture for the autonomous vehicle of FIG. 14A, according to at least one embodiment; FIG. 14D is a diagram illustrating a system for communicating between one or more cloud-based servers and the autonomous vehicle of FIG. 14A, according to at least one embodiment; FIG. 15 is a block diagram illustrating a computer system according to at least one embodiment; FIG. 16 is a block diagram illustrating a computer system according to at least one embodiment; FIG. 17 illustrates a computer system according to at least one embodiment; FIG. 18 illustrates a computer system according to at least one embodiment; FIG. 19A illustrates a computer system according to at least one embodiment; FIG. 19B illustrates a computer system according to at least one embodiment; FIG. 19C illustrates a computer system according to at least one embodiment; FIG. 19D illustrates a computer system according to at least one embodiment; FIGS. 19E-19F show a common programming model, according to at least one embodiment; FIG. 20 illustrates example integrated circuits and associated graphics processors, in accordance with at least one embodiment; FIGS. 21A-21B show example integrated circuits and associated graphics processors, according to at least one embodiment; FIGS. 22A-22B show additional example graphics processor logic, according to at least one embodiment; FIG. 23 illustrates a computer system according to at least one embodiment; FIG. 24A illustrates a parallel processor according to at least one embodiment; FIG. 24B illustrates a partition unit according to at least one embodiment; FIG. 24C illustrates a processing cluster according to at least one embodiment; FIG. 24D illustrates a graphics multiprocessor according to at least one embodiment; FIG. 25 illustrates a system including multiple graphics processing units (GPUs) according to at least one embodiment; FIG. 26 illustrates a graphics processor according to at least one embodiment; FIG. 27 is a block diagram illustrating a processor microarchitecture for a processor, according to at least one embodiment; FIG. 28 illustrates a deep learning application processor according to at least one embodiment; FIG. 29 is a block diagram illustrating a neuromorphic processor according to at least one embodiment; FIG. 30 illustrates at least portions of a graphics processor according to one or more embodiments; FIG. 31 illustrates at least portions of a graphics processor according to one or more embodiments; FIG. 32 illustrates at least portions of a graphics processor according to one or more embodiments; FIG. 33 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment; FIG. 34 is a block diagram of at least portions of a graphics processor core, according to at least one embodiment; FIGS. 35A-35B illustrate the logic of thread execution including an array of processing elements of a graphics processor core, according to at least one embodiment; FIG. 36 illustrates a parallel processing unit ("PPU") according to at least one embodiment; FIG. 37 illustrates a general processing cluster ("GPC"), in accordance with at least one embodiment; FIG. 38 illustrates a memory partition unit of a parallel processing unit ("PPU"), in accordance with at least one embodiment; FIG. 39 illustrates a streaming multiprocessor, according to at least one embodiment; FIG. 40 is an example dataflow diagram for an advanced computer pipeline according to at least one embodiment; FIG. 41 is a system diagram for an example system for training, adjusting, instantiating, and employing machine learning models in an advanced computer pipeline, according to at least one embodiment; FIG. 42 includes an example diagram of an advanced computer pipeline 4110A for processing image data, according to at least one embodiment; FIG. 43A includes an example dataflow diagram of a virtual instrument supporting an ultrasound device, according to at least one embodiment; FIG. 43B includes an example dataflow diagram of a virtual instrument supporting a CT scanner, according to at least one embodiment; FIG. 44A shows a dataflow diagram for a process for training a machine learning model, according to at least one embodiment; FIG. 44B is an example illustration of a client-server architecture for enhancing annotation tools with pre-trained annotation models, according to at least one embodiment; and FIG. 45 illustrates components of a system for accessing a large language model, in accordance with at least one embodiment.DETAILED DESCRIPTIONIn the following description, various techniques and systems are described. For purposes of explanation, specific configurations and details are set forth in order to provide a thorough understanding of the possible implementations of the techniques. However, it will be apparent that the techniques described below may be practiced in various configurations without the specific details. In addition, known aspects may be omitted or simplified in order not to obscure the described techniques.In at least one embodiment, neural networks may not generate high quality speech (e.g., above a signal-to-noise ratio) from low quality input data, where low quality audio data includes noise and distortions such as noise, hum, or distortions due to bad capture devices or environmental factors (e.g., walls of a room causing reverberation). For example, it would be difficult to hear the speaker's voice when recorded in a concert whose walls cause reverberation.In at least one embodiment, a neural network (e.g., one or more of spectrogram encoder 112, context generator 114, waveform encoder 116, inferencing module 122, and waveform decoder 132), executed by one or more processors, generates high-quality speech signals using different features (e.g., spectral features, phase features) of input audio data (e.g., low-quality audio data 102) modified by specifying (high-quality) speech signals in reference audio data, such as reference audio data 104 (e.g., a high-quality audio signal that includes desired SNR, clarity, good spatial relationships between levels, delays). In at least one embodiment, neural network solves at least one technical problem because neural network derives conclusions using spectral and phase characteristics and uses a reference signal as an indication of how high quality outputs should be (e.g., levels of SNR) to generate accurate, high quality audio signals in an appropriate time frame (e.g., a few seconds).In at least one embodiment, neural network executed by a processor includes four portions (e.g., layers, components) that it uses to generate an enhanced audio signal.In at least one embodiment, first portion includes an encoder (e.g., waveform encoder 112) that generates phase characteristics of input data by encoding waveform into a feature map (e.g., a data structure representing phase of waveform). In at least one embodiment, one or more neural networks include a separate encoder (e.g., spectrogram encoder 112) that generates spectral features of input data by encoding spectral features into a different feature map.In at least one embodiment, one or more neural networks include a third portion (e.g., context generator 114) that includes a transformer, where transformer generates context (e.g., relationships between different frequencies, relationships between phases of audio, clarity) using spectral characteristics of reference audio data that include high quality voice signals (e.g., a reference audio signal that includes high quality audio signals with desired SNR). In at least one embodiment, reference audio signal is an example signal that includes desired characteristics of a high-quality audio signal (e.g., a high-quality audio signal recorded in a studio with excellent equipment). In at least one embodiment, one or more neural networks perform feature encoding in these three sections in parallel, reducing time required to generate a signal.In at least one embodiment, a fourth portion of one or more neural networks generates high-quality audio data (e.g., enhanced audio data 106) using encoded characteristics (e.g., spectral characteristics, phase characteristics) of audio data and context encoded from reference audio data 104. In at least one embodiment, one or more neural networks learn what good phase and clarity information is as high-quality reference signal, and use this as an indication in encoding and generating features for its output signal (e.g., enhanced audio data 106).In at least one embodiment, a processor includes one or more circuits to use one or more neural networks to generate one or more speech signals from one or more first signals based at least in part on two or more different features of one or more first signals modified by one or more indications of one or more speech signals in one or more second signals.In at least one embodiment, an audio signal may be denoised in a different manner, such as by ringing the denoised audio signal as it would be in different environments (e.g., studio, outdoors, small room, etc.). In at least one embodiment, a neural network executed by one or more processors uses an environment reference signal to modify a speech signal such that modified speech signal sounds as in another environment. In at least one embodiment, software executed by a processor causes a neural network to identify features of a speech signal and determine whether to adapt those features for decoding depending on whether those features are included in a reference signal. For example, if the speech signal has features corresponding to the wind but the reference signal does not have corresponding features, the neural network would remove the features corresponding to the wind from the features to be decoded to generate the audio signal. In at least one embodiment, a neural network could amplify wind-corresponding features if reference signal contains more wind noise than speech signal.FIG. 1 illustrates an example system 100 for generating high quality speech signals using one or more neural networks, according to at least one embodiment. In at least one embodiment, system 100 includes one or more processors including one or more circuits for performing one or more operations described herein. In at least one embodiment, system 100 includes a spectrogram coder 112, a context generator 114, a waveform decoder 116, an inferencing module 122, and a waveform decoder 132.In at least one embodiment, as used in each implementation described herein, unless context dictates otherwise or expressly stated to the contrary, terms such as "module" and nominal verbs (e.g., spectrogram coder 112, context generator 114, waveform coder 116, inference module 122, waveform decoder 132, Fourier transform module 212, down sampling module 222, Fourier transform module 312, reference coder 314, attention module 316, fusion module 412, condition module 414, bottleneck module 416, audio data acquisition module 912, and speech enhancement module 914) described in FIGS. 1-46 will each denote any combination of software logic, hardware logic, and / or circuitry configured to provide functionality described herein.In at least one embodiment, software described in FIGS. 1-46 includes, alone or in any combination, for example, operating systems, device drivers, application software, database software, graphics software (for example, Radeon, Intel Graphics), web browsers, development software (for example, integrated development environments, code editors, compilers, interpreters), network software (for example, intel PROset, intel Advanced Network Services), simulation software, real-time operating systems (RTOS), artificial intelligence software (for example, Scikillearn, TensorFlow, PyTor, Accord.NET, Approach Machout), robotic software (ROBEL, MS AirSi, Apollo Badu, AWS RoboMaker, ROSbot 2.0, Poppy Project), firmware (e.g., BIOS / UEFI, router, smartphone, consumer electronics, embedded systems, printers, solid state drive (SSD)), application programming interface (API), containerized software (e.g., Nginx, Apache HTTP Server, MySQL, PostgreSQL, Redis, Memcached, Node.js, Elasticsarch, Gitlab, Jenkins, WordPress), container orchestration platform (e.g., Kubernetes, Docker Swarm, Apache Mesos, Nomad, Amazone ECS, Microsoft Azure Kubernetes Service, Google Kubernetes Engine, Red Hat OpenShift, Rancher), or any other embodiment embodied as a software package, code, and / or instruction set or instructions.In at least one embodiment, hardware described in FIGS. 1-46 includes, for example, singly or in any combination, hardwired circuits, programmable circuits, state machine circuits, fixed function circuits, execution units, and / or firmware storing instructions executed by programmable circuits. In at least one embodiment, circuit may be part of a larger system, for example, alone or in any combination, integrated circuit (IC), system on chip (SoC), central processing unit (CPU), graphics processing unit (GPU), computing unit (DPU), digital signal processor (DSP), tensor processing unit (TPU), accelerated processing unit (APU), application specific integrated circuits (ASIC), intelligent processing unit (IPU), neural processing unit (NPU), smart network interface controller (SmartNIC), vision processing unit (VPU), Field-Programmable Gate Array (FPGA), and so forth.In at least one embodiment, unless expressly stated otherwise, each of modules may include one or more neural networks, such as feedforward neural network, convolutional neural network (CNN), recurrent neural network (RNN), long short memory (LSTM) network, generative advanced network (GAN), constrained boltzmann machine (RBM), deep belief networks (DBN), radial base function network (RBFN), hopfield network, self-organizing maps, single- or multi-layer perceptrons, modular neural networks, spking neural networks, Deep reinforcement learning networks, echo state networks, time delay neural networks, support vector machines, attention-based neural networks, auto-encoders, graph neural networks (e.g., graph convolutional networks), variational auto-encoders, and / or transform neural networks (e.g., bidirectional encoder representations from transformers).In at least one embodiment, neural network described herein (e.g., first CNN 214, LSTM 216, SECOND CNN 224, and other neural networks described in connection with at least FIGS. 1-4 ) is an untrained neural network 1206. In at least one embodiment, neural networks may be a trained neural network 1208 that uses training dataset 1202 and training framework 1204. In at least one embodiment, neural networks are trained using various neural network training techniques (e.g., supervised learning, unsupervised learning, reinforcement learning, transfer learning, online learning, batch learning, federated learning). In at least one embodiment, training techniques include using hyperparameters such as a batch size of 256 for audio segments of 1 second duration and a learning rate of 1e^-4 using adam optimizer. In at least one embodiment, hyperparameters include setting a number of neural network parameters to 170 million.In at least one embodiment, spectrogram encoder 112 is a module that generates spectral features from audio data (e.g., low quality audio data 102). In at least one embodiment, poor quality refers to a signal that is degraded in clarity, intelligibility, and / or fidelity. In at least one embodiment, one or more low quality speech features are further described in connection with FIG. 8.In at least one embodiment, spectral characteristics relate to characteristics of audio data represented in a frequency domain. In at least one embodiment, spectral features include elements (e.g., amplitude) represented in a spectrogram, mel-frequency coefficients (MFCCs), chroma feature, spectral centroid and spread, and spectral roll-off. In at least one embodiment, spectrogram refers to a visual representation of spectrum of frequencies in a sound or other signal as they change over time. In at least one embodiment, spectrogram includes a time axis that shows how frequency content of audio signal changes over time. In at least one embodiment, spectrogram comprises a frequency axis showing different frequencies present in audio signal at a particular time. In at least one embodiment, intensity / color at each point of a spectrogram represents amplitude (or energy) of a particular frequency at a particular time, with brighter colors or higher intensity normally indicating higher energy or amplitude.In at least one embodiment, spectrogram encoder 112 generates and stacks real and imaginary values of audio data by generating a compressed absolute magnitude spectrogram as a result of performing a short-term Fourier transform (STFT). In at least one embodiment, spectrogram encoder 112 performs residual convolution operations to encode stacked real and imaginary values and generate spectral features of low quality audio data 102. In at least one embodiment, system 100 includes an audio data acquisition module 912 that generates or receives low quality audio data 102. In at least one embodiment, low quality audio data 102 includes input data 810.In at least one embodiment, context generator 114 is a module that generates context information from high-quality audio data (e.g., from reference audio data 104). In at least one embodiment, context information indicates desired characteristics of high-quality audio data (e.g., high-quality audio data recorded in a studio with excellent equipment, such as reference audio data 104). At least in one embodiment, the context information indicates, for example, phase and spectral information of the reference audio data 104. In at least one embodiment, reference audio data 104 is obtained or generated using audio data acquisition module 912. In at least one embodiment, context information is further described in connection with at least FIG. 3.In at least one embodiment, context generator 114 generates a log-mel spectrogram by performing STFT on reference audio data 104. In at least one embodiment, reference audio data 104 may comprise any high quality speech of any length. In at least one embodiment, context generator 114 generates a fixed context vector using reference audio data 104.In at least one embodiment, high quality as described herein refers to clear and comprehensible sounds that effectively preserve nuances and finenesses of voice of one or more speakers and ensure that one or more listeners can easily understand and interpret speech. In at least one embodiment, an example of high-quality speech audio data is further described in conjunction with FIG. 8.In at least one embodiment, waveform encoder 116 is a module that encodes waveform data such that encoded waveform data is aligned with spectral features (e.g., latent values of stacked real and imaginary values) generated by spectrogram encoder 112. In at least one embodiment, waveform coder 116 compresses speech information of low quality audio data 102 over time dimension while channel / function dimension is increased by a sequence of down-sampling residual convolution blocks. In at least one embodiment, waveform coder 116 generates temporal characteristics of low quality audio data (102). In at least one embodiment, system 100 controls spectrum encoder 112 and waveform encoder 116 such that both encoders have equal latency at end so that outputs of both encoders (e.g., spectral features, waveform features) may be merged together.In at least one embodiment, inferencing module 122 is a module that generates high quality speech signals (e.g., enhanced audio data 106) from low quality audio data 102 and reference audio data 104. In at least one embodiment, inferencing module 122 receives outputs from spectrogram coder 112, context generator 114, and waveform coder 116 to generate refined latent values indicative of one or more characteristics of high quality speech signals.In at least one embodiment, inferencing module 122 merges spectral features and temporal features of low quality audio data 102. In at least one embodiment, inferencing module 122 uses context information of reference audio data 104 to filter merged spectral characteristics and temporal characteristics of low quality audio data 102 to generate refined latent values. In at least one embodiment, filtering includes indicating that one or more first portions of spectral features and temporal features are more important and one or more first portions of spectral features and temporal features are less important. In at least one embodiment, inferencing module 122 includes one or more convolutional transformers that de-interlace acoustic input data of audio data 104 and embed high-quality audio features from context information of reference audio data 104.In at least one embodiment, waveform decoder 132 is a module that decodes or reconstructs audio data using latent values from inferencing module 122. In at least one embodiment, waveform decoder 132 generates enhanced audio data 106 as a result of performing the latent value upsampling. In at least one embodiment, amount of decompression is based on amount of compression of spectrogram encoder 112 and / or waveform encoder 116. For example, in at least one embodiment, if spectrogram encoder 112 and / or waveform encoder 116 uses a down-sampling factor of 2 to perform down-sampling, then waveform decoder 132 uses an up-sampling factor of 2 to perform up-sampling.In at least one embodiment, waveform decoder 132 performs multi-level upsampling to generate enhanced audio data 106. In at least one embodiment, a number of stages corresponds to a number of stages for encoding performed by spectrogram encoder 112 and waveform encoder 116. In at least one embodiment, system 100 includes skip connections (e.g., a line connecting spectrogram encoder 112 and waveform decoder 132, and waveform encoder 116 and waveform decoder 132 that allow some outputs from such encoders to be sent directly to waveform decoder 132 to generate enhanced audio data 106 comprising one or more high quality speech signals.In at least one embodiment, system 100 uses one or more circuitry to use one or more neural networks (e.g., one or more of spectrogram encoders 112, context generator 114, waveform encoder 116, inferencing module 122, and waveform decoder 132) to generate first speech signal tones in a first environment (e.g., generate enhanced audio data 106) based at least in part on second speech signal tone (e.g., low quality audio data 102) and reference tone of a second environment (e.g., reference audio data 104).In at least one embodiment, environments (e.g., first environment and second environment) refer to different physical and acoustic spaces in which audio recordings are made. In at least one embodiment, these spaces are characterized by their unique sound qualities, ambient noise levels, and acoustic characteristics that substantially affect clarity, sound, and overall quality of capture. In at least one embodiment, settings for recordings from controlled, sound-isolated studios designed for precise audio sensing may range to dynamic locations under open sky where natural sounds and ambient sounds play an important role in recording. In at least one embodiment, one environment could contribute to generating low quality audio data 102 while another environment could contribute to generating high quality audio data, such as reference audio data 104, for various reasons that are further described in connection with FIG. 8, as it has controlled, sound-proof studios designed for precise audio capture.In at least one embodiment, one or more signals in enhanced audio data 106 cause listeners to assume that enhanced audio data 106 has been recorded in a controlled environment (e.g., podcast), while one or more signals in low quality audio data 102 cause listeners to assume that enhanced audio data 106 has been recorded in an uncontrolled environment (e.g., a loud restaurant with two speaking persons), and one or more signals in reference audio data 104 cause listener to assume that enhanced sound 106 has been recorded in a controlled environment similar to the controlled environment corresponding to enhanced sound 106 but slightly different (e.g., another podcast). In at least one embodiment, there are similar (and different) environments that can blade somewhat differently.FIG. 2 illustrates an example system 200 for generating features from audio data using one or more neural networks, according to at least one embodiment. In at least one embodiment, system 200 includes a spectral coder 210 and a waveform coder 220. In at least one embodiment, low quality audio data 202 is low quality audio data 102.In at least one embodiment, spectral coder 210 is a module that generates spectral features (e.g., spectral features 204) from audio data with low quality speech signals (e.g., low quality audio data 202). In at least one embodiment, spectral coder 210 is part of spectral coder 112. In at least one embodiment, spectral coder 210 includes a Fourier transform module 212, a first CNN 214, and an LSTM 216.In at least one embodiment, spectral coder 210 receives low quality audio data 202. In at least one embodiment, low quality audio data 202 is recorded in a dynamic open-ended environment where natural noise (e.g., construction work) and environmental noise play an important role during recording. In at least one embodiment, this environment includes use of poor quality receptacles. In at least one embodiment, Fourier transform module 212 is a module that performs Fourier transforms (e.g., STFT) to generate one or more spectrograms. In at least one embodiment, performing Fourier transforms includes converting time domain signals to frequency domain, resulting in complex numbers having both real and imaginary parts. In at least one embodiment, Fourier transform module 212 calculates square root from the sum of square of real part and square of imaginary part to determine magnitudes in one or more spectrograms. In at least one embodiment, one or more spectrograms indicate frequency energy distribution of low quality audio data 202.In at least one embodiment, Fourier transform module 212 applies one or more filter banks to pass a particular frequency range, either before or after generating one or more spectrograms. In at least one embodiment, filter banks refer to a collection of digital filters used to decompose an input signal into multiple components. In at least one embodiment, filter banks include, for example, band pass filters, high pass filters, low pass filters, band rejection filters, triangular filters, mel filters, etc.In at least one embodiment, Fourier transform module 212 sends one or more spectrograms and one or more real and imaginary values calculated as a result of Fourier transforms (e.g., STFT) to first CNN 214. In at least one embodiment, first CNN 214 includes one or more convolutional neural networks that include convolutional residue layers. In at least one embodiment, first CNN 214 encodes one or more spectrograms into one or more time-series vectors and uses these vectors to generate latent values that are sent to LSTM 216.In at least one embodiment, LSTM 216 refers to long short-term memory (LSTM) networks that process sequence data (e.g., audio). In at least one embodiment, LSTM 216 is designed to process sequence of these embeddings (e.g., latent values) to learn relationships and dependencies over different time frames of audio data. In at least one embodiment, spectral features 204 that generate LSTM 216 include a sequence of embeddings of data derived from spectrograms (e.g., magnitudes of frequency components of one or more audio signals from low quality input data 202). In at least one embodiment, spectral features 204 include information such as content of speech and identity of speaker.In at least one embodiment, waveform coder 210 is a module that generates spectral features (e.g., waveform features 206) from audio data with low quality speech signals (e.g., low quality audio data 202). In at least one embodiment, waveform coder 220 is part of waveform coder 116. In at least one embodiment, waveform coder 220 includes a down sampling module 222 and a second CNN 224.In at least one embodiment, down-sampling module 222 is a module that reduces down-sampling rate of signals into low quality audio data 202. In at least one embodiment, down-sampling module 222 employs filters (e.g., low pass filters) and re-samples (e.g., at each nthsample, where n is down-sampling factor determined by down-sampling module 222). In at least one embodiment, down sampling factor must match the up sampling factor described in connection with FIG. 4. In at least one embodiment, down-sampling module 222 sends down-sampled audio data to second CNN 224. In at least one embodiment, down-sampling is performed in multiple stages (e.g., using a stack of down-samplers).In at least one embodiment, second CNN 224 includes one or more convolutional neural networks that include convolutional residue layers. In at least one embodiment, second CNN 224 extracts features, such as waveform features, that obtain phase information. In at least one embodiment, waveform features include temporal features related to characteristics of sound that are primarily related to time domain. In at least one embodiment, temporal features capture dynamics and structure of sound as it develops over time. In at least one embodiment, temporal features include, without limitation, amplitude envelope, energy, zero crossing rate, temporal centroid, rhythm and tempo, attack, decay, sustain, release (ADSR), autocorrelation, temporal variability, phase information, etc.In at least one embodiment, second CNN 224 performs dilation folds by spreading filters by inserting gaps between its elements. In at least one embodiment, the dilation folds increase receptive field of second CNN 224 without increasing number of weights of second CNN 224. In at least one embodiment, the dilation convolutions are to add contextual information to waveform features 206.In at least one embodiment, system 200 uses one or more circuitry to use one or more neural networks (e.g., one or more of spectrogram encoders 210, waveform encoders 220) to generate a first speech signal tone in a first environment based at least in part on a second speech signal tone (e.g., low quality audio data 202) and a reference tone of a second environment.FIG. 3 illustrates an example system 300 for generating context information from reference audio data using one or more neural networks, according to at least one embodiment. In at least one embodiment, system 300 includes a context generator 310. In at least one embodiment, context generator 310 is a module that generates context information (e.g., speech style included in reference audio signal 302) from reference audio signal 302. In at least one embodiment, context generator 310 is part of context generator 114. In at least one embodiment, context generator 310 includes a Fourier transform module 312, a reference encoder 314, and an attention module 316. In at least one embodiment, reference audio data 302 is reference audio data 104. In at least one embodiment, context generator 310 performs channel modelling to analyze one or more speech signals of reference audio data 302 by performing one or more techniques (e.g., multi-head attenuation) described herein, wherein channel refers to a signal in audio data.In at least one embodiment, reference audio data 302 includes one or more high quality voice signals recorded in an environment such as controlled, sonically isolated studios designed for accurate audio capture. In at least one embodiment, this environment includes the use of high-quality receptacles.In at least one embodiment, speakers of audio data may be different (e.g., reference audio data 302 vs. low quality audio data 202). For example, the speaker of the reference audio data 302 is a brite, while the speaker of the low quality speech data 202 may be an american, or vice versa. In at least one embodiment, speaker of reference audio data 302 is female, whereas speaker of inferior speech data 202 may be male, or vice versa. In at least one embodiment, reference audio data 302 is generated with a high-quality microphone that captures speech under good acoustic conditions, causing less noise and reverberation. In at least one embodiment, reference tone 302 is preprocessed to improve quality of speech.In at least one embodiment, Fourier transform module 312 is a module that performs Fourier transforms (e.g., STFT) to generate one or more spectrograms. In at least one embodiment, Fourier transform module 312 includes Fourier transform module 212. In at least one embodiment, Fourier transform module 312 sends one or more spectrograms to reference encoder 314. In at least one embodiment, reference encoder 314 includes one or more convolutional layers and one or more residual layers for further extraction of features (e.g., spectral features) from one or more spectrograms received from Fourier transform module 312.In at least one embodiment, attenuation module 316 is a module for generating context vectors of reference audio data that include high quality speech signals (e.g., reference audio data 302). In at least one embodiment, attenuation module 316 includes one or more transform neural networks that perform multi-head attenuation to extract speech style included in reference audio data 302. In at least one embodiment, style includes time-varying data and frequency-varying data of one or more voice signals in reference audio data 302. In at least one embodiment, style is not affected by speaker type (e.g., male vs. female, American vs. britical) because style of reference audio data 302 depends on environment in which reference audio data 302 was recorded, where environment may include, for example, a podcast studio using a high quality microphone that captures speech under good acoustic conditions. In at least one embodiment, style is determined by performing an analysis of one or more channels of reference audio data 302.In at least one embodiment, each attention mechanism calculates a set of attention weights that focus on different portions of input features. For example, in at least one embodiment, one header concentrates on a spectral characteristic such as MFCCs while another header concentrates on a different spectral characteristic such as spectral centroid and bandwidth. In at least one embodiment, one head concentrates on a temporal feature such as rhythm, while another head concentrates on a different temporal feature such as pitch or tonal features. In at least one embodiment, after performing multi-head attention, attention module 316 generates a context vector 304 that includes context information (e.g., style) of reference audio data 302.In at least one embodiment, system 300 uses one or more circuitry to use one or more neural networks (e.g., context generator 310) to generate a first voice signal tone in a first environment based at least in part on a second voice signal tone and a reference tone of a second environment (e.g., reference audio data 302).FIG. 4 illustrates an example system 400 for generating high quality speech signals using one or more neural networks, according to at least one embodiment. In at least one embodiment, system 400 includes an inferencing module 410. In at least one embodiment, inferencing module 410 is a module for modifying spectral features and waveform features of low quality audio data based on context information of reference audio data to generate latent values, where latent values may be used by waveform decoder 132 to generate enhanced audio data.In at least one embodiment, inferencing module 410 is part of inferencing module 122. In at least one embodiment, inferencing module 410 includes fusion module 412, condition module 414, and bottleneck module 416.In at least one embodiment, fusion module 412 is a module that fuses spectral features (processed by LSTM 216) and waveform features. In at least one embodiment, fusion module 412 receives spectral features 402 and waveform features 404. In at least one embodiment, spectral features 402 include spectral features 202. In at least one embodiment, waveform features 404 include waveform features 204. In at least one embodiment, fusion module 412 includes one or more LSTM nets to fuse spectral features 402 and waveform features 404. In at least one embodiment, merging includes concatenating both features into a single vector. In at least one embodiment, fusion module 412 includes one or more gate recurrent units (GRUs) for identifying one or more dependencies on sequential data (e.g., spectral features 402, waveform features 404). In at least one embodiment, fusion module 412 normalizes spectral features and waveform features 404 such that no single feature predominates.In at least one embodiment, a single vector having both features is input to condition module 414. In at least one embodiment, condition module 414 is a module that combines context vector with single vector having both features. In at least one embodiment, context vector 406 includes context vector 304. In at least one embodiment, condition module 414 combines context vector with said single vector having both features and sends it to bottleneck module 416.In at least one embodiment, bottleneck module 416 is a module that compresses information from audio signals, where compressed information is used to generate one or more high quality voice signals. In at least one embodiment, bottleneck module 416 receives combined information including spectral features and waveform features of low quality reference audio data as well as context information of reference audio data. In at least one embodiment, bottleneck module 416 includes one or more neural networks that retain information important for high quality speech signal reconstruction from combined information and remove any irrelevant information.In at least one embodiment, this process includes filtering spectral features and waveform features of low quality audio data with contextual information from reference audio data. In at least one embodiment, this process includes removing noise and reverberation while identifying one or more speech signals and determining to what extent modification is required to improve on one or more speech signals. In at least one embodiment, bottleneck module 416 generates latent values 408 representing information important for low quality audio reconstruction. In at least one embodiment, latent values are sampled up by waveform decoder 132, for example, to reconstruct or generate enhanced audio data with one or more high quality speech signals.In at least one embodiment, system 400 uses one or more circuitry to use one or more neural networks (e.g., inferencing module 410) to generate a first speech signal tone in a first environment based at least in part on a second speech signal tone and a reference tone of a second environment. In at least one embodiment, first voice signal tone in a first environment refers to an enhanced tone generated using latent values 408. In at least one embodiment, reference tone of a second environment is used to generate context vector 406. In at least one embodiment, second speech signal tone is used to generate spectral features 402 and temporal features 404.FIG. 5 illustrates an example method 500 for generating high quality speech signals using one or more neural networks, according to at least one embodiment. Although process 500 is depicted as a series of steps or operations, it will be understood that at least one embodiment of process 500 includes changed or reordered steps or operations or omits certain steps or operations unless expressly noted or logically required, for example, when an output of one step or operation is used as input to another. In at least one embodiment, each block of process 500 described herein is performed by one or more units described in connection with FIGS. 1-4 and 9-10, individually or in any combination. For example, the one or more entities include the spectrogram encoder 112, the context generator 114, the waveform encoder 116, the inferencing module 122, the waveform decoder 132, the Fourier transform module 212, the first CNN 214, the LSTM 216, the down sampling module 222, the second CNN 224, the Fourier transform module 312, the reference encoder 314, the attention module 316, the fusion module 412, the condition module 414, the bottleneck module 416, the audio capture module 912, and the speech enhancement module 914.In at least one embodiment, one or more units, further comprising, for example, hardware, firmware, and / or software described herein, individually or in any combination, execute process 500. In at least one embodiment, various functions are performed by a processor executing instructions stored in a memory (e.g., computer readable, machine readable) to perform process 500. In at least one embodiment, process 500 may also be implemented as computer usable instructions (e.g., microinstruction, microinstruction) stored on computer storage media or provided by a stand-alone application, service, or hosted service (stand-alone or in combination with another hosted service). In at least one embodiment, computer usable instructions executed by at least one processor (e.g., processor 902) are provided by one or more programming models (e.g., CUDA oneAPI, ROCm). In at least one embodiment, processor 902 executes one or more blocks of process 500. In at least one embodiment, one or more APIs 1010 or software program 1002, alone or in combination, execute one or more blocks of process 500.At block 502, the one or more units according to at least one embodiment receive low quality audio data and reference audio data comprising high quality speech signals. In at least one embodiment, alternatively, one or more units may capture low quality audio data using one or more transcoding devices.At block 504, the one or more units according to at least one embodiment generate spectral characteristics of the inferior audio data using a first encoder, waveform characteristics of the inferior audio data including phase information using a second encoder, and context information of the reference audio data using a third encoder and a transformer. In at least one embodiment, first encoder STFT performs on low quality audio data to generate spectral characteristics. In at least one embodiment, third encoder STFT performs on lower-level audio data to generate information used by transformer to generate context information of reference audio data.At block 506, the one or more units generate enhanced latent values using spectral features, temporal features, and context information, according to at least one embodiment. In at least one embodiment, one or more units merge spectral features and waveform features and use context information to modify merged features to generate extended latent values.At block 508, the one or more units generate audio data with high-quality speech signals using the extended latent values according to at least one embodiment. In at least one embodiment, one or more units use upsampling and / or decoding of extended latent values to generate audio data with high quality speech signals.In at least one embodiment, at least one of blocks 502, 504, 506, and / or 508 uses one or more circuitry to use one or more neural networks to generate a first speech signal tone in a first environment based at least in part on a second speech signal tone and a reference tone in a second environment.FIG. 6 illustrates an example method 600 for generating context information from reference audio data using one or more neural networks, according to at least one embodiment. Although process 600 is depicted as a series of steps or operations, it will be understood that at least one embodiment of process 600 includes changed or reordered steps or operations or omits certain steps or operations unless expressly noted or logically required, for example, when an output of one step or operation is used as input to another. In at least one embodiment, each block of process 600 described herein is performed by one or more units described in connection with FIGS. 1-4 and 9-10, individually or in any combination. For example, the one or more entities include the spectrogram coder 112, the context generator 114, the waveform coder 116, the inferencing module 122, the waveform decoder 132, the Fourier transform module 212, the first CNN 214, the LSTM 216, the down sampling module 222, the second CNN 224, the Fourier transform module 312, the reference coder 314, the attention module 316, the fusion module 412, the condition module 414, the bottleneck module 416, the audio capture module 912, and the speech enhancement module 914.In at least one embodiment, one or more units, further comprising, for example, hardware, firmware, and / or software described herein, individually or in any combination, execute process 600. In at least one embodiment, various functions are performed by a processor executing instructions stored in a memory (e.g., computer readable, machine readable) to perform process 600. In at least one embodiment, process 600 may also be implemented as computer usable instructions (e.g., microinstruction, microinstruction) stored on computer storage media or provided by a stand-alone application, service, or hosted service (stand-alone or in combination with another hosted service). In at least one embodiment, computer usable instructions executed by at least one processor (e.g., processor 902) are provided by one or more programming models (e.g., CUDA oneAPI, ROCm). In at least one embodiment, processor 902 executes one or more blocks of process 500. In at least one embodiment, one or more APIs 1010 or software program 1002, alone or in combination, execute one or more blocks of process 600.At block 602, the one or more devices receive audio comprising high quality voice signals, according to at least one embodiment. In at least one embodiment, audio includes reference audio data 104 and / or reference audio data 302.At block 604, the one or more units use an encoder to generate features of the reference audio data, according to at least one embodiment. In at least one embodiment, encoder STFT performs to generate features.At block 606, the one or more entities use an attention module to generate contextual information using features of the reference audio data, according to at least one embodiment. In at least one embodiment, context information indicates one or more characteristics (e.g., style) of high quality voice signals. In at least one embodiment, attenuation module performs multi-head attenuation to focus on different types of features (e.g., spectral feature, waveform feature, etc.)At block 608, the one or more entities transmit context information to an inferencing module to generate latent values according to at least one embodiment. In at least one embodiment, inferencing module includes inferencing module 122 and / or inferencing module 410. In at least one embodiment, at least one of blocks 602, 604, 606, and / or 608 is to use one or more circuitry to use one or more neural networks to generate a first speech signal tone in a first environment based at least in part on a second speech signal tone and a reference tone in a second environment.FIG. 7 illustrates an example method 700 for generating high quality speech signals using one or more neural networks, according to at least one embodiment. Although process 700 is depicted as a series of steps or operations, it will be appreciated that at least one embodiment of process 700 includes changed or reordered steps or operations or omits certain steps or operations unless expressly noted or logically required, for example, when an output of one step or operation is used as input to another. In at least one embodiment, each block of process 700 described herein is performed by one or more devices described in connection with FIGS. 1-4 and 9-10, individually or in any combination. For example, the one or more entities include the spectrogram coder 112, the context generator 114, the waveform coder 116, the inferencing module 122, the waveform decoder 132, the Fourier transform module 212, the first CNN 214, the LSTM 216, the down sampling module 222, the second CNN 224, the Fourier transform module 312, the reference coder 314, the attention module 316, the fusion module 412, the condition module 414, the bottleneck module 416, the audio capture module 912, and the speech enhancement module 914.In at least one embodiment, one or more units, further comprising, for example, hardware, firmware, and / or software described herein, individually or in any combination, execute process 700. In at least one embodiment, various functions are performed by a processor executing instructions stored in a memory (e.g., computer readable, machine readable) to perform process 700. In at least one embodiment, process 700 may also be implemented as computer usable instructions (e.g., microinstruction, microinstruction) stored on computer storage media or provided by a stand-alone application, service, or hosted service (stand-alone or in combination with another hosted service). In at least one embodiment, computer usable instructions executed by at least one processor (e.g., processor 902) are provided by one or more programming models (e.g., CUDA oneAPI, ROCm). In at least one embodiment, processor 902 executes one or more blocks of process 700. In at least one embodiment, one or more APIs 1010 or software program 1002, alone or in combination, execute one or more blocks of process 700.At block 702, the one or more entities receive spectral and temporal characteristics of audio data with low quality voice signals, according to at least one embodiment. In at least one embodiment, one or more units receive spectral characteristics of spectrogram encoder 112 and / or spectrogram encoder 210. In at least one embodiment, one or more units receive spectral characteristics from waveform coder 116 and / or waveform coder 220.At block 704, the one or more entities fuse the spectral features and the temporal features, according to at least one embodiment. In at least one embodiment, one or more entities include LSTM 216 and fusion module 412. In at least one embodiment, merge includes concatenation of one or more vectors representing both spectral features and temporal features.At block 706, the one or more entities receive context information of reference audio data with high-quality speech signals, according to at least one embodiment. In at least one embodiment, context information indicates one or more characteristics of high-quality speech signals in reference audio data. In at least one embodiment, one or more entities obtain context information from context generator 114, context generator 310, and / or attention module 316.At block 708, the one or more entities generate enhanced latent values based on modifying merged features using the context information, according to at least one embodiment. At block 710, the one or more entities generate an upsampling of the extended latent values to generate extended audio data with high-quality speech signals, according to at least one embodiment. In at least one embodiment, enhanced audio data with high-quality speech signals comprises high-quality speech data 820.In at least one embodiment, at least one of blocks 702, 704, 706, 708, and / or 710 is to use one or more circuits to use one or more neural networks to generate a first speech signal tone in a first environment based, at least in part, on a second speech signal tone and a reference tone of a second environment.FIG. 8 shows an example of audio data 800 with improved speech quality, according to at least one embodiment. At least one embodiment includes indicia indicative of input data 810 having low quality voice signals. In at least one embodiment, poor quality is due to poor quality or placement of microphone, improper placement of microphone, background noise, spatial acoustics (e.g., echoes / reverberation from hard surfaces), electromagnetic interference (e.g., hum noise) caused by nearby electronic devices, poor wiring and connections, limited frequency response of capturing device, low bit rate, poor coding, speaker problems (e.g., non-uniform speech levels, articulation problems, accent), microphone motion, false gain settings, improper selection of microphone type / patterns, etc.In at least one embodiment, input data of audio 810 is recorded in an environment that makes it difficult for listener to identify speech. This environment includes, for example, construction sites, overfilled restaurant, night clubs, etc.In at least one embodiment, systems (e.g., system 100, system 200, system 300, system 400, system 900, system 1000) and / or processes (e.g., process 400, process 500, process 600) generate high-quality voice data 820 from input audio data 810 that includes low-quality voice signals. In at least one embodiment, high-quality speech data 820 includes remote reverberation (or adequate reverberation), a well-defined spectrum, minimal distortion, and remote noise (e.g., traffic, humming machines, voice distortion).In at least one embodiment, listeners can easily understand high-quality voice data 820 without announcing, and each word and phonetic detail is clearly articulated. In at least one embodiment, high-quality speech data 820 includes signals that capture a wide range of sound frequencies, thereby ensuring that natural stimuli and tonal quality of one or more speakers' voice are accurately represented. In at least one embodiment, high-quality speech data 820 includes signals having a balanced dynamic range that includes good contrast between loudest and quietest portions of speech. In at least one embodiment, high-quality speech data 820 includes uniform levels that ensure that all portions of speech are equally audible. In at least one embodiment, high-quality voice data 820 has a near-zero reverberation time (RT) 60. In at least one embodiment, high-quality speech data 820 has a mean opinion score (MOS) of over 4.In at least one embodiment, high-quality voice data 820 sounds as if recorded in a controlled environment (e.g., in a podcast studio). In at least one embodiment, high-quality speech data 820 does not sound exactly as said controlled environment, but sound as if recorded in an environment similar to said controlled environment.FIG. 9 illustrates an example system 900 for improving the speech quality of audio data using one or more neural networks, in accordance with at least one embodiment. In at least one embodiment, system 900 includes a processor 902. In at least one embodiment, system 900 includes a non-transitory machine-readable medium (e.g., a computer) storing instructions that, when executed by one or more processors (e.g., processor 902) of a computer system (e.g., system 900), cause computer system to use one or more circuits to use one or more neural networks to generate a first voice signal tone in a first environment based at least in part on a second voice signal tone and a reference tone of a second environment.In at least one embodiment, processor 902 is used to implement at least a portion of FIGS. 1-4 and 10. In at least one embodiment, processor 902 is used to execute at least one block of process 500, process 600, and / or process 700.In at least one embodiment, processor 902 is part of data center 1300. In at least one embodiment, processor 902 includes a CPU (e.g., CPU 1406, CPU 1418) and / or processor 1410. In at least one embodiment, processor 902 includes CPU 1480(A) or CPU 1480(B). In at least one embodiment, processor 902 includes processor 1502. In at least one embodiment, processor 902 includes processor 1610. In at least one embodiment, processor 902 includes CPU 1702. In at least one embodiment, processor 902 is part of computer 1810. In at least one embodiment, processor 902 includes one of multi-core processors 1905( 1)... 1905(M). In at least one embodiment, processor 902 includes processor 1907. In at least one embodiment, processor 902 includes multi-core processor 1905. In at least one embodiment, processor 902 includes one or more application processors 2005. In at least one embodiment, processor 902 includes processor(s) 2302. In at least one embodiment, processor 902 includes processor 2502. In at least one embodiment, processor 902 includes processor 2700. In at least one embodiment, processor 902 includes processor 3002. In at least one embodiment, processor 902 includes a processor 3100. In at least one embodiment, processor 902 includes processor 4606.In at least one embodiment, processor 902 includes graphics processor 1418, graphics processor 1420, and / or accelerator / accelerators 1414. In at least one embodiment, processor 902 includes one of GPUs 1484(A).. 1484(H). In at least one embodiment, processor 902 includes graphics card 1512. In at least one embodiment, processor 902 includes a parallel processing unit (PPU) 1714. In at least one embodiment, processor 902 includes one of GPUs 1910( 1)... (N). In at least one embodiment, processor 902 is part of graphics acceleration module 1946. In at least one embodiment, processor 902 includes graphics processor 2010. In at least one embodiment, processor 902 includes image processor 2015. In at least one embodiment, processor 902 includes video processor 2020. In at least one embodiment, processor 902 includes graphics processor 2110. In at least one embodiment, processor 902 includes graphics processor 2140. In at least one embodiment, processor 902 includes at least one graphics core 2200. In at least one embodiment, processor 902 is part of a Universal Graphics Processor Unit (GPGPU) 2230. In at least one embodiment, processor 902 includes one or more parallel processors 2312. In at least one embodiment, processor 902 includes a parallel processor 2400. In at least one embodiment, processor 902 includes a graphics multiprocessor 2434. In at least one embodiment, processor 902 is a portion of one of GPGPUs 2506A... 2506D. In at least one embodiment, processor 902 includes graphics processor 2600. In at least one embodiment, processor 902 includes deep learning application processor 2800. In at least one embodiment, processor 902 includes a neuromorphic processor 2900. In at least one embodiment, processor 902 includes graphics processor 3008. In at least one embodiment, processor 902 includes an integrated graphics processor 3108. In at least one embodiment, processor 902 includes graphics processor 3200. In at least one embodiment, processor 902 is a portion of graphics processing engine 3310. In at least one embodiment, processor 902 includes one of shader processors 3407A... 3407F. In at least one embodiment, processor 902 includes shader processor 3502. In at least one embodiment, processor 902 is coupled to graphics execution unit 3508. In at least one embodiment, processor 902 includes PPU 3600. In at least one embodiment, processor 902 is part of general processor cluster (GPC) 3700. In at least one embodiment, processor 902 includes a streaming multiprocessor 3900. In at least one embodiment, processor 902 is part of hardware 4022. In at least one embodiment, processor 902 includes GPUs / graphics processors 4112. In at least one embodiment, processor 902 is to implement model training system 4004. In at least one embodiment, processor 902 is a processor 4506.In at least one embodiment, processor(s) 902 includes an audio data acquisition module 912 and a speech enhancement module 914. In at least one embodiment, audio data acquisition module 912 is a module that receives or generates audio data comprising one or more voice signals. In at least one embodiment, audio data acquisition module 912 generates or receives low quality audio data 102, reference audio data 104, low quality audio data 202, and / or reference audio data 302.In at least one embodiment, audio data acquisition module 912 generates one or more audio data (e.g., audio data acquisition module 912 generates or receives low quality audio data 102, reference audio data 104, low quality audio data 202, and / or reference audio data 302). In at least one embodiment, audio data acquisition module 912 records speech using microphones, digital audio recorders, audio interfaces, earphones, studio monitors, etc. In at least one embodiment, audio data acquisition module 912 samples recorded speech. In at least one embodiment, recording is performed in a studio generating a high quality speech signal (e.g., reference audio data 104, reference audio data 302). In at least one embodiment, audio data acquisition module 912 performs text-to-speech using one or more neural networks (e.g., generative adventaric networks, variation auto-encoders, LSTM) to generate audio data.In at least one embodiment, audio data acquisition module 912 receives one or more audio data from a memory, where memory includes, without limitation, hard disk drives (HDDs), magnetic tapes, solid state coatedries (SSDs), USB flash drives, memory cards, CDs, DVDs, Blu-ray discs, network attached storage (NAS), storage area network (SAN), cloud storage services (e.g., google drive, dropbox, amazone S3), etc.In at least one embodiment, audio data acquisition module 912 preprocesses one or more audio data before being used by different modules described in connection with at least FIGS. 1-4. In at least one embodiment, audio data acquisition module 912 performs, for example, slicing, slicing, aligning different audio clips, noise cancelling, normalization, equalization, compression, filtering (e.g., removing frequencies), reverberation and echo removal, time stretching and pitch shifting, sampling rate conversion, bit depth conversion, channel separation or mixing, silence removal, etc. In at least one embodiment, audio data acquisition module 912 could be used by different modules to perform processing of one or more audio data.In at least one embodiment, speech enhancement module 914 is a module that generates high quality speech signals based on low quality audio data by extracting different features from both low quality audio data and reference audio data and using these different features to identify values that need to be used to generate high quality speech signals.In at least one embodiment, speech enhancement module 914 uses one or more circuits / processors to use one or more neural networks to generate a first speech signal tone in a first environment based at least in part on a second speech signal tone and a reference audio signal of a second environment, wherein reference audio signal comprises one or more speech signals. In at least one embodiment, speech enhancement module 914 uses one or more neural networks to generate one or more spectral characteristics based at least in part on second speech signal tone. In at least one embodiment, speech enhancement module 914 uses one or more neural networks to generate one or more spectral characteristics based at least in part on second speech signal tone. In at least one embodiment, speech enhancement module 914 uses one or more neural networks to generate one or more waveform features based at least in part on second speech signal tone, wherein one or more waveform features comprise phase information. In at least one embodiment, speech enhancement module 914 uses one or more neural networks to generate contextual information based at least in part on second environment's reference tone. In at least one embodiment, speech enhancement module 914 uses one or more neural networks to merge one or more spectral features and one or more waveform features. In at least one embodiment, speech enhancement module 914 uses one or more neural networks to modify one or more different features generated from second speech signal tone based at least in part on reference tone of a second environment. In at least one embodiment, speech enhancement module 914 determines a down-sampling rate to perform down-sampling of second speech signal tone.In at least one embodiment, speech enhancement module 914 includes spectrogram encoder 112, context generator 114, waveform encoder 116, inferencing module 122, waveform decoder 132, Fourier transform module 212, first CNN 214, LSTM 216, down sampling module 222, second CNN 224, Fourier transform module 312, reference encoder 314, attention module 316, fusion module 412, condition module 414, and / or bottleneck module 416.FIG. 10 illustrates an example system 1000 for improving the voice quality of audio data using one or more application programming interfaces (APIs), according to at least one embodiment. In at least one embodiment, system 1000 uses one or more circuits to use one or more neural networks to generate a first speech signal tone in a first environment based at least in part on a second speech signal tone and a reference tone in a second environment.In at least one embodiment, software program 1002 is a software module. In at least one embodiment, software program 1002 includes one or more modules (e.g., spectrogram encoder 112, context generator 114, waveform encoder 116, inferencing module 122, waveform decoder 132, Fourier transform module 212, first CNN 214, LSTM 216, down sampling module 222, second CNN 224, Fourier transform module 312, reference encoder 314, attention module 316, fusion module 412, condition module 414 and / or bottleneck module 416, audio data acquisition module 912, and speech enhancement module 914). In at least one embodiment, one or more APIs 1010 are sets of software instructions that, when executed, cause one or more processors to perform one or more computational operations.In at least one embodiment, one or more APIs 1010 are distributed or otherwise provided as part of one or more libraries 1006, drivers and / or runtimes 1004, and / or another grouping of software and / or executable code further described herein. In at least one embodiment, one or more APIs 1010 perform one or more computing operations in response to being called by software programs 1002. In at least one embodiment, software program 1002 is a collection of software code, instructions, instructions, or other text sequences to direct a computing device to perform one or more computational operations and / or invoke one or more other sets of instructions, such as APIs 1010 or API functions, for execution.In at least one embodiment, APIs 1010 are hardware interfaces to one or more circuits to perform one or more computing operations. In at least one embodiment, one or more software APIs 1010 described herein are implemented as one or more circuits to perform one or more functions described herein in connection with FIGS. 1-9.In at least one embodiment, one or more functions include, for example, generating high quality voice signals from low quality audio data using one or more neural networks described in connection with at least FIGS. 1-9. In at least one embodiment, one or more functions include performing STFT to extract spectral features from low quality audio data. In at least one embodiment, one or more functions include extracting waveform features from low quality audio data that match spectral features. In at least one embodiment, one or more functions includes generating context vectors indicating one or more indications of high-quality speech signal tones from reference audio data. In at least one embodiment, one or more functions include merging spectral features and waveform features such that merged features may be filtered using context features to produce enhanced latent values. In at least one embodiment, one or more functions include upsampling extended latent values to generate extended audio data with high-quality speech signals.In at least one embodiment, an interface is comprised of software application devices that, when executed, provide access to one or more functions (as mentioned above) provided by one or more APIs 1010. In at least one embodiment, a software program 1002 uses a local interface when a software developer compiles one or more software programs 1002 in conjunction with one or more libraries 1006 that include or otherwise provide access to one or more APIs 1010. In at least one embodiment, one or more software programs 1002 are statically compiled in conjunction with precompilation libraries 1006 or noncompilation source code including instructions for executing one or more APIs 1010. In at least one embodiment, one or more software programs 1002 are dynamically compiled, and one or more software programs use a linker to connect to one or more precompilation libraries 1006 that include one or more APIs 1010.In at least one embodiment, a software program 1002 uses a remote interface when a software developer executes a software program that uses or otherwise communicates with a library 1006 comprising one or more APIs 1010 over a network or other remote communication medium. In at least one embodiment, one or more libraries 1006 comprising one or more APIs 1010 are executed by a remote computing service, such as a provider of computing resource services. In another embodiment, one or more libraries 1006 comprising one or more APIs 1010 are executed by another computer host that provides the one or more APIs 1010 to one or more software programs 1002.In at least one embodiment, an API 1010 is an API to facilitate parallel computing. In at least one embodiment, an API 1010 is any other API further described herein. In at least one embodiment, an API 1010 is provided by a driver and / or runtime 1004. In at least one embodiment, an API 1010 is provided by a CUDA user mode driver. In at least one embodiment, an API 1010 is provided by a CUDA runtime. In at least one embodiment, a driver and / or runtime 1004 is data values and software instructions that, when executed, perform or otherwise facilitate operation of one or more functions (see above) of an API 1010 during loading and execution of one or more portions of a software program 1002. In at least one embodiment, drivers and / or runtimes 1004 are data values and software instructions that, when executed, perform or otherwise facilitate operation of one or more functions (as described above) of an API 1010 during execution of a software program 1002. To improve the usability of software programs 1002 and / or to optimize one or more portions of software programs 1002 to be accelerated by one or more PPUs, such as GPUs.In at least one embodiment, examples described in FIGS. 1-45, alone or in combination, provide one or more technical improvements by resolving one or more technical problems encountered in performing audio enhancement using one or more neural networks. In at least one embodiment, one or more technical improvements include solving inaccuracies caused by missing information (e.g., phase information) of audio data. In at least one embodiment, one or more technical improvements include reducing complexity of neural networks performing audio improvement, resulting in inefficient training of neural networks. In at least one embodiment, one or more technical improvements include solving generalizability and model convergence and high quality audio data lack issues available for training one or more neural networks.LOGICFIG. 11A illustrates logic 1115 which, as described elsewhere herein, may be used in one or more devices to perform operations such as those discussed herein, in accordance with at least one embodiment. In at least one embodiment, logic 1115 is used to perform inferencing and / or training operations associated with one or more embodiments. In at least one embodiment, logic 1115 is inference and / or training logic. Details of logic 1115 are described below in connection with FIGS. 11A and / or 11B. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic to provide functions or operations described herein, where logic may be embodied, collectively or individually, as a circuit that forms part of a larger system, such as an integrated circuit (IC), a system-on-a-chip (SoC), or one or more processors (e.g., CPU, GPU).In at least one embodiment, logic 1115 may include, without limitation, code and / or data storage 1101 to store forward and / or output weight and / or input / output data, and / or other parameters to configure neurons or layers of a neural network trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, logic 1115 may include or be coupled to graph code and / or data store 1101 to store graph code or other software that controls timing and / or order in which information about weights and / or other parameters is loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, code, such as graph code, based on a neural network architecture to which that code corresponds loads weights or other parameter information into processor ALUs. In at least one embodiment, code and / or data store 1101 stores weight parameters and / or input / output data of each layer of a neural network trained during forward propagation of input / output data and / or weight parameters during training and / or inferencing using aspects of one or more embodiments or used in conjunction with one or more embodiments. In at least one embodiment, each portion of code and / or data store 1101 may comprise other on-chip or off-chip data stores, including L1, L2, or L3 cache or system memory of a processor.In at least one embodiment, each portion of code and / or data store 1101 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or code and / or data store 1101 may be cache memory, dynamic random access memory ("DRAM"), static random access memory ("SRAM"), non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, selection of whether code and / or code and / or data store 1101 is internal or external to a processor, for example, or comprises DRAM, SRAM, flash, or other type of memory, may depend on available on-chip memory versus off-chip memory, latency requirements of training and / or inferencing functions performed, batch size of data used in inferencing and / or training a neural network, or a combination of these factors.In at least one embodiment, logic 1115 may include, without limitation, code and / or data storage 1105 to store reverse and / or output weight and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, code and / or data store 1105 stores weight parameters and / or input / output data of each layer of a neural network trained during backward propagation of input / output data and / or weight parameters during training and / or inferencing using aspects of one or more embodiments or used in conjunction with one or more embodiments. In at least one embodiment, logic 1115 may include or be coupled to code and / or data store 1105 to store graph code or other software to control timing and / or order in which information about weights and / or other parameters are loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)).In at least one embodiment, code, such as graph code, causes loading information about weights or other parameters into processor ALUs based on a neural network architecture to which such code corresponds. In at least one embodiment, each portion of code and / or memory 1105 may comprise other on-chip or off-chip memories, including L1, L2, or L3 cache or system memory of a processor. In at least one embodiment, any portion of code and / or data store 1105 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data store 1105 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, selection of whether code and / or data store 1105 is internal or external to a processor, for example, or comprises DRAM, SRAM, flash memory, or other type of memory, may depend on available on-chip memory versus off-chip memory, latency requirements of training and / or inferencing functions being performed, batch size of data used in inferencing and / or training a neural network, or a combination of these factors.In at least one embodiment, code and / or data store 1101 and code and / or data store 1105 may be separate storage structures. In at least one embodiment, code and / or data store 1101 and code and / or data store 1105 may be a combined memory structure. In at least one embodiment, code and / or data store 1101 and code and / or data store 1105 may be partially combined and partially separated. In at least one embodiment, each portion of code and / or data store 1101 and code and / or data store 1105 may comprise other on-chip or off-chip data stores, including processor L1, L2, or L3 cache or system memory.In at least one embodiment, logic 1115 may include, without limitation, one or more arithmetic logic unit(s) ("ALU(s)") 1110, including integer and / or floating point units, to perform logical and / or mathematical operations based at least in part on or indicated by training and / or inference code (e.g., graph code), a result of which may generate activations (e.g., output data from layers or neurons within a neural network) stored in an activation memory 1120, which are functions of input / output data and / or output data stored in code and / or data memory 1101 and / or code and / or data memory 1105. In at least one embodiment, activations stored in activation memory 1120 are generated according to linear algebraic and / or matrix-based math executed by ALU(s) 1110 in response to execution instructions or other code, wherein weight values stored in code and / or data memory 1105 and / or data memory 1101 are used as operands along with other values such as bias values, gradient information, pulse values or other parameters or hyperparameters, any or all of which may be stored in code and / or data memory 1105 or code and / or data memory 1101 or other memory on or off-chip.In at least one embodiment, ALU(s) 1110 are included in one or more processors or other hardware logic devices or circuitry, while in another embodiment, ALU(s) 1110 may be external to a processor or other hardware logic device or circuitry that uses it (e.g., a co-processor). In at least one embodiment, ALUs 1110 may be included in execution units of a processor or otherwise included in an ALU bank that execution units of a processor may access either within same processor or distributedly to different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data store 1101, code and / or data store 1105, and enable store 1120 may share a processor or other hardware logic device or circuit, while in another embodiment they may reside in different processors or other hardware logic devices or circuits, or in a combination of same and different processors or other hardware logic devices or circuits. In at least one embodiment, each portion of activation memory 1120 may include other on-chip or off-chip data memories, including L1, L2, or L3 cache or system memory of a processor. Moreover, the inferencing and / or training code may be stored along with other code that is accessible by a processor or other hardware logic or circuitry and that is retrieved and / or processed using a processor's fetch, decode, scheduler, execute, commit, and / or other logic circuitry.In at least one embodiment, activation memory 1120 may be a cache memory, a DRAM, an SRAM, a non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, activation memory 1120 may be located wholly or partially within or outside one or more processors or other logic circuitry. In at least one embodiment, selection of whether activation memory 1120 is internal or external to a processor, for example, or comprises DRAM, SRAM, flash memory, or other type of memory, may depend on available on-chip memory as compared to off-chip memory, latency requirements of training and / or inferencing functions performed, batch size of data used in inferencing and / or training a neural network, or a combination of these factors.In at least one embodiment, logic 1115 shown in FIG. 11A may be used in conjunction with an application specific integrated circuit ("ASIC"), such as a TensorFlow® processing unit from Google, an inference processing unit (IPU) from Graphcore™ or a Nervana® (e.g., "lake crest") processor from Intel Corp. In at least one embodiment, logic 1115 shown in FIG. 11A may be used in conjunction with hardware of central processing unit ("CPU"), graphics processing unit ("GPU"), or other hardware such as field programmable gate arrays ("FPGAs").FIG. 11B illustrates logic 1115 in accordance with at least one embodiment. In at least one embodiment, logic 1115 is inference and / or training logic. In at least one embodiment, logic 1115 may include, without limitation, hardware logic in which computing resources are dedicated or otherwise used exclusively in conjunction with weight values or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, logic 1115 shown in FIG. 11B may be used in conjunction with an application specific integrated circuit (ASIC), such as Google's TensorFlow® processing unit, an inference processing unit (IPU) from Graphcore™ or an Nervana® processor (e.g., Lake Crest) from Intel Corp. In at least one embodiment, logic 1115 shown in FIG. 11B may be used in conjunction with hardware of central processing unit (CPU), graphics processing unit (GPU), or other hardware, such as field programmable gate arrays (FPGAs). In at least one embodiment, logic 1115 includes, without limitation, code and / or data store 1101 and code and / or data store 1105, which may be used to store code (e.g., graph code), weight values, and / or other information including bias values, gradient information, pulse values, and / or other parameter or hyperparameter information. In at least one embodiment shown in FIG. 11B, each code and / or data store 1101 and each code and / or data store 1105 are connected to a dedicated computing resource, such as computer hardware 1102 and, respectively.Computer Hardware 1106. In at least one embodiment, each of computer hardware 1102 and computer hardware 1106 includes one or more ALUs that perform mathematical functions, such as linear algebraic functions, only on information stored in code and / or data store 1101 and code and / or data store 1105, respectively, as a result of which is stored in activation memory 1120.In at least one embodiment, each of code and / or data stores 1101 and 1105 and corresponding computer hardware 1102 and 1106, respectively, correspond to different layers of a neural network, such that resulting activation from one memory / computer pair 1101 / 1102 of code and / or data store 1101 and computer hardware 1102 is provided as input to a next memory / computer pair 1105 / 1106 of code and / or data store 1105 and computer hardware 1106 to reflect a conceptual organization of a neural network. In at least one embodiment, each of memory / compute pairs 1101 / 1102and 1105 / 1106may correspond to more than one layer of neural network. In at least one embodiment, additional memory / compute pairs (not shown) following or parallel to memory / compute pairs 1101 / 1102 and 1105 / 1106 may be included in logic 1115.TRAINING AND DEPLOYMENT OF NEURAL NETWORKFIG. 12 illustrates training and deployment of a deep neural network, according to at least one embodiment. In at least one embodiment, an trained neural network 1206 is trained using a training dataset 1202. In at least one embodiment, training framework 1204 is a PyTor framework, while in other embodiments, training framework 1204 is a TensorFlow, Boost, Coffee, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training framework. In at least one embodiment, training framework 1204 trains an untrained neural network 1206 and enables training thereof using processing resources described herein to generate a trained neural network 1208. In at least one embodiment, weights may be selected randomly or by pre-training using a deep belief network. In at least one embodiment, training may be performed in either monitored, partially monitored, or unsupervised fashion.In at least one embodiment, non-trained neural network 1206 is trained using supervised learning, wherein training dataset 1202 includes an input paired with a desired output for an input, or wherein training dataset 1202 includes an input having a known output and an output of neural network 1206 is manually ranked. In at least one embodiment, trained neural network 1206 is trained and processes inputs from training data set 1202 in a supervised manner and compares resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then tracked back by non-trained neural network 1206. In at least one embodiment, training framework 1204 adjusts weights that control non-trained neural network 1206. In at least one embodiment, training framework 1204 includes tools for monitoring convergence of non-trained neural network 1206 towards a model, e.g., trained neural network 1208, which may generate correct responses, e.g., as a result 1214, based on input data, e.g., a new dataset 1212. In at least one embodiment, training framework 1204 repeatedly trains untrained neural network 1206 while adjusting weights to refine an output of untrained neural network 1206 using a loss function and an adjustment algorithm such as stochastic gradient decay. In at least one embodiment, training framework 1204 trains untrained neural network 1206 until untrained neural network 1206 reaches desired accuracy. In at least one embodiment, trained neural network 1208 may then be deployed to implement any number of machine learning operations.In at least one embodiment, untrained neural network 1206 is trained using unsupervised learning, where untrained neural network 1206 attempts to train itself with unlabeled data. In at least one embodiment, unsupervised learning training dataset 1202 includes input data without associated output data or "Grundwahrheitsdaten". In at least one embodiment, non-trained neural network 1206 may learn groupings within training dataset 1202 and determine how individual inputs are related to non-trained dataset 1202. In at least one embodiment, unsupervised training may be used to generate a self-organizing map in a trained neural network 1208, which may perform operations useful in reducing dimensionality of new dataset 1212. In at least one embodiment, unsupervised training may also be used to perform anomaly detection that enables identification of data points in new dataset 1212 that deviate from normal patterns of new dataset 1212.In at least one embodiment, semi-supervised learning may be used, i.e., a technique in which training dataset 1202 includes a mixture of labeled and unlabeled data. In at least one embodiment, training framework 1204 may be used to perform incremental learning, for example, through transmitted learning techniques. In at least one embodiment, incremental learning allows trained neural network 1208 to adapt to a new dataset 1212 without forgeting knowledge that was input to trained neural network 1208 during initial training.In at least one embodiment, training framework 1204 is a framework that is processed in conjunction with a software development toolkit such as OpenV (Open Visual Inference and Neural Network Optimization). In at least one embodiment, an OpenVINO toolkit is a toolkit as developed by Intel Corporation of Santa Clara, CA. In at least one embodiment, OpenVINO includes logic 1115 or uses logic 1115 to perform operations described herein. In at least one embodiment, an SoC, integrated circuit, or processor uses OpenVINO to perform operations described herein.In at least one embodiment, OpenVINO is a toolkit to facilitate development of applications, particularly neural network applications, for various tasks and operations such as human vision emulation, speech recognition, natural language processing, recommendation systems, and / or variations thereof. In at least one embodiment, OpenVINO supports neural networks such as convolutional neural networks (CNNs), recurrent and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries such as OpenCV, OpenCL, and / or variants thereof.In at least one embodiment, OpenINO supports neural network models for various tasks and operations, such as classification, segmentation, object recognition, face recognition, speech recognition, pose estimation (e.g., of people and / or objects), monocular depth estimation, image embedding, style transfer, action recognition, colorization, and / or variations thereof.In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also called model optimizers. In at least one embodiment, a model optimizer is a command line tool that facilitates transitions between training and deployment of neural network models. In at least one embodiment, a model optimizer optimizes neural network models for execution on various devices and / or processing units, such as GPU, CPU, PPU, GPGPU, and / or variations thereof. In at least one embodiment, a model optimizer generates an internal representation of a model and optimizes model to generate an intermediate representation. In at least one embodiment, a model optimizer reduces a number of layers of a model. In at least one embodiment, a model optimizer removes layers of a model that are used for training. In at least one embodiment, a model optimizer performs various operations of a neural network, such as changing inputs to a model (e.g., changing magnitude of inputs to a model), changing magnitude of inputs to a model (e.g., changing stack size of a model), changing a model structure (e.g., modifying layers of a model), normalization, standardization, quantization (e.g., converting weights of a model from a first representation, e.g., floating point, to a second representation, e.g., integer), and / or variations thereof.In at least one embodiment, OpenVINO includes one or more software libraries for inferencing, also referred to as an inference engine. In at least one embodiment, an inference engine is a C++ library or other suitable library in a programming language. In at least one embodiment, an inference engine is used to derive input data. In at least one embodiment, an inference engine implements various classes to derive input data and generate one or more results. In at least one embodiment, an inference engine implements one or more API functions to process an intermediate representation, set input and / or output formats, and / or execute a model on one or more devices.In at least one embodiment, OpenVINO provides various capabilities for heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or computing refers to one or more computing processes and / or systems that use one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions for executing a program on one or more devices. In at least one embodiment, OpenVINO provides various software functions for executing a program and / or portions of a program on different devices. In at least one embodiment, OpenVINO provides various software functions to execute, for example, a first portion of code on a CPU and a second portion of code on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (e.g., a first group of layers on a first device, such as a GPU, and a second group of layers on a second device, such as a CPU).In at least one embodiment, OpenVINO includes various functionalities similar to functionalities associated with a CUDA programming model, such as various operations for neural network models associated with frameworks such as TensorFlow, PyTor, and / or variants thereof. In at least one embodiment, one or more CUDA programming model operations are performed with OpenVINO. In at least one embodiment, various systems, methods, and / or techniques described herein are implemented using OpenVINO.DATACENTERFIG. 13 illustrates an example data center 1300 in which at least one embodiment may be used. In at least one embodiment, data center 1300 includes a data center infrastructure layer 1310, a framework layer 1320, a software layer 1330, and an application layer 1340.In at least one embodiment, as shown in FIG. 13, data center infrastructure layer 1310 may include resource orchestrator 1312, grouped compute resources 1314, and node compute resources ("node C.R.s") 1316( 1)- 1316(N), where "N" represents a positive integer (which may be a different integer "N" than used in other figures). In at least one embodiment, node C.R.s 1316( 1)- 1316(N) may include any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), storage devices 1318( 1)- 1318(N) (e.g., dynamic read only memory, solid state memory, or hard disk drives), network input / output devices ("NW I / O"), network switches, virtual machines ("VMs"), Power modules and cooling modules, etc. In at least one embodiment, one or more nodes C.R.s among nodes C.R.s 1316( 1)- 1316(N) may be a server having one or more of the computing resources mentioned above.In at least one embodiment, grouped computing resources 1314 may include separate groupings of node C.R.s residing in one or more racks (not shown) or many racks residing in data centers at different geographic locations (also not shown). In at least one embodiment, separate groupings of node C.R.s within grouped computing resources 1314 may include grouped computing, network, storage, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, multiple node C.R.s comprising CPUs or processors may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.In at least one embodiment, resource orchestrator 1312 may configure or otherwise control one or more nodes C.R.s 1316( 1)- 1316(N) and / or grouped computing resources 1314. In at least one embodiment, resource orchestrator 1312 may include a software design infrastructure ("SDI") management unit for data center 1300. In at least one embodiment, resource orchestrator 1112 may comprise hardware, software, or a combination thereof.In at least one embodiment, as shown in FIG. 13, framework layer 1320 includes a job scheduler 1322, a configuration manager 1324, a resource manager 1326, and a distributed file system 1328. In at least one embodiment, framework layer 1320 may include a framework to support software 1332 of software layer 1330 and / or one or more application(s) 1342 of application layer 1340. In at least one embodiment, software 1332 or application(s) 1342 may comprise web-based service software or applications such as provided by Amazone Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 1320 may be any type of free and open source software web application framework, such as, but not limited to, Apache Spark™ (hereinafter "Spark"), which may utilize a distributed file system 1328 to process large amounts of data (e.g., "Big Data"). In at least one embodiment, job scheduler 1322 may include a spark driver to facilitate scheduling workloads supported by different layers of data center 1300. In at least one embodiment, configuration manager 1324 may be capable of configuring different layers, such as software layer 1330 and framework layer 1320, including spark and distributed file system 1328 to support large volume processing. In at least one embodiment, resource manager 1326 may be capable of managing clustered or grouped computing resources associated with support of distributed file system 1328 and job scheduler 1322. In at least one embodiment, clustered or grouped computing resources may include grouped computing resources 1314 in data center infrastructure layer 1310. In at least one embodiment, resource manager 1326 may be coordinated with resource orchestrator 1312 to manage these allocated or allocated computing resources.In at least one embodiment, software 1332 included in software layer 1330 may include software used by at least portions of nodes C.R.s 1316( 1)- 1316(N), grouped computer systems 1314, and / or distributed file systems 1328 of framework layer 1320. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web page search software, email virus scan software, database software, and streaming video content software.In at least one embodiment, application(s) 1342 included in application layer 1340 may comprise one or more types of applications used by at least portions of nodes C.R.s 1316( 1)- 1316(N), grouped computing resources 1314, and / or distributed file systems 1328 of framework layer 1320. In at least one embodiment, one or more types of applications may include any number of a genomic application, a cognitive computing application, and a machine learning application, including, but not limited to, training or inferencing software, machine learning framework software (e.g., PyTor, TensorFlow, Coffee, etc.), or other machine learning applications used in connection with one or more embodiments.In at least one embodiment, configuration manager 1324, resource manager 1326, and resource orchestrator 1312 may implement any number and type of self-modifying actions based on any amount and type of data captured in any technically feasible manner. In at least one embodiment, self-modifying actions may offload an operator of a data center 1300 from making potentially bad configuration decisions and may avoid unutilized and / or malfunctioning portions of a data center.In at least one embodiment, data center 1300 may include tools, services, software, or other resources to train one or more machine learning models or predict or derive information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by computing weight parameters according to a neural network architecture using software and computing resources described above with respect to data center 1300. In at least one embodiment, trained machine learning models corresponding to one or more neural networks may be used to derive or predict information using resources described above with respect to data center 1300 by using weighting parameters calculated by one or more training techniques described herein.In at least one embodiment, data center may use CPUs, application specific integrated circuits (ASICs), GPUs, FPGAs, or other hardware to perform training and / or inferencing using resources described above. Moreover, one or more of the software and / or hardware resources described above may be configured as a service to enable users to train or infer information, such as image recognition, speech recognition, or other artificial intelligence services.Logic 1115 is used to perform inferencing and / or training operations in connection with one or more embodiments. Details of logic 1115 are described herein in connection with FIGS. 11A and / or 11B. In at least one embodiment, logic 1115 in data center 1300 may be used for inferencing or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.In at least one embodiment, FIGS. 1-45 are to generate, using one or more neural networks, one or more enhanced speech signals from inferior audio data based at least in part on spectral and waveform features of inferior audio data and one or more features derived from reference audio data comprising one or more superior speech signals.AUTONOMOUS VEHICLEFIG. 14A shows an example of an autonomous vehicle 1400, according to at least one embodiment. In at least one embodiment, autonomous vehicle 1400 (alternatively referred to herein as "vehicle 1400") may be, without limitation, a passenger car, such as a passenger car, truck, bus, and / or other type of vehicle that receives one or more passengers. In at least one embodiment, vehicle 1400 may be a semi-trailer used for transporting goods. In at least one embodiment, vehicle 1400 may be an aircraft, robotic vehicle, or other type of vehicle.Autonomous vehicles may be described in terms of automation levels available from the National Highway Traffic Safety Administration ("NHTSA"), a division of the U.S. Ministry of Traffic, and the Society of Automotive Engineers ("SAE") "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (e.g., Standard No. J3016-201806 published June 15, 2018, Standard No. J3016-20169 published September 30, 2016, as well as earlier and future versions of this standard). In at least one embodiment, vehicle 1400 may be capable of performing functions according to one or more of autonomous driving level 1 through level 5. For example, in at least one embodiment, vehicle 1400 may be capable of conditional automated (level 3), highly automated (level 4), and / or fully automated (level 5), depending on the embodiment.In at least one embodiment, vehicle 1400 may include, without limitation, components such as a chassis, a vehicle body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of a vehicle. In at least one embodiment, vehicle 1400 may include, without limitation, a propulsion system 1450, such as an internal combustion engine, a hybrid electric power plant, a full electric engine, and / or another type of propulsion system. In at least one embodiment, propulsion system 1450 may be connected to a powertrain of vehicle 1400, which may include, without limitation, a transmission to enable propulsion of vehicle 1400. In at least one embodiment, propulsion system 1450 may be controlled in response to receiving signals from an accelerator pedal / accelerator(s) 1452.In at least one embodiment, a steering system 1454 that may include, without limitation, a steering wheel is used to steer vehicle 1400 (e.g., along a desired path or route) when propulsion system 1450 is operating (e.g., when vehicle 1400 is in motion).In at least one embodiment, steering system 1454 may receive signals from one or more steering actuators 1456. In at least one embodiment, a steering wheel may optionally be for full automation (level 5) function. In at least one embodiment, a brake sensor system 1446 may be used to actuate vehicle brakes in response to receiving signals from brake actuator(s) 1448 and / or brake sensors.In at least one embodiment, controller(s) 1436 which may include, without limitation, one or more system-on-chips ("SoCs") (not shown in FIG. 14A ) and / or graphics processing unit(s) ("GPU(s)") provide signals (e.g., representative of commands) to one or more components and / or systems of vehicle 1400. For example, in at least one embodiment, controller(s) 1436 may send signals to actuate vehicle brakes via brake actuator(s) 1448; actuate steering system 1454 via steering actuator(s) 1456, and actuate propulsion system 1450 via accelerator(s) 1452. In at least one embodiment, controller(s) 1436 may include one or more onboard (e.g., integrated) computing devices that process sensor signals and issue operating commands (e.g., signals representing commands) to enable autonomous driving and / or to assist a human driver in driving vehicle 1400. In at least one embodiment, controller(s) 1436 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence (e.g., computer vision) functions, a fourth controller for infotainment functions, a fifth controller for emergency redundancy, and / or other controllers. In at least one embodiment, a single controller may perform two or more of the above-mentioned functions, two or more controllers may perform a single function, and / or any combination thereof.In at least one embodiment, controller(s) 1436 provides (provide) signals to control one or more components and / or systems of vehicle 1400 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data may be transmitted, for example and without limitation, to one or more GNSS sensor(s) 1458 (e.g., global positioning system sensor(s)), RADAR sensor(s) 1460, ultrasonic sensor(s) 1462, LIDAR sensor(s) 1464, inertial measurement unit ("IMU") sensor(s) 1466 (e.g., accelerometer, gyroscope(s), magnetic compass or compass, magnetometer, etc.), microphone(s) 1496, stereo camera(s) 1468, wide-angle camera(s) 1470 (e.g., fish-eye cameras), infrared camera(s) 1472, environmental camera(s) 1474 (e.g., 360-degree cameras), Long-range cameras (not shown in FIG. 14A ), mid-range camera(s) (not shown in FIG. 14A ), speed sensor(s) 1444 (e.g., for measuring the speed of the vehicle 1400), vibration sensor(s) 1442, steering sensor(s) 1440, brake sensor(s) (e.g., as part of the brake sensor system 1446), and / or other types of sensors.In at least one embodiment, one or more of controllers 1436 may receive input (e.g., in the form of input data) from an instrument cluster 1432 of vehicle 1400 and provide output (e.g., in the form of output data, display data, etc.) via a human-machine interface ("HMI") display 1434, an acoustic detector, a speaker, and / or via other components of vehicle 1400. In at least one embodiment, output data may include information such as vehicle speed, speed, time, map information (e.g., a high resolution map (not shown in FIG. 14A )), location data (e.g., location of vehicle 1400, e.g., on a map), direction, location of other vehicles (e.g., a grid), information about objects, and status of objects as perceived by controller(s) 1436, etc. For example, in at least one embodiment, HMI display 1434 may include information about presence of one or more objects (e.g., a road sign, a warning sign, a changing traffic light, etc.) and / or information about driving maneuvers that vehicle has performed, is being performed or will be performed (e.g., lane change now, two-miles exit 34B, etc.).In at least one embodiment, vehicle 1400 further includes a network interface 1424 that may use wireless antenna(s) 1426 and / or modem(s) for communication over one or more networks. For example, in at least one embodiment, network interface 1424 may be capable of communicating via long term evolution ("LTE"), wideband code division multiple access ("WCDMA"), universal mobile telecommunications system ("UMTS"), global system for mobile communication ("GSM"), IMT-CDMA multi-carrier ("CDMA2000") networks, etc. In at least one embodiment, wireless antenna(s) 1426 may also enable communication between objects in environment (e.g., vehicles, mobile devices, etc.), using local area networks such as Bluetooth, Bluetooth Low Energy ("LE"), Z-Wave, ZigBee, etc., and / or low power wide area networks ("LPWANs") such as LoRaWAN, SigOx, etc.Logic 1115 is used to perform inferencing and / or training operations in connection with one or more embodiments. Details of logic 1115 are described herein in connection with FIGS. 11A and / or 11B. In at least one embodiment, logic 1115 in vehicle 1400 may be used for inferencing or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.In at least one embodiment, FIGS. 1-14A are intended to generate one or more enhanced speech signals from low quality audio data using one or more neural networks based at least in part on spectral and waveform features of low quality audio data and one or more features derived from reference audio data comprising one or more high quality speech signals.FIG. 14B shows an example of camera positions and fields of view for the autonomous vehicle 1400 of FIG. 14A, according to at least one embodiment. In at least one embodiment, cameras and respective fields of view represent an example embodiment and are not to be considered limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or cameras may be disposed at different locations of vehicle 1400.In at least one embodiment, camera types for cameras may include, but are not limited to, digital cameras that may be adapted for use with components and / or systems of vehicle 1400. In at least one embodiment, camera(s) may operate at Automotive Safety Integrity Level ("ASIL") B and / or on another ASIL. In at least one embodiment, camera types may achieve any image capture rate, for example, 60 images per second (fps), 1220 fps, 240 fps, etc., depending on embodiment. In at least one embodiment, cameras may use rolling shutters, global shutters, another type of shutter, or a combination thereof. In at least one embodiment, color filter array may include a red-clear-clear color filter array ("RCCC"), a red-clear-blue color filter array ("RCCB"), a red-blue-green-clear color filter array ("RBGC"), a Foveon X3 color filter array, a Bayer sensor color filter array ("RGGB"), a monochrome sensor color filter array, and / or another type of color filter array. In at least one embodiment, clear pixel cameras, such as cameras with an RCCC, an RCCB, and / or an RBGC color filter array, may be used to increase photosensitivity.In at least one embodiment, one or more cameras may be used to execute advanced driver assistance systems ("ADAS") (e.g., as part of a redundant or fail-safe design). Thus, in at least one embodiment, a multi-function monocamera may be installed that includes functions such as lane keeping assist, road sign assist, and smart headlight control. In at least one embodiment, one or more of cameras (e.g., all cameras) may simultaneously record and provide image data (e.g., video).In at least one embodiment, one or more cameras may be mounted in a mounting arrangement, such as a custom-designed (three-dimensional ("3D") printed) arrangement, to eliminate stray light and reflections within vehicle 1400 (e.g., reflections from dashboard reflected in windshield mirrors), which may interfere with camera image capture capability. With respect to the mounting of exterior mirrors, in at least one embodiment, the exterior mirrors may be custom 3D printed such that a camera mounting plate is in the form of an exterior mirror. At least in one embodiment, camera(s) may be integrated into the exterior mirrors. In at least one embodiment, in side cameras, camera(s) may also be integrated into four columns at each corner of the cabin.In at least one embodiment, cameras having a field of view that includes portions of an environment in front of vehicle 1400 (e.g., forward facing cameras) may be used for environment viewing to aid in identifying forward facing paths and obstacles, and to provide information, via one or more controllers 1436 and / or control SoCs, that is critical to generating a grid for occupying and / or determining preferred vehicle paths. In at least one embodiment, forward facing cameras may be used to perform many similar ADAS functions as LIDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, forward-facing cameras may also be used for ADAS functions and systems including, without limitation, lane departure warnings ("LDW"), autonomous cruise control ("ACC"), and / or other functions such as road sign recognition.In at least one embodiment, a plurality of cameras may be used in a forward-facing configuration, including, for example, a monocular camera platform that includes a complementary metal oxide semiconductor (CMOS) color imager. In at least one embodiment, a wide-angle camera 1470 may be used to detect objects that are in field of view from periphery (e.g., pedestrians, crossing traffic, or bicycles). Although only one wide-angle camera 1470 is shown in FIG. 14B, in other embodiments, the vehicle 1400 may include any number (including zero) of wide-angle cameras. In at least one embodiment, any number of long-range camera(s) 1498 (e.g., a long-range stereo camera pair) may be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, long-range camera(s) 1498 may also be used for object detection and classification as well as for basic object tracking.In at least one embodiment, any number of stereo camera(s) 1468 may also include in a forward-facing configuration. In at least one embodiment, one or more of stereo camera(s) 1468 may include an integrated control unit that includes a scalable processing unit that may provide programmable logic ("FPGA") and a multi-core microprocessor with an integrated network interface ("CAN") or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of vehicle 1400 environment that includes a distance estimate for all points in an image. In at least one embodiment, one or more of stereo camera(s) 1468 may include, without limitation, compact stereo vision sensor(s) that may include, without limitation, two camera lenses (one left and right each) and an image processing chip that may measure distance between vehicle 1400 and target object and use generated information (e.g., metadata) to enable autonomous emergency braking and lane keeping warning functions. In at least one embodiment, other types of stereo camera(s) 1468 may be used in addition to or alternatively to those described herein.In at least one embodiment, cameras having a field of view that includes portions of environment on sides of vehicle 1400 (e.g., side cameras) may be used for environment viewing and provide information used to create and update a grid, as well as to generate side impact collision warnings. For example, in at least one embodiment, surround camera(s) 1474 (e.g., four surround cameras as shown in FIG. 14B ) could be positioned on vehicle 1400. In at least one embodiment, surround camera(s) 1474 may include, without limitation, any number and combination of wide-angle cameras, fish-eye cameras, 360-degree cameras, and / or similar cameras. For example, in at least one embodiment, four fish eye cameras may be positioned at the front, the rear, and the sides of vehicle 1400. In at least one embodiment, vehicle 1400 may use three surround camera(s) 1474 (e.g., left, right, and rear) and utilize one or more other camera(s) (e.g., a front facing camera) as a fourth surround camera.In at least one embodiment, cameras having a field of view including portions of an environment behind vehicle 1400 (e.g., backup cameras) may be used for parking assist, environmental view, rear end collision warnings, and raster creation and update. In at least one embodiment, a plurality of cameras may be used, including at least a plurality of cameras, as described herein, also suitable as forward facing camera(s) (e.g., long-range cameras 1498 and / or mid-range camera(s) 1476, stereo camera(s) 1468, infrared camera(s) 1472, etc.).In at least one embodiment, FIGS. 1-14B are intended to generate one or more enhanced speech signals from inferior audio data using one or more neural networks based at least in part on spectral and waveform features of inferior audio data and one or more features derived from reference audio data comprising one or more superior speech signals.FIG. 14C is a block diagram illustrating an example system architecture for the autonomous vehicle 1400 of FIG. 14A, according to at least one embodiment. In at least one embodiment, each of vehicle 1400 components, features, and systems is shown connected in FIG. 14C as via a bus 1402. In at least one embodiment, bus 1402 may include, without limitation, a CAN data interface (alternatively referred to herein as a "CAN bus"). In at least one embodiment, a CAN may be a network within vehicle 1400 used to assist in controlling various features and functions of vehicle 1400, such as actuation of brakes, acceleration, brakes, steering, windshield wipers, etc. In at least one embodiment, bus 1402 may be configured to include dozens or even hundreds of nodes, each having its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 1402 may be read to determine steering wheel angle, vehicle speed, engine speed, button positions, and / or other vehicle status information. In at least one embodiment, bus 1402 may be a CAN bus that is ASIL B compliant.In at least one embodiment, FlexRay and / or Ethernet protocols may also be used in addition to or as an alternative to CAN. In at least one embodiment, there may be any number of buses forming bus 1402, which may include, without limitation, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses with different protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or may be used for redundancy. For example, a first bus may be used for the collision avoidance functionality and a second bus may be used for the actuation control. In at least one embodiment, each bus of bus 1402 may communicate with any components of vehicle 1400, and two or more buses of bus 1402 may communicate with corresponding components. In at least one embodiment, any of any number of system(s) on chip(s) ("SoC(s)") 1404 (such as SoC 1404(A) and SoC 1404(B)), each of controllers 1436 and / or each computer within vehicle may have access to same input data (e.g., inputs from vehicle 1400 sensors) and be connected to a common bus, such as CAN bus.In at least one embodiment, vehicle 1400 may include one or more controller(s) 1436 as described herein with respect to FIG. 14A. In at least one embodiment, controller(s) 1436 may be used for a plurality of functions. In at least one embodiment, controller(s) 1436 may be coupled to various other components and systems of vehicle 1400 and used for control of vehicle 1400, artificial intelligence of vehicle 1400, infotainment of vehicle 1400, and / or other functions.In at least one embodiment, vehicle 1400 may include any number of SoCs 1404. In at least one embodiment, each of SoCs 1404 may include, without limitation, central processing units ("CPU(s)") 1406, graphics processing units ("GPU(s)") 1408, processor(s) 1410, cache(s) 1412, accelerators 1414, data storage 1416, and / or other components and features not shown. In at least one embodiment, SoC(s) 1404 may be used to control vehicle 1400 in a variety of platforms and systems. For example, in at least one embodiment, SoC(s) 1404 in a system (e.g., vehicle 1400 system) may be combined with a high definition ("HD") map 1422, which may receive updates to map and / or updates from one or more servers (not shown in FIG. 14C ) via a network interface 1424.In at least one embodiment, CPU(s) 1406 may comprise a CPU cluster or complex (alternatively referred to herein as "CCPLEX"). In at least one embodiment, CPU(s) 1406 may include multiple cores and / or level two ("L2") caches. In at least one embodiment, CPU(s) 1406 may include, for example, eight cores in a coherent multiprocessor configuration. In at least one embodiment, CPU(s) 1406 may include four dual core clusters, each cluster having a dedicated L2 cache (e.g., a 2 megabyte (MB) L2 cache). In at least one embodiment, CPU(s) 1406 (e.g., CCPLEX) may be configured to support concurrent clustering operations such that any combination of clusters of CPU(s) 1406 may be active at a particular time.In at least one embodiment, one or more of CPU(s) 1406 may implement power management functions that include, without limitation, one or more of the following features: individual hardware blocks may be automatically idle clocked to conserve dynamic power; each core clock may be clocked when such a core does not actively execute instructions due to execution of wait for interrupt ("WFl") / wait for event ("WFE") instructions; each core may be independently power controlled; each core cluster may be independently clock controlled when all cores are clock controlled or power controlled; and / or each core cluster may be independently power controlled when all cores are power controlled. In at least one embodiment, CPU(s) 1406 may further implement an enhanced power state management algorithm in which allowed power states and expected wake-up times are specified and hardware / microcode determines which power state is best for core, cluster, and CCPLEX. In at least one embodiment, processing cores may support simplified sequences for input of power states in software, offloading work to microcode.In at least one embodiment, GPU(s) 1408 may comprise an integrated GPU (alternatively referred to herein as "iG"). In at least one embodiment, GPU(s) 1408 may be programmable and efficient for parallel workloads. In at least one embodiment, GPU(s) 1408 may use an extended tensor instruction set. In at least one embodiment, GPU(s) 1408(s) may comprise one or more streaming microprocessors, wherein each streaming microprocessor may comprise a level 1 cache ("L1") (e.g., an L1 cache having a storage capacity of at least 96 KB), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache having a storage capacity of 512 KB). In at least one embodiment, GPU(s) 1408 may include at least eight streaming microprocessors. In at least one embodiment, GPU(s) 1408 may use application programming interface(s) (API(s)) for computations. In at least one embodiment, GPU(s) 1408 may use one or more parallel computer platforms and / or programming models (e.g., NVIDIA's CUDA model).In at least one embodiment, one or more of GPU(s) 1408 may be optimized for best performance in automotive and embedding use cases. In at least one embodiment, GPU(s) 1408 may be fabricated on fin field effect transistor ("FinFET") circuits, for example. In at least one embodiment, each streaming microprocessor may include a number of mixed precision processing cores divided into multiple blocks. For example, 64 PF32 cores and 32 FP64 cores could be divided into four processing blocks. In at least one embodiment, each processing block could be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed precision NVIDIA tensor cores for deep learning matrix arithmetic, a level zero instruction cache ("L0"), a scheduler (e.g., warp scheduler), or sequencer, a dispatch unit, and / or a 64 KB register file. In at least one embodiment, streaming microprocessors may include independent parallel integer and floating point data paths to enable efficient execution of workloads with a mixture of computations and addressing computations. In at least one embodiment, streaming microprocessors may include independent thread scheduling capability to enable finer grain synchronization and cooperation between parallel threads. In at least one embodiment, streaming microprocessors may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.In at least one embodiment, one or more of GPU(s) 1408 may include high bandwidth memory ("HBM") and / or a 16 GB HBM2 memory subsystem to provide a peak memory bandwidth of about 900 GB / second, in some examples. In at least one embodiment, in addition to or as an alternative to HBM memory, synchronous graphics random access memory ("SGRAM") may be used, such as dual data rate synchronous random access memory type 5 ("GDDR5").In at least one embodiment, GPU(s) 1408 may comprise unified memory technology. In at least one embodiment, address translation services ("ATS") support may be used to allow GPU(s) 1408 to directly access page tables of CPU(s) 1406. In at least one embodiment, an address translation request may be sent to CPU(s) 1406 if a GPU of GPU(s) 1408 memory management unit ("MMU") fails. In response, the CPU of the CPU(s) 1406 may search in its page tables for a virtual physical mapping for an address and transmit the translation back to the GPU(s) 1408, in at least one embodiment. In at least one embodiment, unified memory technology may enable a single unified virtual address space for memory of both CPU(s) 1406 and GPU(s) 1408, thereby facilitating programming of GPU(s) 1408 and porting applications to GPU(s) 1408.In at least one embodiment, GPU(s) 1408 may include any number of access counters that may track frequency of GPU(s) 1408 accessing memory of other processors. In at least one embodiment, access counters may help move memory pages into physical memory of a processor that most frequently accesses pages, thereby improving efficiency of memory areas shared by processors.In at least one embodiment, one or more SoC(s) 1404 may comprise any number of cache(s) 1412, including those described herein. In at least one embodiment, cache(s) 1412 could include, for example, a level 3 cache ("L3") available to both CPU(s) 1406 and GPU(s) 1408 (e.g., connected to CPU(s) 1406 and GPU(s) 1408). In at least one embodiment, cache(s) 1412 can include a write back cache that can track states of lines, for example, by using a cache coherency protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, an L3 cache may include 4 MB memory or more, depending on embodiment, although smaller cache sizes may also be used.In at least one embodiment, one or more of SoC(s) 1404 may include one or more accelerators 1414 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, SoC(s) 1404 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or a large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4 MB SRAM) may allow a hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, a hardware acceleration cluster may be used to supplement GPU(s) 1408 and offload some tasks from GPU(s) 1408 (e.g., to enable more cycles of GPU(s) 1408 to perform other tasks). In at least one embodiment, accelerator(s) 1414 could be used for targeted workloads (e.g., perception, convolutional neural networks ("CNNs"), recurrent neural networks ("RNNs"), etc.) that are stable enough to be considered for acceleration. In at least one embodiment, a CNN may include a region-based or regional convolutional neural network ("RCNNs") and fast RCNNs (e.g., for object detection) or other type of CNN.In at least one embodiment, accelerator(s) 1414 (e.g., hardware accelerator clusters) may include one or more deep learning accelerators ("DLA"). In at least one embodiment, DLA(s) may include, without limitation, one or more tensor processing units ("TPUs"), which may be configured to provide additional ten billions of operations per second for deep learning applications and inferencing. In at least one embodiment, TPUs may be accelerators configured and optimized for performing image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, DLA(s) may be further optimized for a particular set of neural network types and floating point operations, as well as inferencing. In at least one embodiment, DLA(s) design can provide more performance per millimeter than a typical general purpose GPU and typically far outfits performance of a CPU. In at least one embodiment, TPU(s) may perform multiple functions, including a single instance convolution function that supports, for example, INT8, INT16, and FP16 data types for both features and weights, as well as postprocessor functions. In at least one embodiment, DLA(s) may quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for a variety of functions including, for example and without limitation: a CNN for identifying and recognizing objects using camera sensor data; a CNN for distance estimation using camera sensor data; a CNN for detecting and identifying emergency vehicles and recognition using microphone data; a CNN for face detection and identifying vehicle owners using camera sensor data; and / or a CNN for safety-related and / or safety-related events.In at least one embodiment, DLA(s) may perform any function of GPU(s) 1408, and by using an inference accelerator, for example, a developer may provide either DLA(s) or GPU(s) 1408 to any function. For example, in at least one embodiment, a developer may focus processing CNNs and floating point operations on DLA(s) and leave other functions to GPU(s) 1408 and / or accelerator(s) 1414.In at least one embodiment, accelerator / accelerators 1414 may include a programmable image processing accelerator ("PVA"), which may also be referred to herein as a computer vision accelerator. In at least one embodiment, PVA may be designed and configured to accelerate image processing algorithms for advanced ADAS system 1438, autonomous driving, augmented reality (AR) applications, and / or virtual reality (VR) applications. In at least one embodiment, PVA may provide a balance between performance and flexibility. In at least one embodiment, each PVA may include, for example and without limitation, any number of reduced instruction set cores ("RISC"), direct memory access ("DMA"), and / or any number of vector processors.In at least one embodiment, RISC cores may interact with image sensors (e.g., image sensors of all cameras described herein), image signal processor(s), etc. In at least one embodiment, each RISC core may comprise any amount of memory. In at least one embodiment, RISC cores may use any number of protocols depending on embodiment. In at least one embodiment, RISC cores may execute a real-time operating system ("RTOS"). In at least one embodiment, RISC cores may be implemented with one or more integrated circuits, application specific integrated circuits ("ASICs"), and / or memory devices. In at least one embodiment, RISC cores could include, for example, an instruction cache and / or a close coupled RAM.In at least one embodiment, DMA may allow components of PVA to access system memory independent of CPU(s) 1406. In at least one embodiment, DMA may support any number of features used to optimize a PVA, including, but not limited to, support multi-dimensional addressing and / or circular addressing. In at least one embodiment, DMA may support up to six or more dimensions of addressing, which may include, without limitation, block width, block height, block depth, horizontal block locking, vertical block locking, and / or depth locking.In at least one embodiment, vector processors may be programmable processors that may be configured to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing functions. In at least one embodiment, a PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, a PVA core may include a processor subsystem, DMA engine(s) (e.g., two DMA engines), and / or other peripheral devices. In at least one embodiment, a vector processing subsystem may operate as a primary engine of a PVA and may include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, VPU core may include a digital signal processor, such as a single instruction, multiple data ("SIMD") and very long instruction word ("VLIW") digital signal processor. In at least one embodiment, a combination of SIMD and VLIW may increase throughput and speed.In at least one embodiment, each of vector processors may include an instruction cache and may be coupled to dedicated memory. Thus, in at least one embodiment, each vector processor may be configured to operate independently of other vector processors. In at least one embodiment, vector processors included in a particular PVA may be configured to use data parallelism. For example, in at least one embodiment, a plurality of vector processors included in a single PVA may execute a common computer vision algorithm, but on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may simultaneously execute different image processing algorithms on an image or even different algorithms on successive images or portions of an image. In at least one embodiment, any number of PVAs may be included in a hardware acceleration cluster, among other things, and each PVA may include any number of vector processors. In at least one embodiment, PVA may include additional error correction code ("ECC") memory to increase overall system security.In at least one embodiment, accelerator / accelerators 1414 may include an on-chip computer vision network and a static random access memory ("SRAM") to provide high bandwidth, low latency SRAM to accelerator / accelerators 1414. In at least one embodiment, on-chip memory may include at least 4 MB SRAM, which may include, for example and without limitation, eight field configurable memory blocks accessible by both a PVA and a DLA. In at least one embodiment, each pair of memory blocks may include an extended peripheral bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, a PVA and a DLA may access memory via a backbone that allows a PVA and a DLA to access memory at high speed. In at least one embodiment, a backbone may include an on-chip computer vision network that interconnects a PVA and a DLA with memory (e.g., using APB).In at least one embodiment, a computer vision network on chip may include an interface that determines that both a PVA and a DLA provide ready and valid signals prior to transmission of control signals / addresses / data. In at least one embodiment, an interface may provide separate phases and separate channels for transmission of control signals / addresses / data, as well as burst communication for continuous data transmission. In at least one embodiment, an interface may comply with International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("EC") 61508 standards, although other standards and protocols may also be used.In at least one embodiment, one or more of SoC(s) 1404 may include a hardware accelerator for real-time ray tracing. In at least one embodiment, real-time ray tracing hardware accelerator may be used to quickly and efficiently determine positions and extents of objects (e.g., within a world model), generate real-time visualization simulations, RADAR signal interpretation, sound propagation synthesis and / or analysis, simulate SONAR systems, general wave propagation simulation, compare to LIDAR data for purposes of localization and / or other functions, and / or for other purposes.In at least one embodiment, accelerator / accelerators 1414 may have a wide range of uses for autonomous driving. In at least one embodiment, a PVA may be used for important processing steps in ADAS and autonomous vehicles. In at least one embodiment, PVA capabilities are well suited for algorithmic areas requiring predictable processing at low power and low latency. In other words, a PVA lends itself well to semi-dense or dense regular computations, even for small data sets requiring predictable low latency, low power consumption runtimes. In at least one embodiment, such as in vehicle 1400, PVAs could be designed to execute classical computer vision algorithms because they are efficient in object detection and processing integer mathematical data.For example, according to at least one embodiment of the technology, a PVA is used to perform computer stereo vision. In at least one embodiment, in some examples, a semi-global matching based algorithm may be used, although this is not intended to be limiting. In at least one embodiment, in autonomous driving applications level 3- 5, motion estimation / stereo matching is used during driving (e.g., structure of motion, pedestrian detection, lane detection, etc.). In at least one embodiment, a PVA may perform computer stereo vision functions on inputs from two monocular cameras.In at least one embodiment, a PVA may be used to perform a dense optical flow. In at least one embodiment, a PVA could process raw RADAR data (e.g., using a 4D fast Fourier transform) to provide processed RADAR data, for example. In at least one embodiment, a PVA is used for time-of-flight depth processing by processing raw time-of-flight data to provide processed time-of-flight data, for example.In at least one embodiment, a DLA may be used to operate any type of network to improve control and driving safety, including, for example and without limitation, a neural network that outputs a measure of confidence for each object detection. In at least one embodiment, confidence may be represented or interpreted as a probability, or as a relative "weight" of each recognition as compared to other recognitions. In at least one embodiment, a confidence measure allows system to make further decisions about which detections should be considered true positive detections and which should be considered false positive detections. In at least one embodiment, a system may set a threshold for confidence measure and consider only detections exceeding threshold as true positive detections. In an embodiment where an automatic emergency braking system ("AEB") is used, false positive detections would result in the vehicle automatically performing emergency braking, which is, of course, undesirable. In at least one embodiment, very secure detections may be considered triggers for AEB. In at least one embodiment, a DLA may employ a neural network to regression confidence value. In at least one embodiment, neural network may use as input at least a subset of parameters, such as bounding box dimensions, ground plane estimate obtained (e.g., from another subsystem), output of IMU sensor / s 1466 correlated with vehicle 1400 orientation, distance, 3D position estimates of object obtained from neural network and / or other sensors (e.g., LIDAR sensor(s) 1464 or RADAR sensor(s) 1460), and others.In at least one embodiment, one or more SoC(s) 1404 may include one or more data stores 1416 (e.g., memory). In at least one embodiment, data store(s) 1416 may be an on-chip memory of SoC(s) 1404, which may store neural network(s) to be executed on GPU(s) 1408 and / or a DLA. In at least one embodiment, data store(s) 1416 may be large enough to store multiple instances of neural networks for redundancy and security. In at least one embodiment, data store(s) 1416 may comprise L2 or L3 cache(s).In at least one embodiment, one or more SoC(s) 1404 may include any number of processor(s) 1410 (e.g., embedding processors). In at least one embodiment, processor(s) 1410 may include a boot and power management processor, which may be a dedicated processor and subsystem, for handling boot power and management functions and associated security enforcement. In at least one embodiment, a boot and power management processor may be part of a boot sequence of SoC(s) 1404 and provide runtime power management services. In at least one embodiment, a boot power supply and management processor may take on clock and voltage programming, support for transitions to a low power supply state, management of thermal and temperature sensors of SoC(s) 1404, and / or management of power states of SoC(s) 1404. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and SoC(s) 1404 may use ring oscillators to sense temperatures of CPU(s) 1406, GPU(s) 1408, and / or accelerator(s) 1414. In at least one embodiment, if temperatures are determined to exceed a threshold, a boot and power management processor may enter a temperature fault routine and place SoC(s) 1404 in a lower power state and / or place vehicle 1400 in a chauffer-to-safe stop mode (e.g., place vehicle 1400 in a safe stop).In at least one embodiment, processor(s) 1410 may further include a set of embedded processors that may serve as an audio processing engine, which may be an audio subsystem that enables full hardware support for multi-channel audio over multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, an audio processing engine is a dedicated processing core with a dedicated RAM digital signal processor.In at least one embodiment, processor(s) 1410 may further include an "ways on" processor engine that may provide required hardware functions to support low power sensor management and wake-use cases. In at least one embodiment, an "ways on" processor engine may include, without limitation, a processor core, close-coupled memory, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.In at least one embodiment, processor(s) 1410 may further comprise a safety cluster engine that includes, without limitation, a dedicated processor subsystem for handling safety management for automotive applications. In at least one embodiment, a safety cluster engine may include, without limitation, two or more processor cores, close coupled memory, supporting peripheral devices (e.g., timers, interrupt control, etc.), and / or routing logic. In a safety mode, in at least one embodiment, two or more cores may operate in a lockstep mode and function as a single core with compare logic to detect any differences between their operations. In at least one embodiment, processor(s) 1410 may further include a real-time camera engine, which may include, without limitation, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, processor(s) 1410 may further include a high dynamic range signal processor, which may include, without limitation, an image signal processor that is a hardware engine that is part of a camera processing pipeline.In at least one embodiment, processor(s) 1410 may include a video image combiner, which may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions needed by a video playback application to generate a final image for a player window. In at least one embodiment, a video image combiner may make a lens distortion correction at wide-angle camera(s) 1470, surround camera(s) 1474, and / or at sensors of surveillance camera(s) in cabin. In at least one embodiment, monitoring camera(s) sensor(s) in cabin is / are preferably monitored by a neural network running on another instance of SoC 1404 and configured to identify and respond accordingly to events in cabin. In at least one embodiment, an in-vehicle system may perform lipread without limitation to activate cellular service and place a call, dictate emails, change destination of a vehicle, activate or change infotainment system and settings of a vehicle, or enable voice-controlled browsing on Internet. In at least one embodiment, certain features are available to driver when vehicle is operating in an autonomous mode and are otherwise disabled.In at least one embodiment, a video image compositor may include improved temporal noise suppression for both spatial and temporal noise suppression. For example, in at least one embodiment in which motion occurs in a video, noise suppression appropriately weights spatial information and reduces the weight of information provided by adjacent frames. In at least one embodiment where an image or portion of an image does not include motion, temporal noise reduction performed by the video image compositor may use information from a previous image to reduce noise in the current image.In at least one embodiment, a video image combiner may also be configured to perform stereo rectification on input stereo image frames. In at least one embodiment, a video image compositor may be further used for interface composition when operating system desktop is in use and GPU(s) 1408 are not needed for continuously rendering new surfaces. In at least one embodiment, a video image compositor may be used to offload GPU(s) 1408 to improve performance and responsiveness when GPU(s) 1408 are turned on and active and perform 3D rendering.In at least one embodiment, one or more SoC of SoC(s) 1404 may further include a Mobile Industry Processor Serial Interface ("MIPI") for receiving video and input from cameras, a high-speed interface, and / or a video input block that may be used for a camera and associated pixel input functions. In at least one embodiment, one or more of SoC(s) 1404 may further include one or more input / output controllers that may be controlled by software and used to receive I / O signals that are not bound to a particular role.In at least one embodiment, one or more SoC of SoC(s) 1404 may further include a wide range of peripheral interfaces to enable communication with peripherals, audio encoders / decoders ("codecs"), power management, and / or other devices. In at least one embodiment, SoC(s) 1404 may be used to obtain data from cameras (e.g., via gigabit multimedia serial link and Ethernet channels), sensors (e.g., LIDAR sensor(s) 1464, RADAR sensor(s) 1460, etc., which may be connected via Ethernet channels), data from bus 1402 (e.g., speed of vehicle 1400, steering wheel position, etc.), data from GNSS sensor(s) 1458 (e.g., connected via an Ethernet bus or a CAN bus), etc. In at least one embodiment, one or more SoC of SoC(s) 1404 may further comprise dedicated high-performance mass storage controllers, These may include their own DMA engines and may be used to free the CPU(s) 1406 from routine tasks of data management.In at least one embodiment, SoC(s) 1404(s) may be an end-to-end platform with a flexible architecture that extends across automation levels 3- 5 and thereby provides a comprehensive functional safety architecture that uses computer vision and ADAS techniques for diversity and redundancy and provides a platform for a flexible, reliable driving software stack along with deep learning tools. In at least one embodiment, SoC(s) 1404 may be faster, more reliable, and even more energy and space saving than conventional systems. For example, in at least one embodiment, accelerator / accelerators 1414, in combination with CPU(s) 1406, GPU(s) 1408, and data store(s) 1416, may form a fast, efficient Level 3-5 autonomous vehicle platform.In at least one embodiment, computer vision algorithms can be executed on CPUs that can be configured with a high-level programming language, such as C, to execute a variety of processing algorithms for a wide variety of visual data. However, in at least one embodiment, CPUs are often unable to meet performance requirements of many computer vision applications, such as execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex real-time object detection algorithms used in in-vehicle ADAS applications and practical Level 3-5 autonomous vehicles.The embodiments described herein enable multiple neural networks to be executed simultaneously and / or sequentially and the results combined together to enable the level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executing on a DLA or a discrete GPU (e.g., GPU(s) 1420) may have text and word recognition that enables reading and understanding traffic signs, including signs for which a neural network has not been specifically trained. In at least one embodiment, a DLA may further include a neural network capable of identifying, interpreting, and semantically understanding a character and passing this semantic understanding to planning modules running on a CPU complex.In at least one embodiment, multiple neural networks may run simultaneously, such as driving level 3, 4, or 5. For example, in at least one embodiment, a warning sign indicating "Caution: flashing lights indicate icing" may be interpreted independently or jointly along with an electrical light from multiple neural networks. In at least one embodiment, such a warning sign itself may be identified as traffic signs by a first deployed neural network (e.g., a trained neural network), and text "Flashing lights indicate ice smoothness" may be interpreted by a second deployed neural network informing a vehicle's path planning software (preferably executing on a CPU complex) that when flashing lights are detected, ice smoothness is present. In at least one embodiment, a turn signal light may be identified by operating a third neural network across multiple frames informing path planning software of a vehicle of presence (or absence) of turn signals. In at least one embodiment, all three neural networks may run simultaneously, for example within a DLA and / or on GPU(s) 1408.In at least one embodiment, a CNN for face recognition and vehicle owner identification may use data from camera sensors to identify presence of an authorized driver and / or owner of vehicle 1400. In at least one embodiment, an "ways on" sensor processing engine may be used to unlock a vehicle when an owner approaches a driver door and turns lights on, and to disable such a vehicle in a security mode when an owner leaves such a vehicle. In this way, the SoC(s) 1404 provide security against theft and / or carjacking.In at least one embodiment, a emergency vehicle detection and identification CNN may use data from microphones 1496 to detect and identify emergency vehicle sirens. In at least one embodiment, SoC(s) 1404 use a CNN to classify environmental and urban sounds as well as to classify visual data. In at least one embodiment, a CNN running on a DLA is trained to identify a relative approach speed of a emergency vehicle (e.g., using a Doppler effect). In at least one embodiment, a CNN may also be trained to identify emergency vehicles specific to a local area in which a vehicle is located, as identified by GNSS sensor(s) 1458. In at least one embodiment, a CNN when used in Europe will attempt to identify European sirens, and when used in North America, a CNN will attempt to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program may be used to execute an emergency vehicle safety routine, decelerate a vehicle, drive to roadside, park a vehicle, and / or idle a vehicle, using ultrasonic sensor / s 1462, until emergency vehicles pass.In at least one embodiment, vehicle 1400 may include CPU(s) 1418 (e.g., discrete CPU(s) or dCPU(s)), which may be coupled to SoC(s) 1404 via a high speed interconnect (e.g., PCIe). In at least one embodiment, CPU(s) 1418 may include, for example, an X86 processor. The CPU(s) 1418 may be used to perform a variety of functions, including arbitration for potentially conflicting results between ADAS sensors and SoC(s) 1404, and / or monitoring the status and state of the controller(s) 1436 and / or an infotainment system on a chip ("Infotainment SoC") 1430, for example. In at least one embodiment, SoC(s) 1404 comprises one or more interconnects, and an interconnect may comprise a peripheral component interconnect express (PCIe).In at least one embodiment, vehicle 1400 may include GPU(s) 1420 (e.g., discrete GPU(s) or dG(s)), which may be coupled to SoC(s) 1404 via a high-speed interconnect (e.g., NVIDIAs NVLINK channel). In at least one embodiment, GPU(s) 1420 may provide additional artificial intelligence functionality, for example, by executing redundant and / or different neural networks, and may / may be used to train and / or update neural networks based at least in part on inputs (for example, sensor data) from sensors of a vehicle 1400.In at least one embodiment, vehicle 1400 may further include a network interface 1424, which may include, without limitation, one or more wireless antennas 1426 (e.g., one or more wireless antennas for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface 1424 may be used to enable wireless connection to Internet cloud services (e.g., server(s) and / or other network devices), other vehicles, and / or computing devices (e.g., passenger client devices). In at least one embodiment, a direct connection between vehicle 1400 and another vehicle and / or an indirect connection (e.g., via networks and Internet) may be established for communication with other vehicles. In at least one embodiment, direct connections may be established via a vehicle-to-vehicle communication link. In at least one embodiment, a vehicle-to-vehicle communication link may provide vehicle 1400 with information about vehicles proximate to vehicle 1400 (e.g., vehicles in front of, on a side of, and / or behind vehicle 1400). In at least one embodiment, this aforementioned functionality may be part of a cooperative adaptive cruise control function of vehicle 1400.In at least one embodiment, network interface 1424 may include a SoC that provides modulation and demodulation functions and enables controller(s) 1436 to communicate over wireless networks. In at least one embodiment, network interface 1424 may include a radio frequency front end for up-converting from baseband to radio frequency and down-converting from radio frequency to baseband. In at least one embodiment, frequency transformations may be performed in any technically possible manner.For example, frequency transformations can be performed by known methods and / or using super heterodyne methods. In at least one embodiment, radio frequency front-end functionality may be provided by a separate chip. In at least one embodiment, network interfaces may include wireless features for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWA, and / or other wireless protocols.In at least one embodiment, vehicle 1400 may further include one or more data stores 1428, which may include, without limitation, off-chip memory (e.g., off-SoC(s) 1404). In at least one embodiment, data store(s) 1428 may include, without limitation, one or more memory elements including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash memory, hard drives, and / or other components and / or devices capable of storing at least one bit of data.In at least one embodiment, vehicle 1400 may further include GNSS sensor(s) 1458 (e.g., GPS and / or assisted GPS sensors) to assist in mapping, perception, generation of a grid for occupancy and / or path planning. In at least one embodiment, any number of GNSS sensor(s) 1458 may be used, including, for example and without limitation, a GPS using a USB port with an Ethernet-to-serial bridge (e.g., RS-232).In at least one embodiment, vehicle 1400 may further include RADAR sensor(s) 1460. In at least one embodiment, RADAR sensor(s) 1460 of vehicle 1400 may be used (may) for detecting long-range vehicles, even in darkness and / or bad weather conditions. In at least one embodiment, RADAR sensors 1460 may use a CAN bus and / or a bus 1402 (e.g., to transmit data generated by RADAR sensors 1460) to control and access object tracking data, with raw data being accessed via Ethernet channels in some examples. In at least one embodiment, a wide range of RADAR sensors may be used. For example, and without limitation, RADAR sensor(s) 1460 may be suitable for use as front, rear, and side RADARs. In at least one embodiment, one or more sensors of RADAR sensor / sensors 1460 is a pulse-doppler RADAR sensor.In at least one embodiment, RADAR sensor(s) 1460 may include various configurations, such as a narrow field of view long range, a wide field of view short range, a short range side coverage, etc. In at least one embodiment, a long range RADAR may be used for adaptive cruise control functionality. In at least one embodiment, long range RADAR systems may provide a wide field of view realized by two or more independent scans, for example, within a range of 250 m (meters). In at least one embodiment, RADAR sensor(s) 1460 may aid in distinguishing between static and moving objects and may be used by ADAS system 1438 for emergency brake assist and forward collision warning. In at least one embodiment, sensor(s) 1460 included in a long range RADAR system(s) may (are) include, without limitation, a monostatic multimode RADAR having multiple (e.g., six or more) fixed RADAR antennas and a high speed CAN and FlexRay interface. In at least one embodiment with six antennas, four antennas in the center may generate a focused beam pattern that serves to sense the environment of the vehicle at higher speeds with minimal interference from traffic in the adjacent lanes. In at least one embodiment, two other antennas may extend field of view, thereby making it possible to quickly detect vehicles entering or leaving a lane of vehicle 1400.In at least one embodiment, for example, mid-range RADAR systems may include a range of up to 160 m (forward) or 80 m (rearward) and a field of view of up to 42 degrees (forward) or 150 degrees (rearward). In at least one embodiment, short range RADAR systems may include, without limitation, any number of RADAR sensors 1460, which may be installed at both ends of a rear bumper. In at least one embodiment, a RADAR sensor system, when installed at both ends of a rear bumper, may generate two beams that continuously monitor blind spots in the rear direction and adjacent a vehicle. In at least one embodiment, short range RADAR systems may be used in ADAS system 1438 to detect blind spot and / or to assist lane change.In at least one embodiment, vehicle 1400 may further include ultrasonic sensor(s) 1462. In at least one embodiment, ultrasonic sensor(s) 1462, which may be (may) disposed at a front, rear, and / or lateral location of vehicle 1400, may be(may) used for park assist and / or for raster creation and update. In at least one embodiment, a plurality of ultrasonic sensors 1462 may be used, and different ultrasonic sensors 1462 may be used for different sensing ranges (e.g., 2.5 m, 4 m). In at least one embodiment, ultrasonic sensor(s) 1462 may(may) operate at ASIL B functional safety levels.In at least one embodiment, vehicle 1400 may include LIDAR sensor(s) 1464. In at least one embodiment, LIDAR sensor(s) 1464 may be(can) used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, LIDAR sensor(s) 1464 may(s) operate at functional safety level ASIL B. In at least one embodiment, vehicle 1400 may include multiple LIDAR sensors 1464 (e.g., two, four, six, etc.) that may use an Ethernet channel (e.g., to provide data to a gigabit Ethernet switch).In at least one embodiment, LIDAR sensor(s) 1464 may / may be capable of providing a list of objects and their distances for a 360 degree field of view. In at least one embodiment, commercially available LIDAR sensor(s) 1464 may / may have an advertised range of about 100 m, with an accuracy of 2 cm to 3 cm, and with support for a 100 Mbps Ethernet connection, for example. In at least one embodiment, one or more non-protrusion LIDAR sensors may be used. In such an embodiment, the LIDAR sensor(s) 1464 may / may include a small device that may be embedded in a front, rear, side, and / or corner position of the vehicle 1400. In at least one embodiment, in such an embodiment, LIDAR sensor(s) 1464 may provide a horizontal field of view of up to 120 degrees and a vertical field of view of up to 35 degrees with a range of 200 m even for low reflectivity objects. In at least one embodiment, front-mounted LIDAR sensor(s) 1464 may / may be configured for a horizontal field of view between 45 degrees and 135 degrees.In at least one embodiment, LIDAR technologies, such as 3D flash LIDAR, may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate environment of vehicle 1400 to a distance of about 200 meters. In at least one embodiment, flash LIDAR unit includes, without limitation, a receptor that records laser pulse travel time and reflected light at each pixel, which in turn corresponds to a distance from vehicle 1400 to objects. In at least one embodiment, flash LIDAR may allow highly accurate and distortion-free images of environment to be generated with each laser flash. In at least one embodiment, four flash LIDAR sensors may be employed, one on each side of vehicle 1400. In at least one embodiment, 3D flash LIDAR systems include, without limitation, a solid state 3D star array LIDAR camera that does not have moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, flash LIDAR device may use a 5 nanosecond class I (eye safe) laser pulse per image and acquire reflected laser light as a 3D range point cloud and co-registered intensity data.In at least one embodiment, vehicle 1400 may further include one or more IMU sensors 1466. In at least one embodiment, IMU sensor(s) 1466 may / may be disposed in the center of a rear axle of vehicle 1400. In at least one embodiment, IMU sensor(s) 1466 may include, for example and without limitation, accelerometers, magnetometers, gyroscope(s), magnetic compass, magnetic compass, and / or other types of sensors. In at least one embodiment, for example in six-axis applications, IMU sensor(s) 1466 may include, without limitation, accelerometers and gyroscopes. In at least one embodiment, such as in nine-axis applications, IMU sensor(s) 1466 may / may include, without limitation, accelerometers, gyroscopes, and magnetometers.In at least one embodiment, IMU sensor(s) 1466 may be implemented as a miniaturized, high performance GPS-based inertial navigation system ("GPS / INS") that combines microelectromechanical systems ("MEMS") inertial sensors, a high sensitivity GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and location. In at least one embodiment, IMU sensor(s) 1466 may enable vehicle 1400 to estimate its heading without requiring input from a magnetic sensor by directly observing changes in speed from a GPS and correlating with IMU sensor(s) 1466. In at least one embodiment, IMU sensor(s) 1466 and GNSS sensor(s) 1458 may be combined into a single integrated unit.In at least one embodiment, vehicle 1400 may include one or more microphones 1496 disposed in and / or around vehicle 1400. In at least one embodiment, microphone(s) 1496 may be used to identify emergency vehicles, among other things.In at least one embodiment, vehicle 1400 may further include any number of camera types, including stereo camera(s) 1468, wide-angle camera(s) 1470, infrared camera(s) 1472, surround camera(s) 1474, long-range camera(s) 1498, mid-range camera(s) 1476, and / or other camera types. In at least one embodiment, cameras may be used to capture image data around the entire perimeter of vehicle 1400. In at least one embodiment, vehicle 1400 depends on what types of cameras are used. In at least one embodiment, any combination of camera types may be used to ensure necessary coverage around vehicle 1400. In at least one embodiment, the number of cameras used may vary depending on the embodiment. In at least one embodiment, vehicle 1400 may include, for example, six, seven, ten, twelve, or other number of cameras. In at least one embodiment, cameras may support gigabit multimedia serial link ("GMSL") and / or gigabit Ethernet communication, for example and without limitation. In at least one embodiment, each camera may be configured as described in more detail hereinabove with respect to FIGS. 14A and 14B.In at least one embodiment, vehicle 1400 may further include one or more vibration sensors 1442. In at least one embodiment, vibration sensor(s) 1442 may measure vibrations of components of vehicle 1400, such as axle(s). In at least one embodiment, changes in vibrations may indicate a change in road surface, for example. In at least one embodiment, when two or more vibration sensors 1442 are used, differences between vibrations may be used to determine friction or slip of road surface (e.g., when there is a difference in vibration between a driven axle and a free-rotating axle).In at least one embodiment, vehicle 1400 may include an ADAS system 1438. In at least one embodiment, ADAS system 1438 may include, without limitation, a SoC in some examples. In at least one embodiment, ADAS system 1438 may include, without limitation, any number and combination of an autonomous / adaptive / automatic cruise control ("ACC") system, a cooperative adaptive cruise control ("CACC") system, a forward crash warning ("FCW") system, an automatic emergency braking ("AEB") system, a lane departure warning ("LDW") system, a lane keeping assist ("LKA") system, a blind spot warning ("BSW") system, a rear cross traffic warning ("RCTW") system, a collision warning ("CW") system, a track centering ("LC") system and / or other systems, features and / or functions.In at least one embodiment, ACC system may use RADAR sensor(s) 1460, LIDAR sensor(s) 1464, and / or any number of cameras. In at least one embodiment, ACC system may include a longitudinal ACC system and / or a transverse ACC system. In at least one embodiment, an ACC system monitors and controls distance to another vehicle immediately in front of vehicle 1400 in a longitudinal direction and automatically adjusts speed of vehicle 1400 to maintain a safe distance to preceding vehicles. In at least one embodiment, a lateral ACC system takes over distance keeping and is listening to vehicle 1400 when necessary to change lanes. In at least one embodiment, a lateral ACC system is connected to other ADAS applications, such as LC and CW.In at least one embodiment, a CACC system uses information from other vehicles that may be received via network interface 1424 and / or wireless antenna(s) 1426 from other vehicles via a wireless connection or indirectly via a network connection (e.g., via Internet). In at least one embodiment, direct connections may be provided through a vehicle-to-vehicle ("V2V") communication link, while indirect connections may be provided through an infrastructure-to-vehicle ("I2V") communication link. Generally, V2V communication provides information about immediately preceding vehicles (e.g., vehicles that are immediately in front of and on the same lane as vehicle 1400), while I2V communication provides information about traffic that is further preceding. In at least one embodiment, a CACC system may include either or both I2V and V2V information sources. In at least one embodiment, a CACC system may be more reliable given information about vehicles in front of vehicle 1400, and has potential to improve traffic flow and reduce road congestion.In at least one embodiment, an FCW system is configured to warn a driver of a risk so that that driver may correctively intervene. In at least one embodiment, an FCW system uses a front-facing camera and / or RADAR sensor(s) 1460 that is / are coupled to a dedicated processor, DSP, FPGA, and / or ASIC that / are electrically coupled to provide feedback to driver, such as a display, speaker, and / or vibrating component. In at least one embodiment, an FCW system may provide a warning, such as in the form of a sound, a visual warning, a vibration, and / or a rapid brake pulse.In at least one embodiment, an AEB system detects an imminent forward collision with another vehicle or object and can automatically apply brakes if a driver does not correctively engage within a particular time or distance parameter. In at least one embodiment, AEB system may use forward facing camera(s) and / or RADAR sensor(s) 1460, which are connected to a special purpose processor, DSP, FPGA, and / or ASIC. In at least one embodiment, if an AEB system detects a risk, it will typically first warn a driver to take corrective action to avoid a collision, and if that driver does not take corrective action, AEB system may automatically apply brakes to prevent or at least mitigate effects of a predicted collision. In at least one embodiment, an AEB system may include techniques such as dynamic brake assist and / or crash-intrinsic braking.In at least one embodiment, an LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to warn driver when vehicle 1400 crosses lane markings. In at least one embodiment, an LDW system is not activated when a driver indicates an intentional lane departure, such as by actuating a turn signaler. In at least one embodiment, an LDW system may use front-facing cameras coupled to a special purpose processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide feedback to driver, such as via a display, speaker, and / or vibrating component. In at least one embodiment, an LKA system is a variant of an LDW system. In at least one embodiment, an LKA system provides input to steering or braking to correct vehicle 1400 when vehicle 1400 begins to exit its lane.In at least one embodiment, a BSW system detects and alerts driver to vehicles in the blind spot of vehicle. In at least one embodiment, a BSW system may issue a visual, audible, and / or tactile warning to indicate that merging or lane changing is uncertain. In at least one embodiment, a BSW system may issue an additional warning when a driver actuates a turn signal. In at least one embodiment, a BSW system may use (a) rear facing camera(s) and / or (a) RADAR sensor(s) 1460, which is / are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is / are electrically coupled to feedback to driver, such as a display, speaker, and / or vibrating component.In at least one embodiment, an RCTW system may provide visual, audible, and / or tactile notification when an object outside range of rear camera is detected when vehicle 1400 is backing. In at least one embodiment, an RCTW system includes an AEB system to ensure that vehicle brakes are applied to avoid an accident. In at least one embodiment, an RCTW system may use one or more rear-facing RADAR sensor(s) 1460, which is / are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is / are electrically coupled to provide feedback to driver, such as a display, speaker, and / or vibrating component.In at least one embodiment, conventional ADAS systems may tend to false positives results, which may be annoying and distracted to a driver, but are typically not catastrophic because conventional ADAS systems warn a driver and allow that driver to decide whether a safety condition actually exists and act accordingly. In at least one embodiment, in case of conflicting results, vehicle 1400 itself decides whether to consider result of a primary computer or a secondary computer (e.g., a first controller or a second controller of controllers 1436). In at least one embodiment, ADAS system 1438 may be, for example, a backup and / or secondary computer that provides perception information to a rationality module of backup computer. In at least one embodiment, a backup computer rationality monitor may run redundant various software on hardware components to detect errors in perception and dynamic driving tasks. In at least one embodiment, outputs of ADAS system 1438 may be passed to a higher level MCU. In at least one embodiment, a parent MCU determines how to resolve conflict to ensure safe operation when outputs of a primary computer and outputs of a secondary computer conflict with each other.In at least one embodiment, a primary computer may be configured to provide a score to a parent MCU that indicates how much confidence primary computer has in a selected result. In at least one embodiment, monitoring MCU may follow primary computer instruction when that confidence score exceeds a threshold, regardless of whether secondary computer provides an conflicting or inconsistent result. In at least one embodiment, in cases where a confidence score does not reach a threshold and where primary and secondary computers indicate different results (e.g., conflict), a monitoring MCU may mediate between computers to determine an appropriate result.In at least one embodiment, a monitoring MCU may be configured to execute a neural network trained and configured to determine, based at least in part on primary computer outputs and secondary computer outputs, conditions under which secondary computer provides false alarms. In at least one embodiment, neural network(s) may (may) learn in a monitoring MCU when output of a secondary computer can be trusted and when not. In at least one embodiment, if secondary computer system is a RADAR-based FCW system, a neural network or networks may learn in monitoring MCU when an FCW system identifies metallic objects that do not actually pose hazards, such as a drain grid or channel cap that triggers an alarm. In at least one embodiment, when a secondary computer is a camera-based LDW system, a neural network in a monitoring MCU may learn to override LDW system when cyclists or pedestrians are present and lane departure is actually the safest maneuver. In at least one embodiment, a monitoring MCU may include at least one DLA or GPU suitable for executing neural networks with associated memory. In at least one embodiment, a monitoring MCU may include and / or be included as a component of SoC(s) 1404.In at least one embodiment, ADAS system 1438 may include a secondary computer that performs ADAS functions using conventional rules of computer vision. In at least one embodiment, this secondary computer may use classic computer vision rules (if-then), and presence of a neural network(s) in a parent MCU may improve reliability, security, and performance. At least in one embodiment, the overall system becomes more fault tolerant, particularly to faults caused by software functions (or software-hardware interfaces), through the differential implementation and intentional non-identity. For example, in at least one embodiment, if a software fault occurs in software running on a primary computer and non-identical software code runs on a secondary computer that provides a consistent overall result, then a monitoring MCU may have a greater confidence that an overall result is correct and a fault in software or hardware on that primary computer does not cause a significant fault.In at least one embodiment, an output of ADAS system 1438 may be fed to host perception block and / or host dynamic driving task block. For example, in at least one embodiment, if ADAS system 1438 indicates a forward crash warning due to an object immediately ahead, a perception block may use this information to identify objects. In at least one embodiment, a secondary computer may have its own neural network that is trained to reduce risk of false alarms, as described herein.In at least one embodiment, vehicle 1400 may further include an infotainment SoC 1430 (e.g., an on-board infotainment system (IVI)). Although illustrated and described as SoC, in at least one embodiment, infotainment system SoC 1430 may not be a SoC and may include, without limitation, two or more discrete components. In at least one embodiment, infotainment SoC 1430 may include, without limitation, a combination of hardware and software that may be used to provide audio (e.g., music, a personal digital assistant, navigation commands, messages, radio, etc.), video (e.g., television, movies, streaming, etc.), telephone (e.g., hands-free kit), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation systems, rear parking assist, a radio data system, vehicle-related information such as fuel level, total distance travelled, brake fuel level, oil level, door open / close, air filter information, etc.) to vehicle 1400. The infotainment SoC 1430 could include, for example, radios, disk players, navigation systems, video players, USB and Bluetooth connectivity, carputers, in-car entertainment, WiFi, steering wheel audio control, hands-free kit, heads-up display ("HUD"), HMI display 1434, telematics device, control panel (e.g., for control and / or interaction with various components, functions, and / or systems), and / or other components. In at least one embodiment, infotainment SoC 1430 may be further used to provide (e.g., visually and / or audibly) information to user(s) of vehicle 1400, such as information from ADAS system 1438, autonomous driving information, such as scheduled vehicle maneuvers, trajectories, environmental information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.In at least one embodiment, infotainment SoC 1430 may include any amount and type of GPU functionality. In at least one embodiment, infotainment SoC 1430 may communicate with other devices, systems, and / or components of vehicle 1400 via bus 1402. In at least one embodiment, infotainment SoC 1430 may be coupled to a monitoring MCU such that a GPU of an infotainment system may perform some self-driving functions if primary controller(s) 1436 (e.g., vehicle 1400 primary and / or backup computers) fail. In at least one embodiment, infotainment SoC 1430 may place vehicle 1400 in a chauffeur-to-safe stop mode, as described herein.In at least one embodiment, vehicle 1400 may further include an instrument cluster 1432 (e.g., a digital dashboard, an electronic instrument cluster, a digital instrument panel, etc.). In at least one embodiment, instrument cluster 1432 may include, without limitation, a controller and / or a supercomputer (e.g., a discrete controller or a supercomputer). In at least one embodiment, instrument cluster 1432 may include, without limitation, any number and combination of instruments, such as tachometer, fuel level, oil pressure, tachometer, odometer, turn signal, shift position indicator, seatbelt warning light(s), parking brake warning light(s), engine malfunction light(s), additional restraint system information (e.g., airbags), lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared by infotainment SoC 1430 and instrument cluster 1432. In at least one embodiment, instrument cluster 1432 may be included as part of infotainment SoC 1430, or vice versa.In at least one embodiment, FIGS. 1-14C are to generate, using one or more neural networks, one or more enhanced speech signals from low quality audio data based at least in part on spectral and waveform features of low quality audio data and one or more features derived from reference audio data comprising one or more high quality speech signals.FIG. 14D is a diagram of a system for communication between one or more cloud-based servers and the autonomous vehicle 1400 of FIG. 14A, according to at least one embodiment. In at least one embodiment, system may include, without limitation, server / s 1478 network(s) 1490, and any number and type of vehicle, including vehicle 1400. In at least one embodiment, server / servers 1478 may include, without limitation, a plurality of GPUs 1484(A)-1484(H) (collectively referred to herein as GPUs 1484), PCIe switches 1482(A)-1482(D) (collectively referred to herein as PCIe switches 1482) and / or CPUs 1480(A)-1480(B) (collectively referred to herein as CPUs 1480). In at least one embodiment, GPUs 1484, CPUs 1480, and PCIe switches 1482 may be interconnected with high speed links, such as, for example and without limitation, NVLink interfaces 1488 developed by NVIDIA, and / or PCIe links 1486. In at least one embodiment, GPUs 1484 are connected via an NVLink and / or NVSwitch SoC and GPUs 1484 and PCIe switches 1482 are connected via PCIe interconnects. Although eight GPUs 1484, two CPUs 1480, and four PCIe switches 1482 are shown, this is not to be understood as limiting. In at least one embodiment, each of servers 1478 may include, without limitation, any number of GPUs 1484, CPUs 1480, and / or PCIe switches 1482, in any combination. For example, in at least one embodiment, server(s) 1478 could each include eight, sixteen, thirty-two, and / or more GPUs 1484.In at least one embodiment, server(s) 1478 may receive, via network(s) 1490 and vehicles, image data representative of images showing unexpected or altered road conditions, such as recently initiated paving operations. In at least one embodiment, servers 1478 may transmit, via network(s) 1490 and to vehicles, updated or other neural networks 1492 and / or map information 1494, including, but not limited to, traffic and road condition information. In at least one embodiment, updates to map information 1494 may include, without limitation, updates to HD map 1422, such as information about worksites, holes, diversions, floods, and / or other obstacles. In at least one embodiment, neural networks 1492 and / or map information 1494 may result from retraining and / or experiences represented in data received from any number of vehicles in an environment and / or based at least in part on training performed at a data center (e.g., using server(s) 1478 and / or other servers).In at least one embodiment, server / s 1478 may be used to train machine learning models (e.g., neural networks) based at least in part on training data. In at least one embodiment, training data from vehicles may be generated and / or generated in a simulation (e.g., using a game engine). In at least one embodiment, any set of training data is marked (e.g., when associated neural network benefits from supervised learning) and / or subjected to other preprocessing. In at least one embodiment, any set of training data is not tagged and / or pre-processed (e.g., if associated neural network does not require supervised learning). In at least one embodiment, once trained, machine learning models may be used by vehicles (e.g., transmitted to vehicles via network(s) 1490) and / or machine learning models may be used by server(s) 1478 to remotely monitor vehicles.In at least one embodiment, server(s) 1478 may receive data from vehicles and apply data to current neural networks for real-time intelligent inferencing. In at least one embodiment, server / s 1478 may include deep learning supercomputers and / or dedicated AI computers powered by GPU(s) 1484, such as DGX and DGX station machines developed by NVIDIA. However, in at least one embodiment, server / servers 1478 may also include deep learning infrastructure that uses CPU-powered data centers.In at least one embodiment, deep learning infrastructure of server(s) 1478 may be capable of fast real-time inferencing and utilize that capability to assess and verify state of processors, software, and / or associated hardware in vehicle 1400. For example, in at least one embodiment, deep learning infrastructure may receive periodic updates from vehicle 1400, such as a sequence of images and / or objects that vehicle 1400 has located in that sequence of images (e.g., via computer vision and / or other machine object classification techniques). In at least one embodiment, deep learning infrastructure may run its own neural network to identify objects and compare them to objects identified by vehicle 1400, and if results do not match and deep learning infrastructure concludes that AI in vehicle 1400 is malfunctioning, then server / s 1478 may send a signal to vehicle 1400 instructing a vehicle 1400 fail-safe computer to take control of notifying passengers and performing a safe parking maneuver.In at least one embodiment, server / s 1478 may include GPU(s) 1484, and one or more programmable inference accelerators (e.g., NVIDIAs TensorRT 3 devices). In at least one embodiment, a combination of GPU-based servers and inference accelerators may enable real-time responsiveness. In at least one embodiment, for example, when performance is less critical, inferencing may use servers with CPUs, FPGAs, and other processors. In at least one embodiment, hardware structure(s) 1115 are used to perform one or more embodiments. Details of the hardware structure(s) 1115 are described herein in connection with FIGS. 11A and / or 11B.COMPUTER SYSTEMSFIG. 15 is a block diagram illustrating an example computer system, which may be a system with interconnected devices and components, a system on a chip (SOC), or a combination thereof, formed with a processor that may include execution units for executing an instruction, in accordance with at least one embodiment. In at least one embodiment, computer system 1500 may include, without limitation, a component such as processor 1502 to employ execution units including logic to perform algorithms to process data in accordance with present disclosure, as in embodiment described herein. In at least one embodiment, computer system 1500 may include processors, such as PENTIUM® family of processors, Xeon™ Itanium® XScale™ and / or StrongARM™ Intel® Core™ or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, California, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, and the like) may also be used. In at least one embodiment, computer system 1500 may execute a version of WINDOWS operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX and Linux), embedding software, and / or graphical user interfaces may also be used.Embodiments may be used in other devices such as handheld devices and embedded applications. Some examples of wearable devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, embedded applications may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system capable of executing one or more instructions according to at least one embodiment.In at least one embodiment, computer system 1500 may include, without limitation, a processor 1502, which may include, without limitation, one or more execution units 1508 to perform machine learning model training and / or inferencing according to techniques described herein. In at least one embodiment, computer system 1500 is a desktop or server system having a processor, but in another embodiment, computer system 1500 may be a multiprocessor system. In at least one embodiment, processor 1502 may include, without limitation, a complex instruction set computer (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing a combination of instruction sets, or any other device such as a digital signal processor. In at least one embodiment, processor 1502 may be connected to a processor bus 1510, which may transmit data signals between processor 1502 and other components in computer system 1500.In at least one embodiment, processor 1502 may include, without limitation, an internal level 1 ("L1") cache memory ("cache") 1504. In at least one embodiment, processor 1502 may include a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may be external to processor 1502. Other embodiments may also include a combination of internal and external caches depending on the particular implementation and needs. In at least one embodiment, a register file 1506 may store different types of data in different registers, including, without limitation, integer registers, floating point registers, status registers, and an instruction pointer register.In at least one embodiment, execution unit 1508, which includes, without limitation, logic to perform integer and floating point operations, is also located in processor 1502. In at least one embodiment, processor 1502 may also include microcode ("ucode") read-only memory ("ROM") that stores microcode for certain microinstruction. In at least one embodiment, execution unit 1508 may include logic to handle a packed instruction set 1509. In at least one embodiment, by including packed instruction set 1509 in instruction set of a general purpose processor, along with associated circuitry for executing instructions, operations used by many multimedia applications may be performed using packed data in processor 1502. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by utilizing full width of processor bus for performing packed data operations, thereby eliminating the need to transfer smaller units of data across processor bus to perform one or more operations with one data element each.In at least one embodiment, execution unit 1508 may also be used in microcontrollers, embedding processors, graphics devices, DSPs, and other types of logic circuitry. In at least one embodiment, computer system 1500 may include, without limitation, memory 1520. In at least one embodiment, memory 1520 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, or another memory device. In at least one embodiment, memory 1520 may store instruction(s) 1519 and / or data 1521 represented by data signals executable by processor 1502.In at least one embodiment, a system logic chip may be connected to processor bus 1510 and memory 1520. In at least one embodiment, a system logic chip may include, without limitation, a memory controller hub ("MCH") 1516, and processor 1502 may communicate with MCH 1516 via processor bus 1510. In at least one embodiment, MCH 1516 may provide a high bandwidth storage path 1518 to memory 1520 for storing instructions and data stores as well as for storing graphics instructions, data, and textures. In at least one embodiment, MCH 1516 may route data signals between processor 1502, memory 1520, and other components in computer system 1500, and may bypass data signals between processor bus 1510, memory 1520, and a system I / O interface 1522. In at least one embodiment, a system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 1516 may be coupled to memory 1520 via a high bandwidth memory path 1518, and a graphics / video card 1512 may be coupled to MCH 1516 via an accelerated graphics port ("AGP") interconnect 1514.In at least one embodiment, computer system 1500 may use system I / O interface 1522 as a proprietary hub interface bus to connect MCH 1516 to an I / O controller hub ("ICH") 1530. In at least one embodiment, ICH 1530 may provide direct connections to some I / O devices via a local I / O bus. In at least one embodiment, a local I / O bus may include, without limitation, a high speed I / O bus for connecting peripherals to memory 1520, a chipset, and processor 1502. Examples may include, without limitation, an audio controller 1529, a firmware hub ("flash BIOS") 1528, a wireless transceiver 1526, a data storage 1524, a legacy I / O controller 1523 with user input and keyboard interfaces 1525, a serial expansion port 1527 such as a universal serial bus ("USB") port, and a network controller 1534. In at least one embodiment, data storage 1524 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.In at least one embodiment, FIG. 15 illustrates a system including interconnected hardware devices or "chips", while in other embodiments, FIG. 15 may illustrate an example SoC. In at least one embodiment, devices shown in FIG. 15 may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components of computer system 1500 are interconnected using compute express link (CXL) connections.Logic 1115 is used to perform inferencing and / or training operations in connection with one or more embodiments. Details of logic 1115 are described herein in connection with FIGS. 11A and / or 11B. In at least one embodiment, logic 1115 in computer system 1500 may be used for inferencing or predicting operations based at least in part on weight parameters calculated using neural network training systems, neural network functions and / or architectures, or neural network use cases described herein.In at least one embodiment, FIGS. 1-15 are to generate, using one or more neural networks, one or more enhanced speech signals from inferior audio data based at least in part on spectral and waveform features of inferior audio data and one or more features derived from reference audio data comprising one or more superior speech signals.FIG. 16 is a block diagram illustrating an electronic device 1600 for using a processor 1610 according to at least one embodiment. In at least one embodiment, electronic device 1600 may be, for example and without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or another suitable electronic device.In at least one embodiment, electronic device 1600 may include, without limitation, a processor 1610 communicatively connected to any number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 1610 is coupled via a bus or interface, such as an I2C bus, a system management ("SMBus") bus, a low pin count (LPC) bus, a serial peripheral interface ("SPI"), a high definition audio ("HDA") bus, a serial advance technology attachment ("SATA") bus, a universal serial bus ("USB") (versions 1, 2, 3, etc.), or a universal asynchronous receiver / transmitter ("UART") bus. In at least one embodiment, FIG. 16 illustrates a system including interconnected hardware devices or "chips", while in other embodiments, FIG. 16 may illustrate an example SoC. In at least one embodiment, devices shown in FIG. 16 may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components of FIG. 16 are interconnected using compute express link (CXL) connections.In at least one embodiment, FIG. 16 may include a display 1624, a touch screen 1625, a touchpad 1630, a near field communications ("NFC") unit 1645, a sensor hub 1640, a thermal sensor 1646, an express chipset ("EC") 1635, a trusted platform module ("TPM") 1638, BIOS / firmware / flash memory ("BIOS, FW Flash") 1622, a DSP 1660, a drive 1620 such as a solid state disk ("SSD") or a hard disk drive ("HDD"), a wireless local area network ("WLAN") unit 1650, a Bluetooth unit 1652, a wireless wide area network ("WWAN") unit 1656, a global positioning system (GPS) unit 1655, a camera ("USB 3.0-camera") 1654 such as a USB 3.0-camera, and / or a low power double data rate ("LPDDR") storage unit ("LPDDR3") 1615 implemented according to an LPDDR3 standard, for example. These components may each be implemented in any suitable manner.In at least one embodiment, other components may be communicatively connected to processor 1610 by components described herein. In at least one embodiment, accelerometer 1641, ambient light sensor ("ALS") 1642, compass 1643, and gyroscope 1644 may be communicatively coupled to sensor hub 1640. In at least one embodiment, a thermal sensor 1639, a fan 1637, a keyboard 1636, and a touchpad 1630 may be communicatively connected to EC 1635. In at least one embodiment, speakers 1663, earphones 1664, and a microphone ("mic") 1665 may be communicatively coupled to an audio codec and class D amp ("audio codec and class D amp") 1662, which in turn may be communicatively coupled to DSP 1660. In at least one embodiment, audio unit 1662 may include, for example and without limitation, an audio coder / decoder ("codec") and a class D amplifier. In at least one embodiment, a SIM card ("SIM") 1657 may be communicatively coupled to WWAN unit 1656. In at least one embodiment, components such as WLAN unit 1650 and Bluetooth unit 1652, as well as WWAN unit 1656, may be implemented in a next generation form factor ("NGFF").Logic 1115 is used to perform inferencing and / or training operations in connection with one or more embodiments. Details of logic 1115 are described herein in connection with FIGS. 11A and / or 11B. In at least one embodiment, logic 1115 in electronic device 1600 may be used for inferencing or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.In at least one embodiment, FIGS. 1-16 are to generate, using one or more neural networks, one or more enhanced speech signals from inferior audio data based at least in part on spectral and waveform features of inferior audio data and one or more features derived from reference audio data comprising one or more superior speech signals.FIG. 17 illustrates a computer system 1700, according to at least one embodiment. In at least one embodiment, computer system 1700 is configured to implement various processes and methods described in this disclosure.In at least one embodiment, computer system 1700 includes, without limitation, at least one central processing unit ("CPU") 1702 coupled to a communication bus 1710 implemented using any suitable protocol, such as peripheral component interconnect (PCI); peripheral component interconnect express (PCI express); accelerated graphics port (AGP); hypertransport; or another bus or point-to-point communication protocol. In at least one embodiment, computer system 1700 includes, without limitation, main memory 1704 and control logic (e.g., in form of hardware, software, or a combination thereof), and data is stored in main memory 1704, which may take the form of random access memory ("RAM"). In at least one embodiment, a network interface ("network interface") subsystem 1722 provides an interface to other computing devices and networks to receive data from and transmit data to other systems with computer system 1700.In at least one embodiment, computer system 1700 includes, without limitation, input devices 1708, a parallel processing system 1712, and display devices 1706, which may be implemented using a conventional cathode ray tube ("CRT"), liquid crystal display ("LCD"), light emitting diode display ("LED"), plasma display, or other suitable display technologies. In at least one embodiment, user input is via input devices 1708, such as keyboard, mouse, touchpad, microphone, etc. In at least one embodiment, each module described herein may be packaged on a single semiconductor platform to form a processing system.Logic 1115 is used to perform inferencing and / or training operations in connection with one or more embodiments. Details of inference and / or training logic 1115 are described herein in connection with FIGS. 11A and / or 11B. In at least one embodiment, logic 1115 in computer system 1700 may be used for inferencing or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.In at least one embodiment, FIGS. 1-17 are to generate one or more enhanced speech signals from inferior audio data using one or more neural networks based at least in part on spectral and waveform features of inferior audio data and one or more features derived from reference audio data comprising one or more superior speech signals.FIG. 18 illustrates a computer system 1800 in accordance with at least one embodiment. In at least one embodiment, computer system 1800 includes, without limitation, a computer 1810 and a USB stick 1820. In at least one embodiment, computer 1810 may include, without limitation, any number and type of processor(s) (not shown) and memory (not shown). In at least one embodiment, computer 1810 includes, without limitation, a server, a cloud instance, a laptop, and a desktop computer.In at least one embodiment, USB stick 1820 includes, without limitation, processing unit 1830, USB interface 1840, and USB interface logic 1850. In at least one embodiment, processing unit 1830 may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit 1830 may include, without limitation, any number and type of processing cores (not shown). In at least one embodiment, processing unit 1830 includes an application specific integrated circuit ("ASIC") that is optimized for performing any number and type of machine learning related operations. In at least one embodiment, processing unit 1830 is, for example, a tensor processing unit ("TPC") that is optimized for performing machine learning operations. In at least one embodiment, processing unit 1830 is a machine processing unit ("VPU") that is optimized for performing machine vision and machine learning operations.In at least one embodiment, USB interface 1840 may be any type of USB connector or USB socket. For example, in at least one embodiment, USB interface 1840 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface 1840 is a USB 3.0 type A connector. In at least one embodiment, USB interface 1850 logic may include any amount and type of logic that enables processing unit 1830 to communicate with devices (e.g., computer 1810) via USB port 1840.Logic 1115 is used to perform inferencing and / or training operations in connection with one or more embodiments. Details of logic 1115 are described herein in connection with FIGS. 11A and / or 11B. In at least one embodiment, logic 1115 in computer system 1800 may be used for inferencing or predicting operations based at least in part on weight parameters calculated using neural network training systems, neural network functions and / or architectures, or neural network use cases described herein.In at least one embodiment, FIGS. 1-18 are to generate, using one or more neural networks, one or more enhanced speech signals from inferior audio data based at least in part on spectral and waveform features of inferior audio data and one or more features derived from reference audio data comprising one or more superior speech signals.FIG. 19A illustrates an example architecture in which a plurality of GPUs 1910( 1)- 1910(N) are communicatively coupled to a plurality of multi-core processors 1905( 1)- 1905(M) via high-speed links 1940( 1)- 1940(N) (e.g., buses, point-to-point interconnects, etc.). In at least one embodiment, high speed links 1940( 1)- 1940(N) support communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or more. In at least one embodiment, various interconnect protocols may be used, including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. In various figures, "N" and "M" represent positive integers whose values may vary from figure to figure. In at least one embodiment, one or more GPUs in a plurality of GPUs 1910( 1)- 1910(N) includes one or more graphics cores (also referred to simply as "cores") 2200 as disclosed in FIGS. 22A and 22B. In at least one embodiment, one or more graphics cores 2200 may be referred to as streaming multiprocessors ("SMs"), stream processors ("SPs"), stream processing units ("SPUs"), compute units ("CUs"), execution units ("EUs"), and / or slices, where a slice in this context may refer to a portion of processing resources in a processing unit (e.g., 16 cores, a ray tracing unit, a thread director, or scheduler).Additionally, and in at least one embodiment, two or more GPUs 1910 are interconnected via high-speed links 1929( 1)- 1929( 2), which may be implemented using similar or different protocols / links than those used for high-speed links 1940( 1)- 1940(N). Similarly, two or more multi-core processors 1905 may be connected via a high speed link 1928, which may be symmetric multiprocessor buses (SMPs) operating at 20 GB / s, 30 GB / s, 120 GB / s, or more. Alternatively, all communication between the various system components shown in FIG. 19A may be accomplished using similar protocols / connections (e.g., via a common fabric for interconnection).In at least one embodiment, each multi-core processor 1905 is communicatively coupled to a processor memory 1901( 1)- 1901(M) via memory links 1926( 1)- 1926(M), and each GPU 1910( 1)- 1910(N) is communicatively coupled to GPU memory 1920( 1)- 1920(N) via GPU memory links 1950( 1)- 1950(N). In at least one embodiment, memory links 1926 and 1950 may use similar or different memory access technologies. The processor memories 1901( 1)- 1901(M) and the GPU memories 1920 may be, for example, volatile memories such as dynamic random access memories (DRAMs) (including stacked DRAMs), graphics DDR SDRAM (GDDR) (for example, GDDR5, GDDR6), or high bandwidth memory (HBM), and / or nonvolatile memories such as 3D XPoint or nano-Ram. In at least one embodiment, a portion of processor memory 1901 may be volatile memory and another portion may be nonvolatile memory (e.g., using a two-level memory (2LM) hierarchy).As described herein, while different multi-core processors 1905 and GPUs 1910 may be physically coupled to a particular memory 1901, 1920, respectively, and / or a unified memory architecture may be implemented in which a virtual system address space (also referred to as "effective address space") is distributed among different physical memories. For example, processor memories 1901(1)-1901(M) may each comprise 64 GB system address space and GPU memories 1920(1)-1920(N) may each comprise 32 GB system address space, resulting in a total of 256 GB addressable memories at M=2 and N=4. Other values for N and M are possible.FIG. 19B shows additional details for an interconnection between a multi-core processor 1907 and a graphics acceleration module 1946, according to an example embodiment. In at least one embodiment, graphics acceleration module 1946 may include one or more GPU chips integrated on a line card connected to processor 1907 via a high-speed link 1940 (e.g., a PCIe bus, NVLink, etc.). In at least one embodiment, graphics acceleration module 1946 may alternatively be integrated on a package or chip with processor 1907.In at least one embodiment, processor 1907 includes a plurality of cores 1960A- 1960D (which may be referred to as "execution units"), each with a translation lookaside buffer ("TLB") 1961A- 1961D and one or more caches 1962A- 1962D. In at least one embodiment, cores 1960A- 1960D may include various other components for executing instructions and processing data, not shown. In at least one embodiment, caches 1962A- 1962D may include level 1 (L1) and level 2 (L2) caches. Moreover, one or more shared caches (1956) may be included in caches 1962A- 1962D and shared by groups of cores (1960A- 1960D). For example, one embodiment of processor 1907 includes 24 cores, each with a dedicated L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, one or more L2 and L3 caches are shared by two adjacent cores. In at least one embodiment, processor 1907 and graphics acceleration module 1946 are coupled to system memory 1914, which may include processor memories 1901( 1)- 1901( M) of FIG. 19A.In at least one embodiment, coherency is maintained for data and instructions stored in various caches 1962A- 1962D, 1956 and system memory 1914 via inter-core communication via a coherency bus 1964. For example, in at least one embodiment, each cache may include cache coherency logic / circuitry coupled thereto to communicate over coherency bus 1964 in response to detected reads or writes in particular cache lines. In at least one embodiment, a cache coherency protocol is implemented over coherency bus 1964 to snoop cache accesses.In at least one embodiment, proxy circuitry 1925 communicatively couples graphics acceleration module 1946 to coherency bus 1964, thereby enabling graphics acceleration module 1946 to participate in a cache coherency protocol as peers of cores 1960A- 1960D. In particular, in at least one embodiment, an interface 1935 provides connectivity to proxy circuit 1925 via high speed link 1940, and an interface 1937 connects graphics acceleration module 1946 to high speed link 1940.In at least one embodiment, accelerator integration circuit 1936 provides cache management, memory access, context management, and interrupt management services to a plurality of graphics processing engines 1931(1)-1931(N) of graphics acceleration module 1946. In at least one embodiment, graphics processing engines 1931(1)-1931(N) may each include a dedicated graphics processing unit (GPU). In at least one embodiment, a plurality of graphics processing engines 1931(1)-1931(N) of graphics acceleration module 1946 includes one or more graphics cores 2200 as discussed in connection with FIGS. 22A and 22B. In at least one embodiment, graphics processing engines 1931(1)-1931(N) may alternatively include different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoder / decoder), samplers, and blit engines. In at least one embodiment, graphics acceleration module 1946 may be a GPU having a plurality of graphics processing engines 1931( 1)- 1931(N), or graphics processing engines 1931( 1)- 1931(N) may be individual GPUs integrated on a common package, line card, or chip.In at least one embodiment, accelerator integration circuit 1936 includes a memory management unit (MMU) 1939 for performing various memory management functions, such as virtual to physical memory translations (also referred to as effective to real memory translations) and memory access protocols for accessing system memory 1914. In at least one embodiment, MMU 1939 may also include a translation lookaside buffer (TLB) (not shown) to cache virtual / effective to physical / real address translations. In at least one embodiment, cache 1938 may store instructions and data for efficient access by graphics processing engines 1931(1)-1931(N). In at least one embodiment, data stored in cache 1938 and graphics memories 1933( 1)- 1933(M) is maintained coherent with core caches 1962A- 1962D, 1956 and system memory 1914, possibly using a fetch unit 1944. As mentioned, this may be via proxy circuitry 1925 in the name of cache 1938 and memories 1933(1)-1933(M) (e.g., sending updates to cache 1938 with respect to changes / accesses to cache lines in processor caches 1962A-1962D, 1956, and receiving updates from cache 1938).In at least one embodiment, a set of registers 1945 store context data for threads executed by graphics processing engines 1931(1)-1931(N), and context management circuitry 1948 manages thread contexts. For example, context management circuitry 1948 may perform store and restore operations to store and restore contexts of different threads during context switches (e.g., when a first thread is stored and a second thread is stored to allow a second thread to be executed by a graphics processing engine). For example, for a context switch, context management circuitry 1948 may store the current register values in a particular area in memory (e.g., for identification by a context pointer). It can then restore the register values when it returns to a context. In at least one embodiment, interrupt management circuitry 1947 receives and processes interrupts received from system devices.In at least one embodiment, virtual / effective addresses from a graphics processing engine 1931 are translated by MMU 1939 into real / physical addresses in system memory 1914. In at least one embodiment, accelerator integration circuit 1936 supports multiple (e.g., 4, 8, 16) graphics acceleration modules 1946 and / or other acceleration devices. In at least one embodiment, graphics acceleration module 1946 may be dedicated to a single application executing on processor 1907, or shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented in which graphics processing engines 1931(1)-1931(N) resources are shared among multiple applications or virtual machines (VMs). In at least one embodiment, resources may be divided into "slices" that are associated with different VMs and / or applications based on processing requests and priorities associated with VMs and / or applications.In at least one embodiment, accelerator integration circuit 1936 bridges a system for graphics acceleration module 1946, and provides address translation and system memory cache services. Additionally, in at least one embodiment, accelerator integration circuit 1936 may provide virtualization facilities for a host processor to manage virtualization of graphics processing engines 1931( 1)- 1931( N), interrupts, and memory management.In at least one embodiment, because hardware resources of graphics processing engines 1931(1)-1931(N) are explicitly mapped to a real address space seen by host processor 1907, each host processor can address these resources directly via an effective address value. In at least one embodiment, a function of accelerator integration circuit 1936 is to physically separate graphics processing engines 1931(1)-1931(N) so that they appear as independent units for a system.In at least one embodiment, one or more graphics memories 1933( 1)- 1933(M) are connected to each of graphics processing engines 1931( 1)- 1931(N), where N=M. In at least one embodiment, graphics memories 1933( 1)- 1933(M) store instructions and data processed by each of graphics processing engines 1931( 1)- 1931(N). In at least one embodiment, graphics memories 1933( 1)- 1933(M) may be volatile memories such as DRAMs (including stacked DRAMs), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or may be nonvolatile memories such as 3D XPoint or nano-Ram.In at least one embodiment, to reduce data traffic over high speed link 1940, biasing techniques may be used to ensure that data stored in graphics memories 1933(1)-1933(M) is data most frequently used by graphics processing engines 1931(1)-1931(N), and preferably not by cores 1960A-1960D (at least not frequently). Similarly, in at least one embodiment, a bias mechanism attempts to keep data required by cores (and preferably not graphics processing engines 1931( 1)- 1931( N)) in caches 1962A- 1962D, 1956 and system memory 1914.FIG. 19C shows another example embodiment in which the accelerator integration circuit 1936 is integrated with the processor 1907. In this embodiment, graphics processing engines 1931(1)-1931(N) communicate directly over high speed link 1940 with accelerator integration circuit 1936, via interface 1937, and interface 1935, (which in turn may be any form of bus or interface protocol). In at least one embodiment, accelerator integration circuit 1936 may perform similar operations as described in FIG. 19B, but possibly with a higher throughput because it is in close proximity to coherency bus 1964 and caches 1962A- 1962D, 1956. In at least one embodiment, accelerator integration circuitry supports various programming models, including a dedicated process programming model (without virtualization of graphics acceleration module) and shared programming models (with virtualization), which may include programming models controlled by accelerator integration circuitry 1936, and programming models controlled by graphics acceleration module 1946.In at least one embodiment, graphics processing engines 1931(1)-1931(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application may forward requests from other applications to graphics processing engines 1931(1)-1931(N) to enable virtualization within a VM / partition.In at least one embodiment, graphics processing engines 1931(1)-1931(N) may be shared among multiple VM / application partitions. In at least one embodiment, shared models may use a system supervisor to virtualize graphics processing engines 1931(1)-1931(N) to enable access by each operating system. In at least one embodiment, graphics processing engines 1931(1)-1931(N) are owned by an operating system in systems with a partition without a hypervisor. In at least one embodiment, an operating system may virtualize graphics processing engines 1931(1)-1931(N) to provide access to each process or application.In at least one embodiment, graphics acceleration module 1946 or a single graphics processing engine 1931( 1)- 1931( N) selects a process element using a process handle. In at least one embodiment, process elements are stored in system memory 1914 and are addressable from effective addresses to real addresses using a translation technique described herein. In at least one embodiment, a process handle may be an implementation specific value provided to a host process when it registers its context to graphics processing engine 1931(1)-1931(N) (i.e., when it invokes system software to add a process element to a linked process element list). In at least one embodiment, lower 16 bits of a process handle may be an offset of a process element within a process element list.FIG. 19D shows an example accelerator integration slice 1990. In at least one embodiment, a "slice" includes a particular portion of processing resources of accelerator integration circuit 1936. In at least one embodiment, an application stores process elements 1983 in an effective address space 1982 in system memory 1914. In at least one embodiment, process elements 1983 are stored in response to GPU calls 1981 from applications 1980 executing on processor 1907. In at least one embodiment, a process element 1983 includes state of corresponding application 1980. In at least one embodiment, a work description (WD) 1984 included in process element 1983 may be a single job requested by an application or may include a pointer to a queue of jobs. In at least one embodiment, WD 1984 is a pointer to a job request queue in application effective address space 1982.In at least one embodiment, graphics acceleration module 1946 and / or individual graphics processing engines 1931( 1)- 1931( N) may be shared among all or a subset of processes in a system. In at least one embodiment, an infrastructure for establishing process conditions and sending a WD 1984 to a graphics acceleration module 1946 for starting a job in a virtualized environment may be included.In at least one embodiment, a programming model for dedicated processes is implementation specific. In at least one embodiment, in this model, a single process has a graphics acceleration module 1946 or an individual graphics processing engine 1931. In at least one embodiment, when graphics acceleration module 1946 is owned by a single process, a hypervisor initializes accelerator integration circuit 1936 for a owned partition and an operating system initializes accelerator integration circuit 1936 for a owned process when graphics acceleration module 1946 is assigned.In operation, in at least one embodiment, a WD fetch unit 1991 fetches, in accelerator integration slice 1990, next WD 1984, which includes an indication of work to be performed by one or more graphics processing engines of graphics acceleration module 1946. In at least one embodiment, data from WD 1984 may be stored in registers 1945 and used by MMU 1939, interrupt management circuitry 1947, and / or context management circuitry 1948 as shown. For example, one embodiment of MMU 1939 includes segment / page run circuitry for accessing segment / page tables 1986 within a virtual address space of operating system 1985. In at least one embodiment, circuitry 1947 may process interrupt events 1992 received from graphics acceleration module 1946. In at least one embodiment, when performing graphics operations, an effective address 1993 generated by a graphics processing engine 1931(1)-1931(N) is translated by MMU 1939 to a real address.In at least one embodiment, registers 1945 are duplicated for each graphics processing engine 1931(1)-1931(N) and / or graphics acceleration module 1946, and may be initialized by a hypervisor or operating system. In at least one embodiment, each of these duplicated registers may be included in accelerator integration slice 1990. Example registers that may be initialized by a hypervisor are listed in Table 1. Table 1 - Initialized Hypervisor Registers Table 1 - Initialized Hypervisor Registers1Slice Control Registers2Real Address (RA) Pointer for the Scheduled Process Area3Authority Mask Override Registers4Interrupt Vector Table Entry Offset5Interrupt Vector Table Entry Boundary6Status Register7Partition Logical ID8Real Address (RA) Hypervisor Accelerator Load Set Pointers9Memory Description RegisterExample registers that may be initialized by an operating system are listed in Table 2. Table 2 - Initialized Registers of the Operating System Table 2 - Initialized Registers of the Operating System1Process and Thread Identification2Effective Address (EA) Context Store / Restore Pointer3Virtual Address (VA) Accelerator Load Set Pointer4Virtual Address (VA) Pointer to Memory Segment Table5Authority Mask6Working DescriptionIn at least one embodiment, each WD 1984 is specific to a particular graphics acceleration module 1946 and / or graphics processing engines 1931(1)-1931(N). In at least one embodiment, it contains all information needed by a graphics processing engine 1931(1)-1931(N) to perform work, or it may be a pointer to a storage location where an application has set up a command queue of work to be performed.FIG. 19E shows additional details for an example embodiment of a common model. This embodiment includes a hypervisor real address space 1998 in which a process element list 1999 is stored. In at least one embodiment, hypervisor real address space 1998 is accessible via a hypervisor 1996 virtualizing graphics acceleration module engines for operating system 1995.In at least one embodiment, common programming models allow all or a subset of processes from all or a subset of partitions in a system to use a graphics acceleration module 1946. In at least one embodiment, there are two programming models in which graphics acceleration module 1946 is shared among multiple processes and partitions, namely time-slicing shared and graphics directed shared.In at least one embodiment, in this model, system hypervisor 1996 has graphics acceleration module 1946 and provides its function to all operating systems 1995. In at least one embodiment, a graphics acceleration module 1946 to support virtualization by system supervisor 1996 may meet certain requirements, such as (1) application's job request must be autonomous (i.e., state need not be maintained between jobs), or graphics acceleration module 1946 must provide a mechanism for storing and restoring context, (2) graphics acceleration module 1946 guarantees that application's job request will complete in a certain amount of time, including any translation errors, or graphics acceleration module 1946 provides ability to prefer processing of a job, and (3) graphics acceleration module 1946 must guarantee fairneβ between processes when operating in a directed shared programming model.In at least one embodiment, application 1980 must make a system call of operating system 1995 with a graphics acceleration module type, a work description (WD), an authority mask register (AMR), and a context store / restore pointer (CSRP). In at least one embodiment, type of graphics acceleration module describes a targeted acceleration function for a system call. In at least one embodiment, type of graphics acceleration module may be a system specific value. In at least one embodiment, WD is specially formatted for graphics acceleration module 1946 and may be in the form of a graphics acceleration module 1946 command, a pointer to effective address of a user-defined structure, a pointer to effective address of a command queue, or other data structure describing work to be performed by graphics acceleration module 1946.In at least one embodiment, an AMR value is an AMR state to be used for a current process. In at least one embodiment, a value passed to an operating system is comparable to an application that sets an AMR. In at least one embodiment, if accelerator integration circuit 1936 (not shown) and graphics acceleration module 1946 implementations do not support an authority mask override register (UAMOR), an operating system may apply a current UAMOR value to an AMR value before passing an AMR in a hypervisor call. In at least one embodiment, hypervisor 1996 may optionally apply a current value of authority mask override register (AMOR) before placing an AMR in process element 1983. In at least one embodiment, CSRP is one of registers 1945 that includes an effective address of an area in effective address space 1982 of an application for graphics acceleration module 1946 to store and restore context state. In at least one embodiment, this pointer is optional when no inter-task state needs to be stored or when a task is aborted prematurely. In at least one embodiment, context storage / recovery area may be pinned to system memory.Upon receiving a system call, operating system 1995 may verify whether application 1980 has and has obtained permission to use graphics acceleration module 1946. In at least one embodiment, operating system 1995 then invokes hypervisor 1996 with information shown in Table 3. Table 3 - Parameters for Calling the Operating System to the Hypervisor Table 3 - Parameters for Calling the Operating System to the Hypervisor1A Working Description (WD)2An authority mask register value (AMR) (possibly masked)3An effective address (EA) context store / restore pointer (CSRP)4A process ID (PID) and optionally a thread ID (TID)5A Virtual Address (VA) Accelerator Load Set Pointer (AURP)6Virtual Address of Pointer to Memory Segment Table (SSCP)7A Logical Interrupt Service Number (LISN)In at least one embodiment, upon receiving a hypervisor call, hypervisor 1996 checks whether operating system 1995 has and has obtained permission to use graphics acceleration module 1946. In at least one embodiment, hypervisor 1996 then inserts process element 1983 into a process element list for a corresponding type of graphics acceleration module 1946. In at least one embodiment, a process element may include information shown in Table 4. Table 4 - Process Element Information Table 4 - Process Element Information1A Working Description (WD)2An authority mask register (AMR) value (possibly masked).3An effective address (EA) context store / restore pointer (CSRP)4A process ID (PID) and optionally a thread ID (TID)5A Virtual Address (VA) Accelerator Load Set Pointer (AURP)6Virtual Address of Pointer to Memory Segment Table (SSCP)7A Logical Interrupt Service Number (LISN)8Interrupt Vector Table Derived from Hypervisor Call Parameters9A state register value (SR)10A logical partition ID (LPID)11A Real Address (RA) Accelerator Utilization Set pointer of the Hypervisor12Memory Description Register (SDR)In at least one embodiment, hypervisor initializes a plurality of accelerator integration slice registers 1990 1945.As shown in FIG. 19F, in at least one embodiment, unified memory is used that is addressable via a common virtual memory address space used for accessing physical processor memories 1901( 1)- 1901(N) and GPU memories 1920( 1)- 1920(N). In this implementation, the operations performed on the GPUs 1910( 1)- 1910(N) use the same virtual / effective address space for accessing the processor memories 1901( 1)- 1901(M) and vice versa, which simplifies the programability. In at least one embodiment, a first portion of a virtual / effective address space is associated with processor memory 1901(1), a second portion is associated with second processor memory 1901(N), a third portion is associated with GPU memory 1920(1), etc. In at least one embodiment, this distributes an entire virtual / effective memory space (sometimes referred to as an effective address space) across each of processor memories 1901 and GPU memories 1920, thereby allowing each processor or GPU to access each physical memory with a virtual address associated with that memory.In at least one embodiment, bias / coherency management circuit 1994A- 1994E within one or more MMUs 1939A- 1939E ensures cache coherency between caches of one or more host processors (e.g., 1905) and GPUs 1910, and implements bias techniques that indicate in which physical memories certain types of data should be stored. In at least one embodiment, while multiple instances of bias / coherence management circuitry 1994A- 1994E are shown in FIG. 19F, bias / coherence circuitry may be implemented within an MMU of one or more host processors 1905 and / or within accelerator integration circuitry 1936.One embodiment allows GPU memory 1920 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology without having to accept the performance disadvantages associated with full system cache coherency. In at least one embodiment, the ability to access GPU memories 1920 as system memory without inconvenient cache coherency overhead provides an advantageous operating environment for GPU offload. In at least one embodiment, this arrangement allows host processor 1905 software to adjust operands and access computation results without overhead of traditional I / O DMA copies of data. In at least one embodiment, such conventional copies are associated with driver calls, interrupts, and memory mapping I / O accesses (MMIO), all of which are inefficient compared to simple memory accesses. In at least one embodiment, ability to access GPU memory 1920 without cache coherency overheads may be critical to execution time of an offloaded computation. In at least one embodiment, cache coherency overhead, for example, in cases with substantial streaming write memory traffic, may substantially reduce effective write bandwidth of a graphics processor 1910. In at least one embodiment, operand construction efficiency, result access efficiency, and GPU calculation efficiency may play a role in determining GPU offload effectiveness.In at least one embodiment, selection of GPU bias and host processor bias is controlled by a bias tracker data structure. In at least one embodiment, for example, a bias table may be used, which may be a page granular structure (e.g., controlled at granularity of a memory page) that includes 1 or 2 bits per GPU-connected memory page. In at least one embodiment, a bias table may be implemented in a stolen memory area of one or more GPU memories 1920, with or without bias cache in a GPU 1910 (e.g., to cache frequently / recently used entries of a bias table). Alternatively, in at least one embodiment, an entire bias table may be maintained in a GPU.In at least one embodiment, a bias table entry associated with each access to a memory 1920 connected to GPU is accessed prior to actual access to a GPU memory, causing following operations. In at least one embodiment, local requests from a GPU 1910 that find their page in GPU-biased are forwarded directly to a corresponding GPU memory 1920. In at least one embodiment, local requests from a GPU that find their page in host bias are forwarded to processor 1905 (e.g., via a high-speed link as described herein). In at least one embodiment, requests from processor 1905 that find a requested page in host processor bias concludes a request such as a normal memory read. Alternatively, requests directed to a GPU-biased page may be forwarded to a GPU 1910. In at least one embodiment, a GPU may then forward a page to a host processor bias if it is not currently using page. In at least one embodiment, a bias state of a page may be changed by either a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited number of cases, a purely hardware-based mechanism.In at least one embodiment, a mechanism for changing bias state uses an API call (e.g., OpenCL) that in turn calls device driver of a graphics processor, which in turn sends a message to a graphics processor (or queues a command descriptor) to instruct it to change bias state and perform a cache flushing operation in a host at some transitions. In at least one embodiment, a cache flushing operation is used for a transition from host processor 1905 bias to GPU bias, but not for an opposite transition.In at least one embodiment, cache coherency is maintained by temporarily failing to cache GPU-biased pages from host processor 1905. In at least one embodiment, to access these pages, processor 1905 may request access from GPU 1910, which may or may not immediately grant access. Thus, in at least one embodiment, to reduce communication between processor 1905 and GPU 1910, it is advantageous to ensure that GPU-biased pages are those required by a GPU but not host processor 1905 and vice versa.Hardware structure(s) 1115 are used to perform one or more embodiments. Details of a hardware structure (or multiple hardware structures) 1115 may be provided herein in connection with FIGS. 11A and / or 11B.FIG. 20 illustrates example integrated circuits and associated graphics processors that may be fabricated using one or more IP cores according to various embodiments described herein. In addition to the embodiments shown, other logic and circuitry may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores.FIG. 20 is a block diagram illustrating an example integrated circuit 2000 that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, integrated circuit 2000 includes one or more application processor(s) 2005 (e.g., CPUs), at least one graphics processor 2010, and may additionally include an image processor 2015 and / or a graphics processor 2020, wherein each of these processors may be a modular IP core. In at least one embodiment, integrated circuit 2000 includes peripheral or bus logic including a USB controller 2025, a UART controller 2030, an SPI / SDIO controller 2035, and an I22S / I22C controller 2040. In at least one embodiment, integrated circuit 2000 may include a display device 2045 coupled to one or more of the following interfaces: a high-definition multimedia interface (HDMI) controller 2050 and a mobile industry processor interface (MIPI) 2055. In at least one embodiment, memory may be provided by a flash memory subsystem 2060 that includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 2065 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine 2070.Logic 1115 is used to perform inferencing and / or training operations in connection with one or more embodiments. Details of logic 1115 are described herein in connection with FIGS. 11A and / or 11B. In at least one embodiment, logic 1115 in integrated circuit 2000 may be used for inferencing or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.In at least one embodiment, FIGS. 1-20 are to generate, using one or more neural networks, one or more enhanced speech signals from inferior audio data based at least in part on spectral and waveform features of inferior audio data and one or more features derived from reference audio data comprising one or more superior speech signals.FIGS. 21A-21B show example integrated circuits and associated graphics processors that may be fabricated using one or more IP cores according to various embodiments described herein. In addition to the embodiments shown, other logic and circuitry may also be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores.FIGS. 21A-21B are block diagrams illustrating example graphics processors for use in a SoC, in accordance with embodiments described herein. FIG. 21A illustrates an example graphics processor 2110 of an integrated circuit for a system-on-a-chip that may be fabricated using one or more IP cores, in accordance with at least one embodiment. FIG. 21B illustrates another example graphics processor 2140 of an integrated circuit for a system-on-a-chip system that may be fabricated with one or more IP cores, according to at least one embodiment. In at least one embodiment, graphics processor 2110 of FIG. 21A is a low power graphics processor core. In at least one embodiment, graphics processor 2140 of FIG. 21B is a higher power graphics processor core. In at least one embodiment, each of graphics processors 2110, 2140, may be a variant of graphics processor 2010 of FIG. 20.In at least one embodiment, graphics processor 2110 includes a vertex processor 2105 and one or more fragment processor(s) 2115A- 2115N (e.g., 2115A, 2115B, 2115C, 2115D, through 2115N- 1 and 2115N). In at least one embodiment, graphics processor 2110 may execute different shader programs via separate logic such that vertex processor 2105 is optimized for executing operations for vertex shader programs, while one or more fragment processor(s) 2115A- 2115N execute fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, vertex processor 2105 performs a vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, fragment processor(s) 2115A- 2115N use primitive and vertex data generated by vertex processor 2105 to generate a frame buffer that is displayed on a display device. In at least one embodiment, fragment processor(s) 2115A- 2115N is / are optimized for executing fragment shader programs as provided in an OpenGL API that can be used to perform operations similar to a pixel shader program as provided in a Direct 3D API.In at least one embodiment, graphics processor 2110 additionally includes one or more memory management units (MMUs) 2120A- 2120B, cache(s) 2125A- 2125B, and circuit interconnect(s) 2130A- 2130B. In at least one embodiment, one or more MMU(s) 2120A- 2120B provide for virtual to physical address mapping for graphics processor 2110, including vertex processor 2105 and / or fragment processor(s) 2115A- 2115N, which may / may refer to vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in one or more cache(s) 2125A- 2125B. In at least one embodiment, one or more MMU(s) 2120A- 2120B may be synchronized with other MMUs within a system, including one or more MMUs associated with one or more application processor(s) 2005, image processors 2015, and / or video processors 2020 of FIG. 20, such that each processor 2005- 2020 may participate in a shared or unified virtual storage system. In at least one embodiment, one or more circuit connection(s) 2130A- 2130B enable graphics processor 2110 to interface to other IP cores within SoC, either via an internal bus of SoC or via a direct connection.In at least one embodiment, graphics processor 2140 includes one or more shader core(s) 2155A- 2155N (e.g., 2155A, 2155B, 2155C, 2155D, 2155E, 2155F, through 2155N- 1, and 2155N) as shown in FIG. 21B, which provides a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, number of shader cores may vary. In at least one embodiment, graphics processor 2140 includes an inter-core task manager 2145 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 2155A- 2155N and a tiling unit 2158 to accelerate tiling operations for tile-based rendering in which rendering operations for a scene are divided into image space, for example, to exploit local spatial coherence within a scene or to optimize utilization of internal caches.Logic 1115 is used to perform inferencing and / or training operations in connection with one or more embodiments. Details of logic 1115 are described herein in connection with FIGS. 11A and / or 11B. In at least one embodiment, logic 1115 in graphics processor 2110 and / or 2140 may be used for inferencing or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.In at least one embodiment, FIGS. 1-21B are to generate, using one or more neural networks, one or more enhanced speech signals from low quality audio data based at least in part on spectral and waveform features of low quality audio data and one or more features derived from reference audio data comprising one or more high quality speech signals.FIGS. 22A-22B show additional example graphics processor logic according to embodiments described herein. In at least one embodiment, components illustrated and described in FIGS. 22A-22B are integrated into a single system, such as a graphics processing unit (GPU), a SoC, or other type of processor. FIG. 22A illustrates a graphics core 2200, which in at least one embodiment may include graphics processor 2010 of FIG. 20, and in at least one embodiment may be a unified shader core 2155A- 2155N as in FIG. 21B. FIG. 22B illustrates a general purpose highly parallel graphics processing unit ("GPGPU", which may also be referred to as a "graphics processing unit") 2230 suitable for use on a multi-chip module in at least one embodiment. In at least one embodiment, graphics processing unit 2230 is a GPGPU that includes a graphics processor. In at least one embodiment, integrated circuit 2000 includes graphics core 2200, for example to form an integrated circuit and / or a SoC, where such an integrated circuit and / or a SoC perform operations described herein.In at least one embodiment, graphics core 2200 includes a shared instruction cache 2202, a texture unit 2218, and a cache / shared memory 2220 (e.g., L1, L2, L3, last level cache, or other caches) that are shared with execution resources within graphics core 2200. In at least one embodiment, graphics core 2200 may include multiple slices 2201A- 2201N or a partition for each core, and a graphics processor may include multiple instances of graphics core 2200. In at least one embodiment, each slice 2201A- 2201N refers to graphics core 2200. In at least one embodiment, slices 2201A- 2201N comprise sub-slices that are part of a slice 2201A- 2201N. In at least one embodiment, slices 2201A- 2201N are independent of other slices or dependent on other slices. In at least one embodiment, slices 2201A- 2201N may include support logic including a local instruction cache 2204A- 2204N, a thread scheduler (sequencer) 2206A- 2206N, a thread dispatcher 2208A- 2208N, and a register set 2210A- 2210N. In at least one embodiment, slices 2201A- 2201N may include a set of additional functional units (AFUs 2212A- 2212N), floating point units (FPUs 2214A- 2214N), integer arithmetic logic units (ALUs 2216A- 2216N), address calculation units (ACUs 2213A- 2213N), double precision floating point units (DPFPUs 2215A- 2215N), and matrix processing units (MPUs 2217A- 2217N). In at least one embodiment, MPUs 2217A- 2217N are referred to as matrix engines.In at least one embodiment, each slice 2201A- 2201N includes one or more engines for floating point and integer vector operations and one or more engines for accelerating convolution and matrix operations at workloads in areas KI, machine learning, or large data sets. In at least one embodiment, one or more slices 2201A- 2201N include one or more vector engines for computing a vector (e.g., for computing mathematical operations for vectors). In at least one embodiment, a vector engine may compute a vector operation in 16-bit floating point (also referred to as "FP16"), 32-bit floating point (also referred to as "FP32"), or 64-bit floating point (also referred to as "FP64"). In at least one embodiment, one or more slices 2201A- 2201N include 16 vector engines paired with 16 matrix math units to compute matrix / tensor operations, where vector engines and math units are accessible via matrix extensions. In at least one embodiment, a slice includes a particular portion of processing resources of a processing unit, for example 16 cores and a ray tracing unit or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units for a processor. In at least one embodiment, graphics core 2200 includes one or more matrix engines for computing matrix operations, such as in computing tensor operations.In at least one embodiment, one or more slices 2201A- 2201N includes one or more ray tracing units for computing ray tracing operations (e.g., 16 ray tracing units per slice 2201A- 2201N). In at least one embodiment, a ray tracing unit computes ray traversal, triangle intersection, bounding box insect, or other ray tracing operations.In at least one embodiment, one or more slices 2201A- 2201N includes a media slice that encodes, decodes, and / or transcodes, scales and / or formats data, and / or performs video quality operations on video data.In at least one embodiment, one or more slices 2201A- 2201N are connected to an L2 cache and memory structure, interconnect ports, HBM stacks (e.g., HBM2e, HDM3), and a media engine. In at least one embodiment, one or more slices 2201A- 2201N include multiple cores (e.g., 16 cores) and multiple ray tracing units (e.g., 16) coupled to each core. In at least one embodiment, one or more slices 2201A- 2201N include one or more L1 caches. In at least one embodiment, one or more slices 2201A- 2201N comprise one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLMs) for storing data, e.g., corresponding instructions; one or more samplers for sampling data; one or more ray tracing units for performing ray tracing operations; one or more geometries for performing operations in geometry pipelines and / or for applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image in a vector graphics format (e.g., shape) and converting it into a raster image (e.g., a series of pixels, dots, or lines that together result in an image being represented by shapes when displayed); one or more hierarchical depth buffers (hiz) for buffering data; and / or one or more pixel backends. In at least one embodiment, a slice 2201A- 2201N includes a structure of memory, for example, an L2 cache.In at least one embodiment, FPUs 2214A- 2214N may perform single precision (32 bits) and half precision (16 bits) floating point operations, while DPFPUs 2215A- 2215N may perform double precision (64 bits) floating point operations. In at least one embodiment, ALUs 2216A- 2216N may perform variable precision integer operations at 8-bit, 16-bit, and 32-bit precision and be configured for mixed precision operations. In at least one embodiment, MPUs 2217A- 2217N may also be configured for mixed precision matrix operations that include semi-accurate floating point and 8-bit integer operations. In at least one embodiment, MPUs 2217- 2217N may perform a plurality of matrix operations to speed up machine learning application frameworks, including support for speeded up general matrix-matrix multiplication (GEMM). In at least one embodiment, AFUs 2212A- 2212N may perform additional logical operations not supported by floating point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).Logic 1115 is used to perform inferencing and / or training operations in connection with one or more embodiments. Details of logic 1115 are described herein in connection with FIGS. 11A and / or 11B. In at least one embodiment, logic 1115 in graphics core 2200 may be used for inferencing or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.In at least one embodiment, graphics core 2200 includes an interconnect and link fabric sublayer coupled to a switch and a GPU GPU bridge that enables multiple graphics processors 2200 (e.g., 8) to be coupled together without adhesive, with load / store units (LSUs), communication units, and synchronization semantics via multiple graphics processors 2200. In at least one embodiment, interconnects include standardized interconnects (e.g., PCIe) or a combination thereof.In at least one embodiment, graphics core 2200 includes multiple tiles. In at least one embodiment, a tile is a single die or one or more dies, where individual dies may be connected to an interconnect (e.g., embedded multi-die interconnect bridge (EMIB)). In at least one embodiment, graphics core 2200 includes a compute tile, a memory tile (e.g., when a memory tile of different tiles or different chipsets can be accessed exclusively, such as a rambo tile), a substrate tile, a base tile, an HMB tile, a link tile, and an EMIB tile, where all tiles are packaged together in graphics core 2200 as part of a GPU. In at least one embodiment, graphics core 2200 may include multiple tiles in a single package (also referred to as a "multi-tile package"). In at least one embodiment, a compute tile may include 8 graphics cores 2200, an L1 cache, and a base tile, a host interface including PCIe 5.0, HBM2e, MDFI, and EMIB, a link tile including 8 links, 8 ports, with an embedded switch. In at least one embodiment, tiles are connected to face-to-face (F2F) chip-on-chip bonding via fine graded 36 micron microbumps (e.g., copper pillars). In at least one embodiment, graphics core 2200 includes a structure that includes memory and that is accessible by multiple tiles. In at least one embodiment, graphics core 2200 stores or loads its own hardware contexts in memory, where a hardware context is a set of data that is loaded from registers before a process continues, and where a hardware context may indicate a state of hardware (e.g., a GPU's state).In at least one embodiment, graphics core 2200 includes a serializing / deserialization circuit (SERDES) that converts a serial data stream into a parallel data stream or converts a parallel data stream into a serial data stream.In at least one embodiment, graphics core 2200 includes a high speed coherent structure (from GPU to GPU), load / store units, mass data transfer, and sync semantics, as well as GPUs connected via an embedding switch, wherein a GPU-GPU bridge is controlled by a controller.In at least one embodiment, graphics core 2200 executes an API, where API abstracts hardware of graphics core 2200 and accesses libraries of instructions to perform mathematical operations (e.g., math kernel library), deep neural network operations (e.g., deep neural network library), vector operations, collective communication, thread building blocks, video processing, data analytics library, and / or ray tracing operations.In at least one embodiment, FIGS. 1-22A are to generate, using one or more neural networks, one or more enhanced speech signals from low quality audio data based at least in part on spectral and waveform features of low quality audio data and one or more features derived from reference audio data comprising one or more high quality speech signals.FIG. 22B illustrates the GPGPU 2230, which in at least one embodiment may be configured such that highly parallel computational operations may be performed by an array of graphics processing units. In at least one embodiment, GPGPU 2230 may be directly connected to other instances of GPGPU 2230 to form a multi-GPU cluster and improve training speed for deep neural networks. In at least one embodiment, GPGPU 2230 includes a host interface 2232 to enable connection to a host processor. In at least one embodiment, host interface 2232 is a PCI Express interface. In at least one embodiment, host interface 2232 may be a proprietary communication interface or communication fabric. In at least one embodiment, GPGPU 2230 receives instructions from a host processor and uses a global scheduler 2234 (which may be referred to as a thread sequencer and / or asynchronous compute engine) to distribute execution threads associated with these instructions to a series of compute clusters 2236A- 2236H. In at least one embodiment, compute clusters 2236A- 2236H share a cache memory 2238. In at least one embodiment, cache 2238 may serve as a higher level cache for cache memories in compute clusters 2236A- 2236H. In at least one embodiment, compute clusters 2236A- 2236H comprise a slice or are referred to as "slices.". In at least one embodiment, GPGPU 2230 is part of a SoC, for example, part of integrated circuit 2000 (FIG. 20 ).In at least one embodiment, GPGPU 2230 includes memory 2244A- 2244B coupled to compute clusters 2236A- 2236H via a set of memory controllers 2242A- 2242B (e.g., one or more controllers for HBM2e). In at least one embodiment, memory 2244A- 2244B may include various types of memory devices, including dynamic random access memory (DRAM), or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics dual data rate memory (GDDR).In at least one embodiment, compute clusters 2236A- 2236H each include a set of graphics cores, such as graphics core 2200 of FIG. 22A, which may include multiple types of integer and floating point logic units that may perform computational operations with a number of precisions that are also suitable for machine learning computations. For example, in at least one embodiment, at least a subset of floating point units in each of compute clusters 2236A- 2236H may be configured to perform 16-bit or 32-bit floating point operations, while a different subset of floating point units may be configured to perform 64-bit floating point operations.In at least one embodiment, multiple instances of GPGPU 2230 may be configured to operate as compute clusters. In at least one embodiment, communication used by compute clusters 2236A- 2236H for synchronization and data exchange varies among embodiments. In at least one embodiment, multiple instances of GPGPU 2230 communicate via host interface 2232. In at least one embodiment, GPGPU 2230 includes an I / O hub 2239 that couples GPGPU 2230 to a GPU link 2240 that enables direct connection to other instances of GPGPU 2230. In at least one embodiment, GPU link 2240 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 2230. In at least one embodiment, GPU link 2240 is coupled to a high-speed link to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 2230 reside in separate computing systems and communicate over a network interface accessible via host interface 2232. In at least one embodiment, GPU link 2240 may be configured to enable connection to a host processor in addition to or alternatively to host interface 2232.In at least one embodiment, GPGPU 2230 may be configured to train neural networks. In at least one embodiment, GPGPU 2230 may be used within an inferencing platform. In at least one embodiment where GPGPU 2230 is used for inferencing, GPGPU 2230 may include fewer compute clusters 2236A- 2236H than when GPGPU 2230 is used for neural network training. In at least one embodiment, memory technology associated with memory 2244A- 2244B may be different between inferencing and training configurations, where training configurations are assigned higher bandwidth memory technologies. In at least one embodiment, an inferencing configuration of GPGPU 2230 may support inferencing specific instructions. For example, in at least one embodiment, an inferencing configuration may support one or more 8-bit integer dot product instructions that may be used in inferencing operations for deployed neural networks.Logic 1115 is used to perform inferencing and / or training operations in connection with one or more embodiments. Details of logic 1115 are described herein in connection with FIGS. 11A and / or 11B. In at least one embodiment, logic 1115 in GPGPU 2230 may be used for inferencing or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.In at least one embodiment, FIGS. 1-22B are to generate one or more enhanced speech signals from inferior audio data using one or more neural networks based at least in part on spectral and waveform features of inferior audio data and one or more features derived from reference audio data comprising one or more superior speech signals.FIG. 23 is a block diagram illustrating a computer system 2300, according to at least one embodiment. In at least one embodiment, computer system 2300 includes a processing subsystem 2301 having one or more processor(s) 2302 and system memory 2304, which communicate via an interconnect, which may include a memory hub 2305. In at least one embodiment, memory hub 2305 may be a separate component within a chipset component or integrated into one or more processor(s) 2302. In at least one embodiment, storage hub 2305 is coupled to an I / O subsystem 2311 via communication link 2306. In at least one embodiment, I / O subsystem 2311 includes an I / O hub 2307 that may allow computer system 2300 to receive input from one or more input device(s) 2308. In at least one embodiment, I / O hub 2307 may enable a display controller, which may be included in one or more processor(s) 2302, to provide output to one or more display device(s) 2310A. In at least one embodiment, one or more display device(s) 2310A coupled to I / O hub 2307 may include a local, internal, or embedded display device.In at least one embodiment, processing subsystem 2301 includes one or more parallel processor(s) 2312 that is / are connected to memory hub 2305 via bus or other communication link 2313. In at least one embodiment, communication link 2313 may use any number of standard-based communication link technologies or protocols, such as, but not limited to, PCI Express, or a proprietary communication interface or communication fabric. In at least one embodiment, one or more parallel processor(s) 2312 form a compute-intensive parallel or vector processing system that may include a large number of processing cores and / or processing clusters, such as a many integrated core (MIC) processor. In at least one embodiment, some or all of parallel processors 2312 form a graphics processing subsystem that can output pixels to one or more display device(s) 2310A coupled via I / O hub 2307. In at least one embodiment, parallel(s) processor(s) 2312 may also include a display controller and display interface (not shown) to enable direct connection to one or more display device(s) 2310B. In at least one embodiment, parallel processor(s) 2312 include one or more cores, such as graphics cores 2200 discussed herein.In at least one embodiment, a system storage unit 2314 may be coupled to I / O hub 2307 to provide a storage mechanism for computer system 2300. In at least one embodiment, an I / O switch 2316 may be used to provide an interface that enables connections between I / O hub 2307 and other components, such as a network adapter 2318 and / or a wireless network adapter 2319 that may be integrated into platform, and various other devices that may be added via one or more add-in device(s) 2320. In at least one embodiment, network adapter 2318 may be an Ethernet adapter or other wired network adapter. In at least one embodiment, wireless network adapter 2319 may include one or more of Wi-Fi, Bluetooth, Near Field Communication (NFC), or other network devices including one or more wireless radios.In at least one embodiment, computer system 2300 may include other components not explicitly shown, including USB or other connector connections, optical storage devices, video capture devices, and the like, which may also be connected to I / O hub 2307. In at least one embodiment, communication paths interconnecting various components in FIG. 23 may be implemented using any suitable protocols, such as peripheral component interconnect (PCI)-based protocols (e.g., PCI express), or other bus or point-to-point communication links and / or protocols, such as high speed NV-link links or interconnect protocols.In at least one embodiment, parallel processor(s) 2312 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and form a graphics processing unit (GPU), for example, parallel processor(s) 2312 includes graphics core 2200. In at least one embodiment, parallel(s) processor(s) 2312 includes(s) general processing optimized circuitry. In at least one embodiment, components of computer system 2300 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, parallel processor(s) 2312, memory hub 2305, processor(s) 2302, and I / O hub 2307 may be integrated into an integrated circuit for a system-on-a-chip (SoC) system. In at least one embodiment, components of computer system 2300 may be integrated into a single package to form a system in package (SIP) configuration. In at least one embodiment, at least a portion of components of computer system 2300 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules to form a modular computer system.Logic 1115 is used to perform inferencing and / or training operations in connection with one or more embodiments. Details of logic 1115 are described herein in connection with FIGS. 11A and / or 11B. In at least one embodiment, logic 1115 in computer system 2300 may be used for inferencing or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.In at least one embodiment, FIGS. 1-23 are to generate, using one or more neural networks, one or more enhanced speech signals from low quality audio data based at least in part on spectral and waveform features of low quality audio data and one or more features derived from reference audio data comprising one or more high quality speech signals.PROCESSORSFIG. 24A illustrates a parallel processor 2400, in accordance with at least one embodiment. In at least one embodiment, various components of parallel processor 2400 may be implemented using one or more integrated circuits, such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGAs). In at least one embodiment, parallel processor 2400 shown is a variant of one or more parallel processors 2312 shown in FIG. 23, according to an example embodiment. In at least one embodiment, a parallel processor 2400 comprises one or more graphics cores 2200.In at least one embodiment, parallel processor 2400 comprises a parallel processing unit 2402. In at least one embodiment, parallel processing unit 2402 includes an I / O unit 2404 that enables communication with other devices, including other instances of parallel processing unit 2402. In at least one embodiment, I / O unit 2404 may be directly connected to other devices. In at least one embodiment, I / O unit 2404 is connected to other devices via a hub or switch interface, such as a storage hub 2405. In at least one embodiment, connections between storage hub 2405 and I / O unit 2404 form a communication link 2413. In at least one embodiment, I / O unit 2404 is coupled to a host interface 2406 and a memory crossbar 2416, where host interface 2406 receives commands to perform processing operations and memory crossbar 2416 receives commands to perform memory operations.In at least one embodiment, when host interface 2406 receives a command buffer via I / O unit 2404, host interface 2406 may forward operational operations to execute these commands to front end 2408. In at least one embodiment, front end 2408 is coupled to a scheduler 2410 (which may also be referred to as a sequencer) configured to distribute instructions or other work items to a processing cluster array 2412. In at least one embodiment, scheduler 2410 ensures that processing array 2412 is properly configured and is in a valid state before tasks are distributed to a cluster of processing array 2412. In at least one embodiment, scheduler 2410 is implemented via firmware logic executing on a microcontroller. In at least one embodiment, microcontroller-implemented scheduler 2410 is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, enabling fast preemption and context switching of threads executing on processing array 2412. In at least one embodiment, host software may detect workloads for planning on processing cluster array 2412 via one of multiple graphics processing paths. In at least one embodiment, workloads may then be automatically distributed across processing array cluster 2412 by scheduler 2410 logic within a microcontroller including scheduler 2410.In at least one embodiment, processing array 2412 may include up to "N" processing clusters (e.g., cluster 2414A, cluster 2414B, up to cluster 2414N), where "N" represents a positive integer (which may be a different integer "N" than used in other figures). In at least one embodiment, each cluster 2414A- 2414N of processing array 2412 may execute a large number of simultaneous threads. In at least one embodiment, scheduler 2410 may assign work to clusters 2414A- 2414N of processing array 2412 by using various planning and / or work distribution algorithms that may vary depending on workload incurred for each type of program or calculation. In at least one embodiment, scheduling may be performed dynamically by scheduler 2410, or partially supported by compiler logic during compilation of program logic configured for execution by processing cluster array 2412. In at least one embodiment, different clusters 2414A- 2414N of processing array 2412 may be allocated for processing different program types or for performing different computational types.In at least one embodiment, processing cluster array 2412 may be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 2412 is configured to perform parallel general purpose computational operations. In at least one embodiment, processing cluster array 2412 may include, for example, logic for performing processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.In at least one embodiment, processing cluster array 2412 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array 2412 may include additional logic to assist in performing such graphics processing operations, including, but not limited to, texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing cluster array 2412 may be configured to execute graphics processing-related shader programs, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit 2402 may transfer data from system memory via I / O unit 2404 for processing. In at least one embodiment, during processing, transmitted data may be stored in on-chip memory (e.g., parallel processor memory 2422) and then written back to system memory.In at least one embodiment, when graphics processing unit 2402 is used to perform graphics processing, scheduler 2410 may be configured to split a workload into approximately equal sized tasks to allow better distribution of graphics processing operations among multiple clusters 2414A- 2414N of processing array 2412. In at least one embodiment, portions of processing cluster array 2412 may be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 2414A- 2414N may be stored in buffers to enable transmission of intermediate data between clusters 2414A- 2414N for further processing.In at least one embodiment, processing cluster array 2412 may receive processing tasks to be executed via scheduler 2410 receiving instructions to define processing tasks from front end 2408. In at least one embodiment, processing tasks may include indices of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands that define how to process data (e.g., which program is to be executed). In at least one embodiment, scheduler 2410 may be configured to fetch indexes corresponding to tasks or receive indexes from front end 2408. In at least one embodiment, front end 2408 may be configured to ensure that processing cluster array 2412 is placed in a valid state before a workload specified by incoming command buffers (e.g., stack buffers, push buffers, etc.) is introduced.In at least one embodiment, each of one or more instances of parallel processing unit 2402 may be coupled to parallel processor memory 2422. In at least one embodiment, parallel processor memory 2422 may be accessed via memory crossbar 2416, which may receive memory requests from processing cluster array 2412 as well as from I / O unit 2404. In at least one embodiment, memory crossbar 2416 may access parallel processor memory 2422 via a memory interface 2418. In at least one embodiment, memory interface 2418 may include multiple partition units (e.g., partition unit 2420A, partition unit 2420B, through partition unit 2420N) that may each be coupled to a portion (e.g., memory unit) of parallel processor memory 2422. In at least one embodiment, a number of partition units 2420A- 2420N are configured to be equal to a number of memory units such that a first partition unit 2420A includes a corresponding first memory unit 2424A, a second partition unit 2420B includes a corresponding memory unit 2424B, and an Nth partition unit 2420N includes a corresponding Nth memory unit 2424N. In at least one embodiment, a number of partition units 2420A- 2420N may not be equal to a number of memory units.In at least one embodiment, memory units 2424A- 2424N may comprise various types of memory devices, including dynamic random access memory (DRAM), or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics dual data rate memory (GDDR). In at least one embodiment, memory units 2424A- 2424N may also include 3D stack memories, including, but not limited to, high width memories (HBM), HBM2e, or HDM3. In at least one embodiment, rendering targets, such as image buffers or texture maps, may be stored across storage units 2424A- 2424N, allowing partition units 2420A- 2420N to write portions of each rendering target in parallel to efficiently utilize available bandwidth of parallel processor memory 2422. In at least one embodiment, a local instance of parallel processor memory 2422 may be excluded in favor of a uniform memory design that utilizes system memory in conjunction with local cache memory.In at least one embodiment, each of clusters 2414A- 2414N of processing array 2412 may process data written to each of storage units 2424A- 2424N within parallel processor memory 2422. In at least one embodiment, memory crossbar 2416 may be configured to transmit an output of each cluster 2414A- 2414N to any partition unit 2420A- 2420N or to another cluster 2414A- 2414N that can perform additional processing operations on an output. In at least one embodiment, each cluster 2414A- 2414N may communicate with memory interface 2418 via memory crossbar 2416 to read from or write to various external devices. In at least one embodiment, memory crossbar 2416 includes a connection to memory interface 2418 to communicate with I / O unit 2404, as well as a connection to a local instance of parallel processor memory 2422 that allows processing units in different processing clusters 2414A- 2414N to communicate with system memory or other memory that does not locally belong to parallel processing unit 2402. In at least one embodiment, memory crossbar 2416 may use virtual channels to separate traffic streams between clusters 2414A- 2414N and partition units 2420A- 2420N.In at least one embodiment, multiple instances of parallel processing unit 2402 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of parallel processing unit 2402 may be configured to cooperate with each other even if different instances include a different number of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 2402 may include floating point units with higher precision compared to other instances. In at least one embodiment, systems including one or more instances of parallel processing unit 2402 or parallel processor 2400 may be implemented in a variety of configurations and form factors including, but not limited to, desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedding systems.FIG. 24B is a block diagram of a partition unit 2420 according to at least one embodiment. In at least one embodiment, partition unit 2420 is an example of one of partition units 2420A- 2420N of FIG. 24A. In at least one embodiment, partition unit 2420 includes an L2 cache 2421, a frame buffer interface 2425, and a ROP 2426 (raster operations unit). In at least one embodiment, L2 cache 2421 is a read / write cache configured to perform load and store operations received from memory crossbar 2416 and ROP 2426. In at least one embodiment, read errors and urgent writeback requests are issued from L2 cache 2421 to frame buffer interface 2425 for processing. In at least one embodiment, updates may also be sent to a frame buffer via frame buffer interface 2425 for processing. In at least one embodiment, frame buffer interface 2425 interfaces with one of memory units in parallel processor memory, such as memory units 2424A- 2424N of FIG. 24A (e.g., within parallel processor memory 2422).In at least one embodiment, ROP 2426 is a processing unit that performs raster operations such as templates, Z-test, merging, etc. In at least one embodiment, ROP 2426 then outputs processed graphics data that is stored in graphics memory. In at least one embodiment, ROP 2426 includes compression logic for compressing depth or color data written to memory and decompressing depth or color data read from memory. In at least one embodiment, compression logic may be lossless compression logic that uses one or more of multiple compression algorithms. In at least one embodiment, type of compression performed by ROP 2426 may vary based on statistical properties of data to be compressed. For example, in at least one embodiment, delta color compression is performed on depth and color data on a per tile basis.In at least one embodiment, ROP 2426 is included in each processing cluster (e.g., clusters 2414A- 2414N of FIG. 24A ) rather than in partition unit 2420. In at least one embodiment, read and write requests for pixel data are transmitted over memory crossbar 2416 instead of pixel fragment data. In at least one embodiment, processed graphics data may be forwarded on a display device, such as one or more display device(s) 2310 of FIG. 23, for further processing by processor(s) 2302, or for further processing by one of processing units within parallel processor 2400 of FIG. 24A.FIG. 24C is a block diagram of a processing cluster 2414 within a parallel processing unit, according to at least one embodiment. In at least one embodiment, a processing cluster is an instance of one of processing clusters 2414A- 2414N of FIG. 24A. In at least one embodiment, processing cluster 2414 may be configured to execute multiple threads in parallel, where "thread" refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single instruction (multiple data) issue techniques are used to support parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) techniques are used to support parallel execution of a large number of generally synchronized threads using a common instruction unit configured to issue instructions to a set of processing engines in each of processing clusters.In at least one embodiment, operation of processing cluster 2414 may be controlled via a pipeline manager 2432, which distributes processing tasks to parallel SIMT processors. In at least one embodiment, pipeline manager 2432 receives instructions from scheduler 2410 of FIG. 24A and manages execution of these instructions via graphics multiprocessor 2434 and / or texture unit 2436. In at least one embodiment, graphics multiprocessor 2434 is an example instance of a SIMT parallel processor. However, in at least one embodiment, processing cluster 2414 may include various types of SIMT parallel processors with different architectures. In at least one embodiment, one or more instances of graphics multiprocessor 2434 may include in a processing cluster 2414. In at least one embodiment, graphics multiprocessor 2434 may process data and a data crossbar 2440 may be used to distribute processed data to one of several possible destinations, including other shader units. In at least one embodiment, pipeline manager 2432 may facilitate distribution of processed data by indicating destinations for processed data to be distributed across data crossbar 2440.In at least one embodiment, each graphics multiprocessor 2434 within processing cluster 2414 may include an identical set of functional execution logic (e.g., arithmetic logic units, load / store units, etc.). In at least one embodiment, functional execution logic may be configured in a pipeline in which new instructions may be issued before previous instructions are completed. In at least one embodiment, functional execution logic supports a variety of operations, including integer and floating point arithmetic, comparison operations, boolean operations, bit shifting, and computation of various algebraic functions. In at least one embodiment, same hardware with functional units may be used to perform different operations, and there may be any combination of functional units.In at least one embodiment, instructions transferred to processing cluster 2414 form a thread. In at least one embodiment, a set of threads executing over a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a shared program on different input data. In at least one embodiment, each thread within a thread group may be assigned to a different engine within a graphics multiprocessor 2434. In at least one embodiment, a thread group may include fewer threads than a number of processing engines within graphics multiprocessor 2434. In at least one embodiment, if a thread group comprises fewer threads than a number of processing engines, one or more of processing engines may be idle during cycles in which that thread group is processed. In at least one embodiment, a thread group may also include more threads than a number of processing engines within graphics multiprocessor 2434. In at least one embodiment, if a thread group includes more threads than number of processing engines in graphics multiprocessor 2434 processing may occur in successive clock cycles. In at least one embodiment, multiple thread groups may execute simultaneously on a graphics multiprocessor 2434.In at least one embodiment, graphics multiprocessor 2434 includes an internal cache memory for performing load and store operations. In at least one embodiment, graphics multiprocessor 2434 may omit an internal cache and use a cache memory (e.g., L1 cache 2448) within processing cluster 2414. In at least one embodiment, each graphics multiprocessor 2434 also has access to L2 caches within partition units (e.g., partition units 2420A- 2420N of FIG. 24A ) that are shared by all processing clusters 2414 and may be used for data transfer between threads. In at least one embodiment, graphics multiprocessor 2434 may also access off-chip global memory, which may include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 2402 may be used as global memory. In at least one embodiment, processing cluster 2414 includes multiple instances of graphics multiprocessor 2434 and may share common instructions and data that may be stored in L1 cache 2448.In at least one embodiment, each processing cluster 2414 may include a memory management unit (MMU 2445) configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 2445 may be located in memory interface 2418 of FIG. 24A. In at least one embodiment, MMU 2445 includes a set of page table entries (PTEs) used to map a virtual address to a physical address of a tile, and optionally a cache line index. In at least one embodiment, MMU 2445 may include address translation lookaside buffers (TLBs) or caches, which may be located in graphics multiprocessor 2434 or L1 2448 cache or processing cluster 2414. In at least one embodiment, a physical address is processed to locally distribute access to surface data and enable efficient interleaving of requests between partition units. In at least one embodiment, a cache line index may be used to determine whether a request for a cache line is a hit or miss.In at least one embodiment, a processing cluster 2414 may be configured such that each graphics multiprocessor 2434 is coupled to a texture unit 2436 to perform texture mapping operations, such as determining texture pattern positions, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor 2434, and retrieved from an L2 cache, local parallel processor memory, or system memory as needed. In at least one embodiment, each graphics multiprocessor 2434 outputs processed tasks to data crossbar 2440 to provide processed task to another processing cluster 2414 via memory crossbar 2416 for further processing, or to store processed task in an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, pre-raster operations unit (preROP 2442) is configured to receive data from graphics multiprocessor 2434 and to pass data to ROP units that may be arranged with partition units as described herein (e.g., partition units 2420A- 2420N of FIG. 24A ). In at least one embodiment, preROP unit 2442 may perform optimizations for color blending, organizing pixel color data, and performing address translations.Logic 1115 is used to perform inferencing and / or training operations in connection with one or more embodiments. Details of logic 1115 are described herein in connection with FIGS. 11A and / or 11B. In at least one embodiment, logic 1115 in graphics processing cluster 2414 may be used for inferencing or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.In at least one embodiment, FIGS. 1-24C are intended to generate one or more enhanced speech signals from inferior audio data using one or more neural networks based at least in part on spectral and waveform features of inferior audio data and one or more features derived from reference audio data comprising one or more superior speech signals.FIG. 24D illustrates a graphics multiprocessor 2434 in accordance with at least one embodiment. In at least one embodiment, graphics multiprocessor 2434 is coupled to pipeline manager 2432 of processing cluster 2414. In at least one embodiment, graphics multiprocessor 2434 includes an execution pipeline that includes, but is not limited to, an instruction cache 2452, an instruction unit 2454, an address allocator unit 2456, a register file 2458, one or more graphics processing units (GPGPU cores) 2462, and one or more load / store units 2466, wherein one or more load / store units 2466 may perform load / store operations for load / store instructions according to performance of an operation. In at least one embodiment, GPGPU cores 2462 and load / store units 2466 are coupled to cache memory 2472 and shared memory 2470 via a memory and cache interconnect 2468. In at least one embodiment, GPGPU cores 2462 are part of a SoC, such as part of integrated circuit 2000 in FIG. 20.In at least one embodiment, instruction cache 2452 receives a stream of instructions to be executed from pipeline manager 2432. In at least one embodiment, instructions are cached in instruction cache 2452 and dispatched for execution by an instruction unit 2454. In at least one embodiment, instruction unit 2454 may dispatch instructions in the form of thread groups (e.g., warps, waves, waves), each thread of a thread group being associated with a different execution unit within GPGPU cores 2462. In at least one embodiment, a command may access a local, shared, or global address space by indicating an address within a uniform address space. In at least one embodiment, address mapping unit 2456 may be used to translate addresses in a uniform address space into a unique memory address that load / store units 2466 can access.In at least one embodiment, register file 2458 provides a set of registers for functional units of graphics multiprocessor 2434. In at least one embodiment, register file 2458 provides temporary storage for operands coupled to data paths of functional units (e.g., GPGPU cores 2462, load / store units 2466) of graphics multiprocessor 2434. In at least one embodiment, register file 2458 is partitioned between individual functional units such that each functional unit is associated with a separate portion of register file 2458. In at least one embodiment, register file 2458 is divided among different warps (which may be referred to as wavefronts and / or waves) executed by graphics multiprocessor 2434.In at least one embodiment, GPGPU cores 2462 may each include floating point units (FPUs) and / or integer arithmetic logic units (ALUs) used to execute instructions of graphics multiprocessor 2434. In at least one embodiment, GPGPU cores 2462 may be similar in architecture or different in architecture. In at least one embodiment, a first portion of GPGPU cores 2462 includes a single precision FPU and an integer ALU, while a second portion of GPGPU cores includes a double precision FPU. In at least one embodiment, FPUs may implement IEEE 754-2008 standard floating point arithmetic or enable variable precision floating point arithmetic. In at least one embodiment, graphics multiprocessor 2434 may additionally include one or more fixed function or special function units to perform specific functions such as copying rectangles or merging pixels. In at least one embodiment, one or more of GPGPU cores 2462 may also include fixed function logic or special purpose function logic.In at least one embodiment, GPGPU cores 2462 include SIMD logic capable of applying a single instruction to multiple data sets. In at least one embodiment, GPGPU cores 2462 may physically execute SIMD4, SIMD8, and SIMD4 logical instructions and SIMD1, SIMD4, and SIMD32 logical instructions. In at least one embodiment, SIMD instructions for GPGPU cores may be generated by a shader compiler at compile time or automatically generated when executing programs written and compiled for single program multiple data (SPMD) or SIMT architectures. In at least one embodiment, multiple threads of a program configured for a SIMT execution model may be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads that perform similar or similar operations may be executed in parallel via a single SIMD8 logic unit.In at least one embodiment, memory and cache interconnect 2468 is an interconnect network that connects each functional unit of graphics multiprocessor 2434 to register file 2458 and shared memory 2470. In at least one embodiment, memory and cache interconnect 2468 is a crossbar interconnect that allows load / store unit 2466 to perform load and store operations between shared memory 2470 and register file 2458. In at least one embodiment, register file 2458 may operate at the same frequency as GPGPU cores 2462, such that data transfer between GPGPU cores 2462 and register file 2458 may have very low latency. In at least one embodiment, shared memory 2470 may be used to enable communication between threads executing on functional units within graphics multiprocessor 2434. In at least one embodiment, cache 2472 may be used, for example, as a data cache to cache texture data transferred between functional units and texture unit 2436. In at least one embodiment, shared memory 2470 may also be used as a program-managed cache. In at least one embodiment, threads executing on GPGPU cores 2462 may programmatically store data in shared memory in addition to automatically cached data stored in cache memory 2472.In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to host / processor cores to speed up graphics operations, machine learning operations, pattern analysis operations, and various general GPU functions (GPGPU). In at least one embodiment, a GPU may be communicatively coupled to host processor / processor cores via a bus or other interconnect (e.g., a high speed interconnect such as PCIe or NVLink). In at least one embodiment, a SoC includes a parallel processor or GPGPU as described herein, wherein parallel processor or GPGPU executes on SoC. In at least one embodiment, a GPU may be integrated on a package or chip as cores and communicatively coupled to cores via an internal processor bus / interconnect within a package or chip. In at least one embodiment, regardless of how GPU is attached, processor cores may assign work to that GPU in sequences of instructions / instructions included in a work description. In at least one embodiment, GPU then uses special circuitry / logic to efficiently process these commands / commands.Logic 1115 is used to perform inferencing and / or training operations in connection with one or more embodiments. Details of logic 1115 are described herein in connection with FIGS. 11A and / or 11B. In at least one embodiment, logic 1115 in graphics multiprocessor 2434 may be used for inferencing or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.In at least one embodiment, FIGS. 1-24D are to generate one or more enhanced speech signals from low quality audio data using one or more neural networks based at least in part on spectral and waveform features of low quality audio data and one or more features derived from reference audio data comprising one or more high quality speech signals.FIG. 25 illustrates a multi-GPU computer system 2500, according to at least one embodiment. In at least one embodiment, multi-GPU computer system 2500 may include a processor 2502 coupled to multiple general graphics processing units (GPGPUs) 2506A-D via a host interface switch 2504. In at least one embodiment, host interface switch 2504 is a PCI Express switch device that connects processor 2502 to a PCI Express bus through which processor 2502 can communicate with GPGPUs 2506A-D. In at least one embodiment, GPGPUs 2506A-D may be interconnected via a series of high speed point-to-point GPU-to-GPU connections 2516. In at least one embodiment, GPU-to-GPU links 2516 are connected to each of GPGPUs 2506A-D via a dedicated GPU link. In at least one embodiment, P2P GPU connections 2516 enable direct communication between individual GPGPUs 2506A-D without requiring communication via interface 2504 to which processor 2502 is connected. In at least one embodiment where GPU-to-GPU traffic is routed on P2P GPU links 2516, host interface bus 2504 remains available for system memory access or communication with other instances of multi-GPU computer system 2500, for example, via one or more network devices. While in at least one embodiment GPGPUs 2506A-D are connected to processor 2502 via host interface switch 2504, in at least one embodiment processor 2502 includes direct support for P2P-GPU connections 2516 and may be directly connected to GPGPUs 2506A-D. In at least one embodiment, GPGPUs 2506A-D are part of a SoCs, such as part of integrated circuit 2000 in FIG. 20, where GPGPUs 2506A-D perform operations described herein.Logic 1115 is used to perform inferencing and / or training operations in connection with one or more embodiments. Details of logic 1115 are described herein in connection with FIGS. 11A and / or 11B. In at least one embodiment, logic 1115 in multi-GPU computer system 2500 may be used for inferencing or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases described herein.In at least one embodiment, multi-GPU computer system 2500 includes one or more graphics cores 2200.In at least one embodiment, FIGS. 1-25 are to generate, using one or more neural networks, one or more enhanced speech signals from inferior audio data based at least in part on spectral and waveform features of inferior audio data and one or more features derived from reference audio data comprising one or more superior speech signals.FIG. 26 is a block diagram of a graphics processor 2600 in accordance with at least one embodiment. In at least one embodiment, graphics processor 2600 includes ring interconnect 2602, pipeline front end 2604, media engine 2637, and graphics cores 2680A-...

Claims

A processor comprising: one or more circuitry to use one or more neural networks to generate a first speech signal tone in a first environment based at least in part on a second speech signal tone and a reference tone in a second environment.The processor of claim 1, wherein the reference tone comprises one or more voice signals.The processor of claim 1, wherein the one or more circuits further use the one or more neural networks to generate one or more spectral characteristics based at least in part on the second speech signal tone.The processor of claim 1, wherein the one or more circuits use the one or more neural networks to generate one or more waveform features based at least in part on the second speech signal tone, wherein the one or more waveform features comprise phase information.The processor of claim 1, wherein the one or more circuits further use the one or more neural networks to generate context information based at least in part on the second environment's reference tone.The processor of claim 1, wherein the one or more circuits further use the one or more neural networks to merge one or more spectral features and one or more waveform features.The processor of claim 1, wherein the one or more circuits further use the one or more neural networks to modify one or more different features generated from the second speech signal tone based at least in part on the reference tone of a second environment.The processor of claim 1, wherein the one or more circuits are further to determine a down-sampling rate to perform the down-sampling of the second speech signal tone.A method comprising: generating, using one or more neural networks, a first speech signal tone in a first environment based at least in part on a second speech signal tone and a reference tone of a second environment.The method of claim 9, wherein the reference tone comprises one or more speech signals.The method of claim 9, further comprising: generating, using the one or more neural networks, one or more spectral characteristics based, at least in part, on the second speech signal tone.The method of claim 9, further comprising: generating, using the one or more neural networks, one or more waveform features based, at least in part, on the second speech signal tone.The method of claim 9, further comprising: generating, using the one or more neural networks, contextual information based, at least in part, on the reference tone of the second environment.The method of claim 9, further comprising: modifying, using the one or more neural networks, one or more different features of the second speech signal tone based, at least in part, on the reference tone of a second environment.A system comprising: one or more processors to use one or more circuits to use one or more neural networks to generate a first speech signal tone in a first environment based, at least in part, on a second speech signal tone and a reference tone of a second environment.The system of claim 15, wherein the reference tone comprises one or more voice signals.The system of claim 15, wherein the one or more processors further use the one or more neural networks to generate one or more spectra based at least in part on the second speech signal tone.The system of claim 15, wherein the one or more processors further use the one or more neural networks to generate one or more waveform features based at least in part on the second speech signal tone, wherein the one or more waveform features comprise phase information.The system of claim 15, wherein the one or more processors further use the one or more neural networks to generate contextual information based at least in part on the second environment's reference tone.The system of claim 15, wherein the one or more circuits further use the one or more neural networks to concatenate separate data structures indicative of one or more spectral features and one or more waveform features.

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