TECHNIQUES FOR ANALOGUE CORRECTED MULTIPLE SCROLLING

Abstract

Systems, devices, and methods relating to analog-to-digital converters (ADCs) with split digital-to-analog converters (DACs) are described. The ADC can include a sample-and-hold circuit arrangement with multiple sample-and-hold branches, each branch being coupled to a separate DAC. The total capacitor area for all separate DACs in the ADC can combine to provide the total capacitor area required in a non-branched ADC configuration. Exemplary ADCs can enable analog correlated multiple sampling to reduce noise or otherwise improve the signal-to-noise ratio. The ADC can include a configurable gain and a configurable number of correlated multiple-sampling read operations.Exemplary embodiments include an image sensor with a pixel output coupled to a readout circuit arrangement, wherein the readout circuit arrangement includes an ADC having a split DAC architecture, enabling lower read noise and higher frame rates with lower power consumption.

Description

BACKGROUND

[0001] This application relates generally to image sensors and in particular to improved techniques for reading the output of pixels in low-noise and high-speed image sensors.

[0002] Low-noise, high-speed image sensors are used in a wide variety of applications. In automotive and industrial applications, for example, the sensor's ability to detect fast-moving objects in a variety of lighting conditions enables accurate object recognition. Such sensors can also be used in applications such as high-speed photography and videography, machine vision, surveillance systems, scientific research, and the like. Integrating such sensors into diverse systems leads to improvements in performance, reliability, and ease of use across a wide range of applications.

[0003] Image sensors often include an array of pixel sensors, referred to as pixels, which can be arranged in rows and columns. An image sensor can convert the pixel output into image data by reading pixel rows and converting the pixel signals into image data using a column signal chain. The column signal chains can include electronic circuit arrangements associated with each pixel column in the pixel array. The column signal chain typically includes components such as amplifiers, analog-to-digital converters (ADCs), noise reduction circuitry, and the like, which convert the raw pixel data into processed digital data that can be used to generate a digital image.

[0004] Low-noise image sensors require low dark noise and higher analog gain in the column signal chain to improve object detection in low or very low light conditions. For example, high dynamic range (HDR) image sensors rely on low read noise and high analog gain to improve the detail resolution of the resulting images in low light. Generally, higher gain in the column signal chain helps to reduce any nonlinearities and / or imperfections further down the signal chain, such as in the ADC, in circuit arrangements implementing various image-related algorithms, or similar components.

[0005] Reading noise in low-light conditions can be caused by noise from the pixel source follower, current sources, column amplifier, and column ADC. Band-limiting the noise at the ADC input with a large-power capacitor at the amplifier output can reduce thermally induced noise, but it also leads to lower refresh rates. Furthermore, the flicker noise caused by the source follower is not reduced.

[0006] Alternatively or additionally, digital correlated multiple sampling (CMS) techniques can be used to average source-follower flicker noise, high-frequency thermal noise remaining after bandlimiting, and column ADC noise such as reset noise (also known as KTC noise), quantization noise, and comparator noise. Digital CMS techniques require additional read operations for digital averaging. For example, digital double CMS operations require additional sampling and conversion. The additional read operations increase the power required to perform read operations and decrease the achievable frame rate.

[0007] It would therefore be desirable to provide improved devices and methods for operating low-noise and high-speed image sensors. BRIEF DESCRIPTION OF THE DRAWING FIGURES Fig. Figure 1 is a block diagram of an exemplary image sensor according to different embodiments. Fig. Figure 2 is a schematic representation showing an exemplary readout circuit arrangement coupled to the output of a pixel according to various embodiments. Fig. Figure 3 is a schematic representation showing an exemplary scanning and holding circuit arrangement according to various embodiments. Fig. Figure 4 is an illustrative timing diagram for operating an exemplary analog-to-digital converter (ADC) according to various embodiments. Fig. Figure 5 is a flowchart illustrating a procedure for operating an exemplary ADC according to a selected gain mode according to various embodiments. SUMMARY

[0008] Various embodiments relate to systems, devices and methods for performing pixel readout in low-noise and high-speed image sensors.

[0009] In various embodiments, an image sensor can include: a pixel comprising an output; and a readout circuit arrangement coupled to the pixel output, wherein the readout circuit arrangement comprises: an amplifier having an input and an output, the input being coupled to the pixel output; and an analog-to-digital converter (ADC) comprising: a sample-and-hold circuit arrangement (SH circuit arrangement) comprising an input, an output, a first SH branch coupled between the input of the SH circuit arrangement and the output of the SH circuit arrangement, and a second SH branch coupled in parallel to the first SH branch between the input of the SH circuit arrangement and the output of the SH circuit arrangement, wherein: the input of the SH circuit arrangement is coupled to the output of the amplifier;and the output of the SH circuit arrangement is configured to determine a combined value based on the first SH branch and the second SH branch. The ADC may further include a first digital-to-analog converter (DAC) coupled to the first SH branch; and a second DAC coupled to the second SH branch.

[0010] In various embodiments, a method for performing a readout of an image sensor pixel using an analog-to-digital converter (ADC) may include: storing, at a first time and using a first sample-and-hold (SH) branch of an SH circuit arrangement, a first reset value based on a first output of the pixel; storing, at a second time and using a second SH branch of the SH circuit arrangement, a second reset value based on the first output, wherein: the first SH branch is coupled in parallel with the second SH branch between an input of the SH circuit arrangement and an output of the SH circuit arrangement; and the output of the SH circuit arrangement provides a combined value based on the first SH branch and the second SH branch;Performing a first analog-to-digital conversion (AD conversion) of a first combined value from the output of the SH circuit arrangement using the ADC to generate a digital reset value; storing, at a third time and using the first SH branch, a first image value based on a second pixel output; storing, at a fourth time and using the second SH branch, a second image value based on the second output; performing a second AD conversion of a second combined value from the output of the SH circuit arrangement using the ADC to generate a digital image value; and determining a final pixel value based on the digital reset value and the digital image value.

[0011] In various embodiments, an analog-to-digital converter (ADC) can include a sample-and-hold circuit arrangement (SH circuit arrangement) comprising an input, an output, a first SH branch coupled between the input and output of the SH circuit arrangement, and a second SH branch coupled in parallel with the first SH branch between the input and output of the SH circuit arrangement, wherein the input of the SH circuit arrangement is coupled to an input of the ADC and the output of the SH circuit arrangement is configured to determine a combined value based on the first SH branch and the second SH branch. The ADC can include a first digital-to-analog converter (DAC) coupled to a sample-and-hold node of the first SH branch and a second DAC coupled to the sample-and-hold node of the second SH branch.

[0012] These and other examples are described in more detail below. DETAILED DESCRIPTION

[0013] The following detailed description is intended to provide several examples illustrating the broader concepts set forth herein, but it is not intended to limit the invention or its application and use. Furthermore, there is no intention to be bound by the theory set forth in the preceding background or in the following detailed description.

[0014] According to various embodiments, analog-to-digital conversion (ADC) systems and methods are used to provide improved analog readouts with correlated multiple sampling (CMS) for an image sensor. Various embodiments may include ADC circuit arrangements with a split digital-to-analog converter (DAC), using multiple smaller DACs instead of a single larger one. Various ADC embodiments may include multiple parallel sample-and-hold paths, each coupled to one of the smaller DACs. Various embodiments may provide multiple sampling of a pixel output using the multiple parallel sample-and-hold paths, resulting in reduced readout time, flexibility in the number of CMS reads performed, and selectable gain options for the ADC.

[0015] According to various embodiments, CMS techniques are described for performing averaging and noise reduction from various pixel and column readout sources without using additional capacitor area for sampling and holding as well as DAC circuit arrangements. Furthermore, the disclosed systems and methods do not require additional conversions and require a shorter CMS sampling time, thereby saving power and line readout time compared to other digital and analog CMS techniques. The disclosed techniques can reduce noise using CMS without a significant increase in line readout time, compared to a single read operation in other digital and analog CMS techniques. These and other advantages enable improved, low-noise, high-speed image sensors.Furthermore, the disclosed ADC systems and methods can be used in any suitable application and are not limited to use with image sensors.

[0016] CMS readout can involve sampling and converting at least one pixel reset signal and one pixel image signal so that the reset signal can be subtracted from the image signal to produce a final pixel value. CMS can, for example, remove fixed pattern noise to achieve a more accurate measurement of the final pixel value. Techniques for analog CMS can involve capturing multiple samples of the pixel reset signal and a corresponding number of samples of the pixel image signal. For example, CMS2 can involve capturing two reset samples and two image samples, CMS4 can involve capturing four reset samples and four image samples, and so on.The multitude of reset samples can be averaged, the multitude of image samples can be averaged, and the averaged reset signal can be subtracted from the averaged image signal to provide a final pixel value with an improved signal-to-noise ratio (SNR). Various embodiments described herein may include separating sample acquisition events by at least one period required for noise decorrelation.

[0017] Fig. Figure 1 illustrates a block diagram of an exemplary image sensor 100. In some embodiments, the configuration of the image sensor, the arrangement of various components therein, and the operation of the various components may resemble in some aspects those described in U.S. Patent No. 11,722,794, which is incorporated herein by reference. However, the embodiments described herein may be applied to other configurations of image sensors, pixel arrays, pixels, and the like. Some embodiments may be applied to systems other than image sensors. In some embodiments, the image sensor 100 may be implemented as a semiconductor device on a single substrate, stacked substrates, a system-on-a-chip, or the like.

[0018] In some embodiments, the image sensor 100 can include a pixel array 110 with multiple image sensor pixels 120. A pixel can include any suitable structures configured to convert incident photons into an electrical signal. For example, the pixel can include a photodiode, a transmission gate, a reset transistor, a floating diffusion (FD) region, a source-follower transistor configured to output a pixel signal based on the charge present in the floating diffusion region, an anti-blooming gate, gain configuration structures such as gain selection transistors and / or capacitors, and / or the like. The pixels 120 can be arranged in any suitable way. For example, the pixels 120 can be arranged in groups, such as in a stacked sensor array. In some embodiments, the pixels 120 can be arranged in rows and columns.

[0019] The image sensor 100 may further include a control and processing circuit arrangement 130, which may be referred to herein as the control circuit arrangement 130. The control circuit arrangement 130 may be coupled to a row control circuit arrangement 140 and a column readout and control circuit arrangement 150, which may be referred to herein as the readout circuit arrangement 150. The control circuit arrangement 130 may provide timing controls for the row control circuit arrangement 140. Based on the timing controls, the row control circuit arrangement 140 may provide appropriate row control signals, such as reset, row selection, charge transfer, double-conversion amplification, readout, and / or any other suitable pixel control signals, to each pixel row 120 via one or more conductive row control paths 145.

[0020] In some embodiments, the image sensor 100 can include conductive column lines 155 coupled to each pixel column 120 in the pixel array 110. The column lines 155 can be used to read signals from the pixels 120 and to supply bias currents and / or bias voltages to the pixels 120. In some embodiments, a pixel readout operation can include selecting and controlling a row of pixels in the pixel array 120 using the row control circuit arrangement 140 and reading the pixel values ​​generated by the pixels 120 in the selected row using the column lines 155. The pixel values ​​can be analog values, for example, an analog voltage or an analog current.

[0021] The readout circuit arrangement 150 can control the operation, including the readout, of the pixels 120 and can receive the pixel values ​​from the column lines 155. The readout circuit arrangement 150 can include a memory circuit arrangement for permanently or temporarily storing calibration signals, such as reset level signals and reference level signals, and / or pixel signals read from the pixel array 120. The readout circuit arrangement 150 can include an amplifier circuit arrangement, an analog-to-digital conversion (ADC) circuit arrangement, a bias circuit arrangement, a control circuit arrangement, and / or other circuit arrangements coupled to the pixel columns of the pixel array 110.

[0022] The amplifier circuit arrangement can amplify the pixel values ​​read from pixel 120, for example, reset values ​​and image values, and the ADC circuit arrangement can convert the analog pixel values ​​into digital pixel values. The readout circuit arrangement 150 can provide the digital pixel values ​​to the control circuit arrangement 130 and / or other storage and processing circuit arrangements of the image sensor 100 for further processing. This additional processing can include converting the digital pixel values ​​into image data, performing HDR processing by appropriately combining multiple exposures and / or pixel readouts with varying amplification, and the like.

[0023] In some embodiments, one or more of the control circuit arrangement 130, the line control circuit arrangement 140, and / or the readout circuit arrangement 150 may include an associated storage circuit arrangement configured to store instructions, such as firmware, software, or the like, executable by a processing component of the respective control circuit arrangement 130, 140, or 150. The associated storage circuit arrangement may, for example, include non-transitory, computer-readable media. When executed by the respective processing component, the stored instructions may implement one or more processes described herein, such as one or more timing diagrams for controlling one or more pixels 120 and / or readout circuit arrangements 150, one or more process flow diagrams for performing pixel readout and conversion, and / or the like.

[0024] Fig. Figure 2 is a schematic representation showing an exemplary readout circuit arrangement 150 coupled to the output of pixel 120, configured, for example, to read a pixel value based on the charge in a floating diffusion region 205 via a row selector switch 210 and a source follower transistor 215. For clarity, the rest of pixel 120 is shown in Fig. 2 not reproduced.

[0025] In some embodiments, the pixel 120 may include a source-follower transistor 215 and a pixel or row selector switch 210, forming an output circuit arrangement section of the pixel 120. The selector switch 210 may be configured to receive a control signal, 'RS', for controlling the selector switch 210. In some embodiments, the selector switch 210 may include a transistor with a control input, such as a gate, configured to receive the 'RS' control signal. The source-follower transistor 215 may couple a voltage terminal (not shown) to the selector switch 210, and the control terminal of the source-follower transistor 215 may be coupled to the floating diffusion region 205. The voltage terminal may provide a voltage reference signal, such as an analog-level supply voltage.

[0026] The selector switch 210 can couple the source-follower transistor 215 to a column line 155 of the pixel array 110. In some embodiments, a column line 155 can be linked to one or more pixel columns, and the 'RS' signal can be activated to read a pixel signal from a specific pixel row. In some embodiments, the column line 155 can be coupled to a current source 220, which may be referred to herein as the VLN circuit arrangement 220. The current source 220 can further be coupled to a common-mode voltage, such as ground. The current source 220 can provide a reference current for the column line 155 and can enable accurate measurement of a voltage or voltage change on the column line 155 as a result of reading a pixel value. In some embodiments, the readout circuit arrangement 150 can include the current source 220.

[0027] When the control signal 'RS' is activated, a corresponding pixel output signal, with a magnitude proportional to the amount of charge in the floating diffusion area 205, is passed to the column line 155 via the source-follower transistor 215 and the selector switch 210. If the floating diffusion area 205 stores charge generated by a photodiode (not shown) of pixel 120 in response to receiving incident light, the corresponding pixel output signal can be referred to as the image signal or image level signal. If the floating diffusion area 205 stores a reset voltage level charge, for example, after a reset operation, the corresponding pixel output signal can be referred to as the reset signal or reset level signal. The pixel output signal can be provided, as desired, to the readout circuitry 150 and the control circuitry 130 and / or other processing circuitry.

[0028] In some embodiments, for example for HDR applications, the Pixel 120 can be adapted and controlled to generate more than one set of image and reset signals for each integration period. The multiple image and reset signals can be read out in two or more operations using different gains. For example, the Pixel 120 can be adapted and controlled to perform a low conversion gain (LCG) readout, a medium conversion gain (MCG) readout, and / or a high conversion gain (HCG) readout. In some embodiments, the Pixel 120 can include one or more conversion gain devices configured to enable the LCG, MCG, and / or HCG readouts.

[0029] In some embodiments, the readout circuit arrangement 150 may include an amplifier 225. The amplifier 225 may include any suitable circuit arrangement configured to provide at its output an amplified version of a voltage level received at its input. For example, an input of the amplifier 225 may be coupled to the column line 155, and the amplifier 225 may be configured to amplify a voltage level or voltage fluctuation on the column line 155 caused by reading a pixel value from the pixel 120 and provide the amplified voltage at its output.

[0030] In some embodiments, the amplifier 225 can include a positive and a negative input (not shown). For example, the column line 155 can be coupled to the negative input of the amplifier 225, and the positive input of the amplifier 225 can be coupled to a voltage reference, such as a common-mode voltage reference. The common-mode voltage reference can be any suitable voltage, for example, about 1 volt (V). Other examples include the column line 155 coupled to the positive input of the amplifier 225 and a voltage reference coupled to the negative input. It can be seen that the output of the amplifier 225 can be configured to be positive or negative, depending on the design of the readout circuit arrangement 150, the voltage levels at which the image sensor 100 operates, and / or the like.

[0031] The output of amplifier 225 can be coupled to an input of an analog-to-digital converter (ADC) 200. The ADC 200 can include circuit arrangements and / or methods configured to convert an analog voltage level at the input of the ADC 200 into a digital representation of the analog voltage level and to provide the digital representation at an output of the ADC 200. In some embodiments, the ADC 200 can be configured or otherwise controllable to provide one or more digital representations with a gain compared to the analog input, for example, a gain of 1, 2, 4, 8, 16, and / or the like.

[0032] In some embodiments, the ADC 200 may include a successive approximation (SA) ADC. The ADC 200 may include suitable circuit arrangements and / or methods configured to convert the analog level to the digital representation using an SA algorithm. A suitable SA algorithm may include performing a binary search through a series of quantization stages to merge the digital representation. In some embodiments, the SA algorithm may include the use of one or more charge-scaling DACs, each of which may include an array of individually switched, binary-weighted capacitors providing the quantization stages. The amount of charge on each capacitor in the array may be used, in combination with the SH circuit arrangement 230, a comparator 260, and an ADC control circuit arrangement 270, to perform a binary search.

[0033] In some embodiments, the ADC 200 can include a sample-and-hold circuit arrangement (SHS) 230, which has an input 232 coupled to the output of the amplifier 225. The input 232 of the SHS 230 can form the input of the ADC 200. The SHS 230 can include a circuit arrangement configured to detect (sample) and maintain (hold) a voltage level from the input of the SHS 230, thereby enabling stable measurements and / or processing of the detected voltage level. In various embodiments, the control circuit arrangement 130 and / or the readout circuit arrangement 150 can control the SHS 230 to detect voltage levels corresponding to a reset signal and / or image signal from various readouts of the pixel 120.

[0034] In some embodiments, the SH circuit arrangement 230 can include several parallel scan and hold branches. For example, the SH circuit arrangement 230 can include a first SH branch 240 and a second SH branch 250. Each SH branch 240, 250 can include a suitable circuit arrangement for performing scan and hold operations. In some embodiments, each SH branch 240, 250 can include an identical circuit arrangement. For example, the first SH branch 240 can include a switch 242 that is connected in series between the input of the SH circuit arrangement 230 and an SH capacitor 244, the SH capacitor 244 being connected in series between the switch 242 and an output 234 of the SH circuit arrangement 230.The second SH branch 250 can also include a switch 252, which is coupled in series between the input of the SH circuit arrangement 230 and an SH capacitor 254, wherein the SH capacitor 254 is coupled in series between the switch 252 and the output 234 of the SH circuit arrangement. The SH capacitors 244 and 254 can also be referred to as coupling capacitors.

[0035] The switch 242 and the SH capacitor 244 of the first SH branch 240 can be coupled to a first sample-hold node 246, which is configured to be coupled to a digital-to-analog converter (DAC). The switch 252 and the SH capacitor 254 of the second SH branch 250 can be coupled to a second sample-hold node 256, which is configured to be coupled to a digital-to-analog converter (DAC). The sample-hold node of each SH branch can include the electrical node where the value sampled at the input of the SH circuit arrangement 232 is stored, for example, the node between the switch and the capacitor of the respective SH branch. The first sampling hold node 246 may be referred to herein as Vdac1 node 246, and the second sampling hold node 256 may be referred to herein as Vdac2 node 256.

[0036] Switches 242 and 252 can enclose any suitable electrical switch, for example, a transistor with a control terminal such as a gate contact. In some embodiments, switches 242 and 252 can enclose a complementary metal-oxide-semiconductor transistor (CMOS transistor). Switch 242 of the first SH branch 240 can be controlled by a signal 'SH1', and switch 252 of the second SH branch 250 can be controlled by a signal 'SH2'. Each switch 242 and 252 can be closed according to the respective control signals to obtain a voltage level from the input 232 of the SH circuit arrangement for storage by the respective SH capacitors 244 and 254. Each switch 242, 252 can be opened according to the respective control signals in order to maintain the voltage level from the input 232 of the SH circuit arrangement according to the value stored by the respective SH capacitors 244, 254.

[0037] In some embodiments, the SH capacitors 244, 254 can be configured to have the same dimensions, for example, the same capacitance, area, and the like. Furthermore, according to various embodiments, increasing the number of SH branches in the SH circuit arrangement 230 does not require an increase in the total area required for SH capacitors. For example, the total area required for all the SH capacitors of the SH circuit arrangement 230 can be the same as, or approximately the same as, the area required for a capacitor used to store the amplified pixel signal value in a non-branched sample-and-hold circuit arrangement (or for the single SH capacitor in an SH circuit arrangement 230 with only a single SH branch), regardless of the number of SH branches.

[0038] Accordingly, in a configuration of the SH circuit arrangement 230 with two SH branches, as in Fig. Figure 2 illustrates that the capacitance and area of ​​each SH capacitor 244, 254 can be half that of the SH capacitor in a single-branch (or unbranched) configuration. For example, if the capacitor in an unbranched configuration is designed with a capacitance of 200 femtofarads (fF), then each SH capacitor 244, 254 of the two-branch configuration can be designed with a capacitance of 100 fF. As another example, in a four-branch configuration of the SH circuit arrangement 230, the capacitance and area of ​​each SH capacitor can be one-quarter that of an SH capacitor in a single-branch configuration, for example, four capacitors, each with a capacitance of 50 fF, compared to a single capacitor with a capacitance of 200 fF.It is evident that the exemplary capacity values ​​discussed above can be appropriately selected or modified based on design requirements, performance targets and / or the like.

[0039] The output 234 of the SH circuit arrangement can determine and provide a combined value based on each of the SH branches of the SH circuit arrangement 230. In some embodiments, the combined value can be based on the principle of a capacitive divider, where the node voltage at the output 234 of the SH circuit arrangement is equal to the average of the voltage or voltage change occurring at the input of each SH capacitor in each SH branch of the SH circuit arrangement 230. For example, the illustrated SH circuit arrangement 230 of Fig. 2 provide a combined value based on the average voltage at Vdac1 node 246 and Vdac2 node 256. Advantageously, when sampling a signal with noise, the signal sampled in each SH branch 240, 250 will, on average, produce the same signal at the output 234 of the SH circuit arrangement, while the noise, for example, uncorrelated noise that is random, is reduced by a factor of √2 for a configuration of the SH circuit arrangement 230 with two SH branches. The signal-to-noise ratio (SNR) is accordingly increased by a factor of approximately 1.4 for an SH circuit arrangement 230 with two SH branches 240, 250.

[0040] The systems and methods described herein are advantageously scalable for a higher number of CMS samples. Briefly, with reference to Fig. In some embodiments, the SH circuit arrangement 230 can include four SH branches, including the first SH branch 240, the second SH branch 250, a third SH branch 300 and a fourth SH branch 310, thereby enabling up to CMS4.

[0041] As described above, in some embodiments each SH branch 240, 250, 300, 310 can include an identical circuit arrangement. For example, the third SH branch 300 can include a switch 302 connected in series between the input of the SH circuit arrangement 230 and an SH capacitor 304, wherein the SH capacitor 304 is connected in series between the switch 302 and an output 234 of the SH circuit arrangement 230. The fourth SH branch 310 can include a switch 312 connected in series between the input of the SH circuit arrangement 230 and an SH capacitor 314, wherein the SH capacitor 314 is connected in series between the switch 312 and an output 234 of the SH circuit arrangement 230. The first SH branch 240, the second SH branch 250, the third SH branch 300 and the fourth SH branch 310 can be electrically coupled in parallel.

[0042] Switch 302 and SH capacitor 304 of the third SH branch 300 can be coupled to a third node 306, which is configured to be coupled to a digital-to-analog converter (DAC). Switch 312 and SH capacitor 314 of the fourth SH branch 310 can be coupled to a fourth node 316, which is configured to be coupled to a digital-to-analog converter (DAC). The third node 306 may be referred to herein as Vdac3 node 306, and the fourth node 316 may be referred to herein as Vdac4 node 316. Switches 302 and 312 for the third 300 and fourth 310 SH branches can perform the same function, be controlled similarly, and can be of the same type as switches 242 and 252 used in the first 240 and second 250 SH branches. Switch 302 can be controlled by a signal 'SH3', and switch 312 can be controlled by a signal 'SH4'.

[0043] In some embodiments, the SH capacitors 244, 254, 304, 314 can be configured to have the same dimensions, for example, the same capacitance, surface area, and the like. As described above, in some embodiments, the total area required for all the SH capacitors 244, 254, 304, 314 of the SH circuit arrangement 230 can be equal to or approximately equal to the area required for a capacitor used to store the amplified pixel signal value in a non-branched sample-and-hold circuit arrangement. Accordingly, in a configuration of the SH circuit arrangement 230 with four SH branches 240, 250, 300, 310, as shown in Fig. Figure 3 illustrates that the capacitance, surface area and / or the like of each SH capacitor 244, 254, 304, 314 may be about half that of the SH capacitors 244, 254 in a two-branch configuration and may be about a quarter that of the storage capacitor in a non-branch sample-and-hold circuit arrangement.

[0044] In some embodiments, the total area required for all SH capacitors 244, 254, 304, 314 may only be approximately equal to the area required in a non-branched sample-and-hold circuit arrangement, with variations in size, capacitance, and / or the like occurring due to errors, tolerances, design choices, and / or the like. For example, differential nonlinearity constraints, integral nonlinearity constraints, and / or the like may affect the design size of the respective capacitors and / or the finished size of the respective capacitors.Furthermore, as another example, it may be that due to manufacturing limitations an exact duplication or size reduction of capacitor features such as electrode plates, dielectric thickness and / or the like is not possible, for example due to nonlinear scaling of capacitors, and the design can be adapted to take these limitations into account without deviating from the embodiments described herein.

[0045] Still referring to Fig. 3. The output 234 of the SH circuit arrangement can provide a combined value based on each of the four SH branches 240, 250, 300, 310 of the SH circuit arrangement 230. As described above, the combined value can be based on the average of the voltage or voltage change occurring at the input of each SH capacitor in each SH branch of the SH circuit arrangement 230. For example, the illustrated SH circuit arrangement 230 of Fig. 3 provides a combined value based on the average voltage at Vdac1 node 246, Vdac2 node 256, Vdac3 node 306, and Vdac4 node 316. Advantageously, when sampling a signal with noise, the signal sampled in each SH branch 240, 250, 300, 310 will, on average, produce the same signal at the output 234 of the SH circuit arrangement, while the noise, for example, uncorrelated noise, is reduced by a factor of √4 for an SH circuit configuration 230 with four SH branches. The signal-to-noise ratio (SNR) can accordingly increase by a factor of approximately 2 for an SH circuit arrangement 230 with four SH branches 240, 250, 300, 310.

[0046] More generally, the SH circuit arrangement 230 can include any suitable number of SH branches. The above refers to the Fig. 2 and Fig. The principles described in section 3 for the multi-branch SH circuit arrangement 230 can be used to extend the SH circuit arrangement 230 as desired to include a larger or smaller number of SH branches. In each case, the signal is averaged, the noise is reduced by the square root of the number of SH branches if the samples are decorrelated, and the overall capacitor dimensioning and / or capacitance will be equal to or approximately equal to that of the storage capacitor for an unbranched sample-and-hold circuit arrangement.

[0047] With regard to the Fig. 2 and Fig. 3. In some embodiments, the ADC 200 can include a DAC for each SH branch of the SH circuit arrangement 230. Each DAC can be coupled to the sample-hold node of a corresponding SH branch. For example, embodiments according to the one described in Fig. The SH circuit arrangement 230 illustrated in Figure 2 includes a first DAC 280 coupled to the Vdac1 node 246 and a second DAC 285 coupled to the Vdac2 node 256. As a further example, embodiments according to the one shown in Figure 2 can include a first DAC 280 coupled to the Vdac1 node 246 and a second DAC 285 coupled to the Vdac2 node 256. Fig. 3 illustrated SH circuit arrangement 230 include a first DAC 280 coupled to the Vdac1 node 246, a second DAC 285 coupled to the Vdac2 node 256, a third DAC 320 coupled to the Vdac3 node 306, and a fourth DAC 330 coupled to the Vdac4 node 316.

[0048] In some embodiments, each DAC 280, 285, 320, 330 can include an array of individually switched capacitors, each capacitor in the array having a different capacitance value. The array of switched capacitors can include an array of binary-weighted capacitors such that the capacitance of each capacitor in the array is related by powers of two. For example, each DAC 280, 285, 320, 330 can include a 12-bit DAC with 12 capacitors, where a capacitor representing the least significant bit (LSB) has a relative capacitance of 1, the second least significant bit has a relative capacitance twice that of the capacitor representing the LSB, and so on, with the capacitor representing the most significant bit (MSB) having a relative capacitance of 2. 11In some of these embodiments, each subsequent capacitor from the LSB to the MSB can be twice the size of the preceding capacitor. As discussed above, nonlinearity and / or other considerations may result in the capacitor being approximately sized.

[0049] The arrays of binary-weighted switched capacitors can be configured to enable the execution of the SA algorithm by the ADC 200. In some embodiments, a first terminal of each capacitor in the arrays of switched capacitors for a DAC 280, 285, 320, 330 can be coupled to the respective sample-hold nodes, for example, Vdac1 node 246, Vdac2 node 256, Vdac3 node 306, and Vdac4 node 316. The first terminal of a capacitor can be referred to here as the top plate or first plate of the capacitor. A second terminal of each capacitor in the arrays of switched capacitors can be configured to be switchable to a 'high' and 'low' signal, for example, to a reference voltage (e.g., 'high') and a common-mode voltage such as ground (e.g., 'low'). The reference voltage can correspond to the full-scale range of the ADC 200.The reference voltage can be selectable, for example, if a different gain factor is selected for the ADC 200, as described in more detail below. The second terminal of a capacitor can be referred to here as the bottom plate or second plate of the capacitor.

[0050] During the operation of a DAC, switching the bottom plate of a capacitor in the capacitor array to 'high' or 'low' after a voltage value has been sampled and held at the sample-hold node results in a change in the voltage at that respective sample-hold node. The voltage change is proportional to the weight of the binary-weighted capacitor that was switched. For example, switching the bottom plate of the capacitor for the second-lowest bit causes twice the change at the sample-hold node compared to switching the bottom plate of the capacitor for the LSB, switching the third-lowest bit causes twice the change compared to switching the second-lowest bit, and so on.

[0051] The successive switching of each capacitor in the DAC's capacitor array, for example from the MSB to the LSB, results in a series of analog voltage steps at the respective sample-hold node. For example, if, after sampling and holding a voltage value at the Vdac1 node 246, each capacitor in the array of binary-weighted capacitors of the first DAC 280 is successively switched, this results in a series of analog voltage steps at the Vdac1 node 246. The voltage changes at the sample-hold node are transmitted via the respective coupling capacitor; for example, voltage changes at the Vdac1 node 246 are transmitted via the SH capacitor 244 to the output 234 of the SH circuit arrangement.

[0052] Each DAC 280, 285, 320, 330 can be controlled to switch its capacitor array simultaneously in order to execute the SA algorithm concurrently for each respective SH branch 240, 250, 300, 310. Each stepped voltage value transmitted through the respective coupling capacitors can then be averaged at the output 234 of the SH circuit arrangement as described above.

[0053] In some embodiments, each array of switched capacitors in each DAC 280, 285, 320, 330 can be configured to have the same set of capacitor sizes. For example, each DAC 280, 285, 320, 330 can have the same number of capacitors in the capacitor array, with each array having the same set of capacitor sizes (such as capacitance, area, or the like). Furthermore, according to various embodiments, increasing the number of SH branches in the SH circuit arrangement 230, and thus the number of DACs, does not require an increase in the total area required for the switched DAC capacitors.For example, the total area required for all switched DAC capacitors of the ADC 200 can be equal to or approximately equal to the total area required for an array of switched capacitors used for the single DAC in a non-branched sample-and-hold circuit configuration, regardless of the number of SH branches. Each DAC in a multi-branch configuration of the SH circuit arrangement 230 can have the same number of switched capacitors, for example, 12 capacitors for a 12-bit DAC, regardless of the number of SH branches used by the SH circuit arrangement 230.

[0054] Accordingly, in a configuration of the SH circuit arrangement 230 with two SH branches, as in Fig. Figure 2 illustrates that the total capacitance and area of ​​the array of switched capacitors in each DAC 280, 285 can be half that of the array of switched capacitors in a DAC in a single-branch (or non-branch) configuration. For example, if the array of switched capacitors in a DAC for a non-branch configuration is designed with a combined capacitance of 1 picofarad (pF), then each array of capacitors for each DAC 280, 285 of the two-branch configuration can be designed with a capacitance of 500 fF. As a further example, referring to Fig. 3 in a configuration of the SH circuit arrangement 230 with four SH branches, the capacitance and area of ​​each capacitor array for each DAC 280, 285, 320, 330 shall be one quarter of that of a DAC in a configuration with one branch, wherein, for example, each capacitor array shall have a combined capacitance of 250 fF.

[0055] Referring again to Fig. 2. In some embodiments, the ADC 200 may include a comparator 260 with a first and a second input. The comparator 260 may include any suitable circuit arrangement configured to compare the values ​​at its inputs, for example, analog voltage levels, and to provide an output based on the comparison result. The output may include a differential output, an unbalanced output, a binary output, and / or the like. In some embodiments, the output of the comparator 260 may include a differential output with a first and a second output signal that oscillate in opposite voltage directions, based on whether an input of the first comparator 260 is greater or less than an input of the second comparator 260 and / or based on the magnitude of the difference between the first and second inputs.

[0056] In some embodiments, the comparator 260 can have a first input coupled to the output 234 of the SH circuit arrangement and a second input coupled to a reference voltage, for example, a common-mode voltage such as ground. The comparator 260 can compare the averaged stepped voltage value from the output 234 of the SH circuit arrangement with the reference voltage for each stepped voltage value caused by the series-connected capacitors of the DACs 280, 285, 320, and 330. In some embodiments, the first input can be a negative input to the comparator 260, and the second input can be a positive input to the comparator 260. In alternative embodiments, the positive input can optionally be coupled to the output 234 of the SH circuit arrangement, and the negative input can be coupled to a reference voltage.The comparator 260 can optionally be coupled to the reference voltage via a capacitor 266.

[0057] The output(s) of comparator 260 can be coupled to one or more of its respective inputs via one or more switches 262, 264. The switches can be controlled such that they automatically zero out comparator 260 before performing a comparison. In some embodiments, a first output signal of the differential output can be coupled to the first input of comparator 260 via a switch 262, and a second output signal of the differential output can be coupled to the second input of comparator 260 via a switch 264. Switches 262, 264 can be controlled by a control signal 'AZ'.

[0058] In some embodiments, the ADC 200 may include an ADC control circuit arrangement 270. The ADC control circuit arrangement 270 may include any suitable circuit arrangement and / or any suitable method configured to control each DAC 280, 285 coupled to the SH circuit arrangement 230 based on the comparison result received from the comparator 260. The ADC control circuit arrangement 270 may be configured to control each DAC 280, 285 according to the SA algorithm. For example, the ADC control circuit arrangement 270 can include a suitable circuit arrangement that serves to control the switched capacitors of the DACs 280, 285 such that they perform the binary search of the SA algorithm, with each capacitor in the array of capacitors of each DAC 280, 285 being switched sequentially to provide a digital representation (e.g., binary value) for the respective bit position (e.g.,MSB, LSB, etc.), which corresponds to the capacitor under test, to test and determine. In some embodiments, the ADC control circuit arrangement 270 may include the comparator 260.

[0059] The ADC control circuit arrangement 270 can have one or more inputs coupled to one or more outputs of the comparator 260. The ADC control circuit arrangement 270 can have an output that, for example, provides one or more control signals that are coupled to and configured for controlling each DAC connected to the individual SH branches. For example, in Fig. In the 2 illustrated embodiments of the ADC control circuit arrangement 270, an output is coupled to each of the two DACs 280, 285, and in Fig. In the three illustrated embodiments, the ADC control circuit arrangement 270 can have an output coupled to each of the four DACs 280, 285, 320, 330. The ADC control circuit arrangement 270 can provide identical control of each DAC coupled to the SH circuit arrangement 230.

[0060] Referring again to Fig. 2. In some embodiments, each DAC 280, 285 coupled to each SH branch 240, 250 of the SH circuit arrangement 230 can receive the same control signals from the ADC control circuit arrangement 270. The control signals output by the ADC control circuit arrangement 270 can be configured to control the switching of the arrays of switched capacitors of the DACs 280, 285, and can provide an indication of a determined value, for example, a logical '1' or '0', for the capacitor currently being tested (e.g., corresponding to MSB, LSB, etc.). The determined value can represent the determined digital representation of the analog voltage value sampled from the input of the SH circuit arrangement 232 for the bit being tested.

[0061] In some embodiments, the ADC control circuit arrangement 270 can include a latch 272 and a SA feedback circuit arrangement 274. The latch 272 can include any suitable device for converting the output of the comparator 260 into a binary value. For example, the latch 272 can include a set-reset latch (SR latch) that receives a differential output from the comparator 260, and the latch 272 can set (binary '1') or reset (binary '0') its output based on the received differential output signals.

[0062] In some embodiments, the SA feedback circuit arrangement 274 can be coupled to receive the output of the latch 272. The SA feedback circuit arrangement 274 can include any suitable circuit arrangement configured to determine a binary value for the tested bit position based on the comparison result from the comparator 260 and the latch 272. The SA feedback circuit arrangement 274 can also include any suitable circuit arrangement configured to control the switching of the capacitor arrays of the DACs 280 and 285 according to the SA algorithm, for example, configured to provide the control signals to the DACs 280 and 285.

[0063] The SA feedback circuit arrangement 274 can be configured to determine, based on the comparison result, whether the currently tested bit in the DACs should be reset or remain set. Resetting the currently tested bit can include setting the currently switched capacitor to its untested state. The SA feedback circuit arrangement 274 can then be configured to control (switch, set) the next capacitor to be tested. The SA feedback circuit arrangement 274 can be configured to provide a signal to the DACs 280, 285, and / or other components of the image sensor 100 indicating the determined binary value for the given tested bit position.

[0064] The SA feedback circuit arrangement 274 can start with the capacitor corresponding to the MSB with the highest weight, resolve each bit position sequentially, and end with the LSB with the lowest weight. For example, in 12-bit DACs, the SA feedback circuit arrangement 274 can set the 12th bit if the comparison result indicates that the value was too high; then the SA feedback circuit arrangement 274 can reset the 12th bit and then test the 11th bit, and so on.

[0065] In some embodiments, the ADC control circuit arrangement 270, for example via the SA feedback circuit arrangement 274, can store in a memory, output or otherwise provide the combined digital representation (a digital value) from performing the SA algorithm for a given analog value sampled at the input of the SH circuit arrangement 232.

[0066] In some embodiments, one or more of the DACs 280, 285 can store or otherwise output the determined (combined) digital representation. In some embodiments, one or more DACs 280, 285 can store the determined digital representation in a column memory (not shown). The ADC 200 can include an ADC output 290 configured to provide the determined digital representation of the analog value sampled at input 232 of the SH circuit arrangement, for example, from the one or more DACs 280, 285, from the SA feedback circuit arrangement 274, and / or the like.

[0067] Fig. Figure 4 is an illustrative timing diagram 400 for operating the ADC 200 to perform an A / D conversion of several reset values ​​and image values ​​from an output of pixel 120, for example during a CMS2 readout operation. The timing diagram 400 can correspond to a two-branch SH circuit arrangement 230, as shown in Fig. Figure 2 illustrates this. In some embodiments, the control signals described above, such as 'AZ', 'SH1', and 'SH2', can be used to control the operation of the ADC 200. For example, a control circuit arrangement such as the control circuit arrangement 130 and the readout circuit arrangement 150 can be configured to provide one or more of these control signals to the corresponding components of the ADC 200 via their respective control paths.

[0068] The control circuit arrangement can operate the ADC 200 during a reset signal readout period 405 and a picture signal readout period 410. During the reset signal period 405, the control circuit arrangement can control pixel 120 to output a pixel signal corresponding to a reset level of pixel 120, which is to be received, for example, by the readout circuit arrangement 150. During the picture signal period 410, the control circuit arrangement can control pixel 120 to output a pixel signal corresponding to a picture level of pixel 120, which is to be received, for example, by the readout circuit arrangement 150.

[0069] While pixel 120 outputs a reset signal during the reset signal period 405, ADC 200 can be controlled to automatically zero comparator 260. Automatic zeroing of comparator 260 can include setting the common-mode mode for comparator 260, for example, by setting the inputs and outputs of comparator 260 to the same or a known value before sampling. Comparator 260 can be automatically zeroed by activating the 'AZ' signal, which controls switches 262 and 264 of comparator 260 (415). At the end of the 'AZ' activation (415), switches 262 and 264 open, allowing comparator 260 to make comparison decisions based on the input(s) to comparator 260.

[0070] The SH circuit arrangement 230 can acquire two or more samples of the reset signal output by pixel 120 during the reset signal period 405. As a non-restrictive example, a sample of the pixel signal value read from pixel 120 can be stored by an SH branch of the SH circuit arrangement 230 on the falling edge of the respective 'SH' signal. The number of reset samples and subsequent image samples that can be stored by the SH circuit arrangement 230 corresponds to the number of SH branches of the SH circuit arrangement 230. The number of storable reset and image samples therefore corresponds to the number of CMS read operations that are capable of being performed for a reset signal or an image signal from pixel 120.For example, an SH circuit arrangement 230 with two SH branches 240, 250 can perform a CMS2 readout and conversion, and an SH circuit arrangement 230 with four SH branches can perform a CMS4 readout and conversion.

[0071] A multi-branch SH circuit arrangement 230 can also perform a smaller CMS read operation than the total number of available storable samples. As a non-limiting example, in some embodiments, a multi-branch, four-branch SH circuit arrangement 230 can perform CMS2 by capturing an identical sample at multiple sample-hold nodes of the SH circuit arrangement 230. For example, the control signals 'SH1' and 'SH2' can be operated such that their falling edges are aligned to capture an initial sample at both the Vdac1 node 246 and the Vdac2 node 256, and the control signals 'SH3' and 'SH4' can be operated such that their falling edges are aligned at a later time T CMSare aligned to capture a second sample at both the Vdac3 node 306 and the Vdac4 node 316. The SH circuit arrangement 230 therefore offers flexibility to improve the frame rate or perform a higher CMS read operation as required.

[0072] One or more SH branches, for example the first SH branch 240 and the second SH branch 250, can each be controlled to sample and hold an analog voltage value based on the reset signal output by pixel 120. The respective control signals, for example 'SH1' and 'SH2', can be activated to cause switches 242 and 252 to close, allowing the analog voltage at input 232 of the SH circuit arrangement to charge the respective SH capacitors 244 and 254. The control signal 'SH1' can be deactivated at a first time 420, at which time a first sample of the reset signal is stored on the Vdac1 node 246. The control signal 'SH2' can be deactivated at a second time 425 after the first time, whereby at the second time 425 a second sample of the reset signal is stored on the Vdac2 node 256.

[0073] The first time and the second time can be distinguished by a decorrelation period T. CMS be separated, with this being a minimum period required to provide the desired noise decorrelation between the first reset sample and the second reset sample. In some embodiments, by extending the time T CMS The noise decorrelation is increased. In some embodiments, T CMS in the nanosecond (ns) range, for example hundreds of nanoseconds, such as about 300 ns, 400 ns, 500 ns, and / or the like. Advantageously, acquiring each additional reset sample after the first sample in a multi-branch SH circuit arrangement 230 requires only one additional period T. CMS for each such additional sampling. For example, capturing two reset samples requires only a single additional period T. CMScompared to acquiring a single reset sample in a non-branched SH circuit arrangement, and acquiring four reset samples in a four-branch SH circuit arrangement 230 requires only three additional time periods T in comparison. CMS .

[0074] During the reset signal period 405, and after storing the reset samples at the first and second timestamps 420, 425, the first and second reset samples can be averaged at the output 234 of the SH circuit arrangement as described above, and the ADC 200 can begin executing the SA algorithm 430. As described above, the ADC control circuit arrangement 270, or another suitable control circuit arrangement, can control the DACs 280, 285 to sequentially switch the respective arrays of switched capacitors to converge to a digital representation based on the multiple sampled reset values ​​stored at the first and second timestamps 420, 425. After completion 435 of the SA algorithm, the digital representation of the reset value can be stored by the ADC 200 or otherwise provided.

[0075] While pixel 120 outputs an image signal during the image signal period 410, the SH circuit arrangement 230 can capture two or more samples of the image signal output by pixel 120. The capture of multiple image signal samples can be staggered. For example, the first SH branch 240 and the second SH branch 250 can each be controlled to sample and hold an analog voltage value based on the image signal output by pixel 120. The control signal 'SH1' can be activated first to cause switch 242 to close, allowing the analog voltage at input 232 of the SH circuit arrangement to charge the SH capacitor 244. The control signal 'SH1' can then be deactivated at a third time 440, whereby at the third time 440 a first sample of the image signal is stored on the Vdac1 node 246.

[0076] In some embodiments, staggering the reset sampling in an analogous manner may not be possible, depending on the KTC noise caused by the reset process of pixel 120. Once the KTC reset noise has been captured in all reset samples acquired by the SH circuit arrangement 230, the image samples acquired by the SH circuit arrangement 230 can be staggered.

[0077] In some embodiments, after the control signal 'SH1' has been deactivated at the third time 440, the control signal 'SH2' can be activated to cause the switch 252 to close, allowing the analog voltage at input 232 of the SH circuit arrangement to charge the SH capacitor 254. The control signal 'SH2' can then be deactivated at a fourth time 445, causing a second sample of the image signal to be stored on the Vdac2 node 256 at the fourth time 445. In some alternative embodiments, the control signal 'SH2' can be activated while the control signal 'SH1' is still activated.

[0078] Advantageously, the settling and sampling time required for each captured image signal sample in a configuration of an SH circuit arrangement 230 with two SH branches can be half the time required for settling and sampling in a non-branched SH circuit arrangement, since the respective capacitors of each SH branch 240, 250 are only half the size required for the non-branched SH circuit arrangement. Similarly, the settling and sampling time required for each captured image signal sample in a configuration of an SH circuit arrangement 230 with four SH branches can be one-quarter of the time required for settling and sampling in a non-branched SH circuit arrangement.Consequently, acquiring an image signal sample in a multi-branch SH circuit arrangement 230 does not require any additional time compared to a single sample in a non-branched SH circuit arrangement.

[0079] The staggered sampling provides sufficient space between sampling events to allow for noise decoupling between image samples, without requiring any additional time compared to sampling a single image value in a non-branched SH circuit. Furthermore, in a non-branched SH circuit, a second sampling of the image signal, separated by T, would be necessary. CMS , required for CMS2 in the unbranched case. An SH circuit arrangement 230, which has two SH branches 280, 285 and performs a CMS2 read operation, therefore saves a period T. CMScompared to the unbranched case, where two image samples are taken, and an SH circuit arrangement 230 which has four SH branches and performs a CMS4 read operation, therefore saves 3 × T CMS Compared to the non-branched case, when four image samples are acquired, these time savings improve the frame rate of the image sensor 100. Furthermore, the staggered image signal sampling in a multi-branch SH circuit arrangement 230 also improves digitally correlated double sampling (DCDS) due to better correlation of low-frequency flicker components.

[0080] During the image signal period 410 and after storing the image signal samples at the third and fourth times 440, 445, the first and second image samples can be averaged at the output 234 of the SH circuit arrangement as described above, and the ADC 200 can begin performing the SA algorithm 450. As described above, the ADC control circuit arrangement 270 or another suitable control circuit arrangement can control the DACs 280, 285 to sequentially switch the respective arrays of switched capacitors to converge to a digital representation based on the multiple sampled image signal values ​​from the third and fourth times 440, 445. After completion 455 of the SA algorithm, the digital representation of the image value can be stored by the ADC 200 or otherwise made available.

[0081] According to the CMS process illustrated in the timing diagram 400, the ADC 200 acquires and averages multiple samples of the reset signal from pixel 120 and the image signal from pixel 120, and provides a digital representation of the reset signal (as a digital reset value) and the image signal (as a digital image value). The image sensor 100 can then, for example, via the readout circuit arrangement 150, subtract the digital reset value from the digital image value to obtain a final pixel value for pixel 120 that exhibits less noise and takes the reset voltage level into account.

[0082] The time sequence diagram in Fig. Figure 4 is merely illustrative, and any suitable modification can be made to the timing diagram. For example, the timing diagram 400 can be adapted to an SH circuit arrangement 230 with 3, 4, or more SH branches, for example, for use with the one described in Fig. Figure 3 illustrated the SH circuit arrangement 230 with four branches. As discussed above, additional reset scans can be performed with additional T CMS The images can be captured at intervals, and additional image scans can be acquired in a staggered manner. Furthermore, the image signals can be acquired before the reset scans, if desired.

[0083] Therefore, implementations of an ADC 200 with a two-branch SH circuit arrangement 230 as described herein perform analog CMS2 without requiring additional capacitor area, offer better DCDS flicker noise suppression, and require less time compared to other digital and analog CMS techniques that require additional capacitors or capacitor area, additional T CMSrequire and offer lower DCDS flicker suppression. These benefits extend to implementations of the SH circuit arrangement 230 with more than two SH branches, such as in Fig. 3 illustrated.

[0084] As described above, if each SH branch of the SH circuit arrangement 230 samples a reset or image signal and each corresponding DAC participates in the A / D conversion, the ADC 200 can provide unity gain. Advantageously, the systems and methods described herein also allow selectable gain in the ADC 200 by appropriate control of the ADC 200.

[0085] Fig. Figure 5 illustrates an exemplary gain selection method 500 for implementing selectable gain via the ADC 200 for a four-branch SH circuit arrangement 230, as described in relation to Fig. 3 described. In step 505, a unity gain (1x gain) can be selected for the ADC 200. In step 510, the sampling and conversion described above can be continued, for example, using each of the SH branches 240, 250, 300, 310 and the corresponding DACs 280, 285, 320, 330 to sample and A / D convert the four sampled reset signal values ​​and the four sampled video signal values, as described in the Fig. 3 and Fig. As described in section 4. In step 515, the readout circuitry 150 can then determine the final unity-gain pixel value in the ADC 200 by subtracting the unity-gain digital image value from the unity-gain digital reset value. It should be noted that other gains may be present in the signal chain of column 155, for example, gains due to conversion gain options in pixel 120, gain from the source-follower transistor 215, gain from amplifier 225, and / or the like.

[0086] In step 520, a gain of 2 (2x gain) can be selected for the ADC 200. In step 525, half of the DACs coupled to the SH circuit arrangement 230 can be AC ​​grounded. For example, in an SH circuit arrangement 230 with four branches, as in Fig. Figure 3 illustrates that the first DAC 280 and the second DAC 285 are AC-grounded. The lower plates of the first and second DACs 280 and 285 can remain AC-grounded, so they do not participate in the conversion process. When one or more of the DACs are AC-grounded, for the same change at output 234 of the SH circuit arrangement, the effective reference for the ungrounded DACs is reduced, thereby increasing the gain. If half of the DACs are AC-grounded, the gain doubles.

[0087] In step 530, sampling and conversion can continue, but only the ungrounded DACs participate in the A / D conversion. For example, the 2x ADC gain mode selected in step 520 can use two of the four SH branches, for example, SH branches 300 and 310, and the corresponding DACs 320 and 330, to sample the reset signal and video signal values ​​and subject them to A / D conversion. In some embodiments, the sampling signals 'SH1', 'SH2', 'SH3', and 'SH4' can remain the same, while the number of DACs 280, 285, 320, and 330 involved in the conversion process is changed. In step 535, the readout circuit arrangement 150 can then determine the final pixel value with 2x gain by subtracting the digital image value with 2x gain from the digital reset value with 2x gain.

[0088] In step 540, a gain of 4 (4x gain) can be selected for the ADC 200. In step 545, three of the four DACs coupled to the SH circuit arrangement 230 can be AC ​​grounded. For example, in an SH circuit arrangement 230 with four branches, as in Fig. Figure 3 illustrates that the first DAC 280, the second DAC 285, and the third DAC 320 are AC grounded. If three of the four DACs are grounded, the gain can be quadrupled. In step 550, sampling and conversion can continue, but only the ungrounded DAC(s) participate in the ADC conversion. For example, the 4x ADC gain mode selected in step 540 can use one of the four SH branches, for example, SH branch 310, and the corresponding DAC 330 to sample and perform ADC conversion on the sampled reset signal and video signal values. In step 555, the readout circuit arrangement 150 can then determine the final pixel value with 4x gain by subtracting the digital image value with 4x gain from the digital reset value with 4x gain.

[0089] In some embodiments, for readouts from pixel 120 that require higher gain, for example, during readouts from pixel 120 with high or medium conversion gain, a higher gain can be selected in the ADC 200, for example, a 2x or 4x gain. The higher-gain ADC mode provides improved low-light sensitivity during high-conversion-gain readouts with reduced ADC quantization noise. In some embodiments, for readouts from pixel 120 that do not require higher gain, for example, during a low-conversion-gain readout, a lower gain can be selected in the ADC 200, for example, a 1x gain. The lower or unity-gain ADC mode maintains the dynamic range during low-conversion-gain readouts.

[0090] Various embodiments therefore provide systems, devices, and methods capable of performing analog CMS readout and conversion with an improved frame rate. Furthermore, with reference to an exemplary four-branch SH circuit arrangement 230, as described in Fig. Figure 3 illustrates the selectable combinations of SH1, SH2, SH3, SH4 and DAC1, DAC2, DAC3, DAC4, providing selectable ADC gains of 1x, 2x, 4x, and CMS2, CMS4. The ADC 200 architecture described herein is further scalable to include additional or fewer SH branches as required. Unlike digital CMS techniques, scaling the ADC 200 as described herein requires only an increase in the time between reset samples (Treset). CMS), but requires no additional A / D conversions. These features and benefits are provided in the ADC 200 with minimal additional complexity or minimal additional active circuitry.

[0091] Exemplary embodiments provide improved low-noise and / or high-speed image sensors. In some cases, read noise can be reduced by more than 30%. Furthermore, the analog CMS systems and methods described herein provide, in some cases, lower power consumption compared to digital CMS systems and methods at the same or lower noise levels. For example, implementing the analog CMS systems and methods described herein can provide exemplary power savings of about 50 mW, which can represent about 10% of the total chip power for modern image sensors. Exemplary systems and methods also provide a higher frame rate compared to digital CMS techniques, for example, an improvement in the frame rate of more than 30% for readouts with high conversion gain (e.g.,using a reinforced SH circuit arrangement 230) and an increase in the overall frame rate of 10%. Systems and methods according to various embodiments can be used as a time- and power-saving replacement for conventional techniques for analog or digital CMS.

[0092] The various components and functions shown and described in the readout circuit arrangement 150 and the ADC 200, as well as their control, as described in the processes of Fig. 4 and Fig. 5. can be distributed among the various components of the image sensor 100 in any suitable manner, and different embodiments can organize the processing of various features and information in any number of different ways. Some of the features and systems described herein can be implemented in software and / or firmware, which resides in non-transient data storage, for execution by one or more processors to perform the various (automated) processes described herein.

[0093] It should be noted that the arrangement of the image sensor 100, the pixel 120, and the readout circuit arrangement 150 described herein is for illustrative purposes only. In general, any desired image sensor circuit arrangements and / or systems can be combined with the one described in the following: Fig. 2 and Fig.The circuit arrangement of the ADC 200 shown in Figure 3 can be used. Furthermore, the circuit arrangements and methods described herein for performing an A / D conversion using an exemplary circuit arrangement of the ADC 200 can be used in conjunction with any number of systems and methods and are not limited to use in conjunction with image or other optical sensors.

[0094] It is understood that the circuit arrangements described herein can alternatively or additionally be implemented as computer instructions (software, firmware, or the like) configured to instruct a processor to perform the functions of the described circuit arrangements. It is also understood that the computer instructions described herein can alternatively or additionally be implemented as a hardware circuit arrangement capable of performing the functions of the described computer instructions.

[0095] In the sense used herein, a node or electrical node can be a point in an electrical network where two or more components are interconnected, enabling the transmission of electrical signals, power, and / or the like. Different components can be coupled if they are electrically connected, whether directly or indirectly (e.g., via intermediate components). According to some embodiments, binary signals can be enabled or disabled, which may involve changing the binary state of the signal from one of two possible states to the other. Enabling a binary signal may, depending on the design choices, involve setting it to the equivalent of a logical high or low state.

[0096] The general concepts set forth herein can be adapted to any number of alternative but equivalent embodiments. The term "exemplary" is used herein to represent an example, instance, or illustration that may have any number of alternatives. Each implementation described herein as "exemplary" is not necessarily to be construed as preferable or advantageous over other implementations, nor is it necessarily intended as a model that must be duplicated in other implementations. Although several exemplary embodiments have been presented in the preceding detailed description, it should be apparent that a large number of alternative but equivalent variations exist, and the examples presented herein are not intended to limit the scope of protection, applicability, or configuration of the invention in any way.In contrast, various changes can be made to the function and arrangement of the described elements without affecting the scope of protection of the claims and their legal equivalents. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 11,722,794

[0017]

Claims

[1] Image sensor, comprising: a pixel that includes an output; and a readout circuit arrangement coupled to the pixel output, wherein the readout circuit arrangement comprises: an amplifier with one input and one output, wherein the input is coupled to the pixel output; and an analog-to-digital converter (ADC), comprising: a sample-and-hold circuit arrangement (SH circuit arrangement), comprising an input, an output, a first SH branch that is coupled between the input of the SH circuit arrangement and the output of the SH circuit arrangement, and a second SH branch, which is coupled in parallel to the first SH branch between the input of the SH circuit arrangement and the output of the SH circuit arrangement, wherein: The input of the SH circuit arrangement is coupled to the output of the amplifier; and the output of the SH circuit arrangement is configured to determine a combined value based on the first SH branch and the second SH branch; a first digital-to-analog converter (DAC) coupled to the first SH branch; and a second DAC, which is coupled to the second SH branch. [2] Image sensor according to claim 1, wherein: the ADC includes a third DAC and a fourth DAC; and the SH circuit arrangement comprises a third SH branch and a fourth SH branch, wherein: the first SH branch, the second SH branch, the third SH branch and the fourth SH branch are coupled in parallel between the input of the SH circuit arrangement and the output of the SH circuit arrangement; the output of the SH circuit arrangement is configured to determine the combined value based on the first SH branch, the second SH branch, the third SH branch, and the fourth SH branch; the third DAC is coupled to the third SH branch; and the fourth DAC is coupled with the fourth SH branch. [3] Image sensor according to claim 1, wherein: the first SH branch comprises a first switch coupled in series with a first capacitor at a first node, with the first DAC being coupled to the first SH branch at the first node; and the second SH branch includes a second switch which is coupled in series with a second capacitor at a second node, with the second DAC being coupled to the second SH branch at the second node. [4] Image sensor according to claim 1, wherein the ADC comprises: a comparator comprising a first input, a second input and an output, wherein: the comparator is configured to provide a comparison result at the comparator output; and the comparison result is based on the first input and the second input; and an ADC control circuit arrangement comprising an input and an output, wherein: the input of the ADC control circuit arrangement is coupled to the comparator output; and The ADC control circuit arrangement is configured to control the first DAC and the second DAC via the output of the ADC control circuit arrangement. [5] Image sensor according to claim 4, wherein: the second input of the comparator is coupled to a reference signal; the comparator is configured to compare the reference signal with the combined value; and The ADC control circuit arrangement is configured to control the first DAC and the second DAC according to a successive approximation (SA) algorithm. [6] Image sensor according to claim 5, wherein: The first DAC includes a first large number of switched capacitors; the second DAC comprises a second set of switched capacitors; the ADC control circuit arrangement is configured to switch the first set of switched capacitors and the second set of switched capacitors according to the SA algorithm; and The ADC is configured to provide a digital representation of the input to the SH circuit arrangement based on one or more comparison results provided by the comparator. [7] Image sensor according to claim 1, wherein the image sensor is configured to: Control the first SH branch to store an initial reset value at an initial time; Control the second SH branch to store a second reset value at a second time; Performing an initial analog-to-digital conversion (AD conversion) of a first combined value using the ADC to generate a digital reset value, where the first combined value is based on the first and second reset values; Controlling the first SH branch to store a first image value at a third time; Controlling the second SH branch to store a second image value at a fourth time; Performing a second ADC conversion of a second combined value using the ADC to generate a digital image value, where the second combined value is based on the first and second image values; and Determining a final pixel value based on the digital image value and the digital reset value. [8] Image sensor according to claim 7, wherein: the second time a period T CMS after the first time, where the period T CMSa minimum time required to provide noise decorrelation; and the fourth time the period T CMS after the third time. [9] Method for performing a readout of an image sensor pixel using an analog-to-digital converter (ADC), comprising: Saving, at a first time and using a first sampling and Hold branch (SH branch) of an SH circuit arrangement, a first reset value based on a first output of the pixel; Store, at a second time and using a second SH branch of the SH circuit arrangement, a second reset value based on the first output, wherein: the first SH branch is coupled in parallel with the second SH branch between an input of the SH circuit arrangement and an output of the SH circuit arrangement; and the output of the SH circuit arrangement provides a combined value based on the first SH branch and the second SH branch; Performing an initial analog-to-digital conversion (AD conversion) of an initial combined value from the output of the SH circuit arrangement using the ADC to generate a digital reset value; Store, at a third time and using the first SH branch, a first image value based on a second output of the pixel; Store, at a fourth time and using the second SH branch, a second image value based on the second output; Performing a second ADC conversion of a second combined value from the output of the SH circuit arrangement using the ADC to generate a digital image value; and Determining a final pixel value based on the digital reset value and the digital image value. [10] The method of claim 9, further comprising: Store, at a fifth time and using a third SH branch of the SH circuit arrangement, a third reset value based on the first output; Store, at a sixth time and using a fourth SH branch of the SH circuit arrangement, a fourth reset value based on the first output; Store, at a seventh time and using the third SH branch, a third image value based on the second output; Store, at an eighth time and using the fourth SH branch, a fourth image value based on the first output, wherein: the first, second, third and fourth SH branches are coupled in parallel between the input of the SH circuit arrangement and the output of the SH circuit arrangement; and The output of the SH circuit arrangement provides the combined value based on the first SH branch, the second SH branch, the third SH branch, and the fourth SH branch. [11] Method according to claim 9, wherein the ADC comprises a first digital-to-analog converter (DAC) coupled to the first SH branch and a second DAC coupled to the second SH branch, and wherein: Performing the first A / D conversion involves simultaneously controlling the first DAC and the second DAC; and Performing the second A / D conversion involves simultaneously controlling the first DAC and the second DAC. [12] Method according to claim 11, wherein performing each AD conversion includes performing a successive approximation algorithm (SA algorithm) by the ADC. [13] Method according to claim 12, wherein: the first DAC comprises a first array of switched capacitors; the second DAC includes a second array of switched capacitors; Controlling the first DAC involves switching the first array of switched capacitors according to the SA algorithm; and Controlling the second DAC involves switching the second array of switched capacitors according to the SA algorithm. [14] Method according to claim 9, wherein determining the final pixel value comprises subtracting the digital reset value from the digital image value. [15] Method according to claim 9, wherein the second time is a period T CMS after the first time, where the period T CMS corresponds to a minimum time required to provide noise decorrelation. [16] Method according to claim 15, wherein the fourth time is the period T CMS after the third time. [17] Analog-to-digital converters (ADCs), comprising: a sample-and-hold circuit arrangement (SH circuit arrangement) comprising an input, an output, a first SH branch coupled between the input of the SH circuit arrangement and the output of the SH circuit arrangement, and a second SH branch coupled in parallel to the first SH branch between the input of the SH circuit arrangement and the output of the SH circuit arrangement, wherein: the input of the SH circuit arrangement is coupled to an input of the ADC; and the output of the SH circuit arrangement is configured to determine a combined value based on the first SH branch and the second SH branch; a first digital-to-analog converter (DAC) coupled to a sample-hold node of the first SH branch; and a second DAC that is coupled to the sample-hold node of the second SH branch. [18] ADC according to claim 17, further comprising: a comparator comprising a first input, a second input and an output, wherein: the comparator is configured to provide a comparison result at the comparator output based on the first and second comparator inputs; and an ADC control circuit arrangement comprising an input and an output, wherein: the input of the ADC control circuit arrangement is coupled to the comparator output; and The ADC control circuit arrangement is configured to control the first DAC and the second DAC via the output of the ADC control circuit arrangement. [19] ADC according to claim 18, wherein the ADC control circuit arrangement is configured to control the first DAC and the second DAC according to a successive approximation (SA) algorithm. [20] ADC according to claim 19, wherein: The first DAC includes a first large number of switched capacitors; the second DAC comprises a second set of switched capacitors; the ADC control circuit arrangement is configured to switch the first set of switched capacitors and the second set of switched capacitors according to the SA algorithm; and The ADC is configured to provide a digital representation of the input to the SH circuit arrangement based on one or more comparison results provided by the comparator.

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