INTEGRATED CIRCUIT AND LAYOUT METHOD FOR STANDARD CELL STRUCTURES

Abstract

An integrated circuit comprises multiple cells that are adjacent to one another, each cell corresponding to a specific circuit component. Each cell comprises: multiple active regions extending along a first lateral direction; multiple gate structures extending along a second lateral direction perpendicular to the first lateral direction and traversing one or more of the active regions; multiple first interconnect structures extending along the first lateral direction and arranged vertically above the gate structures; and multiple second interconnect structures extending along the second lateral direction and arranged vertically above the first interconnect structures. Each of the second interconnect structures is offset from a corresponding gate structure by a distance along the first lateral direction.

Description

CROSS-REFERENCE TO RELATED REGISTRATION

[0001] This application claims priority over the preliminary US application No. 63 / 690,477, filed on September 4, 2024, entitled “METALLIZATION LAYER SHIFT FORAUTO PLACE AND ROUTE”, which is hereby incorporated by reference in full and for all purposes into the present text. BACKGROUND

[0002] The integrated semiconductor (IC) industry has experienced exponential growth. Semiconductor IC design typically employs standard cell methodologies for designing semiconductor devices on a single chip. These methodologies use standard cells as abstract representations of specific functions to integrate millions of devices onto a single chip. As ICs continue to miniaturize, more and more devices are integrated onto a single chip. This miniaturization process generally delivers benefits by increasing production efficiency and reducing manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood with reference to the following detailed description, when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various structural elements are not drawn to scale. Rather, the dimensions of the various structural elements may be enlarged or reduced as necessary for the sake of clarity in this discussion. Fig. Figure 1 illustrates a layout of an exemplary standard cell having M1 conductor tracks shifted in a first direction, according to some embodiments. Fig. Figure 2 illustrates a layout of an exemplary standard cell which has M1 conductor tracks shifted in a second, opposite direction, according to some embodiments. Fig. Figure 3 illustrates a layout that includes one or more of the features shown in Fig. 1 standard cells shown and one or more of the ones in Fig. 2 standard cells shown, according to some embodiments. Fig. Figure 4 illustrates a cross-sectional view of an exemplary semiconductor device according to some embodiments. Fig. Figure 5 illustrates a layout of an exemplary standard cell having M1 conductor tracks shifted in a first direction, according to some embodiments. Fig. Figure 6 illustrates a layout of an exemplary standard cell which has M1 conductor tracks shifted in a second, opposite direction, according to some embodiments. Fig. Figure 7 illustrates a layout of an exemplary standard cell having M1 conductor tracks shifted in a first direction, according to some embodiments. Fig. Figure 8 illustrates a layout of an exemplary standard cell which has M1 conductor tracks shifted in a second, opposite direction, according to some embodiments. Fig. Figure 9 illustrates a layout of an exemplary standard cell having M1 conductor tracks shifted in a first direction, according to some embodiments. Fig. Figure 10 illustrates a layout of an exemplary standard cell which has M1 conductor tracks shifted in a second, opposite direction, according to some embodiments. Fig. Figure 11 illustrates a layout of an exemplary standard cell having M1 conductor tracks shifted in a first direction, according to some embodiments. Fig. Figure 12 illustrates a layout of an exemplary standard cell which has M1 conductor tracks shifted in a second, opposite direction, according to some embodiments. Fig. Figure 13 illustrates an exemplary flowchart of a method for optimizing cell placement according to some embodiments. Fig. Figure 14 illustrates an exemplary computer system for implementing the disclosed method according to some embodiments. Fig. Figure 15 illustrates an exemplary flowchart of a method for forming standard cell structures according to some embodiments. Fig. Figure 16 illustrates a flowchart of a procedure for forming a section of an integrated circuit based on the layout of Fig. 1 and / or the layout of Fig. 2 according to some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the subject matter discussed herein. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not intended to limit the scope of the disclosure. For example, the formation of a first structural element above or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, so that the first and second structural elements are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not automatically create a relationship between the various designs and / or facilities discussed.

[0005] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," "above," "below," and the like, may be used in this text to simplify the description and to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated by 90 degrees, or in other orientations), and the spatially relative descriptors used in this text may be interpreted accordingly.

[0006] In general, standard cell methodologies design integrated circuits by placing various standard cells with different functions. These standard cells can be, for example, logic gates such as AND gates, OR gates, XOR gates, NOT gates, NAND gates, NOR gates, and XNOR gates, and combinational logic circuits such as multiplexers, flip-flops, adders, and counters. Standard cells can be implemented to realize complex IC functions. To simplify integrated circuit design, a library is created that includes commonly used standard cells and their corresponding layouts.Accordingly, when designing an integrated circuit, a designer can select desired standard cells from the library and place the selected standard cells in an automatic placement and routing block to generate a layout of the integrated circuit.

[0007] For example, when designing an integrated circuit with specific functions, standard cells are selected from a previously created standard cell library. Next, designers or EDA (Electronic Design Automation) or ECAD (Electronic Computer-Aided Design) tools create design layouts of the integrated circuit, incorporating the selected standard and / or non-standard cells. These design layouts are then converted into photomasks. Finally, integrated semiconductor circuits can be fabricated by transferring arrangements of different layers, defined by photographic processes using the photomasks, onto a substrate.

[0008] The existing standard cells typically comprise one or more active regions extending in a first lateral direction and one or more gate structures extending in a second, perpendicular lateral direction, thereby operationally forming a specific number of transistors. Each of the existing standard cells further comprises a plurality of middle-end and back-end interconnect structures that connect the transistors or provide input / output pins, thereby operationally realizing a specific circuit function. The middle-end interconnect structures can be formed across the transistors (for example, the active regions and the gate structures) to extend or permit their electrical connection, and the back-end interconnect structures can be formed across multiple metallization layers arranged above those middle-end interconnect structures.

[0009] For example, a first group of back-end interconnect structures can be formed in one of the lowest metallization layers (sometimes referred to as Mo traces), a second group of back-end interconnect structures can be formed in one of the second-lowest metallization layers (sometimes referred to as M1 traces), and so on. Typically, the Mo traces extend in the same direction as the active regions (for example, in the first lateral direction), and the M1 traces extend in the same direction as the gate structures (for example, in the second lateral direction). Furthermore, in existing standard cell methodologies, the M1 traces are often restricted in such a way that they overlap the gate structures or the middle-end interconnect structures.Such a constraint forces some of the Mo traces to extend beyond the boundary of each standard cell, which adversely limits the flexibility in arranging the standard cells. For example, if some of the Mo traces extend beyond the boundary, adjacent to two or more such standard cells can cause some of the traces to be short-circuited in an undesirable way. Therefore, existing standard cell methodologies are not entirely satisfactory in several respects.

[0010] This disclosure provides various embodiments of systems and methods for the design of an integrated circuit using novel standard cells whose M1 traces are each offset by a distance from corresponding gate structures. For example, the standard cell disclosed herein may have a number of active regions extending in a first lateral direction and a number of gate structures extending in a second lateral direction perpendicular to the first lateral direction. The (mutually parallel) gate structures are spaced apart from each other by a first distance along the first lateral direction. Above the active regions and the gate structures, the standard cell may have a number of Mo traces extending in the first lateral direction and a number of M1 traces extending in the second lateral direction.In various embodiments, each of the M1 traces, instead of overlapping a corresponding gate structure, can be offset by a second distance along the first lateral direction from the gate structure. The second distance can be equal to or less than half the first distance. In this way, more access points on the Mo traces can be made available. Furthermore, each of the Mo traces can be prevented from extending beyond the cell boundary. Or, put another way, the disclosed standard cell may not have any M0 trace extending beyond the corresponding cell boundary. Consequently, using the disclosed standard cells to form an integrated circuit can significantly improve the flexibility in placing similar standard cells and advantageously increase the density of standard cells in a given area.

[0011] Fig. 1 and Fig. Figure 2 illustrates layouts of exemplary standard cells 100 and 200 according to some embodiments. Standard cells 100 and 200 can operationally correspond to the same circuit component, for example, an AND-OR inverter. It is understood that the layouts shown in Figure 2 are not intended to be interpreted in this way. Fig. 1 and Fig. The standard cells 100 and 200 shown have been simplified, and thus each of the layouts can have any number of different other components (for example, arrangements for forming respective structures) without leaving the scope of protection of the present disclosure.

[0012] Generally, each of the in Fig. 1 and Fig. The layouts shown in Figure 2 (and the following figures) represent a plurality of arrangements configured to form various structures, such as gate structures, middle-end interconnect structures, via structures, back-end interconnect structures, etc. Accordingly, such arrangements of the disclosed layouts will be referred to in the following discussion as the structures to be formed.

[0013] We turn first Fig. 1. Standard cell 100 has a cell boundary 101. A cell boundary is a virtual line that can define the cell region of a corresponding standard cell, and the cell regions of neighboring standard cells do not overlap.Surrounded by the cell boundary 101, the standard cell 100 can have: one or more active regions 102 and 104 extending in the X direction, gate structures 110, 112, 114, 116, 118 and 120 extending in the Y direction, middle-end interconnect structures 121-1, 121-2, 121-3, 121-4 and 121-5 extending in the Y direction, first via structures 122, 124, 126, 128 and 130, second via structures 132, 134, 136 and 138, first back-end interconnect structures 140, 142, 144, 146, 148, 150, 152 and 154, which extend in the X direction, third via structures 156, 158, 160, 162 and 164, and second back-end interconnect structures 166, 168, 170, 172 and 174, which extend in the Y direction.

[0014] In some embodiments, Standard Cell 100 transistors can each be configured as a gate-all-around transistor (GAA transistor). A GAA transistor can have a gate structure that wraps around each of several semiconductor nanostructures that together serve as its channel, with its source / drain structures physically located on opposite sides of the gate structure and electrically coupled to the channel. However, Standard Cell 100 transistors can also be configured as any of several other transistor structures without exceeding the scope of protection of this disclosure. For example, Standard Cell 100 transistors can be configured as fin-based field-effect transistors (FinFETs), planar transistors, complementary FETs (CFETs), nanowire transistors, and so on.

[0015] In the example of GAA transistor structures, the active regions 102 and 104 can each be formed as a stacked structure projecting from the front face of a substrate. The stack comprises a number of first semiconductor nanostructures (e.g., nanolayers) and second semiconductor nanostructures (e.g., nanolayers) extending along the X-direction, with the first and second semiconductor nanostructures stacked alternately. Following the formation of the stack, a number of dummy gate structures (e.g., polysilicon gate structures) can be added, defined by the Fig. The gate structures 110 to 120 shown in Figure 1 are defined such that they lie above the stack defined by the [unclear text]. Fig. The active regions 102 and 104 shown in Figure 1 are defined. Next, respective sections of the first and second semiconductor nanostructures remain in the stack, over which the dummy gate structures are placed, while other sections are replaced by a number of epitaxial structures. Next, the dummy gate structures, along with the remaining sections of the second semiconductor nanostructures, are replaced by a number of active (e.g., metallic) gate structures.The remaining sections of the first semiconductor nanostructures can be configured as the channel of a corresponding transistor, and the epitaxial structures coupled to both ends of the channel (for example, along the X direction) can be configured as source / drain structures (or source / drain terminals) of the transistor, and the active gate structures that lie over the remaining sections of the first semiconductor nanostructures (for example, wrapping around them) can be configured as a gate terminal of the transistor.

[0016] Following the formation of the transistors (based on the active regions 102 to 104 and the gate structures 110 to 120), the middle-end interconnect structures 121-1 to 121-5 can be formed such that each electrically contacts the epitaxial structure (the source / drain terminal) of a corresponding transistor. These middle-end interconnect structures 121-1 to 121-5 generally extend in the Y direction and are each located between adjacent gate structures 110 to 120. As a representative example, middle-end interconnect structure 121-1 is located between gate structures 110 and 112. Furthermore, each of the middle-end interconnect structures 121-1 to 121-5 is spaced from each of the corresponding gate structures (for example, the nearest gate structure) by half a distance “D1”, which separates the gate structures along the X direction.This separation distance D1 is sometimes also referred to as a grid spacing of the gate structures 110 to 120. Such middle-end interconnect structures 121-1 to 121-5 are sometimes referred to as MDs.

[0017] Following the formation of MDs 121-1 to 121-5, the first via structures 122 to 130 and the second via structures 132 to 138 can be formed. The first via structures 122 to 130 are each coupled to a corresponding MD 121-1 to 121-5, and the second via structures 132 to 138 are each coupled to a corresponding gate structure 110 to 120. The first via structures 122 to 130 are sometimes referred to as VDs, and the second via structures 132 to 138 are sometimes referred to as VGs.These VDs and VGs allow the underlying source / drain connections (through the MDs) and gate connections to be electrically connected to the respective back-end interconnect structures (for example, the first back-end interconnect structures 140 to 154, the second back-end interconnect structures 166 to 174), which will be discussed below.

[0018] In some embodiments, the first back-end interconnect structures 140 to 154 can extend in the same direction as the active regions 102 and 104 (for example, in the X direction) and be formed in one of several metallization layers arranged above the front surface of the substrate. Each of these metallization layers can have (for example, embed) a plurality of metal conductors in one or more dielectric layers (formed, for example, from an oxide material or a dielectric material with a low k-value). Such a bottom metallization layer is sometimes referred to as the M0 layer, and accordingly, the first back-end interconnect structures 140 to 154 can sometimes be referred to as M0 conductors.The second back-end interconnect structures 166 to 174 can extend in the same direction as the gate structures (for example, in the Y direction) and be formed in a second-lowest of several metallization layers. This second-lowest metallization layer is sometimes referred to as the M1 layer, and accordingly, the second back-end interconnect structures 166 to 174 can sometimes be referred to as M1 traces. The M0 traces (for example, 140 to 154) can each be coupled to a corresponding M1 trace (for example, 166 to 174) through one or more of the third via structures 156 to 164, which are sometimes referred to as Vos.

[0019] As in Fig. As shown in Figure 1, the M0 traces 140 and 154, which are formed along the edges of the cell boundary 101, can be configured as busbars to carry a first supply voltage (e.g., VDD) and a second supply voltage (e.g., VSS), respectively. The M0 trace 142 can be coupled through the VDs 122, 124, and 126 to the underlying MDs 121-1, 121-3, and 121-5e, respectively. The M0 trace 144 can be coupled through the VG 132 to the gate structure 114. The M0 trace 146 can be coupled through the VG 134 to the gate structure 116. The M0 trace 148 can be coupled through the VG 136 to the gate structure 118. M0 conductor 150 can be connected to gate structure 112 through VG 138. M0 conductor 152 can be connected to MDs 121-3 and 121-4 below them through VDs 128 and 130, respectively.M1 conductor 166 can be connected to M0 conductor 144 via V0 156. M1 conductor 168 can be connected to M0 conductor 150 via Vo 162. M1 conductor 170 can be connected to M0 conductor 146 via V0 158. M1 conductor 172 can be connected to M0 conductor 152 via Vo 164. M1 conductor 174 can be connected to M0 conductor 148 via V0 160.

[0020] In some embodiments of the present disclosure, the M1 conductor tracks 166 to 174 are displaced in the X-direction away from the respective gate structures 112 to 120. More precisely, each of the M1 conductor tracks 166 to 174 is displaced to the left by a distance "D2" from a corresponding (for example, nearest) gate structure 112 to 120. The distance D2 can be equal to or less than half the separation distance D1 (for example, the grid spacing of the gate structures 110 to 120). Adjacent MDs 121-1 to 121-5 can be separated by the same grid spacing D1. Accordingly, each of the M1 conductor tracks 166 to 174 can be described as being displaced by a distance (for example, D1 - D2) in the direction of a corresponding MD 121-1 to 121-5.By laterally shifting the M1 traces with respect to the corresponding gate structures or MDs, more access points can be provided on some of the M0 traces, which advantageously ensures that none of the M0 traces extend beyond cell boundary 101 (as in . Fig. 1 shown).

[0021] We will turn next Fig. 2. The standard cell 200 is essentially similar to the standard cell 100, except that the M1 conductor tracks of the standard cell 200 may be shifted to the right of the respective gate structures.For example, the standard cell 200 has a cell boundary 201, and surrounded by the cell boundary 201, the standard cell 200 can have: one or more active regions 202 and 204 extending in the X direction, gate structures 210, 212, 214, 216, 218 and 220 extending in the Y direction, middle-end interconnect structures (MDs) 221-1, 221-2, 221-3, 221-4 and 221-5 extending in the Y direction, first via structures (VDs) 222, 224, 226, 228 and 230, second via structures (VGs) 232, 234, 236 and 238, first back-end interconnect structures (M0 traces) 240, 242, 244, 246, 248, 250, 252, and 254 extending in the X direction, third via structures (V0s) 256, 258, 260, 262, and 264, and second back-end interconnect structures (M1 traces) 266, 268, 270, 272, and 274 extending in the Y direction.

[0022] More precisely, each of the M1 traces 266 to 274 is shifted to the right by a distance "D2" from a corresponding (for example, nearest) gate structure 212 to 220. The distance D2 can be equal to or less than half the separation distance D1 (for example, the grid spacing of gate structures 210 to 220). Adjacent MDs 221-1 to 221-5 can be separated by the same grid spacing D1. Accordingly, each of the M1 traces 266 to 274 can be described as shifted by a distance (for example, D1 - D2) in the direction of a corresponding MD 221-1 to 221-5. By laterally shifting the M1 traces relative to the corresponding gate structures or MDs, more access points can be provided on some of the M0 traces, which advantageously prevents any of the M0 traces from extending beyond cell boundary 201 (as in Fig. 2 shown).

[0023] Using these two types of standard cells, 100 and 200 (corresponding to the same circuit component), an integrated circuit can be constructed to contain a larger number of the component. For example, a standard cell 200 can be flipped with respect to the Y-direction and freely inserted into any adjacent standard cell 100 arranged along the X-direction, or a standard cell 100 can be flipped with respect to the Y-direction and freely inserted into any adjacent standard cell 200 arranged along the X-direction. In other words, each standard cell 200 or 100 can be placed between a pair of standard cells 100 or 200 after being flipped. By flipping some of the standard cells and inserting them into adjacent ones, the standard cell density can be significantly increased.Since none of the M0 conductor tracks (of the standard cell 100 or 200) protrude beyond their cell boundary, the insertion of the inverted standard cell into the adjacent, non-inverted standard cells can take place without causing a short circuit with the respective metal conductor tracks.

[0024] Fig. Figure 3 illustrates a section of a layout 300 for forming an integrated circuit according to some embodiments. The layout 300 can comprise two of the standard cells 100, which accommodate one of the inverted standard cells 200 between them. It should be noted that—for clarity only—some of the components of the standard cells 100 and 200 (for example, the active regions 102–104, the MDs 121-1 to 121-5, the M0 traces 140 to 154, the active regions 202–204, the MDs 221-1 to 221-5, the M0 traces 240 to 254) in Fig. Figure 3 is not shown. As shown, after inverting the standard cell 200, the M1 traces 266 to 274 are each shifted to the left of the corresponding gate structure. Thus, all M1 traces across the entire layout 300 are shifted in the same direction, which can advantageously maximize the density of standard cells that can be placed in a given area.

[0025] Fig. Figure 4 illustrates a cross-sectional view of a section of a semiconductor device 400, which includes the components based on the one described in Fig. 1 or Fig. The layouts shown in the two examples were formed according to some embodiments. For example, the cross-sectional view of Fig. 4. Cut along the longitudinal direction of an active region (for example, the X-direction). It should be noted that the cross-sectional view of Fig. 4 serves only illustrative purposes and does not intend to limit the scope of protection of the present disclosure.

[0026] As shown, the semiconductor device 400 comprises a number of nanostructures 401 extending in the X direction and arranged over a substrate. The nanostructures 401 are vertically spaced apart. Each of the nanostructures 401 has a first end and a second end connected to a first epitaxial structure 402 and a second epitaxial structure 402. A gate structure 404 surrounds each of the nanostructures 401. The nanostructures 401 can operatively serve as the channel of a transistor. Furthermore, the epitaxial structures 402 can operatively serve as the source and drain terminals of the transistor, and the gate structure 404 can operatively serve as a gate terminal of the transistor. The nanostructures, the epitaxial structures, and the gate structures are generally referred to as part of the front-end processing. In some embodiments, the nanostructures 401 can be configured based on the active region of the Fig. 1 and Fig. The two layouts shown can be formed, and the gate structure 404 can be based on the gate structures of the one shown in Fig. 1 and Fig. The two layouts shown can be created.

[0027] The semiconductor device 400 further comprises an MD 406 connected to the epitaxial structure 402, a VG 408 connected to the gate structure 404, and a VD 410 connected to the MD 406. The MD 406 can extend along the same direction as the gate structure 404 (for example, the Y direction). In some embodiments, the MDs, VDs, and VGs are generally referred to as part of the middle-end processing. The semiconductor device 400 further comprises a number of M0 traces 412, some of which are connected to the VD and some of which are connected to the VG, and a number of M1 traces 416, each of which is coupled to a corresponding M0 trace 412 through a V0 414.The M0 traces 412 can extend along the same direction as the nanostructures 401 (for example, the X-direction), and the M1 traces 416 can extend along the same direction as the gate structure 404 (for example, the Y-direction). In some embodiments, the Mo traces, the Vos, and the M1 traces are generally referred to as part of the back-end processing.

[0028] Fig. 5 and Fig. Figure 6 illustrates layouts of exemplary standard cells 500 and 500 according to some embodiments. The standard cells 500 and 600 can operationally correspond to the same circuit component, for example, an inverter. It is understood that the layouts shown in Figure 6 are not representative of the standard cell configurations. Fig. 5 and Fig. The standard cells 500 and 600 shown in the 6 have been simplified, and thus each of the layouts can have any number of different other components (for example, arrangements for forming respective active regions, MDs, etc.) without leaving the scope of protection of the present disclosure.

[0029] We turn first Fig. 5 to. The standard cell 500 has a cell boundary 501. Surrounded by the cell boundary 501, the standard cell 500 can have: one or more active regions extending in the X direction (not shown for clarity), gate structures 510, 212, and 514 extending in the Y direction, MDs extending in the Y direction (not shown for clarity), VDs 522, 524, and 526, VG 532, M0 traces 540, 542, 544, and 546 extending in the X direction, Vos 556 and 558, and M1 traces 566 and 568. As shown, the M1 trace 566 is located from the gate structure 512 by a distance D2, which is equal to or less than the Gate grid spacing D1 can be shifted to the right, and the M1 conductor track 568 is shifted to the right from the gate structure 510 by the distance D2.

[0030] We will turn next Fig. 6 to. The standard cell 600 has a cell boundary 601. Surrounded by the cell boundary 601, the standard cell 600 can have: one or more active regions extending in the X direction (not shown for clarity), gate structures 610, 612, and 614 extending in the Y direction, MDs extending in the Y direction (not shown for clarity), VDs 622, 624, and 626, VG 632, M0 traces 640, 642, 644, and 646 extending in the X direction, Vos 656 and 658, and M1 traces 666 and 668. As shown, the M1 trace 666 is located from the gate structure 614 by a distance D2, which is equal to or less than the The gate grid spacing D1 can be shifted to the left, and the M1 conductor track 668 is shifted to the left of the gate structure 612 by the distance D2.

[0031] Fig. 7 and Fig. Figure 8 illustrates layouts of exemplary standard cells 700 and 800 according to some embodiments. Standard cells 700 and 800 can operationally correspond to the same circuit component, for example, an AND gate. It is understood that the layouts shown in Figure 8 are not representative of standard cells 700 and 800. Fig. 7 and Fig. The standard cells 700 and 800 shown in the 8 have been simplified, and thus each of the layouts can have any number of different other components (for example, arrangements for forming respective active regions, MDs, etc.) without leaving the scope of protection of the present disclosure.

[0032] We turn first Fig. 7. The standard cell 700 has a cell boundary 701. Surrounded by the cell boundary 701, the standard cell 700 can have: one or more active regions extending in the X direction (not shown for clarity), gate structures 710, 712, 714, 716 and 718 extending in the Y direction, MDs extending in the Y direction (not shown for clarity), VDs 722, 724, 726, 728, 730 and 732, VGs 734, 736 and 738, M0 traces 740, 742, 744, 746, 748, 750 and 752 extending in the X direction, Vos 756, 758, 760, 762 and 764, and M1 conductor tracks 766, 768, 770 and 772.As shown, the M1 conductor 766 is shifted to the right from the gate structure 710 by a distance D2, which can be equal to or less than the gate grid spacing D1, the M1 conductor 768 is shifted to the right from the gate structure 712 by a distance D2, the M1 conductor 770 is shifted to the right from the gate structure 714 by a distance D2, and the M1 conductor 772 is shifted to the right from the gate structure 716 by a distance D2.

[0033] We turn first Fig. 8. The standard cell 800 has a cell boundary 801. Surrounded by the cell boundary 801, the standard cell 800 can have: one or more active regions extending in the X direction (not shown for clarity), gate structures 810, 812, 814, 816 and 818 extending in the Y direction, MDs extending in the Y direction (not shown for clarity), VDs 822, 824, 826, 828, 830 and 832, VGs 834, 836 and 838, M0 traces 840, 842, 844, 846, 848, 850 and 852 extending in the X direction, Vos 856, 858, 860, 862 and 864, and M1 conductor tracks 866, 868, 870 and 872.As shown, the M1 conductor 866 is shifted to the left of the gate structure 812 by a distance D2, which can be equal to or less than the gate grid spacing D1; the M1 conductor 868 is shifted to the left of the gate structure 814 by a distance D2; the M1 conductor 870 is shifted to the left of the gate structure 816 by a distance D2; and the M1 conductor 872 is shifted to the left of the gate structure 818 by a distance D2.

[0034] Fig. 9 and Fig. Figure 10 illustrates layouts of exemplary standard cells 900 and 1000 according to some embodiments. The standard cells 900 and 1000 can operationally correspond to the same circuit component, for example, a flip-flop. It is understood that the layouts shown in Figure 10 are not representative of the standard cell 900 and 1000. Fig. 9 and Fig. The standard cells 900 and 1000 shown in Figure 10 have been simplified, and thus each of the layouts can have any number of different other components (for example, arrangements for forming respective active regions, MDs, VDs, VGs, etc.) without leaving the scope of protection of the present disclosure.

[0035] We turn first Fig. 9 to. The standard cell 900 has a cell boundary 901. Within the cell boundary 901, the standard cell 900 can have: one or more active regions extending in the X direction (not shown for clarity), gate structures 910, 911, 912, 913, 914, 915, 916 and 917 extending in the Y direction, MDs extending in the Y direction (not shown for clarity), M0 traces 940, 941, 942, 943, 944, 945, 946, 947, 948, 949, 950, 951 and 952 extending in the X direction, and M1 traces 960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970 and 971.As shown, M1 traces 960 and 961 are each shifted to the right of gate structure 910 by a distance D2, which can be equal to or less than the gate grid spacing D1; M1 traces 962, 963, and 964 are each shifted to the right of gate structure 911 by a distance D2; M1 traces 965 and 966 are each shifted to the right of gate structure 912 by a distance D2; M1 trace 967 is shifted to the right of gate structure 913 by a distance D2; M1 trace 968 is shifted to the right of gate structure 914 by a distance D2; M1 trace 969 is shifted to the right of gate structure 915 by a distance D2; and M1 traces 970 and 971 are Each is shifted to the right by a distance D2 from gate structure 916.

[0036] We will turn next Fig. 10 to. The standard cell 1000 has a cell boundary 1001. Within cell boundary 1001, the standard cell 1000 can contain: one or more active regions extending in the X direction (not shown for clarity), gate structures 1010, 1011, 1012, 1013, 1014, 1015, 1016, and 1017 extending in the Y direction, MDs extending in the Y direction (not shown for clarity), and M0 traces 1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, and 1052 extending in the X direction. and M1 conductor tracks 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071 and 1072.As shown, M1 traces 1060 and 1061 are each shifted to the left of gate structure 1011 by a distance D2, which can be equal to or less than the gate grid spacing D1; M1 traces 1062, 1063, and 1064 are each shifted to the left of gate structure 1012 by a distance D2; M1 traces 1065 and 1066 are each shifted to the left of gate structure 1013 by a distance D2; M1 traces 1067 and 1068 are each shifted to the left of gate structure 1014 by a distance D2; M1 trace 1069 is shifted to the left of gate structure 1015 by a distance D2; and M1 traces 1070 and 1071 are each shifted from gate structure 1015 by a distance D2. 1016 is shifted to the left by a distance D2, and the M1 conductor track 1072 is shifted to the left by a distance D2 from the gate structure 1017.

[0037] Fig. 11 and Fig. Figure 12 illustrates layouts of exemplary standard cells 1100 and 1200 according to some embodiments. The standard cells 1100 and 1200 can operationally correspond to the same circuit component, for example, a flip-flop. It is understood that the layouts shown in Figure 12 are not representative of the standard cell 1100 and 1200. Fig. 11 and Fig. The standard cells 1100 and 1200 shown in Figure 12 have been simplified, and thus each of the layouts can have any number of different other components (for example, arrangements for forming respective active regions, MDs, VDs, VGs, etc.) without leaving the scope of protection of the present disclosure.

[0038] We turn first Fig. 11 to. The standard cell 1100 has a cell boundary 1101. Within the cell boundary 1101, the standard cell 1100 can have: one or more active regions extending in the X direction (not shown for clarity), gate structures 1110, 1111, 1112, 1113, 1114, 1115, 1116 and 1117 extending in the Y direction, MDs extending in the Y direction (not shown for clarity), M0 traces 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151 and 1152 extending in the X direction, and M1 conductor tracks 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167, 1168 and 1169.As shown, M1 traces 1160 and 1161 are each shifted to the right of gate structure 1110 by a distance D2, which can be equal to or less than the gate grid spacing D1; M1 trace 1162 is shifted to the right of gate structure 1111 by a distance D2; M1 traces 1163 and 1164 are each shifted to the right of gate structure 1112 by a distance D2; M1 trace 1165 is shifted to the right of gate structure 1113 by a distance D2; M1 trace 1166 is shifted to the right of gate structure 1114 by a distance D2; M1 trace 1167 is shifted to the right of gate structure 1115 by a distance D2; and M1 traces 1168 and 1169 are each shifted to the right of gate structure 1116 by a distance D2.

[0039] We will turn next Fig. 12 to. The standard cell 1200 has a cell boundary 1201. Within the cell boundary 1201, the standard cell 1200 can have: one or more active regions extending in the X direction (not shown for clarity), gate structures 1210, 1211, 1212, 1213, 1214, 1215, 1216 and 1217 extending in the Y direction, MDs extending in the Y direction (not shown for clarity), M0 traces 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247, 1248, 1249, 1250, 1251 and 1252 extending in the X direction, and M1 conductor tracks 1260, 1261, 1262, 1263, 1264, 1265, 1266, 1267, 1268, 1269 and 1270.As shown, M1 traces 1260 and 1261 are each shifted to the left of gate structure 1211 by a distance D2, which can be equal to or less than the gate grid spacing D1; M1 trace 1262 is shifted to the left of gate structure 1212 by a distance D2; M1 traces 1263 and 1264 are each shifted to the left of gate structure 1213 by a distance D2; M1 traces 1265 and 1266 are each shifted to the left of gate structure 1214 by a distance D2; M1 trace 1267 is shifted to the left of gate structure 1215 by a distance D2; M1 trace 1268 is shifted to the left of gate structure 1216 by a distance D2; and the M1 traces 1269 and 1270 are each shifted to the left of gate structure 1217 by a distance D2.

[0040] Fig. Figure 13 illustrates a flowchart of a method 1300 for optimizing standard cell layout designs in integrated circuits according to some embodiments. The method 1300 can be part of a method for fabricating an integrated circuit. For example, the sequence of the method 1300 can be configured to fabricate an integrated circuit based on the Fig. to produce the layouts (or standard cells) shown in Figures 1-12. Accordingly, the following discussion of Procedure 1300 may occasionally refer to the figures above. It should be noted that the in Fig. The 13 shown in Procedure 1300 is merely an example and it is not intended to limit the present disclosure. Therefore, it is understood that the sequence of operations in Procedure 1300 is not limited to the present disclosure. Fig. 13 can be amended. For example, additional operations may be provided before, during, and after procedure 1300, and some operations may only be briefly described here.

[0041] Method 1300 can begin with operation 1310, where a first standard cell is provided that has a number of first gate structures and a number of first M1 traces, the first M1 traces being offset to the left of the first gate structures by a distance. In some embodiments, the first gate structures and the first M1 traces can extend along the same lateral direction. Using the layout of the in Fig. In the standard cell 100 shown as an example, the first standard cell 100 comprises the first gate structures 110 to 120 and the first M1 traces 166 to 174, extending in the Y direction. Furthermore, the first standard cell 100 may include the active regions 102-104, extending in the X direction, the M0 traces 140 to 154, also extending in the X direction, and a plurality of via structures (for example, VDs 122-130, VGs 132-138, V0s 156-164). In some embodiments, each of the first M1 traces 166 to 174 is shifted to the left by a distance D2 from a corresponding (for example, nearest) first gate structure 110 to 120. The distance D2 can be equal to or less than the gate grid spacing D1.

[0042] Method 1300 can proceed to Operation 1320, where a second standard cell is provided, comprising a number of second gate structures and a number of second M1 traces, the second M1 traces being offset to the right of the second gate structures by a distance. In some embodiments, the second gate structures and the second M1 traces may extend along the same lateral direction. Using the layout of the in Fig. In the standard cell 200 shown as an example, the first standard cell 200 comprises the second gate structures 210 to 220 and the second M1 traces 266 to 274, which extend in the Y direction. Furthermore, the second standard cell 200 can include the active regions 202-204, which extend in the X direction, the M0 traces 240 to 254, which extend in the X direction, and a plurality of via structures (for example, VDs 222-230, VGs 232-238, V0s 256-264). In some embodiments, each of the second M1 traces 266 to 274 is shifted to the right by a distance D2 from a corresponding (for example, nearest) second gate structure 210 to 220. The distance D2 can be equal to or less than the gate grid spacing D1.

[0043] Procedure 1300 can proceed to operation 1330, where the second standard cell is flipped. As in Fig. As shown in Figure 3, standard cell 200 can be reversed with respect to the Y-direction. After reversal, the second M1 traces 266 to 274 of standard cell 200 can be shifted to the left. That is, each of the second M1 traces 266 to 274 is shifted to the left by a distance D2 from the corresponding (for example, nearest) second gate structures 210 to 220.

[0044] Procedure 1300 can proceed to operation 1340, where the inverted second standard cell is attached to one or more of the first standard cells. Continuing the same example from Fig. 3. The inverted second standard cell 200 can be positioned such that it abuts at least one of the first standard cells 100. As shown, the inverted second standard cell 200 is arranged between a pair of the first standard cells 100 along the X-direction. A plurality of layout rows can be formed or positioned over a given area for fabricating the integrated circuit. In some embodiments, each of these layout rows can have or accommodate one or more such inverted second standard cells, and each of the inverted second standard cells can be arranged between a corresponding pair of first standard cells. This allows the inverted second standard cells to abut one or more first standard cells along the X-direction or the Y-direction.

[0045] Fig. Figure 14 illustrates an exemplary computer system 1400 according to some embodiments. The computer system 1400 can be any generally known computer capable of performing the functions and operations described herein. For example, and without limitation, the computer system 1400 can be capable of selecting standard cells to be optimized, such as an EDA tool. The computer system 1400 can, for example, be used to perform one or more operations in the procedure 1300 of Fig. 13 to execute.

[0046] The computer system 1400 comprises one or more processors (also called central processing units or CPUs), such as a processor 1404. The processor 1404 is connected to a communication infrastructure or bus 1406. The computer system 1400 also comprises one or more input / output devices 1403, such as monitors, keyboards, pointing devices, etc., which communicate with the communication infrastructure or bus 1406 via one or more input / output interfaces 1402. An EDA tool can send instructions via the input / output devices 1403 to implement the functions and operations described in this text, for example, the procedure 1300 of Fig. 13, received. The computer system 1400 also includes a main or primary memory 1408, such as random-access memory (RAM), wherein the main memory 1408 may have one or more cache levels. Control logic (for example, computer software) and / or data are stored in the main memory 1408. In some embodiments, the control logic (for example, computer software) and / or the data may include one or more of the operations described above in relation to method 1300. Fig. 13 were described.

[0047] The Computer System 1400 may also include one or more secondary storage devices or a secondary storage device 1410. The secondary storage device 1410 may, for example, include a hard disk drive 1412 and / or a removable storage device or a removable drive 1414. The removable drive 1414 may be a floppy disk drive, a magnetic tape drive, a compact disk drive, an optical storage device, a tape backup device, and / or another storage device or drive. The removable drive 1414 may interact with a removable storage device 1418. The removable storage device 1418 comprises a computer-usable or -readable storage device in which computer software (control logic) and / or data are stored. The removable storage device 1418 may be a floppy disk, a magnetic tape, a compact disk, a DVD, an optical storage disc, and / or another computer data storage device.The removable drive 1414 reads from and / or writes to the removable storage unit 1418.

[0048] The secondary storage 1410 may include other means, instrumentality, or other approaches that allow the computer system 1400 to access computer programs and / or other instructions and / or data. Such means, instrumentality, or other approaches may include, for example, a removable storage unit 1422 and an interface 1420. Examples of the removable storage unit 1422 and the interface 1420 may include: a program cartridge and a cartridge interface (such as those found in video game devices), a removable memory chip (such as an EPROM or PROM) and an associated slot, a memory stick and a USB port, a memory card and an associated memory card slot, and / or any other removable storage unit and associated interface.In some embodiments, the secondary memory 1410, the removable storage unit 1418 and / or the removable storage unit 1422 may include one or more of the operations described above in relation to method 1300. Fig. 13 were described.

[0049] The computer system 1400 may further include a communication or network interface 1424. The communication interface 1424 enables the computer system 1400 to communicate and interact with any combination of geographically separated devices, geographically separated networks, geographically separated entities, etc. (individually and collectively designated by the reference numeral 1428). For example, the communication interface 1424 may allow the computer system 1400 to communicate with geographically separated devices 1428 via a communication path 1426, which may be wired and / or wireless and may include any combination of LANs, WANs, the Internet, etc. Control logic and / or data may be transmitted to and from the computer system 1400 via the communication path 1426.

[0050] The operations in the preceding embodiments can be implemented in a wide variety of configurations and architectures. Therefore, some or all of the operations in the preceding embodiments, for example, method 1300 of Fig. 13 and the procedure 1500 of Fig. 15 (which is described below), may be implemented in hardware, in software, or in both. In some embodiments, a tangible device or tangible product comprising a tangible computer-usable or -readable medium with control logic (software) stored thereon is also referred to in this text as a computer program product or program storage device. These include, but are not limited to, the computer system 1400, the main memory 1408, the secondary memory 1410, and the removable storage units 1418 and 1422, as well as tangible products embodying any combination of the foregoing. When such control logic is executed by one or more data processing devices (such as, for example, the computer system 1400), it causes such data processing devices to operate as described in this text.In some embodiments, the computer system 1400 is equipped with software to perform operations in the manufacture of photomasks and circuits, as in the method 1500 of . Fig. Figure 15 (which is described below) illustrates this. In some embodiments, the computer system 1400 includes hardware / equipment for photomask manufacturing and circuit fabrication. For example, the hardware / equipment may be connected to or part of element 1428 (one or more spatially separated devices, networks, entities) of the computer system 1400.

[0051] Fig. Figure 15 illustrates an exemplary method 1500 for circuit fabrication according to some embodiments. The operations of method 1500 can also be performed in a different sequence and / or vary. Variations of method 1500 are also to be considered as falling within the scope of protection of this disclosure.

[0052] Operation 1510 provides a GDS file. The GDS file can be generated by an EDA tool and contains the standard cell structures that have already been optimized using the described procedure. The operation shown in 1510 can, for example, be performed by an EDA tool running on a computer system such as the computer system 1400 described above.

[0053] In Operation 1520, photomasks are created based on the GDS file. In some embodiments, the GDS file provided in Operation 1510 is passed to a tape-out operation to generate photomasks for the fabrication of one or more integrated circuits. In some embodiments, a circuit layout contained in the GDS file can be read and transferred to a quartz or glass substrate to create opaque arrays corresponding to the circuit layout. The opaque arrays can be made of, for example, chromium or other suitable metals. Operation 1520 can be performed by a photomask manufacturer, where the circuit layout is read using suitable software (for example, an EDA tool) and the circuit layout is transferred to a substrate using a suitable printing / deposition tool.The photomasks reflect the circuit layout / structural elements contained in the GDS file.

[0054] In Operation 1530, one or more circuits are formed based on the photomasks generated in Operation 1520. In some embodiments, the photomasks are used to form arrangements / structures of the circuit contained in the GDS file. In some embodiments, various manufacturing tools (for example, photolithography equipment, deposition equipment, and etching equipment) are used to form structural elements of the one or more circuits.

[0055] Fig. Figure 16 illustrates a flowchart of a method 1600 for forming a section of an integrated circuit based on at least one of the layouts 100 of Fig. 1 or Fig. 200 of Fig. 2 according to some embodiments of the present disclosure. It should be noted that method 1600 is merely an example and that there is no intention to limit the present disclosure. Accordingly, it is understood that additional operations before, during, and after method 1600 are not to be considered. Fig. 16 can be performed and that some other operations may only be briefly described in the present text.

[0056] For example, procedure 1600 begins with operation 1602, where a substrate is provided. Procedure 1600 proceeds to operation 1604, where a stack is formed, consisting of an alternating series of first and second nanostructures stacked on top of each other. The stack can contain a number of active regions (for example, 102 and 104 of Fig. 1, Fig. 202 and Fig. 204 of Fig. 2) exhibiting, each extending along a first lateral direction (for example, the X-direction of Fig. 1 and Fig. 2) extend. In some embodiments, the first nanostructures may comprise silicon-germanium sacrificial nanostructures (SiGe sacrificial nanostructures), and the second nanostructures may comprise silicon channel nanostructures (Si channel nanostructures). Method 1600 proceeds to operation 1606, where a number of dummy gate structures are formed across the active regions. The dummy gate structures (for example, 110-120 of Fig. 1, 210-220 of Fig. 2) can extend along a second lateral direction (for example, the Y-direction of Fig. 1 and Fig. 2) extend perpendicular to the first lateral direction. Procedure 1600 proceeds to Operation 1608, where internal spacers are formed by replacing end sections of each of the first nanostructures with a dielectric material. Procedure 1600 proceeds to Operation 1610, where a number of epitaxial structures are formed. Procedure 1600 proceeds to Operation 1612, where the dummy gate structures and the remaining first nanostructures are replaced by respective active gate structures. Procedure 1600 proceeds to Operation 1614, where a number of middle-end interconnect structures are formed. Each of the middle-end interconnect structures or MDs (for example, 121-1 to 121-5 of Fig. 1, 221-1 to 221-5 in Fig. 2) can extend along the second lateral direction and be located between adjacent active gate structures in the first lateral direction. Procedure 1600 proceeds to Operation 1616, where a number of back-end interconnect structures are formed. These back-end interconnect structures can have a number of M0 traces (for example, 140 to 154 of Fig. 1, 240 to 254 of Fig. 2), extending along the first lateral direction, and a number of M1 conductor tracks (for example, 166 to 174 of Fig. 1, 266 to 274 of Fig. 2), which extend along the second lateral direction.

[0057] In some embodiments, each of the M1 traces can be shifted laterally to the left or right of the nearest active gate structures. For example, in Fig. 1. M1 trace 166 is shifted to the left of gate structure 112; M1 trace 168 is shifted to the left of gate structure 114; M1 trace 170 is shifted to the left of gate structure 116; M1 trace 172 is shifted to the left of gate structure 118; and M1 trace 174 is shifted to the left of gate structures 120. As another example, in Fig. 2. M1 trace 268 is shifted to the right away from gate structure 212; M1 trace 270 is shifted to the right away from gate structure 214; M1 trace 272 is shifted to the right away from gate structure 216; and M1 trace 274 is shifted to the right away from gate structure 218.

[0058] In one aspect of the present disclosure, an integrated circuit is disclosed. The integrated circuit comprises several cells that are adjacent to one another, each of the several cells corresponding to a respective circuit component. Each of the several cells comprises: several active regions extending along a first lateral direction; several gate structures extending along a second lateral direction perpendicular to the first lateral direction and traversing one or more of the several active regions; several first interconnect structures extending along the first lateral direction and arranged vertically above the several gate structures; and several second interconnect structures extending along the second lateral direction and arranged vertically above the several first interconnect structures.Each of the multiple second interconnect structures is shifted by a distance along the first lateral direction from a corresponding one of the multiple gate structures.

[0059] In another aspect of the present disclosure, a layout for forming an integrated circuit is disclosed. The layout comprises a first cell having a first boundary and operationally corresponding to a circuit component, wherein the first cell comprises several first arrangements for forming a first gate structure, a first interconnect structure vertically above the first gate structure, and a second interconnect structure vertically above the first interconnect structure, wherein the first gate structure extends along a first lateral direction, the first interconnect structure extends along a second lateral direction perpendicular to the first lateral direction, and the second interconnect structure extends along the first lateral direction.The layout comprises a second cell arranged along the second lateral direction or the first lateral direction with respect to the first cell, having a second boundary and operationally corresponding to the circuit component, wherein the second cell comprises multiple second arrangements to form a second gate structure, a third interconnect structure vertically above the second gate structure, or a fourth interconnect structure vertically above the third interconnect structure, and wherein the second gate structure extends along the first lateral direction, the third interconnect structure extends along the second lateral direction, and the fourth interconnect structure extends along the first lateral direction.The second interconnect structure is shifted a distance from the first gate structure along the second lateral direction, and the fourth interconnect structure is shifted a distance from the second gate structure along the second lateral direction.

[0060] In a further aspect of the present disclosure, a method is disclosed. The method comprises forming an active region extending along a first lateral direction. The method comprises forming multiple gate structures extending across the active region along a second lateral direction. The method comprises forming a number of first interconnect structures in a first metallization layer above the multiple gate structures. The method comprises forming a number of second interconnect structures in a second metallization layer above the first metallization layer. Viewed from above, each of the second interconnect structures is shifted to the right or left of the nearest gate structure along the first lateral direction by a certain distance.

[0061] For the purposes of this text, the terms "approximately" and "about" generally refer to the value of a given quantity, which may vary based on a specific technology node associated with the semiconductor device in question. Based on the specific technology node, the term "about" may indicate a value of a given quantity that varies, for example, within 10–30% of the value (e.g., +10%, ±20%, or ±30% of the value).

[0062] The above outlines features of various embodiments so that the person skilled in the art can better understand the aspects of the present disclosure. It is clear to the person skilled in the art that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as in the embodiments presented in this text. It should also be clear to the person skilled in the art that such equivalent designs do not depart from the essence and scope of protection of the present disclosure, and that they can make various changes, substitutions, and modifications to the present invention without departing from the essence and scope of protection of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 690,477

[0001]

Claims

[1] Integrated circuit comprising: multiple cells adjacent to one another, with each of the multiple cells corresponding to a respective circuit component; where each of the multiple cells comprises: several active regions extending along a first lateral direction; multiple gate structures extending along a second lateral direction perpendicular to the first lateral direction and traversing one or more of the multiple active regions; several first interconnect structures extending along the first lateral direction and arranged vertically above the multiple gate structures; and several second interconnect structures extending along the second lateral direction and arranged vertically above the several first interconnect structures; wherein each of the multiple second interconnect structures is shifted by a corresponding of the multiple gate structures by a distance along the first lateral direction. [2] Integrated circuit according to claim 1, wherein all multiple second interconnect structures are shifted to the left or to the right of the multiple gate structures. [3] Integrated circuit according to claim 1 or 2, wherein the distance is equal to or less than half a separation distance between adjacent gate structures along the first lateral direction. [4] Integrated circuit according to one of claims 1 to 3, wherein at least one first of the several cells, one second of the several cells and one third of the several cells correspond to the same circuit component. [5] Integrated circuit according to claim 4, wherein the first to third cells are adjacent to each other along the first lateral direction, the second cell being arranged between the first and the third cell. [6] Integrated circuit according to claim 5, wherein the first cell comprises at least one of its first interconnect structures reaching a first edge of a boundary of the first cell, the second cell comprises at least one of its first interconnect structures reaching a first edge of a boundary of the second cell, and the third cell comprises at least one of its first interconnect structures reaching a first edge of a boundary of the third cell. [7] Integrated circuit according to claim 6, wherein the boundary of the second cell comprises a second edge reaching the first edge of the boundary of the first cell, and the boundary of the third cell comprises a second edge reaching the first edge of the boundary of the second cell. [8] Integrated circuit according to claim 6, wherein the at least one first interconnect structure of the first cell does not extend beyond the first edge of the boundary of the first cell, the at least one first interconnect structure of the second cell does not extend beyond the first edge of the boundary of the second cell, and the at least one first interconnect structure of the third cell does not extend beyond the first edge of the boundary of the third cell. [9] Integrated circuit according to any one of claims 1 to 8, wherein at least one of the first interconnect structures is coupled to various of the offset second interconnect structures by means of via structures. [10] Integrated circuit according to claim 9, wherein the via structures are arranged vertically between the first interconnect structures and the second interconnect structures. [11] Integrated circuit according to any one of claims 1 to 10, wherein the circuit component comprises an inverter, an AND-OR inverter, an AND gate and a flip-flop. [12] Layout for forming an integrated circuit, comprising: a first cell having a first boundary and operationally corresponding to a circuit component, wherein the first cell comprises several first arrangements for forming a first gate structure, a first interconnect structure vertically above the first gate structure, and a second interconnect structure vertically above the first interconnect structure, and wherein the first gate structure extends along a first lateral direction, the first interconnect structure extends along a second lateral direction perpendicular to the first lateral direction, and the second interconnect structure extends along the first lateral direction; and a second cell, arranged with respect to the first cell along the second lateral direction or the first lateral direction, having a second boundary and operationally corresponding to the circuit component, wherein the second cell comprises multiple second arrangements to form a second gate structure, a third interconnect structure vertically above the second gate structure or a fourth interconnect structure vertically above the third interconnect structure, and wherein the second gate structure extends along the first lateral direction, the third interconnect structure extends along the second lateral direction, and the fourth interconnect structure extends along the first lateral direction; wherein the second interconnect structure is shifted a distance from the first gate structure along the second lateral direction, and the fourth interconnect structure is shifted a distance from the second gate structure along the second lateral direction. [13] Layout according to claim 12, wherein the distance is equal to or less than half a separation distance between the first gate structure and the second gate structure along the second lateral direction. [14] Layout according to claim 12 or 13, wherein the first interconnect structure extends towards an edge of the first boundary, while the third interconnect structure is spaced away from an edge of the second boundary. [15] Layout according to claim 14, wherein the edge of the first boundary and the edge of the second boundary, each extending along the first lateral direction, are adjacent to each other. [16] Layout according to claim 14 or 15, wherein the first interconnect structure does not extend beyond the edge of the first boundary. [17] Layout according to one of claims 14 to 16, wherein the second interconnect structure and the fourth interconnect structure, which are coupled to the first interconnect structure and the third structure respectively, are operationally configured as the same input / output connection of the circuit component. [18] Procedures, including: Forming an active region that extends along a first lateral direction; Forming multiple gate structures that extend along a second lateral direction across the active region; Forming a number of initial interconnect structures in a first metallization layer over the multiple gate structures; and Forming a number of second interconnect structures in a second metallization layer above the first metallization layer, wherein, viewed from above, each of the second interconnect structures is shifted a distance to the right or left of a nearest gate structure along the first lateral direction. [19] Method according to claim 18, wherein the distance is equal to or less than half a separation distance between adjacent of the multiple gate structures along the first lateral direction. [20] The method of claim 18 or 19, further comprising: Forming a number of third interconnect structures extending along the second lateral direction; wherein the third interconnect structures are arranged vertically between the gate structures and the first metallization layer, and wherein, viewed from above, each of the second interconnect structures is shifted to the right or left by the distance from a nearest of the third interconnect structures along the first lateral direction.

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