Hardware-based parallel context-based estimation for video coding

Abstract

Various implementations involve methods for encoding a media image. A video encoder encodes media images in a video stream by dividing the media images into blocks of pixels and encoding numerical coefficients associated with the blocks to generate a bitstream. As part of the encoding process, the video encoder estimates the bitrate required to encode a set of blocks of the media image. The video encoder produces more accurate bitrates for encoding the blocks by performing the bitrate estimation based on various context-based parameters of the coefficients, rather than just the coefficients themselves. This context-based bitrate estimation method can improve the visual quality of the encoded video stream.Furthermore, the video encoder encodes blocks using various simplifying assumptions to eliminate inter-block dependencies without unduly reducing visual quality. As a result, each block can be encoded independently and in parallel with the encoding of other blocks.

Description

BACKGROUND Area of ​​the various designs

[0001] Different implementations generally relate to video coding architectures and, in particular, to hardware-based parallel context-based estimation for video coding. Description of the state of the art

[0002] When streaming live or pre-recorded video, a first computer system, such as a server, data center, cloud storage system, and / or the like, transmits a video stream to a second computer system, such as a smartphone, tablet computer, laptop computer, and / or the like. Transmitting video streams between computer systems can consume a significant amount of network bandwidth, reducing the bandwidth available for other uses. Therefore, one goal of computer systems transmitting video streams is to compress and encode the video streams before transmission without significantly reducing the video quality. Computer systems receiving such video streams decompress and decode them before displaying them on one or more display devices.

[0003] When encoding a video stream containing a series of media images, a computer system may include a hardware video encoder that can predict pixels of a current media image based on corresponding pixels within the same current media image and / or in one or more reference media images. The video encoder divides each media image contained in the video stream into blocks, with each block containing a group of adjacent pixels of the media image. Each block of adjacent pixels may be an 8×8 block of pixels, a 16×16 block of pixels, a 32×32 block of pixels, a 64×64 block of pixels, and / or the like.

[0004] The encoding of pixels from a current media image based on corresponding pixels within the same current media image is referred to herein as intra-image encoding. In intra-image encoding, the video encoder encodes a block of pixels by analyzing neighboring pixels within the same block and / or within neighboring blocks of the current media image and determining the difference between the pixel values ​​of the current block and the pixel values ​​of the neighboring pixels. Intra-image encoding utilizes spatial coherence, where neighboring pixels are likely to have the same or similar pixel values ​​as the pixels of the block being encoded.

[0005] The encoding of pixels from a current media image based on a match between pixels within the current media image and corresponding pixels in one or more reference media images is referred to herein as inter-image encoding. In inter-image encoding, the video encoder encodes a block of pixels by analyzing matching pixels within the blocks of one or more reference media images and determining the difference between the pixel values ​​of the current block in the current media image and the pixel values ​​of the blocks in the reference media image(s). The reference media image(s) may contain one or more media images preceding the current media image and / or one or more media images following the current media image.Inter-image coding utilizes temporal coherence, whereby objects represented by pixels in the current media image are likely to also be present in the same or a different location in the reference media image.

[0006] Regardless of whether intra-frame or inter-frame encoding is used, the video encoder can reduce the amount of data—that is, the number of bits—required to encode the media frames of the video stream by encoding only the difference data, also referred to as residuals or residual data, instead of encoding the full pixel values ​​of all pixels contained in each media frame. The difference data for each block can be expressed as a set of coefficients, where a coefficient has a zero value for an exact match or a non-zero value that increases with the magnitude of the difference.Consequently, the amount of difference data encoded for the video stream is smaller the closer the pixel values ​​of the current block being encoded are to the neighboring pixels in the current media image for intra-image encoding, or to the matching blocks of the reference media image(s) for inter-image encoding.

[0007] Before encoding a group of blocks, the video encoder performs a bitrate estimation on the group of blocks based on the coefficients in the difference data for that group. One goal of the video encoder is to accurately estimate the bitrate of the groups of blocks in each media frame of the video stream in order to predict the video encoding resources required to encode the video stream with acceptable visual quality. The amount of difference data to be encoded affects the bitrate of the video stream, where the bitrate is a measure of the number of encoded bits the video encoder can produce per unit of time. The lower the amount of difference data, the higher the bitrate, and conversely, the higher the amount of difference data, the lower the bitrate.

[0008] One problem with this approach to encoding a video stream is that encoding only the coefficients contained in the difference data does not always result in a video stream of acceptable visual quality. The coefficients alone may not contain all the data needed to encode the video stream with high visual quality, especially when the amount of difference data is large, such as when the degree of spatial intra-frame coherence and temporal inter-frame coherence is low. Furthermore, bitrate estimation can become difficult as the amount of difference data increases. As a result, the visual quality of the video stream can be negatively affected by conventional video encoding approaches.

[0009] Furthermore, current intra-frame and inter-frame video coding techniques may involve analyzing pixel data and difference data coefficients of blocks other than the current block being encoded. As a result, the video encoder typically encodes the blocks of a media image sequentially, such as encoding the blocks of a given block row from left to right and encoding block rows from top to bottom. Consequently, the video encoder may have to wait until blocks to the left of and / or above the current block have been encoded first before encoding a given block of a media image. This sequential encoding of blocks can lead to reduced video encoder performance, especially when encoding blocks in an area of ​​the media image where the amount of difference data is high and the video encoder's bitrate is low.

[0010] As the above illustrates, more effective techniques for encoding blocks of a media image by a video encoder in a computing system are required in the prior art. SUMMARY

[0011] Various embodiments of the present disclosure constitute a computer-implemented method for encoding a first block of a current media image. The method includes determining one or more first parameters for a first set of coefficients associated with the first block. The method further includes estimating a first bit rate for encoding the first block based on the one or more first parameters, independently of one or more second parameters for a second set of coefficients associated with a second block of the current media image. The method further includes encoding the first block based on the first bit rate.

[0012] Other embodiments include, but are not limited to, a system implementing one or more aspects of the disclosed techniques, and one or more computer-readable media containing instructions for carrying out one or more aspects of the disclosed techniques, as well as a method for carrying out one or more aspects of the disclosed techniques.

[0013] At least one technical advantage of the disclosed techniques compared to the prior art is that the video encoder using the disclosed techniques estimates the bitrate for encoding blocks of an actual media image based on various parameters associated with the coefficients of the blocks, rather than solely based on the coefficients themselves. As a result, the visual quality of the resulting video stream can be higher compared to conventional approaches. Furthermore, the video encoder using the disclosed techniques can predict the bitrate of the encoded video stream more accurately, which allows the video encoder to select encoding parameters that further improve the accuracy and visual quality of the encoded video stream.Another technical advantage of the disclosed techniques is that the encoding of a current block of the current media image is no longer dependent on other blocks of the current media image. As a result, adjacent blocks of a media image can be encoded in parallel rather than sequentially, leading to improved video encoding performance compared to conventional video encoding techniques. These advantages represent one or more technological improvements over prior art approaches. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] To enable a detailed understanding of the nature of the aforementioned features of the various embodiments, a more precise description of the inventive concepts summarized above can be provided by reference to various embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings only illustrate typical embodiments of the concepts according to the invention and are therefore in no way to be considered as limiting the scope, and that other equally effective embodiments exist. Fig. Figure 1 is a block diagram of a computer system designed to implement one or more aspects of the various embodiments; Fig. Figure 2 is a block diagram of a parallel processing unit (PPU), which, according to various embodiments, is located in the auxiliary processing subsystem of Fig. 1 is present; Fig. Figure 3 is a block diagram of a general processing cluster (GPC) located in the parallel processing unit (PPU) of Fig. 2 according to different embodiments; Fig. Figure 4 is a block diagram of a video encoder designed to provide encoding data for multiple blocks of a media image to the computer system of the Fig. 1-3 to produce and process according to different embodiments; Fig. Figure 5 illustrates a functional view of a video encoder that converts a media image for the computer system of the Fig. 1-4 can be coded according to different embodiments; Fig. Figure 6 illustrates how the video encoders of the Fig. 4-5 can perform a sequential bit rate estimation of coding groups in a current media image according to various embodiments; Fig. Figure 7 illustrates how the video encoders of the Fig. 4-5 can perform a parallel bitrate estimation of coding groups in a current media image according to various embodiments; and Fig. Figure 8 is a flowchart of process steps for encoding blocks of a media image by the video encoders of the Fig. 4-5 according to various embodiments. DETAILED DESCRIPTION

[0015] The following description presents numerous specific details to enable a more thorough understanding of the various embodiments. However, it is clear to those skilled in the art that the concepts according to the invention can also be implemented without one or more of these specific details. System overview

[0016] Fig. Figure 1 is a block diagram of a computer system 100, designed to implement one or more aspects of the various embodiments. As shown, the computer system 100, without restriction, has a central processing unit (CPU) 102 and a system memory 104, which is coupled to an auxiliary processing subsystem 112 via a memory bridge 105 and a communication path 113. The memory bridge 105 is furthermore coupled to an input / output (I / O) bridge 107 via a communication path 106, and the I / O bridge 107 is in turn coupled to a switch 116.

[0017] In operation, the I / O bridge 107 is configured to receive user input information from input devices 108, such as a keyboard or mouse, and forwards the input information to the CPU 102 for processing via the communication path 106 and the memory bridge 105. In some examples, the input devices 108 are used to verify the identity of one or more users, to grant authorized users access to the computer system 100, and to deny unauthorized users access. The switch 116 is configured to establish connections between the I / O bridge 107 and other components of the computer system 100, such as a network adapter 118 and various add-in cards 120 and 121.In some examples, network adapter 118 serves as the primary or exclusive device for receiving input data for processing by the disclosed methods.

[0018] As also shown, the I / O bridge 107 is coupled to a system disk 114, which can be configured to store content, applications, and data for use by the CPU 102 and the auxiliary processing subsystem 112. In general, the system disk 114 provides non-volatile storage for applications and data and can include fixed or removable hard disk drives, flash memory devices, and CD-ROM (Compact Disc Read-Only Memory), DVD-ROM (Digital Versatile Disc-ROM), Blu-ray, HD-DVD (High Definition DVD), or other magnetic, optical, or solid-state storage devices. Finally, although not explicitly shown, other components, such as Universal Serial Bus or other connectors, Compact Disc drives, Digital Versatile Disc drives, movie recording devices, and the like, can also be connected to the I / O bridge 107.

[0019] In various embodiments, the memory bridge 105 can be a northbridge chip and the I / O bridge 107 a southbridge chip. Furthermore, the communication paths 106 and 113, as well as other communication paths within the computer system 100, can be implemented using any technically suitable protocols, including, but not limited to, Peripheral Component Interconnect Express (PCIe), HyperTransport, or other bus or point-to-point communication protocols known in the art.

[0020] In some embodiments, the auxiliary processing subsystem 112 comprises a graphics subsystem that supplies pixels to a display device 110, which may be a conventional cathode ray tube, liquid crystal display, light-emitting diode display, or the like. In such embodiments, the auxiliary processing subsystem 112 includes a circuit optimized for graphics and video processing, which, for example, includes a video output circuit. As in Fig. As described in more detail in Section 2, such circuits can be contained in one or more auxiliary processors present in Auxiliary Processing Subsystem 112. An auxiliary processor has one or more processing units capable of executing instructions, such as a RISC (Reduced Instruction Set Computer), a central processing unit (CPU), or a parallel processing unit (PPU). Fig. 2-4, a graphics processing unit (GPU), a direct memory access (DMA) unit, an intelligence processing unit (IPU), a neural accelerator unit (NAU), a tensor processing unit (TPU), a neural network processor (NNP), a data processing unit (DPU), a vision processing unit (VPU), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) and / or the like.

[0021] In some embodiments, the auxiliary processing subsystem 112 includes two processors, referred to herein as the primary processor (normally a CPU) and the secondary processor. Typically, the primary processor is a CPU and the secondary processor is a GPU. Additionally or alternatively, both the primary processor and the secondary processor may consist of one or more of the types of auxiliary processors disclosed herein, in any technically feasible combination. The secondary processor receives safe instructions from the primary processor via an unsecured communication path. The secondary processor accesses memory and / or other storage systems, such as system memory 104, Compute eXpress Link (CXL) memory extensions, memory-managed disk storage, on-chip memory, and / or the like.The secondary processor accesses this memory and / or another storage system over an insecure connection. The primary and secondary processors can communicate with each other via a GPU-to-GPU communication channel, such as Nvidia Link (NVLink). Additionally, the primary and secondary processors can communicate with each other via network adapter 118. Generally, the distinction between an insecure and a secure communication path is application-dependent. A given application program generally considers communication within a die, chip, or package to be secure. The communication of unencrypted data over a standard communication channel such as PCIe is considered insecure.

[0022] In some embodiments, the auxiliary processing subsystem 112 includes circuits optimized for general-purpose use and / or data processing. Such circuitry may also be contained in one or more auxiliary processors within the auxiliary processing subsystem 112, configured to perform such general-purpose and / or computational operations. In other embodiments, the one or more auxiliary processors within the auxiliary processing subsystem 112 may be configured to perform graphics processing, general-purpose processing, and arithmetic operations. The system memory 104 includes at least one device driver 103 configured to manage the processing operations of the one or more auxiliary processors within the auxiliary processing subsystem 112.

[0023] In other versions, the auxiliary processing subsystem 112 can be combined with one or more other elements of the Fig. 1 can be integrated into a single system. For example, the auxiliary processing subsystem 112 can be integrated with the CPU 102 and other interconnect circuitry on a single chip to form a system on a chip (SoC).

[0024] It is clear that the system shown here is illustrative and that variations and modifications are possible. The connection topology, which includes the number and arrangement of the bridges, the number of CPUs 102, and the number of auxiliary processing subsystems 112, can be changed as desired. In some embodiments, for example, the system memory 104 could be connected directly to the CPU 102, rather than via the memory bridge 105, and other devices could communicate with the system memory 104 via the memory bridge 105 and the CPU 102. In other alternative topologies, the auxiliary processing subsystem 112 could be connected to the I / O bridge 107 or directly to the CPU 102, rather than via the memory bridge 105. In other embodiments, the I / O bridge 107 and the memory bridge 105 could be integrated on a single chip, instead of existing as one or more discrete devices.Finally, in certain embodiments, one or more of the features described in . Fig. The components shown in Figure 1 may not be present. For example, the switch 116 can be omitted, and the network adapter 118 and the add-on cards 120, 121 can be directly connected to the I / O bridge 107.

[0025] Fig. Figure 2 is a block diagram of a parallel processing unit (PPU) 202, which is located in the auxiliary processing subsystem 112 of Fig. 1 according to various embodiments. Although in Fig. Since PPU 202 is represented in Figure 2, the auxiliary processing subsystem 112, as indicated above, can have any number of PPUs 20. Furthermore, PPU 202 is the Fig. 2. An example of an auxiliary processor located in the auxiliary processing subsystem 112 of the Fig. 1 is included. Alternative auxiliary processors include, without limitation, RISCs, CPUs, GPUs, DMA units, IPUs, NPUs, TPUs, NNPs, DPUs, VPUs, ASICs, FPGAs and / or the like. The ones in the Fig. The methods disclosed in Sections 2 and 3 relating to the PPU 202 apply equally to any type of auxiliary processor(s) included in the auxiliary processing subsystem 112, in any combination. As shown, the PPU 202 is coupled to a local parallel processing (PP) memory 204. The PPU 202 and the PP memory 204 can be implemented with one or more integrated circuits, such as programmable processors, application-specific integrated circuits (ASICs), or memory devices, or in any other technically feasible form.

[0026] In some embodiments, the PPU 202 includes a graphics processing unit (GPU) that may be configured to implement a graphics rendering pipeline for performing various operations related to generating pixel data based on graphics data supplied by the CPU 102 and / or the system memory 104. When processing graphics data, the PP memory 204 can be used as graphics memory, storing one or more conventional image buffers and, if necessary, one or more other rendering targets. The PP memory 204 can be used, among other things, to store and update pixel data and to deliver the final pixel data or display images to the display device 110 for display. In some embodiments, the PPU 202 may also be configured for general-purpose processing and computational operations.

[0027] In operation, the CPU 102 is the main processor of the computer system 100 and controls and coordinates the operations of other system components. In particular, the CPU 102 issues instructions that control the operation of the PPU 202. In some embodiments, the CPU 102 writes a stream of instructions for the PPU 202 into a data structure (neither in Fig. 1 still in Fig. 2 (explicitly shown), which may be located in system memory 104, in PP memory 204, or in another memory location accessible to both CPU 102 and PPU 202. Additionally or alternatively, processors and / or auxiliary processors other than CPU 102 may write one or more instruction streams for PPU 202 into a data structure. A pointer to the data structure is written to a push buffer to initiate the processing of the instruction stream in the data structure. PPU 202 reads the instruction streams from the push buffer and then executes the instructions asynchronously to the operation of CPU 102. In embodiments where multiple push buffers are created, execution priorities for each push buffer can be set by an application program via device driver 103 to control the timing of the different push buffers.

[0028] As also shown, the PPU 202 has an I / O (input / output) unit 205, which communicates with the rest of the computer system 100 via the communication path 113 and the memory bridge 105. The I / O unit 205 generates packets (or other signals) for transmission on the communication path 113 and also receives all incoming packets (or other signals) from the communication path 113 and forwards the incoming packets to the appropriate components of the PPU 202. For example, commands relating to processing tasks can be directed to a host interface 206, while commands relating to memory operations (e.g., reading from or writing to the PP memory 204) can be directed to a crossbar unit 210. The host interface 206 reads each push buffer and transmits the instruction stream stored in the push buffer to a front end 212.

[0029] As above in connection with Fig. As mentioned in Figure 1, the connection of the PPU 202 to the rest of the computer system 100 can be varied. In some embodiments, the auxiliary processing subsystem 112, which includes at least one PPU 202, is implemented as an add-in card that can be inserted into an expansion slot of the computer system 100. In other embodiments, the PPU 202 can be integrated on a single chip with a bus bridge, such as the memory bridge 105 or the I / O bridge 107. In still other embodiments, some or all elements of the PPU 202 can be present together with the CPU 102 in a single integrated circuit or system of chips (SoC).

[0030] During operation, the front end 212 transmits the processing tasks received from the host interface 206 to a workload distribution unit (not shown) within the task / work unit 207. The workload distribution unit receives pointers to processing tasks, which are encoded as task metadata (TMD) and stored in memory. The pointers to TMDs are contained in an instruction stream, which is stored as a push buffer and received by the front end 212 from the host interface 206. Processing tasks, which can be encoded as TMDs, have indices associated with the data to be processed, as well as state parameters and instructions that define how the data is to be processed. The state parameters and instructions could, for example, define the program to be executed on the data.The task / work unit 207 receives tasks from the front end 212 and ensures that the GPCs 208 are configured to a valid state before initiating the processing tasks specified by the individual TMDs. A priority can be specified for each TMD, which is used to schedule the execution of the processing task. Processing tasks can also be received from the processing cluster array 230. Optionally, the TMDs can have a parameter that controls whether the TMD is added to the head or the end of a list of processing tasks (or to a list of pointers to the processing tasks), thus providing another layer of control over the execution priority.

[0031] The PPU 202 advantageously implements a highly parallel processing architecture based on a processing cluster arrangement 230, which has a set of C general processing clusters (GPCs) 208, where C ≥ 1. Each GPC 208 is capable of executing a large number (e.g., hundreds or thousands) of threads concurrently, with each thread being an instance of a program. In different applications, different GPCs 208 can be allocated for processing different types of programs or for performing different types of computations. The allocation of GPCs 208 can vary depending on the workload associated with each type of program or computation.

[0032] The memory interface 214 has a set of D partition units 215, where D ≥ 1. Each partition unit 215 is coupled to one or more dynamic random-access memory (DRAM) units 220 located in the PP memory 204. In one embodiment, the number of partition units 215 is equal to the number of DRAM units 220, and each partition unit 215 is coupled to a different DRAM unit 220. In other embodiments, the number of partition units 215 may differ from the number of DRAM units 220. It is understood that a DRAM unit 220 can be replaced by any other technically suitable arrangement. During operation, various rendering targets, such as texture maps and frame buffers, can be stored across DRAMs 220, allowing the partition units 215 to write sections of each rendering target in parallel to efficiently utilize the available bandwidth of the PP memory 204.

[0033] A specific GPC 208 can process data to be written to one of the DRAMs 220 within the PP memory 204. The crossbar unit 210 is configured to forward the output of each GPC 208 to the input of any partition unit 215 or to another GPC 208 for further processing. The GPCs 208 communicate with the memory interface 214 via the crossbar unit 210 to read from or write to various DRAMs 220. In one embodiment, the crossbar unit 210 has a connection to the I / O unit 205, in addition to a connection to the PP memory 204 via the memory interface 214, enabling the processing cores within the various GPCs 208 to communicate with the system memory 104 or other memory not belonging to the PPU 202. In the embodiment of the Fig. In 2, the crossbar unit 210 is directly connected to the I / O unit 205. In various embodiments, the crossbar unit 210 can use virtual channels to separate traffic flows between the GPCs 208 and the partition units 215.

[0034] Here too, the GPCs 208 can be programmed to perform processing tasks related to a variety of applications, including but not limited to linear and nonlinear data transformations, filtering of video and / or audio data, modeling operations (e.g., applying physical laws to determine the position, velocity, and other attributes of objects), image rendering operations (e.g., tessellation shader, vertex shader, geometry shader, and / or pixel / fragment shader programs), general arithmetic operations, etc. In operation, the PPU 202 is configured to transfer data from system memory 104 and / or PP memory 204 to one or more on-chip memory units, process the data, and write the resulting data back to system memory 104 and / or PP memory 204.The result data can then be accessed by other system components that have a CPU 102, another PPU 202 within the auxiliary processing subsystem 112, or another auxiliary processing subsystem 112 within the computer system 100.

[0035] As mentioned above, any number of PPUs 202 can be present in an accelerator processing subsystem 112. For example, multiple PPUs 202 can be located on a single add-in card, or multiple add-in cards can be connected via the communication path 113, or one or more of the PPUs 202 can be integrated into a bridge chip. The PPUs 202 in a multi-PPU system can be identical or different from one another. For example, different PPUs 202 can have a different number of processor cores and / or different amounts of PP memory 204. In implementations where multiple PPUs 202 are present, these PPUs can be operated in parallel to process data at a higher throughput than is possible with a single PPU 202.Systems containing one or more PPUs 202 can be implemented in a variety of configurations and form factors, including without limitation desktops, laptops, portable personal computers or other portable devices, servers, workstations, game consoles, embedded systems and the like.

[0036] Fig. Figure 3 is a block diagram of a general processing cluster (GPC) 208, which is located in the parallel processing unit (PPU) 202 of Fig. 2 according to various embodiments. In operation, the GPC 208 can be configured to execute a large number of threads in parallel to perform graphics, general processing, and / or computational operations. As used herein, a "thread" refers to an instance of a particular program running with a specific set of input data. Some embodiments employ Single-Instruction, Multiple-Data (SIMD) instruction output methods to support the parallel execution of a large number of threads without providing multiple independent instruction units.In other implementations, SIMT (Single-Instruction, Multiple-Thread) methods are used to support the parallel execution of a large number of generally synchronized threads, employing a common instruction unit configured to issue instructions to a number of processing engines within GPC 208. Unlike a SIMD execution regime, where all processing engines typically execute identical instructions, SIMT execution allows different threads to more easily follow different execution paths through a given program. A person skilled in the art understands that a SIMD processing regime is a functional subset of a SIMT processing regime.

[0037] The operation of the GPC 208 is controlled by a pipeline manager 305, which distributes the processing tasks received from a work distribution unit (not shown) within the task / work unit 207 to one or more streaming multiprocessors (SMs) 310. The pipeline manager 305 can also be configured to control a work distribution crossbar 330 by specifying destinations for processed data output by the SMs 310.

[0038] In one embodiment, the GPC 208 has a set of M SMs 310, where M ≥ 1. Each SM 310 also has a set of functional execution units (not shown), such as execution units and load memory units. Processing operations specific to each of the functional execution units can be grouped in a pipeline so that a new instruction can be issued for execution before a previous instruction has completed its execution. Any combination of functional execution units within a given SM 310 can be provided. In various embodiments, the functional execution units can be configured to support a variety of different operations, including integer and floating-point arithmetic (e.g., addition and multiplication), comparison operations, Boolean operations (e.g.,AND, OR, XOR), bit shifting and the calculation of various algebraic functions (e.g. planar interpolation and trigonometric, exponential and logarithmic functions, etc.). Advantageously, one and the same functional execution unit can be designed to perform different operations.

[0039] In operation, each SM 310 is configured to process one or more thread groups. As used herein, a "thread group" or "warp" refers to a group of threads that simultaneously execute the same program with different input data, with one thread of the group being assigned to a different execution unit within an SM 310. A thread group can have fewer threads than the number of execution units within the SM 310; in this case, part of the execution may be idle during the cycles in which the thread group is processed. A thread group can also have more threads than the number of execution units within the SM 310; in this case, processing may occur in successive clock cycles. Since each SM 310 can support up to G thread groups concurrently, it follows that up to G*M thread groups can be executed in a GPC 208 at any given time.

[0040] Furthermore, a large number of related thread groups can be active simultaneously in an SM 310 (at different stages of execution). This collection of thread groups is referred to here as a "cooperative thread array" ("CTA") or "thread array." The size of a given CTA is equal to m*k, where k is the number of concurrently executing threads in a thread group, which is typically an integer multiple of the number of execution units within the SM 310, and m is the number of concurrently active thread groups within the SM 310. In various implementations, a software application written in the CUDA (Compute Unified Device Architecture) programming language describes the behavior and operation of threads running on the GPC 208, including the behaviors and operations described above.A given processing task can be specified in a CUDA program, so that the SM 310 can be designed to perform and / or manage multi-purpose computing operations.

[0041] Although in Fig. Not shown in Figure 3, each SM 310 contains a Level 1 cache (L1 cache) or uses space in a corresponding L1 cache outside the SM 310 to support, among other things, load and store operations performed by the execution units. Each SM 310 also has access to Level 2 caches (L2) (not shown) shared by all GPCs 208 in the PPU 202. The L2 caches can be used to transfer data between threads. Finally, the SMs 310 also have access to the "global" memory outside the chip, which may include PP memory 204 and / or system memory 104. It is understood that any memory outside the PPU 202 can be used as global memory. Additionally, as shown in Figure 3, the SMs 310 can also be used as global memory. Fig. Figure 3 shows an L1.5 cache 335 present in the GPC 208 and configured to receive and hold data requested from memory by the SM 310 via the memory interface 214. Such data can include instructions, uniform data, and constant data. In embodiments with multiple SMs 310 within the GPC 208, the SMs 310 can advantageously utilize common instructions and data cached in the L1.5 cache 335.

[0042] Each GPC 208 can have an associated memory management unit (MMU) 320, configured to map virtual addresses to physical addresses. In various embodiments, the MMU 320 can be located either within the GPC 208 or in the memory interface 214. The MMU 320 includes a set of page table entries (PTEs) used to map a virtual address to a physical address of a tile or memory page, and optionally to a cache row index. The MMU 320 can include address translation lookaside buffers (TLBs) or caches, which may be located in SMs 310, in one or more L1 caches, or within the GPC 208.

[0043] In graphics and computing applications, the GPC 208 can be configured so that each SM 310 is coupled with a texture unit 315 to perform texture mapping operations, such as determining texture sampling positions, reading texture data, and filtering texture data.

[0044] In operation, each SM 310 transfers a processed task to the work-distribution crossbar 330 to make the processed task available to another GPC 208 for further processing or to store the processed task in an L2 cache (not shown), a PP memory 204, or a system memory 104 via the crossbar unit 210. In addition, a pre-raster operations (preROP) unit 325 is configured to receive data from the SM 310, forward data to one or more raster operations (ROP) units within the partition units 215, perform color mixing optimizations, organize pixel color data, and perform address translations.

[0045] It is clear that the core architecture described here is illustrative and that variations and modifications are possible. Among other things, any number of processing units, such as SMs 310, texture units 315, or preROP units 325, can be included in the GPC 208. Furthermore, the PPU 202, as described above in conjunction with Fig. 2 described, comprising any number of GPCs 208 configured to be functionally similar to one another, such that the execution behavior does not depend on which GPC 208 receives a particular processing task. Furthermore, each GPC 208 operates independently of the other GPCs 208 in the PPU 202 to execute tasks for one or more application programs. In light of the foregoing, the person skilled in the art understands that the Fig. The architecture described in 1-3 does not in any way limit the scope of the various embodiments of the present disclosure.

[0046] It should be noted that references to shared memory, as used here, may include one or more technically possible memories, including, without limitation, local memory shared by one or more SMs 310, or memory accessible via memory interface 214, such as cache memory, PP memory 204, or system memory 104. It should also be noted that references to cache memory, as used here, may include one or more technically feasible memories, including, but not limited to, an L1 cache, an L1.5 cache, and the L2 caches. Hardware-based parallel context-based estimation for video coding

[0047] Various implementations include a video encoder that performs context-based bitrate estimation to generate more accurate bitrates for encoding transformation units (TUs) in a media image. Bitrates can be expressed as a cost value, so the cost increases with increasing bitrate. A transformation unit is the basic unit in certain video coding standards for applying transformations to difference data to produce an encoded video stream. This difference data is also referred to as residuals or residual data. Each transformation unit is a group of pixels of a specific size, such as a 4×4 group of pixels, an 8×8 group of pixels, a 16×16 group of pixels, a 32×32 group of pixels, and / or the like.The video encoder divides each media image into multiple media segments, also known as slices, with each media segment containing multiple transformation units. The video encoder estimates the bitrate for encoding blocks of a given media image based on various parameters associated with the block coefficients, rather than solely on the coefficients themselves. The video encoder uses the estimated bitrate derived from this estimation to encode the transformation units within the video segment.

[0048] Additionally, the disclosed techniques eliminate certain data dependencies when encoding the difference data associated with the blocks of the media image. Specifically, when the video encoder encodes a first block that has adjacent pixels in a second block, the video encoder can encode the first block using default pixel values ​​instead of using the actual pixel data from the pixels of the second block. As a result, the video encoder can encode the first block and the second block independently and in parallel.

[0049] Fig. Figure 4 is a block diagram of a video encoder 400, which is designed to provide encoding data for multiple blocks of a media image for the computer system 100. Fig. 1-3 to produce and process according to different embodiments. As shown, the video encoder 400 includes, without limitation, a controller 405, a full-pixel search (FPS) unit 410, a subpixel search (SPS) unit 415, a motion compensation filter type selection (MCT) unit 420, a rate distortion optimization (RDO) unit 425, a reconstruction (Rekon) unit 430, a filter 435, an entropy encoder 440, a link 445, a pixel direct access (DMA) unit 450, a read collocation motion vector (RCOL) unit 455, an external motion vector prediction (DMA) unit 457, a read motion vector prediction (RMVP) unit 459, a cache 460, a mode decision processor (MDP) 465, a Multimedia Pipeline Encoder B (MPEB) Unit 466, Multimedia Pipeline Encoder C (MPEC) Unit 467, History (HIST) Unit 470, Motion Estimation DMA (MEDMA) Unit 475,a Write Motion Vector Prediction (WMVP) unit 477 and an Image Buffer Interface (FB-I / F) 480.,

[0050] Various units of the Video Encoder 400 communicate with each other via connection 445. These various units include the FPS unit 410, the SPS unit 415, the MCT unit 420, the RDO unit 425, the RCOL unit 455, the RHINT unit 457, the RMVP unit 459, the cache memory 460, the MDP unit 465, the MPEB unit 466, the MPEC unit 467, the history unit 470, the MEDMA unit 475, the WMVP unit 477, and / or the like. Connection 445 can include any suitable interconnect bus, mesh network, point-to-point connection, and / or the like for transmitting and receiving data between and among these units of the Video Encoder 400.

[0051] The Video Encoder 400 can be configured to encode a video according to any one or more video encoding formats. In some embodiments, the Video Encoder 400 can encode a video stream compatible with the Advanced Video Coding (AVC) format, also known as the H.264 format or the Motion Picture Experts Group 4 (MPEG-4) Part 10 format. Additionally or alternatively, the Video Encoder 400 can encode a video stream compatible with the High Efficiency Video Coding (HEVC) format, also known as the H.265 format or the Motion Picture Experts Group High Efficiency (MPEG-H) Part 2 format. Additionally or alternatively, the Video Encoder 400 can encode a video stream compatible with the Video Compression 9 (VP9) format and / or the Alliance for Open Media (AOMedia) Video 1 (AV1) format.Additionally or alternatively, the Video Encoder 400, as is and / or with minor modification, can encode a video stream compatible with any other technically feasible video coding format, including, without limitation, Motion Joint Pictures Experts Group (JPEG) 2000 (MJ2), MPEG-2 or H.262, H.263v2 or H.263+, Video Coding 1 (VC-1 or SMPTE 421), Versatile Video Coding (VVC or H.266), VP8, VP10 and / or the like.

[0052] In some embodiments, certain units of the Video Encoder 400 can be general-purpose coding units that support operations for encoding a video into multiple encoding formats. Additionally or alternatively, certain units of the Video Encoder 400 can be format-specific encoding units that support operations for encoding a video into a single encoding format or into two or three related encoding formats. For example, general-purpose encoding units of the Video Encoder 400 can include, without limitation, the FPS unit 410, the SPS unit 415, the MCT unit 420, the PDMA unit 450, the RCOL unit 455, the RHINT unit 457, the RMVP unit 459, the cache memory 460, the MEDMA unit 475, the WMVP unit 477, and / or the like. Additionally or alternatively, format-specific coding units of the Video Encoder 400 can be used, which perform operations for encoding a video into the H.264 format and / or the H.Supporting the 265 format without restriction may include the MDP unit 465, the MPEB unit 466, the MPEC unit 467, the history unit 470, and / or similar components. Additionally or alternatively, format-specific coding units of the video encoder 400, which support operations for encoding from a video into the AV1 format and / or the VP9 format, may include, without restriction, the RDO unit 425, the reconstruction unit 430, the filter 435, the entropy encoder 440, and / or similar components.

[0053] In operation, the Controller 405 encodes media images into a video stream in conjunction with other units and / or components of the Video Encoder 400. The Controller 405 may include any one or more processors capable of executing instructions, including, without limitation, a microcontroller, a RISC processor, a CPU, a PPU, a GPU, a DMA unit, an IPU, a NAU, a TPU, an NNP, a DPU, a VPU, an ASIC, an FPGA, and / or the like. The Controller 405 may include memory for storing instructions that can program the Controller 405 to perform various operations described herein. The Controller 405 may also include memory for storing data associated with these operations.In this respect, the CPU 102, the auxiliary processing subsystem 112, and / or similar components can store instructions and / or data in the memory of the controller 405 via the memory bridge 105 and the communication path 113. Likewise, the controller 405 can communicate with the memory bridge 105 via the communication path 113. Through the memory bridge 105, the controller 405 can communicate with various other units and / or components of the computer system 100.

[0054] Furthermore, the controller 405 can communicate with various units and / or components of the video encoder 400, including, but not limited to, the FPS unit 410, the SPS unit 415, the MCT unit 420, the RDO unit 425, the reconstruction unit 430, the filter 435, the entropy encoder 440, and / or the like. The controller 405 can configure one or more of the video encoder 400 units. Furthermore, the controller 405 can control the execution and operation of one or more of the video encoder 400 units, including various operations for encoding media images of a video stream. The controller 405 can receive data from the video encoder 400 units resulting from the execution of these various operations.

[0055] Media images can be divided into block rows, with each block row containing a set of blocks extending from the left edge to the right edge of the media image. Depending on the format used by the Video Encoder 400, the blocks may be referred to as macroblocks, coding tree units (CTUs), coding tree blocks (CTBs), superblocks, and / or the like. In some embodiments, the Video Encoder 400 encodes a video stream in the H.264 format, with media images divided into 16 × 16 pixel macroblocks. In some embodiments, the Video Encoder 400 encodes a video stream in the HEVC format, with media images divided into 32 × 32 pixel coding tree blocks. In some embodiments, the Video Encoder 400 encodes a video stream in the AV1 format, with media images divided into 64 × 64 pixel superblocks.In various formats, including HEVC, AV1, and / or the like, the video encoder 400 generates predictions or indications of a coding unit granularity. In some embodiments, a coding unit is a square pixel block of various sizes, including, but not limited to, 16 × 16 pixel coding units, 32 × 32 pixel coding units, 64 × 64 pixel coding units, and / or the like. In various formats, including HEVC, AV1, and / or the like, the video encoder 400 generates predictions or indications of a prediction unit granularity. In some embodiments, a prediction unit is a rectangular pixel block of various sizes, including, without limitation, 8 × 16 pixel prediction units, 16 × 8 pixel prediction units, 16 × 32 pixel prediction units, 32 × 16 pixel prediction units and / or the like.In some embodiments, a prediction unit is a square pixel block of various sizes, including, without limitation, 16 × 16 pixel prediction units, 32 × 32 pixel prediction units, 64 × 64 pixel prediction units and / or the like.

[0056] The controller 405, in conjunction with other units and / or components of the video encoder 400, can control various operations for generating interframe candidates for media frames of a video stream. To generate an interframe candidate, the controller 405 performs motion estimation and / or motion compensation for a block contained within a media frame of the video stream. The controller 405 performs motion estimation and / or motion compensation to generate an interframe candidate for the specified block based on temporal redundancy between media frames. Specifically, the controller 405 performs one or both of a full-pixel search in conjunction with the FPS unit 410 and / or a subpixel search in conjunction with the SPS unit 415.The 405 controller performs one or both of these searches by scanning a reference media image, such as the preceding media image and / or the following media image, for blocks that match corresponding blocks in the current media image being encoded. A block in the reference media image matches the block in the current media image if the pixel data of the block in the reference media image is the same as or similar to the pixel data of the current block in the current media image. The matching block is the block in the reference media image with pixel data that most closely matches the pixel data of the block in the current media image.If the objects in the scene have not moved and the camera view has not changed between the reference media image and the current media image, then the position of the current block within the current media image can be the same as the position of the corresponding block in the reference media image. However, if the objects in the scene have moved and / or the camera view has changed between the reference media image and the current media image, then the position of the current block within the current media image can differ from the position of the corresponding block in the reference media image. Control 405 generates a motion vector for the current block in the current media image that identifies the position of the corresponding block in the reference media image.Motion compensation predicts the pixels of a current media frame based on a preceding and / or subsequent media frame by determining effects caused by movement of the camera recording the video stream and / or movement of objects within the scene being recorded by the camera. Control 405 generates difference data, also known as residuals, which specify the differences between the pixel data of the matching block in the reference media frame and the pixel data of the current block in the current media frame. As the similarity between the pixel data of the block in the reference media frame and the pixel data of the current block increases, the amount of difference data decreases, resulting in lower inter-frame costs.Conversely, if the similarity of the pixel data of the block in the reference media image to the pixel data of the current block decreases, the amount of difference data increases, leading to high inter-image costs.

[0057] The 405 controller generates a motion vector for the current block, which predicts the block of the current media frame from the corresponding block of a reference media frame. The 405 controller, in conjunction with other units and / or components of the 400 video encoder, generates motion vector prediction data, also known as motion vector cue data or simply cue data, for each media frame. This cue data includes forward prediction cue data and backward prediction cue data. The 405 controller generates forward prediction cue data based on block data for a current block and block data for a corresponding block of the previous media frame. Similarly, the 405 controller generates backward prediction cue data based on block data for the current block and block data for a corresponding block of the following media frame.The Video Encoder 400 can use the motion vector data as an interframe candidate. Based on the motion vector data, the Controller 405 generates motion-compensated pixels for the interframe candidate.

[0058] Depending on the encoding format currently in use, the controller 405 transmits motion vector data and / or pixel block data to the MDP unit 465, the MPEB unit 466, and / or the MCT unit 420. When encoding in certain formats, such as H.264, H.265, and / or similar, the controller 405 transmits motion vector data and / or pixel block data to the MDP unit 465 and the MPEB unit 466. When encoding in certain other formats, such as AV1 and / or similar, the controller 405 transmits motion vector data and / or pixel block data to the MCT unit 420.

[0059] Furthermore, the controller 405, in conjunction with other units of the video encoder 400, can control various operations for generating intra-frame candidates for media frames of a video stream. To generate an intra-frame candidate, the controller 405 performs an intra-frame estimation and / or intra-frame prediction to generate an intra-frame candidate for the specified block based on spatial redundancy within a media frame.

[0060] To perform intra-image estimation, the controller 405 selects an intra-image prediction mode based on the current pixels in the current media image and the neighboring pixels of the reconstructed current media image. In some embodiments, the controller 405 can select the intra-image prediction mode that best predicts the pixels of the current block. The controller 405 can select the intra-image prediction mode that results in the lowest rate distortion cost based on the sum of squared errors (SSE) with respect to the distortions for the current block, as determined by the rate distortion optimization unit 425. The number and type of available prediction modes can vary based on the block size.For example, the number and type of available prediction modes may differ for 4 × 4 pixel blocks, 8 × 8 pixel blocks, 16 × 16 pixel blocks, 32 × 32 pixel blocks, and / or the like. In this respect, the controller 405 can select different intra-image prediction modes for each of the possible block sizes based on which intra-image prediction mode results in the lowest rate distortion cost value, as determined by the rate distortion optimization unit 425 for that block size. Furthermore, the controller 405 can select different intra-image prediction modes for the luma values ​​in the block as opposed to the chroma sample values ​​in the block. In some embodiments, the intra-image prediction mode determines the order in which the pixels in the current block are sampled to generate the predicted intra-image candidate.For example, the intra-image prediction mode can specify vertical scanning, horizontal scanning, diagonal scanning down left, diagonal scanning down right, vertical scanning left, vertical scanning right, horizontal scanning down, horizontal scanning up and / or the like.

[0061] To perform an intra-image prediction, the 405 control generates an intra-image candidate based on the selected intra-image prediction mode. The 405 controls sample the pixel values ​​in the current block in the order specified by the selected intra-image prediction mode. For each sampled pixel, the 405 controls determine a predicted pixel value based on the differences between that pixel value and the pixel values ​​of neighboring pixels. From these predicted pixel values, the 405 controls generate the intra-image candidate.

[0062] The 405 controller uses various other units contained within the 400 video encoder to perform the operations described herein. Specifically, the 405 controller uses the 410 FPS unit to perform full-pixel motion estimation. The 410 FPS unit performs a full-pixel search using integer pixel addresses to generate motion estimation data between pixels of a current media frame and corresponding pixels of a previous and / or subsequent media frame on a pixel-by-pixel basis. Similarly, the 405 controller uses the 415 PLC unit to perform subpixel motion estimation.The PLC unit 415 performs a subpixel search using fractional pixel addresses to generate motion estimation data between subpixels of a current media image and corresponding subpixels of a previous and / or subsequent media image on a subpixel-by-subpixel basis. Each subpixel can be half the size of a full pixel, a quarter the size of a full pixel, and / or the like.

[0063] The 405 controller uses the 420 MCT unit to perform motion compensation. The 420 MCT unit selects a filter type to predict motion compensation. Specifically, it selects a motion compensation filter type to account for the interpolation of subpixels resulting from fractional motion vectors. Subpixels can be determined by filtering full pixels and full-pixel motion vectors. Motion compensation filter types can include bicubic filtering, bilateral filtering, and / or similar methods.

[0064] The RCOL unit 455 reads collocated motion vector data from memory and stores this collocated motion vector data in memory for access during motion estimation and / or other encoding operations. This collocated motion vector data for a previous media image is written to memory beforehand by the MPEC unit 467.

[0065] The RMVP unit 459 reads motion vector prediction data, also known as motion vector hint data, from memory. In some embodiments, this motion vector hint data is first written to memory by the WMVP unit 477.

[0066] The MDP unit 465 determines the mode for encoding each block of the media image. Possible modes include inter-image mode, intra-image mode, and / or the like. In some embodiments, the MDP unit 465 encodes the current block according to several encoding modes and selects the mode that yields the lowest cost, with the lowest cost resulting in the smallest amount of residual data for the block. The MDP unit 465 determines the final selection from among all motion estimation candidates, determines the optimal partitioning for inter-image coding, and determines the final choice between inter-image and intra-image coding. Furthermore, the MDP unit 465 can generate motion estimation result data, motion compensation result data, and / or the like.

[0067] The MPEB Unit 466 performs and / or supports various functions for the Video Encoder 400. These functions may include, without limitation, intra-frame prediction, block size search and / or sub-block size search, reconstruction, unblocking filtering, sample adaptive offset (SAO) filtering, and / or the like. Furthermore, these functions may include, without limitation, the transformation, quantization, inverse quantization, and inverse transformation described herein.

[0068] The MPEC unit 467 performs and / or supports various functions for the video encoder 400. These functions may, without limitation, include certain entropy coding modes, such as context-adaptive variable-length coding (CAVLC), context-based adaptive binary arithmetic coding (CABAC), and / or the like.

[0069] The history unit 470 stores data in memory and loads data from memory, including spatial clues, intra-frame predictions, SAO filtering data, and entropy coding data for the current block row and / or previous block row being encoded by the video encoder 400. The history unit 470 can receive data from processed blocks in a block row, which is then accessed again while encoding blocks in the next block row. As a result, different units of the video encoder 400 can access data for adjacent blocks in the block row above the current block row being encoded.

[0070] The WMVP unit 477 writes motion vector prediction data, also known as motion vector hint data, to memory for each media frame. This motion vector hint data can be used as hint data when the video encoder 400 encodes subsequent media frames. The RMVP unit 459 can then read this motion vector hint data from memory.

[0071] Rate Distortion Optimizer Unit 425 performs rate distortion optimization on the blocks contained in a media frame of the video stream. Rate Distortion Optimizer Unit 425 selects a winning candidate for a block from between the inter-frame candidate for that block and the intra-frame candidate for that block. Rate Distortion Optimizer Unit 425 selects a winning candidate partly based on a predicted importance score generated from forward prediction clue data and backward prediction clue data. Rate Distortion Optimizer Unit 425 further receives the reconstructed pixels of the block in the reconstructed current media frame from Reconstruction Unit 430 via the feedback loop from Reconstruction Unit to FPS Unit 410.Based on the reconstructed pixels of the block in the reconstructed current media image, the rate distortion optimization unit 425 determines a rate distortion cost value based on the sum of squared errors (SSE) with respect to the distortions for the current block. The rate distortion optimization unit 425 selects the winning candidate at least partially based on the rate distortion cost value for the current block, as determined from the inter-image cost value and the intra-image cost value. In some embodiments, the rate distortion optimization unit 425 further performs a transformation operation and / or a quantization operation on the block as part of the encoding procedure. The rate distortion optimization unit 425 may also determine various mode selections, including, without limitation, block size and / or type selection, transformation size and / or type selection, and / or the like.

[0072] Reconstruction Unit 430 performs image reconstruction for the blocks contained in a media frame of the video stream, based on mode selection results received from Rate Distortion Optimization Unit 425. Reconstruction Unit 430 performs image reconstruction using frequency coefficients that were previously transformed and quantized during the encoding process. Reconstruction Unit 430 performs an inverse quantization function to reverse the quantization previously performed on the block. Reconstruction Unit 430 also performs an inverse transformation function to reverse the transformation previously performed on the block. In doing so, Reconstruction Unit 430 produces reconstructed residual data.The Reconstruction Unit 430 sums the reconstructed residual data with the winning candidate generated by the Rate Distortion Optimization Unit 425 to produce the Reconstructed Current Image Block. The Reconstructed Current Image Block is a proxy of the corresponding block of the media image that a video decoder produces when the video stream generated by the Video Encoder 400 is decoded. In some embodiments, the Reconstruction Unit 430 can improve the visual quality of the video stream by performing a secondary type search and / or size search for inter-image coding. The Reconstruction Unit 430 can also improve the visual quality of the video stream by performing an intra-image coding mode search based on accurate neighbor pixel data.

[0073] Filter 435 performs one or more filtering techniques on the blocks contained in a media frame of the video stream. These techniques may include unblocking filtering, sample adaptive offset filtering, and / or similar methods. With unblocking filtering, Filter 435 improves the visual quality of the reconstructed current block of the media frame by smoothing the sharp edges resulting from the transformation and / or quantization performed by the Rate Distortion Optimization Unit 425 during encoding, followed by the inverse quantization and / or inverse transformation performed by the Reconstruction Unit 430 during reconstruction.Furthermore, with sample adaptive offset filtering, filter 435 filters the reconstructed current block of the media image by selectively adding offsets to the pixel values ​​of the reconstructed current block of the media image based on the pixel value of a given pixel and / or the pixel values ​​of one or more neighboring pixels.

[0074] The entropy encoder 440 generates the final encoded bitstream for the video encoder 400 from the encoded blocks produced by the filter 435. In some embodiments, the entropy encoder 440 generates the final encoded bitstream, i.e., the output video stream, using a lossless compression technique. Additionally or alternatively, the entropy encoder 440 generates the final encoded bitstream using a lossy compression technique. The entropy encoder 440 encodes the blocks of a media image sequentially in raster-sampling order. The entropy encoder 440 waits until the final winning candidate data for each sequential block has been generated before encoding the bitstream for that block. In this way, the entropy encoder 440 encodes the blocks of each block row of the image sequentially and individually in raster-sampling order.In raster sampling order, the entropy encoder 440 encodes blocks on each block line of the media image from left to right and encodes the block lines of the media image from top to bottom. Since the entropy encoder 440 completes the encoding of the blocks in each media image, it stores the encoded blocks at a suitable location in the image buffer memory via the image buffer interface 480.

[0075] The Video Encoder 400 incorporates various memory-related units and / or components, including, but not limited to, DMA engines and cache memory 460. DMA engines, such as the PDMA unit 450, the RHINT unit 457, and the MEDMA unit 475, can perform block copies of data and / or instructions from one location in memory to another. Specifically, DMA engines can copy a block of data and / or instructions within a given memory location or between one memory location and another. Therefore, DMA engines can copy a block of data and / or instructions within or between one or more shared memory locations, PP memory 204, system memory 104, and / or the like.

[0076] Specifically, the PDMA unit 450 is a pixel DMA unit that loads original media image data from memory. The PDMA unit 450 can buffer multiple blocks of the original media image pixel data for motion estimation operations and for the MPEC unit 467. The PDMA unit 450 stores this original media image data in local memory for access by the FPS unit 410 and / or other units and components of the video encoder 400. The RHINT unit 457 loads external motion vector hint data from memory. The RHINT unit 457 stores this external motion vector hint data in local memory for access by the FPS unit 410 and / or other units and components of the video encoder 400. The MEDMA unit 475 stores data generated by the MDP unit 465 in memory.In particular, the MEDMA unit 475 can store motion estimation result data, motion compensation result data, original pixel data and / or the like in a dedicated MEDMA buffer in memory.

[0077] Cache 460 can store short-term data and / or commands that have recently been accessed, or are predicted to be accessed soon, by various units and / or components of the Video Encoder 400. These units include, without limitation, the FPS unit 410, the SPS unit 415, the MCT unit 420, and / or the like. In particular, Cache 460 can store reference pixels contained in reference media images for the units of the Video Encoder 400. The data and / or commands stored in Cache 460 may be copies of data and / or commands stored in other memory, including, without limitation, shared memory, PP memory 204, system memory 104, and / or the like.Typically, access times for loading data from and / or storing data in the cache memory are 460 lower than loading data from and / or storing data in these other stores.

[0078] The video encoder 400 units and / or components can access the image buffer memory (not shown) via the image buffer interface 480. The image buffer memory can be a special memory for storing image data or it can be a section of another memory, which includes, without limitation, PP memory 204, system memory 104, and / or the like. In some embodiments, the image buffer interface 480 can support data write operations from video encoder 400 units to the memory simultaneously with data read operations from the memory to the video encoder 400.

[0079] In some embodiments, the Video Encoder 400 can include feedback loops from a later stage to an earlier stage. For example, the visual quality of the output video stream can be improved by a feedback loop from the Rate Distortion Optimizer Unit 425 to the FPS Unit 410, and from the FPS Unit 410 to the SPS Unit 415 and the MCT Unit 420. With such a feedback loop, the FPS Unit 410, the SPS Unit 415, and the MCT Unit 420 can generate motion vector data for the current block in order to generate the motion vector for the following block. In this way, the Video Encoder 400 can generate a motion vector for the current block based on pixel data from the current block, as well as the motion vector from the previous block and / or the motion vector from the following block, resulting in improved motion estimation.This improved motion estimation can in turn lead to improved motion compensation.

[0080] Fig. Figure 5 illustrates a functional view of a video encoder 500, which generates a media image for the computer system 100. Fig. 1-4 according to various embodiments. The Video Encoder 500 can encode a video stream compatible with the High Efficiency Video Coding (HEVC) standard, also known as the H.265 format or the Motion Picture Experts Group High Efficiency (MPEG-H) Part 2 format. Additionally or alternatively, the Video Encoder 500, as is and / or with minor modifications, can encode a video stream compatible with any other technically feasible video coding standard.

[0081] As shown, the Video Encoder 500 receives an input media image to be encoded. This received media image is considered the current media image (F n) 505. The current media image (F n The 505 and other media images processed by the Video Encoder 500 are divided into multiple blocks. Each block contains a group of adjacent pixels, such as an 8×8 block of pixels, a 16×16 block of pixels, and / or the like. Each block is further divided into partitions, with each partition containing luminance pixels (luma pixels) and / or chrominance pixels (chroma pixels). The luma pixels contain the luma or Y pixel values ​​for the pixels in the block. The chroma pixel values ​​contain the chroma pixel values ​​for the pixels in the block. The chroma pixel values ​​are typically color difference values, also called chrominance difference values, and can be of two types: (1) red color difference (U or Cr) pixel values; and (2) blue color difference (V or Cb) pixel values.

[0082] The Video Encoder 500 also includes a reconstructed media image based on the previously received and encoded media image. This reconstructed media image is referred to as the reference media image (F'). n-1 ) 510. Based on the current pixels in the current media image (F n ) 505 and on the reference pixels in the reference media image (F' n-1The Motion Estimator (ME) 510 generates a motion vector for the current block, predicting the block of the current media frame from the corresponding block of the reference media frame. The reference media frame can be a previous media frame and / or a subsequent media frame. The Video Encoder 500 can use the motion vector as an inter-frame candidate. The Motion Estimator 515 passes the inter-frame candidate to the Motion Compensation Unit (MC) 520. The Motion Compensation Unit 520 generates motion-compensated pixels for the inter-frame candidate. The Motion Compensation Unit 520 passes the motion-compensated pixels for the inter-frame candidate to the "Inter" input of the Selector 525.

[0083] Additionally, the intra-image estimation unit selects 570 based on the current pixels in the current media image (F n) 505 and on the adjacent pixels of the reconstructed current media image uF' nThe data received by the summing unit 565 selects an intra-image prediction mode. In some embodiments, the intra-image estimating unit 570 can select the intra-image prediction mode that best predicts the pixels of the current block. The intra-image estimating unit 570 can select the intra-image prediction mode that results in the lowest rate distortion cost value based on the sum of squared errors (SSE) with respect to the distortions for the current block, as determined by the rate distortion optimization unit of the selector 525. The number and type of available prediction modes can vary based on the block size. For example, the number and type of available prediction modes may differ for 4 × 4 pixel blocks, 8 × 8 pixel blocks, 16 × 16 pixel blocks, 32 × 32 pixel blocks and / or the like.In this respect, the Intra-Image Estimation Unit 570 can select different prediction modes for each of the possible block sizes based on which prediction mode results in the lowest rate bias cost, as determined by the rate bias optimization unit for that block size. Furthermore, the Intra-Image Estimation Unit 570 can select different prediction modes for the luma values ​​in the block compared to the chroma color values ​​in the block. In some embodiments, the prediction mode determines the order in which the pixels in the current block are sampled to generate the predicted intra-image candidate.For example, the prediction mode can specify vertical scanning, horizontal scanning, diagonal scanning down left, diagonal scanning down right, vertical scanning left, vertical scanning right, horizontal scanning down, horizontal scanning up and / or the like.

[0084] Based on the selected intra-image prediction mode, the intra-image prediction unit 575 generates an intra-image candidate. The intra-image prediction unit 575 samples the pixel values ​​in the current block in the order specified by the selected intra-image prediction mode. For each sampled pixel, the intra-image prediction unit 575 determines a predicted pixel value based on the differences between the pixel value and the pixel values ​​of neighboring pixels. From the predicted pixel values, the intra-image prediction unit 575 generates the intra-image candidate. The intra-image prediction unit 575 transmits the intra-image candidate to the "Intra" input of the selector 525.

[0085] Selector 525 determines whether to select the compensated pixels for the inter-frame candidate received by the motion compensation unit 520 or the intra-frame candidate received by the intra-frame prediction unit 575. The determination of whether to select the inter-frame candidate or the intra-frame candidate can be made at any level of granularity, including, without limitation, a block-to-block, media-frame-to-media-frame basis, and / or the like. The technique for determining whether to select the inter-frame candidate or the intra-frame candidate can be relatively simple or relatively complex. Typically, the more complex the technique used to determine whether to select the inter-frame candidate or the intra-frame candidate, the higher the video quality of the resulting encoded stream.The candidate selected between the inter-image candidate and the intra-image candidate is called the winning candidate. In some embodiments, the selector 525 determines the winning candidate solely based on luma pixel values. In other embodiments, the selector 525 determines the winning candidate based on both luma pixel values ​​and chroma pixel values. In general, basing the selection on both luma pixel values ​​and chroma pixel values ​​can be more accurate and therefore result in higher visual quality than basing the selection on luma pixel values ​​alone.

[0086] In some embodiments, the selector 525 can also perform rate distortion optimization (RDO) when selecting the winning candidate. The rate distortion optimization unit (in Fig. (5 not shown) of selector 525 receives the inter-image candidate and the intra-image candidate. The rate distortion optimization unit further receives the reconstructed pixels of the reconstructed current media image uF'. n , which are received by the inverse quantization unit 555, the inverse transformation unit 560, and the summing unit 565. Based on the reconstructed pixels of the reconstructed current media image uF' n The rate bias optimization unit determines a rate bias cost value based on the sum of squared errors (SSE) with respect to the biases for the current block. Selector 525 selects the winning candidate, at least in part, based on the rate bias cost value for the current block as determined by the rate bias optimization unit. Selector 525 then passes the winning candidate to summer 530 and summer 565.

[0087] The summing unit 530 inverts the winning candidate received by the selector 525 before the winning candidate is combined with the current media image (F n ) 505 is combined. As a result, the summing unit 530 determines the difference resulting from subtracting the winning candidate from the current media image (F n ) 505. This difference is called residual pixel, residual data, or more generally, residual D. n The summing mixer 530 transmits the residual D. n to the transformation unit (T) 535.

[0088] The transformation unit 535 converts the residual D nThe data received by the summing unit 530 is transformed into an array of frequency coefficients representing the image segment contained in the respective block. The transformation unit 535 transfers the frequency coefficients to the quantization unit (Q) 540. The quantization unit 540 reduces the total number of unique frequency coefficients received by the transformation unit 535 by quantizing the frequency coefficients according to defined frequency ranges or bins. The quantization unit 540 transfers the quantized frequency coefficients X to the reordering unit 545. The reordering unit 545 sorts the quantized frequency coefficients X in descending order of value, so that all coefficients with a value of zero ("0") are sorted to the end of the set of frequency coefficients.The reordering unit 545 transmits the sorted quantized frequency coefficients to the entropy encoder 550. The entropy encoder 550 generates the final coded bitstream for the video encoder 500. In some embodiments, the entropy encoder 550 generates the final coded bitstream, i.e., the output video stream, using a lossless compression technique. Additionally or alternatively, the entropy encoder 550 generates the final coded bitstream using a lossy compression technique. The final coded bitstream generated by the video encoder 500 can then be decoded by a suitable video decoder (not shown).

[0089] In addition to transferring the quantized frequency coefficients X to the reordering unit 545, the quantization unit 540 transfers the quantized frequency coefficients X to the inverse quantization unit (Q). -1) 555. The inverse quantization unit 555 performs an inverse quantization function to reverse the quantization performed by the quantization unit 540. The inverse quantization unit 555 transfers the inverse quantized frequency coefficients to the inverse transformation unit (T). -1 ) 560. The inverse transformation unit 560 performs an inverse transformation function to reverse the transformation performed by the transformation unit 535. In doing so, the inverse transformation unit 560 generates reconstructed residual data D' n The inverse transformation unit 560 transfers the reconstructed residual data D' n to the summing unit 565.

[0090] The summing unit 565 adds the reconstructed residual data D' n to the winning candidate, which is generated by selector 525 to reconstruct the current media image uF' nto generate. The reconstructed current media image uF' n is a proxy of the media image that a video decoder generates when the video stream generated by the video encoder 500 is decoded. As described herein, the summing unit 565 transmits the reconstructed actual media image uF' n to the intra-image estimation unit 570 to generate the intra-image candidate in conjunction with the intra-image prediction unit 575. Additionally, the summer 565 transmits the reconstructed current media image uF'. n to the filter 580. In some embodiments, the filter 580 is a deblocking filter that improves the visual quality of the reconstructed actual media image uF' nImproved. Filter 580 improves visual quality by smoothing the sharp edges resulting from the transformation performed by the Transformation Unit 535 and / or the quantization performed by the Quantization Unit 540, followed by inverse quantization performed by the Inverse Quantization Unit 555 and / or inverse transformation performed by the Inverse Transformation Unit 560. Filter 580 passes the filtered image to the Sample Adaptive Offset (SAO) Filter 585. The Sample Adaptive Offset Filter 585 further filters the reconstructed actual media image uF'. n by selectively adding offsets to the pixel values ​​of the reconstructed current media image uF' nbased on the pixel value of a given pixel and / or the pixel values ​​of one or more neighboring pixels. The Sample Adaptive Offset Filter 585 stores the SAO-filtered image as the final reconstructed current media image (F'). n ) 590.

[0091] After the video encoder 500 has processed the current media image (F n ) Once 505 has completed, the video encoder 500 receives the following input media image, which then becomes the new current media image (F n ) 505 will be. Furthermore, the reconstructed current media image (F') will be n ) 590 the new reference media image (F' n-1 ) 510. The 500 video encoder uses this new reference media image (F' n-1 ) 510, to select the Inter-Bild candidate for the new current media image (F n ) to generate 505.

[0092] In some embodiments, the visual quality of the output video stream can be further improved by a feedback loop (not shown) from the selector 525 to the motion estimation unit 515. Upon selecting the winning candidate, the selector 525 determines the final motion vector for the current block. The selector 525 transmits the final motion vector for the current block to the motion estimation unit 515. The motion estimation unit 515 can use this final motion vector for the current block to generate the motion vector for the following block. In this way, the motion estimation unit 515 can generate a motion vector for the current block based on pixel data from the current block, as well as the motion vector from the previous block and / or the motion vector from the following block, resulting in improved motion estimation.This improved motion estimation can in turn lead to improved motion compensation, as performed by the motion compensation unit 520, and improved selection accuracy, as performed by the selector 525.

[0093] In some embodiments, a given block can contain multiple subblocks or partitions. The subblocks can be of different sizes. For example, a 16 × 16-pixel block can contain 8 × 16-pixel subblocks, 16 × 8-pixel subblocks, 8 × 8-pixel subblocks, and / or the like in any combination. In such embodiments, the motion estimation unit 515 can generate a motion vector for each subblock and combine the motion vectors from the different subblocks to generate a final motion vector for the block.

[0094] In some embodiments, the Video Encoder 500 can be combined with the architecture of the Video Encoder 400 from Fig. 4 can be implemented. In such embodiments, media images that, without restriction, are the current media image (F) can be used. n ) 505, the reference media image (F' n-1 ) 510 and the reconstructed current media image (F' n ) 590, be stored in any technically feasible storage medium. In particular, these media images may be stored in shared storage, cache memory 460, image buffer memory, and / or the like. The motion estimation unit 515 and / or the motion compensation unit 520 may, without restriction, control the controller 405, the FPS unit 410, the PLC unit 415, and the MCT unit 420 of Fig. 4 represent. The intra-image estimation unit 570 and / or the intra-image prediction unit 575 can, without restriction, control the controller 405, the MPEB unit 466 and the history unit 470 of Fig. 4 represent. One or more of the selector 525 (including the rate bias optimization unit of selector 525), the summer 530, the transformation unit 535 and / or the quantization unit 540 can, without restriction, represent the rate bias optimization unit 425 of Fig. 4 represent. The inverse quantization unit 555, the inverse transformation unit 560 and / or the summing unit 565 can, without restriction, represent the reconstruction unit 430 of Fig. 4 represent. The Filter 580 and / or the Sample Adaptive Offset Filter 585 can, without restriction, replace the Filter 435 of Fig. 4 represent. The Entropy Encoder 550 can, without restriction, replace the Entropy Encoder 440 from Fig. 4 represent.

[0095] It is understood that the system shown herein is for illustrative purposes only and that variations and modifications are possible. The techniques described herein can be performed by one or more alternative auxiliary processors, including, without limitation, CPUs, GPUs, video encoders, DMA units, IPUs, NPUs, TPUs, NNPs, DPUs, VPUs, ASICs, FPGAs, and / or the like in any combination. More generally, the techniques described herein can be applied with any CPU 102, PPU 202, video encoder, and / or any other processing unit in any combination.

[0096] Fig. Figure 6 illustrates how the video encoders 400 and 500 of the Fig. 4-5 can perform a sequential bitrate estimation of coding groups in a current media image according to various embodiments. As shown, the video encoder 400 and / or 500, including the controller 405, in conjunction with other units and / or components of the video encoder 400 and 500, performs a bitrate estimation for pixels contained in multiple coding groups 610(i-1), 610(i), and 610(i+1).

[0097] As described herein, the video encoder divides a media image into multiple blocks, each containing a group of pixels. In the HEVC encoding format, these blocks can be referred to as coding tree units (CTUs). In some implementations, the video can select different CTU sizes, with the size determining the number of pixels in each CTU. The size can be expressed as the number of pixel rows in the CTU (vertical dimension) multiplied by the number of pixels in each row of the CTU (horizontal dimension). Thus, the size of each CTU can be 16 × 16 pixels, 32 × 32 pixels, 64 × 64 pixels, and / or the like. Each CTU contains multiple coding tree blocks (CTBs) and syntax elements that define various parameters of the CTU.

[0098] The video encoder can further subdivide each CTU into multiple CTBs plus the syntax elements, where the CTBs include one luma (Y) CTB and two chroma (Cr and Cb) CTBs. A luma CTB has the same dimensions as the CTU, so a luma CTB covers the same pixel area as the corresponding CTU. The vertical dimension for each of the two chroma CTBs is equal to the vertical dimension of the corresponding CTU. The horizontal dimension for each of the two chroma CTBs is half the horizontal dimension of the corresponding CTU. For example, a 64 × 64-pixel CTU would contain a 64 × 64-pixel Y CTB, a 64 × 32-pixel Cr CTB, a 64 × 32-pixel Cb CTB, and various syntax elements of the CTU.In various embodiments, the video encoder can further subdivide the CTBs into one or more coding units (CUs), the CUs into prediction units (PUs), the PUs into transformation units (TUs), and the TUs into coding groups (CGs). In some embodiments, the video encoder subdivides the PUs into 16 × 16-pixel TUs and the TUs into 4 × 4-pixel CGs.

[0099] A transformation unit is the basic unit in certain video coding standards for applying transformations to difference data to produce an encoded video stream. The video encoder can use the smaller coding groups to perform context-based bitrate estimation. For each coding group, the video encoder determines the difference data coefficients for that coding group. The video encoder also determines various context-based coefficient parameters for the coefficients in that coding group. These parameters may be in the form of flags that identify specific properties of the coefficients in that coding group.

[0100] In a first example, the video encoder determines a significance coefficient flag (sig_coeff_flag) for each coding group, indicating whether all coefficients for that group are zero. The video encoder can set the significance coefficient flag to logical FALSE if all coefficients for the coding group are zero, and to logical TRUE if at least one coefficient for the coding group is not zero. In a second example, the video encoder determines an absolute level greater than one flag (coeff_abs_level_greater1_flag) for each coding group, indicating whether at least one coefficient for that group is greater than one. The video encoder can set the flag for absolute levels greater than one to logical FALSE if all coefficients for the coding group are less than or equal to one, and to logical TRUE if at least one of the coefficients for the coding group is greater than one.In a third example, the video encoder determines an absolute level greater than two flag (coeff_abs_level_greater2_flag) for each coding group, indicating whether at least one of the coefficients for that coding group is greater than two. The video encoder can set the absolute level greater than two flag to logical FALSE if all coefficients for the coding group are less than or equal to two, and to logical TRUE if at least one coefficient for the coding group is greater than two. Additionally or alternatively, the video encoder can determine other parameters associated with the coefficients for the coding groups.

[0101] Because the coding groups are small in size, such as a 4×4 group of pixels, the probability that the video encoder will find an exact match or a near match in the current media image and / or in a reference media image is high. If the video encoder finds an exact match to the current coding group, then all coefficients of the coding block are zero, and the video encoder sets the significance coefficient flag to logical FALSE. Additionally or alternatively, if the video encoder finds a near match to the current coding group, then all coefficients of the coding block can be one or zero, and the video encoder sets the absolute level greater than one flag to logical FALSE.Additionally or alternatively, if the video encoder finds a nearly identical coding group to the current coding group, then all coefficients of the coding block can be two, one, or zero, and the video encoder sets the flag for absolute levels greater than two to logical FALSE. The video encoder can use these flags to quickly estimate the bit rate needed to efficiently encode a transformation unit containing multiple coding groups. Since the probability of one or more of these flags being set to logical FALSE for a given coding group is relatively high, using these flags can be more efficient and accurate than directly analyzing the coefficients themselves.By performing a bitrate estimation using these coefficient parameters instead of just the coefficient values ​​themselves, the video encoder can estimate the bitrate more accurately by simulating how the difference data is encoded at the syntax level.

[0102] In some embodiments, the video encoder performs a bit rate estimation for a coding group based on the parameters, such as the flags described herein, for the immediately preceding coding group, as well as the parameters for the current coding group. As shown, the video encoder performs a bit rate estimation for coding group 610(i-1) based on the parameters 620(i-2) for coding group 610(i-2) (not shown) and the parameters 620(i-1) for coding group 610(i-1). The video encoder performs a bit rate estimation for coding group 610(i) based on the parameters 620(i-1) for coding group 610(i-1) and the parameters 620(i) for coding group 610(i). The video encoder performs a bitrate estimation for coding group 610(i+1) based on the parameters 620(i) for coding group 610(i) and the parameters 620(i+1) for coding group 610(i+1).The video encoder performs a bitrate estimation for encoding group 610(i+2) (not shown) based on the parameters 620(i+1) for encoding group 610(i+1) and the parameters (not shown) for encoding group 610(i+2), and so on.

[0103] In some implementations, the video encoder performs bitrate estimation as part of entropy coding according to the context-based adaptive binary arithmetic coding (CABAC) entropy coding mode. CABAC is an entropy coding technique used in HEVC encoding that adapts probability models based on the local context of the data (coefficients and syntax elements) being encoded. CABAC entropy coding can improve compression efficiency by using different probability models for different contexts, thereby reducing redundancy by adapting to different contexts. To perform bitrate estimation for CABAC, the video encoder binarizes the syntax elements associated with a coding group. These syntax elements may include a `sig_coeff_flag`, a `coeff_abs_level_greater1_flag`, a `coeff_abs_level_greater2_flag`, and / or similar elements.Binarization is a process for converting a set of elements, such as a set of syntax elements, into a binary number that uniquely identifies various relevant combinations of the elements. The video encoder determines context conditions for a coding group based on the coefficients and the binarized syntax elements for both the current coding group and the immediately preceding one. The video encoder determines a context state table index based on the context conditions for the coding group. The video encoder accesses an entry in a context state table based on the context state table index to retrieve the corresponding state. The video encoder accesses an entry in an entropy bit table based on the state to retrieve the corresponding estimated bits for the coding group.The video encoder determines the estimated bitrate based on the estimated bits for the encoding group. The video encoder updates the entry in the context state table so that subsequent bitrate estimates are more accurate for encoding groups that have the same context state table index as the current encoding group.

[0104] In some embodiments, the video encoder can determine a cost value based on the bitrate estimate. The video encoder can determine this cost value as part of rate distortion optimization, as in conjunction with the Fig. As described in sections 4-5, the video encoder can determine the cost value as cost = (λ × rate) + distortion, where λ is a fixed parameter based on the quantization parameter (QP), the rate is the estimated bit rate, and the distortion is the sum of squared errors (SSE) with respect to the distortions for the current transformation unit. The quantization parameter (QP) is a dimensionless value that determines the quantization step size applied to the coefficients of the transformation unit.

[0105] These techniques improve the accuracy of bitrate estimation compared to techniques that only analyze the coefficients for the coding groups. However, this improved accuracy can come at the cost of reduced performance due to the sequential processing of certain steps. First, because the bitrate estimation of a current coding group partially depends on parameters from a previous coding group, the video encoder waits for the bitrate estimation for the previous group to complete before performing a bitrate estimation for the current group. For example, the `coeff_abs_level_greater1_flag` for the current coding group might depend on the `coeff_abs_level_greater1_flag` for a previous coding group.Second, because a current encoding group may have the same context state table index as a previous encoding group, the video encoder waits for the bit rate estimation to complete for previous encoding groups that have the same context state table index before performing a bit rate estimation for the current encoding group. Therefore, as described herein, certain modifications can be made to the bit estimation procedure to improve encoding performance.

[0106] Fig. Figure 7 illustrates how the 400 and 500 video encoders of the Fig. 4-5 can perform a parallel bitrate estimation of coding groups in a current media image according to various embodiments. As shown, the video encoder 400 and / or 500, including the controller 405 in conjunction with other units and / or components of the video encoder 400 and 500, performs a bitrate estimation of pixels contained in multiple coding groups 710(j-1), 710(j), and 710(j+1) in parallel and not sequentially, as in conjunction with Fig. Figure 6 shows that, in order to perform a bitrate estimation on pixels contained in multiple encoding groups 710(j-1), 710(j) and 710(j+1), the video encoder makes certain assumptions and implements certain trade-offs.

[0107] First, the video encoder removes the dependence of the bitrate estimation of a current coding group on parameters from a previous coding group. Instead of using the parameters from a previous coding group, the video encoder can assign default values ​​to pixel values ​​and parameters from the previous coding group. For example, if determining certain parameters for the current coding group relies on neighboring pixels within the current coding group, the video encoder pre-samples the coefficients in the current coding group to determine the neighboring pixel values ​​for the coefficients of the current coding group.However, if determining certain parameters for the current encoding group depends on neighboring pixels that are in one or more other encoding groups, then the video encoder assigns default values ​​such as zero to these neighboring pixels or treats these neighboring pixels as if they were unavailable.

[0108] For example, in sequential bitrate estimation, the video encoder can select the context conditions for a coding group based on the `coeff_abs_level_greater1_flag` for the immediately preceding coding group and the `coeff_abs_level_greater1_flag` for the current coding group. In parallel bitrate estimation, the video encoder can assume that the immediately preceding coding group contains no coefficients greater than one (that is, that the `coeff_abs_level_greater1_flag` for the immediately preceding coding group is assumed to be logically FALSE). The video encoder determines the `coeff_abs_level_greater1_flag` for the current coding group based on the pre-sampled coefficients for the current coding group.The video encoder determines the context conditions and the corresponding context state table index based on a logically FALSE value for the `coeff_abs_level_greater1_flag` for the immediately preceding coding group and on the `coeff_abs_level_greater1_flag` determined by the pre-sampled coefficients for the current coding group. This technique eliminates the dependency of pixel data on neighboring coding groups.

[0109] Second, the video encoder can eliminate the bitrate estimation step of updating the context state table entry based on the results of the current coding group's bitrate estimation. Instead, the video encoder uses a fixed-value context state table to estimate the bitrate for each coding group. As a result, subsequent coding groups that have the same context state table index as the current coding group do not benefit from context state table updates based on the results of the current coding group's bitrate estimation. On the other hand, the bitrate estimation for these subsequent coding groups no longer depends on, or waits for, the bitrate estimation results from the current coding group.

[0110] One or both of these assumptions can improve coding performance by running multiple coding groups in parallel, at the cost of slightly reduced bitrate estimation accuracy compared to those associated with Fig. The six described techniques can be used. As a result, the video encoder can generate parameter 720(j-1) for coding group 710(j-1) without waiting for parameters or results from previous coding groups (not shown). Similarly, the video encoder can generate parameter 720(j) for coding group 710(j) without waiting for parameter 720(j-1) or results from coding group 710(j-1) and / or parameters or results from previous coding groups (not shown). Likewise, the video encoder can generate parameter 720(j+1) for coding group 710(j+1) without waiting for parameter 720(j) or results for coding group 710(j), parameter 720(j-1) or results from coding group 710(j-1) and / or parameters or results from previous coding groups (not shown), and so on.Instead, the video encoder can generate parameter 720(j-1) for coding group 710(j-1), parameter 720(j) for coding group 710(j), parameter 720(j+1) for coding group 710(j+1) and parameter 720 for other component groups 710 independently and in parallel without dependencies between the coding groups 710.

[0111] It is understood that the system shown herein is for illustrative purposes only and that variations and modifications are possible. The disclosed techniques are described in the context of the HEVC video coding format. However, the techniques can be applied to encode a video stream in any suitable coding format. Furthermore, the disclosed techniques are described in the context of 16×16 pixel transform units and 4×4 pixel coding groups. However, the techniques can be applied to encode a video stream with any size of transform units and / or coding groups.

[0112] Fig. Figure 8 is a flowchart of process steps for encoding blocks of a media image using the 400 and 500 video encoders. Fig. 4-5 according to various embodiments. Additionally or alternatively, the process steps can be performed by one or more alternative auxiliary processors, including, without limitation, microcontrollers, RISC processors, CPUs, GPUs, DMA units, IPUs, NPUs, TPUs, NNPs, DPUs, VPUs, ASICs, FPGAs and / or the like in any combination. Although the process steps in conjunction with the systems of Fig. As described in 1-7, the person skilled in the art will understand that any system configured to perform the process steps in any order is within the scope of this disclosure.

[0113] As shown, a procedure 800 begins at step 802, where a video encoder, such as the Video Encoder 400 and / or the Video Encoder 500, determines one or more parameters for a set of coefficients associated with a block, such as the current coding group for which a bit rate estimation is performed. The one or more parameters may include a significance coefficient flag indicating whether all coefficients for the block are zero. Additionally or alternatively, the one or more parameters may include an absolute level greater than one flag indicating whether at least one of the coefficients for the coding group is greater than one. Additionally or alternatively, the one or more parameters may include an absolute level greater than two flag indicating whether at least one of the coefficients for the coding group is greater than two.Additionally or alternatively, one or more parameters may include other suitable parameters for the coefficients of the coding group.

[0114] At step 804, the video encoder estimates a bit rate for encoding the block based on one or more set parameters. The video encoder determines context conditions for the coding group based on the coefficients in the coding group and on one or more parameters for the current coding group. The video encoder determines the context conditions for the current coding group independently of the parameters of other coding groups. The video encoder determines an index of a context state table based on the context conditions for the coding group. The video encoder accesses an entry in the context state table based on the context state table index to retrieve a corresponding state. The video encoder accesses an entry in an entropy bit table based on the state to retrieve corresponding estimated bits for the coding group.The video encoder determines the estimated bitrate based on the estimated bits for the encoding group.

[0115] At step 806, the video encoder determines a cost value based on the estimated bit rate. The video encoder can determine this cost value as part of rate distortion optimization. The video encoder can determine the cost value as Cost = (λ × Rate) + Distortion, where λ is a fixed parameter based on the quantization parameter (QP), the rate is the estimated bit rate, and the distortion is the sum of squared errors (SSE) with respect to the distortions for the current transformation unit. The quantization parameter (QP) is a dimensionless value that determines the quantization step size applied to the transformation unit coefficients.

[0116] At step 808, the video encoder encodes the block based on its cost value and / or estimated bitrate. The video encoder can encode the block according to the High Efficiency Video Coding (HEVC) format, also known as the H.265 format or the Motion Picture Experts Group High Efficiency (MPEG-H) Part 2 format. Additionally or alternatively, the video encoder can encode the block according to any one or more other suitable video coding formats.

[0117] In step 810, the video encoder determines whether resources are available to encode another block in parallel with blocks currently being encoded. If resources are available to encode another block in parallel, procedure 800 returns to step 802 as described above. Conversely, if resources are not available to encode another block in parallel, procedure 800 proceeds to step 812, where the video encoder waits until resources are available to encode additional blocks. Procedure 800 then returns to step 802 as described above.

[0118] In summary, a video encoder performs context-based bitrate estimation to generate more accurate bitrates for encoding transformation units in a media image. Bitrates can be expressed as a cost value, so the cost increases with increasing bitrate. A transformation unit is the basic unit in certain video coding standards for applying transformations to difference data to produce an encoded video stream. This difference data is also called residuals or residual data. Each transformation unit is a group of pixels of a specific size, such as a 4×4 group of pixels, an 8×8 group of pixels, a 16×16 group of pixels, a 32×32 group of pixels, and / or the like. The video encoder divides each media image into multiple media segments, also called slices, with each media segment containing multiple transformation units.The video encoder estimates the bitrate for encoding blocks of a current media image based on various parameters associated with the block coefficients, rather than solely on the coefficients themselves. The video encoder then uses the estimated bitrate to encode the transformation units within the video segment.

[0119] Additionally, the disclosed techniques eliminate certain data dependencies when encoding the differential data associated with the blocks of the media image. Specifically, when the video encoder encodes a first block that has adjacent pixels in a second block, the video encoder can encode the first block using default pixel values ​​instead of using the actual pixel data from the pixels of the second block. As a result, the video encoder can encode the first and second blocks independently and in parallel.

[0120] At least one technical advantage of the disclosed techniques compared to the prior art is that the video encoder using the disclosed techniques estimates the bitrate for encoding blocks of an actual media image based on various parameters associated with the coefficients of the blocks, rather than solely based on the coefficients themselves. As a result, the visual quality of the resulting video stream can be higher compared to conventional approaches. Furthermore, the video encoder using the disclosed techniques can predict the bitrate of the encoded video stream more accurately, which allows the video encoder to select encoding parameters that further improve the accuracy and visual quality of the encoded video stream.Another technical advantage of the disclosed techniques is that the encoding of a current block of the current media image is no longer dependent on other blocks of the current media image. As a result, adjacent blocks of a media image can be encoded in parallel rather than sequentially, leading to improved video encoding performance compared to conventional video encoding techniques. These advantages represent one or more technological improvements over prior art approaches.

[0121] All combinations of claim elements listed in the claims and / or of elements described in this application fall in any way within the considered scope of the present disclosure and protection.

[0122] The descriptions of the various embodiments serve for illustrative purposes but do not claim to be exhaustive or limited to the disclosed embodiments. Many modifications and variations are obvious to the person skilled in the art without affecting the scope and spirit of the described embodiments.

[0123] Aspects of the present embodiments may be implemented as a system, method, or computer program product. Accordingly, aspects of the present disclosure may take the form of a purely hardware implementation, a purely software implementation (including firmware, resident software, microcode, etc.), or an embodiment that combines software and hardware aspects, all of which may be generally referred to herein as a "module" or "system." Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer-readable media containing computer-readable program code.

[0124] Any combination of one or more computer-readable media can be used. The computer-readable medium can be a computer-readable signaling medium or a computer-readable storage medium. A computer-readable storage medium can be, for example, but not exclusively, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing.More specific examples (a non-exhaustive list) of computer-readable storage medium would include: an electrical connection with one or more wires, a portable computer disk, a hard disk, random-access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only storage device (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. For the purposes of this document, computer-readable storage medium can be any tangible medium capable of containing or storing a program for use by or in conjunction with a command-execution system, device, or apparatus.

[0125] Aspects of the present disclosure are described above with reference to flowchart diagrams and / or block diagrams of processes, devices (systems), and computer program products according to embodiments of the disclosure. It is understood that each block of the flowchart diagrams and / or block diagrams, and combinations of blocks in the flowchart diagrams and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to create a machine such that the instructions executed by the processor of the computer or other programmable data processing device enable the implementation of the functions / actions specified in the flowchart and / or in a block or blocks of a block diagram.Such processors can be, without restriction, general-purpose processors, special-purpose processors, application-specific processors, or field-programmable gate arrays.

[0126] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, procedures, and computer program products according to various embodiments of the present disclosure. In this respect, each block in the flowchart or block diagrams can represent a module, segment, or section of code comprising one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions specified in the blocks may occur in a different order than that shown in the figures. For example, two blocks shown consecutively may in reality be executed essentially simultaneously, or the blocks may sometimes be executed in reverse order, depending on the specific functionality.It should also be noted that each block of the block diagrams and / or flowchart representation, as well as combinations of blocks in the block diagrams and / or flowchart representation, can be implemented by special hardware-based systems that perform the specified functions or actions, or by combinations of special hardware and computer instructions.

[0127] While the foregoing relates to embodiments of the present disclosure, other and further embodiments of the disclosure may be developed without affecting the fundamental scope of the disclosure, and the scope of the disclosure is determined by the following claims.

Images