Semiconductor device

Abstract

A semiconductor device according to the present disclosure comprises a dummy active trench having an upper electrode and a lower electrode. The upper electrode is connected to the gate electrode or the emitter electrode, or is at an unconnected potential. The lower electrode is connected to the gate electrode or the emitter electrode, or is at an unconnected potential. The dummy active trench has an upper insulating layer formed on a side surface of the upper electrode, a lower insulating layer formed on a side surface of the lower electrode, and a boundary insulating layer formed between the upper electrode and the lower electrode. The thickness of the upper insulating layer in a right-to-left direction is greater than the thickness of the lower insulating layer in the same right-to-left direction.In a cross-sectional view, the area of ​​the upper electrode is smaller than the area of ​​the lower electrode.

Description

Background Technical field

[0001] The present disclosure relates to a semiconductor device that can be controlled by a gate signal in a conductor. Description of the state of the art

[0002] An insulated-gate bipolar transistor (IGBT) must achieve both a reduction in recovery dv / dt, which correlates with a disturbance signal, and a reduction in turn-on loss. This is effectively accomplished by increasing Cgc / Cge, which represents the gate capacitance ratio. Here, Cgc is the capacitance between a gate electrode and a collector electrode, and Cge is the capacitance between the gate electrode and an emitter electrode.

[0003] In a conventionally known semiconductor device, an increase in Cgc / Cge is stimulated by providing a two-part dummy active trench structure (see, for example, the published Japanese patent application No. 2022-78755).

[0004] According to published Japanese patent application No. 2022-78755, a breakthrough of a boundary insulation layer formed between an upper dummy part and a lower active part of the two-part dummy-active trench can be caused by a potential difference generated between the upper dummy part and the lower active part, resulting in a problem with the reliability of the insulation layer. The reliability of the insulation layer can be improved by increasing the thickness of a lower insulation layer formed on a side surface of the lower active part. However, increasing the thickness of the lower insulation layer increases the stress exerted on a cell part, leading to significant chip warping. Thus, a problem to be solved is to achieve both an improvement in the reliability of the insulation layer and the suppression of chip warping. Summary

[0005] The present disclosure aims to provide a semiconductor device suitable for achieving both an improvement in the reliability of an insulating layer and a suppression of chip warping.

[0006] A semiconductor device according to the present disclosure comprises: a semiconductor substrate; an emitter electrode formed on the semiconductor substrate; a gate electrode formed on the semiconductor substrate; a drift layer of a first conductivity type formed in the semiconductor substrate; a source layer of a first conductivity type formed in an upper surface face of the semiconductor substrate; a base layer of a second conductivity type formed in the upper surface face of the semiconductor substrate; a collector electrode formed below the semiconductor substrate; and a dummy active trench comprising an upper electrode and a lower electrode, respectively, provided in an upper and a lower part of a trench in the semiconductor substrate. The upper electrode is connected to the gate electrode or the emitter electrode or is at an unconnected potential.The lower electrode is connected to the gate electrode or the emitter electrode, or it is at an unconnected potential. The dummy active trench has an upper insulating layer formed on a side surface of the upper electrode, a lower insulating layer formed on a side surface of the lower electrode, and a boundary insulating layer formed between the upper and lower electrodes. The thickness of the upper insulating layer in a right-to-left direction is greater than the thickness of the lower insulating layer in the same direction. In a sectional view, the area of ​​the upper electrode is smaller than the area of ​​the lower electrode.

[0007] According to the present disclosure, it is possible to achieve both an improvement in the reliability of an insulating layer and a suppression of chip warping.

[0008] These and other tasks, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present disclosure when it is taken in conjunction with the accompanying drawings. Brief description of the drawings Fig. 1 is a sectional view of a semiconductor device according to a first preferred embodiment; Fig. 2 is a sectional view of a semiconductor device according to a first modification of the first preferred embodiment; Fig. 3 is a sectional view of a semiconductor device according to a second modification of the first preferred embodiment; Fig. 4 is a sectional view of a semiconductor device according to a fourth modification of the first preferred embodiment; Fig. Figure 5 is a sectional view of a semiconductor device according to a seventh modification of the first preferred embodiment; Fig. 6 is a sectional view of a semiconductor device according to an eighth modification of the first preferred embodiment; Fig. Figure 7 is a sectional view of a semiconductor device according to a ninth modification of the first preferred embodiment; Fig. Figure 8 is a sectional view of a semiconductor device according to a tenth modification of the first preferred embodiment; Fig. 9 is a sectional view of a semiconductor device according to a twelfth modification of the first preferred embodiment; Fig. 10 is a sectional view of a semiconductor device according to a thirteenth modification of the first preferred embodiment; Fig. 11 is a sectional view of a semiconductor device according to a fourteenth modification of the first preferred embodiment; Fig. 12 is a top view of the semiconductor device according to the fourteenth modification of the first preferred embodiment; Fig. 13 is a sectional view of a semiconductor device according to a fifteenth modification of the first preferred embodiment; Fig. Figure 14 is a sectional view of a semiconductor device according to a sixteenth modification of the first preferred embodiment; Fig. 15 is a sectional view of a semiconductor device according to a seventeenth modification of the first preferred embodiment; Fig. 16 is a sectional view of a semiconductor device according to a second preferred embodiment; Fig. 17 is a sectional view of a semiconductor device according to a first modification of the second preferred embodiment; Fig. 18 is a sectional view of a semiconductor device according to a second modification of the second preferred embodiment; Fig. 19 is a sectional view of a semiconductor device according to a third modification of the second preferred embodiment; Fig. 20 is a sectional view of a semiconductor device according to a fourth modification of the second preferred embodiment; Fig. 21 is a sectional view of a semiconductor device according to a fifth modification of the second preferred embodiment; Fig. Figure 22 is a sectional view of a semiconductor device according to a sixth modification of the second preferred embodiment; Fig. 23 is a sectional view of a semiconductor device according to the sixth modification of the second preferred embodiment, taken along Y1 - Y2; Fig. Figure 24 is a top view of a semiconductor device according to a seventh modification of the second preferred embodiment; Fig. 25 is a sectional view of a semiconductor device according to the seventh modification of the second preferred embodiment, taken along Y3 - Y4; Fig. 26 is a sectional view of a semiconductor device according to an eighth modification of the second preferred embodiment; and Fig. Figure 27 is a sectional view of a semiconductor device according to another example of a ninth modification of the second preferred embodiment. Description of preferred embodiments

[0009] Semiconductor devices according to preferred embodiments are described below by reference to the drawings. The same or corresponding components are assigned the same reference numerals, and repeated descriptions thereof may be omitted. In the following description, n and p denote conductivity types of a semiconductor. In the present disclosure, a description is given with a first conductivity type, which is characterized as the n-type, and a second conductivity type, which is characterized as the p-type. These conductivity types may be reversed. <Erste bevorzugte Ausführungsform>

[0010] Fig. Figure 1 is a sectional view of a semiconductor device according to a first preferred embodiment. Fig. 1. A semiconductor substrate lies in a region from a source layer 3 to a collector layer 14. In Fig. 1. The upper end of the source layer 3 in the plane of the drawing is called the upper surface of the semiconductor substrate, and the lower end of the collector layer 14 in the plane of the drawing is called the lower surface of the semiconductor substrate. The upper surface and the lower surface are opposite each other.

[0011] As in Fig. As shown in Figure 1, the semiconductor device has an n-type drift layer 12 provided between the upper surface and the lower surface of the semiconductor substrate.

[0012] An n-type charge carrier accumulation layer 5, which has a higher n-type impurity concentration than the drift layer 12, is provided on an upper surface face of the drift layer 12. The charge carrier accumulation layer 5 is located between a base layer 4 and the drift layer 12. The provision of the charge carrier accumulation layer 5 causes an electric field to concentrate at a lower end of the charge carrier accumulation layer 5. This allows an electric field strength to be relaxed between an upper electrode 7 and a lower electrode 10, which makes it possible to improve the reliability of an insulating layer. In the configuration of the semiconductor device, instead of providing the charge carrier accumulation layer 5, the drift layer 12 can be further extended in a Fig. The area shown in Figure 1 is provided for the charge carrier accumulation layer 5.

[0013] The base layer 4 of the p-type is located on an upper surface of the charge carrier accumulation layer 5. The source layer 3 of the n-type is located on an upper surface of the base layer 4.

[0014] The semiconductor substrate is provided with a dummy active trench 11. The dummy active trench 11 has an upper electrode 7 and a lower electrode 10, each located in an upper and lower part of a trench in the semiconductor substrate. The upper electrode 7 is connected to a gate electrode (not shown in the drawings) or to an emitter electrode 1, or is at an unconnected potential. The lower electrode 10 is connected to the gate electrode (not shown in the drawings) or to the emitter electrode 1, or is at an unconnected potential. As an example, the upper electrode 7 is connected to a part other than the gate electrode, and the lower electrode 10 is connected to the gate electrode. The "trough" represents a hole provided in the semiconductor substrate or a structure formed in the hole.

[0015] The dummy active trench 11 has an upper insulating layer 6 formed on a side surface of the upper electrode 7, a lower insulating layer 9 formed on a side surface of the lower electrode 10, and a boundary insulating layer 8 formed between the upper electrode 7 and the lower electrode 10. The upper electrode 7 and the lower electrode 10 are electrically separated from each other by means of the boundary insulating layer 8. The thickness T1 of the upper insulating layer 6 in a right-to-left direction is greater than the thickness T3 of the lower insulating layer 9 in the same right-to-left direction. The right-to-left direction mentioned here is a direction (a lateral direction of the dummy active trench 11) perpendicular to a depth direction of the dummy active trench 11. In a cross-sectional view, the area of ​​the upper electrode 7 is smaller than the area of ​​the lower electrode 10.

[0016] An intermediate insulation layer 2 is provided on the dummy active trench 11. The emitter electrode 1 is provided above the source layer 3 and the intermediate insulation layer 2.

[0017] An n-type buffer layer 13, which has a higher n-type impurity concentration than the drift layer 12, is provided on a lower surface side of the drift layer 12. In the configuration of the semiconductor device, instead of providing the buffer layer 13, the drift layer 12 can be extended further in a region of the Fig. Buffer layer 13 shown in 1 is provided.

[0018] The p-type collector layer 14 is provided on a lower surface side of the buffer layer 13. A collector electrode 15 is provided on a lower surface side of the collector layer 14.

[0019] According to the first preferred embodiment, the small thickness T3 of the lower insulating layer 9 prevents chip warping. Furthermore, the large thickness T1 of the upper insulating layer 6 reduces the area of ​​the upper electrode 7, thus improving the reliability of the insulating layer. Because the area of ​​the upper electrode 7, which faces the thick upper insulating layer 6 and is subject to high stress, is smaller than the area of ​​the lower electrode 10, which faces the thin insulating layer 9 and is subject to low stress, the overall stress is further reduced, preventing chip warping. In particular, the first preferred embodiment makes it possible to achieve both an improvement in the reliability of the insulating layer and the suppression of chip warping. <Erste Modifikation>

[0020] Fig. Figure 2 is a sectional view of a semiconductor device according to a first modification of the first preferred embodiment. As in Fig. As shown in Figure 2, in the semiconductor device according to the first modification, the thickness T2 of the boundary insulation layer 8 is greater in a top-to-bottom direction than the thickness T3 of the lower insulation layer 9 in a right-to-left direction. In a sectional view, the area of ​​the upper electrode 7 is smaller than the area of ​​the lower electrode 10. The top-to-bottom direction mentioned here is the depth direction of the dummy active trench 11.

[0021] According to the first modification, the small thickness T3 of the lower insulation layer 9 in the right-to-left direction prevents chip warping. Furthermore, the large thickness T2 of the boundary insulation layer 8 in the top-to-bottom direction increases the distance between the upper electrode 7 and the lower electrode 10, thus improving the reliability of the insulation layer. <Zweite Modifikation>

[0022] Fig. Figure 3 is a sectional view of a semiconductor device according to a second modification of the first preferred embodiment. As in Fig. As shown in Figure 3, the thickness T1 of the upper insulation layer 6 (from right to left), the thickness T2 of the boundary insulation layer 8 (from top to bottom), and the thickness T3 of the lower insulation layer 9 (from right to left) have the following ratio: thickness T2 of the boundary insulation layer 8 (from top to bottom) > thickness T1 of the upper insulation layer 6 (from right to left) > thickness T3 of the lower insulation layer 9 (from right to left). That is, thickness T2 of the boundary insulation layer 8 (from top to bottom) is the greatest thickness, thickness T1 of the upper insulation layer 6 (from right to left) is the next greatest thickness, and thickness T3 of the lower insulation layer 9 (from right to left) is the smallest thickness.

[0023] According to the second modification, since the thickness T2 of the boundary insulation layer 8 is greater in the top-to-bottom direction than the thickness T1 of the upper insulation layer 6 in the right-to-left direction, it is possible to reduce the length ratio of the length L1 of the upper electrode 7 in the top-to-bottom direction (the depth of the upper electrode 7) relative to the length W1 of the upper electrode 7 in the right-to-left direction (the width of the upper electrode 7) (L1 / W1). This makes it possible to improve the embedding of the upper electrode 7. <Dritte Modifikation>

[0024] As in the Fig. 1 and Fig. In the semiconductor devices shown in Figure 3, the boundary insulation layer 8 can be arranged above the center of the dummy active trench 11 in the direction from top to bottom.

[0025] Using this configuration makes the area of ​​the upper electrode 7, which faces the thick upper insulation layer 6, which is subject to high stress, smaller than the area of ​​the lower electrode 10, which faces the thin lower insulation layer 9, which is subject to low stress. This reduces the overall stress, making it possible to prevent chip warping. <Vierte Modifikation>

[0026] Fig. 4 is a sectional view of a semiconductor device according to a fourth modification of the first preferred embodiment. As in Fig. As shown in Figure 4, a length L2 from the upper surface of the semiconductor substrate to an upper end of the lower electrode 10 is greater than a length P1 from the upper surface of the semiconductor substrate to a lower end of the base layer 4 in the top-to-bottom direction.

[0027] If the upper end of the lower electrode 10 protrudes into the base layer 4, Cge is increased, thus reducing Cgc / Cge. According to the fourth modification, designing the length L2 from the upper surface of the semiconductor substrate to the upper end of the lower electrode 10 to be greater than the length P1 of the base layer 4 in the top-to-bottom direction allows for a reduction in Cge, which makes it possible to achieve both a reduction in recovery dv / dt and a reduction in turn-on loss.

[0028] Although the fourth modification in the exemplary case described above is in Fig. The fourth modification can be implemented in the semiconductor device shown in 3, which is used in the Fig. 1 or Fig. The semiconductor device shown in section 2 can be used. <Fünfte Modifikation>

[0029] As in the Fig. In the semiconductor devices shown in Figures 1 to 3, the boundary insulation layer 8 can be arranged above the lower end of the charge carrier accumulation layer 5.

[0030] The use of this configuration allows the boundary insulation layer 8, which is involved in the reliability of the insulation layer, to be separated from the lower end of the charge carrier accumulation layer 5 as a region of a high electric field, thus enabling the reliability of the insulation layer to be improved. <Sechste Modifikation>

[0031] As in the Fig. In the semiconductor devices shown in 1 to 3, the boundary insulation layer 8 can be arranged above the center of the charge carrier accumulation layer 5.

[0032] The use of this configuration allows the boundary insulation layer 8, which is involved in the reliability of the insulation layer, to be further separated from the lower end of the charge carrier accumulation layer 5 as a region of high electric field, thus enabling the reliability of the insulation layer to be improved. <Siebte Modifikation>

[0033] Fig. Figure 5 is a sectional view of a semiconductor device according to a seventh modification of the first preferred embodiment. Fig. Figure 5 shows a distribution of an impurity concentration in the charge carrier accumulation layer 5 in the in Fig. 3 semiconductor device shown. As in Fig. As shown in Figure 5, the boundary insulation layer 8 can be arranged above a maximum value position of the impurity concentration in the charge carrier accumulation layer 5.

[0034] Compared to a position lower than the peak impurity concentration in charge carrier accumulation layer 5 (a position closer to the lower surface of the semiconductor substrate), it is difficult to extend a depletion layer to reduce the electric field at a position shallower than the peak impurity concentration in charge carrier accumulation layer 5 (a position closer to the upper surface of the semiconductor substrate). According to the seventh modification, it is possible to further separate the boundary insulation layer 8, which contributes to the reliability of the insulation layer, from the peak impurity concentration in charge carrier accumulation layer 5, a region of high electric field, thus improving the reliability of the insulation layer.

[0035] Although the seventh modification in the exemplary case described above is in Fig. The seventh modification of the semiconductor device shown in section 3 can be used in the Fig. 1 or Fig. The semiconductor device shown in section 2 can be used. <Achte Modifikation>

[0036] Fig. Figure 6 is a sectional view of a semiconductor device according to an eighth modification of the first preferred embodiment. As in Fig. As shown in Figure 6, the length L3 of the lower electrode 10 in the top-to-bottom direction can be greater than the length L1 of the upper electrode 7 in the top-to-bottom direction.

[0037] According to the eighth modification, by making the length L3 of the lower electrode 10 in the top-to-bottom direction, which has a side surface provided with the thin lower insulating layer 9, which is effective against chip bulging, greater than the length L1 of the upper electrode 7 in the top-to-bottom direction, which has a side surface provided with the thick upper insulating layer 6, it is possible to improve the effect of preventing chip bulging.

[0038] Although the eighth modification in the exemplary case described above is in Fig. The eighth modification in the semiconductor device shown in section 3 can be used. Fig. 1 or Fig. The semiconductor device shown in section 2 can be used. <Neunte Modifikation>

[0039] Fig. Figure 7 is a sectional view of a semiconductor device according to a ninth modification of the first preferred embodiment. As in Fig. As shown in Figure 7, the length L1 of the upper electrode 7 in the top-to-bottom direction can be shorter than the length P1 from the upper surface of the semiconductor substrate to a lower end of the base layer 4 in the top-to-bottom direction.

[0040] According to the ninth modification, reducing the length L1 of the upper electrode 7 in the top-to-bottom direction makes it possible to reduce the length ratio of the length L1 of the upper electrode 7 in the top-to-bottom direction (the depth of the upper electrode 7) relative to the length W1 of the upper electrode 7 in the right-to-left direction (the width of the upper electrode 7) (L1 / W1). This improves the embedding properties of the upper electrode 7.

[0041] Although the ninth modification in the exemplary case described above is in Fig. The semiconductor device shown in section 3 is used, and the ninth modification can be implemented in the Fig. 1 or Fig. The semiconductor device shown in section 2 can be used. <Zehnte Modifikation>

[0042] Fig. Figure 8 is a sectional view of a semiconductor device according to a tenth modification of the first preferred embodiment. As in Fig. As shown in Figure 8, the length L1 of the upper electrode 7 in the top-to-bottom direction can be shorter than the length W1 of the upper electrode 7 in the right-to-left direction.

[0043] According to the tenth modification, by reducing the length L1 of the upper electrode 7 in the top-to-bottom direction and increasing the length W1 of the upper electrode 7 in the right-to-left direction, it is possible to reduce the length ratio of the length L1 of the upper electrode 7 in the top-to-bottom direction (the depth of the upper electrode 7) relative to the length W1 of the upper electrode 7 in the right-to-left direction (the width of the upper electrode 7) (L1 / W1). This makes it possible to improve the embedding properties of the upper electrode 7.

[0044] Although the tenth modification in the exemplary case described above is in Fig. The semiconductor device shown in section 3 is used, and the tenth modification can be found in the Fig. 1 or Fig. The semiconductor device shown in section 2 can be used. <Elfte Modifikation>

[0045] In the Fig. In the semiconductor devices shown in 1 to 3, the material for the lower electrode 10 can be amorphous silicon.

[0046] According to the eleventh modification, by using amorphous silicon, which has fewer surface irregularities than polysilicon, as a material for the lower electrode 10, it becomes possible to relax an electric field strength between the upper electrode 7 and the lower electrode 10, which makes it possible to improve the reliability of the insulating layer. <Zwölfte Modifikation>

[0047] Fig. Figure 9 is a sectional view of a semiconductor device according to a twelfth modification of the first preferred embodiment. As in Fig. As shown in Figure 9, the length ratio of the length L1 of the upper electrode 7 in the direction from top to bottom (the depth of the upper electrode 7) relative to the length W1 of the upper electrode 7 in the direction from right to left (the width of the upper electrode 7) (L1 / W1) can be designed to be smaller than the length ratio of a length L2 of the lower electrode 10 in the direction from top to bottom (the depth direction of the lower electrode 10) relative to a length W2 of the lower electrode 10 in the direction from right to left (the width of the lower electrode 10) (L2 / W2).

[0048] According to the twelfth modification, by designing the length ratio of the upper electrode 7 (L1 / W1) to be smaller than the length ratio of the lower electrode 10 (L2 / W2), it is possible to improve the embedding of the upper electrode 7.

[0049] Although the twelfth modification in the exemplary case described above is in Fig. The semiconductor device shown in section 3 is used, and the twelfth modification can be found in the Fig. 1 or Fig. The semiconductor device shown in section 2 can be used. <Dreizehnte Modifikation>

[0050] Fig. Figure 10 is a sectional view of a semiconductor device according to a thirteenth modification of the first preferred embodiment. As in Fig. As shown in Figure 10, the intermediate insulation layer 2 can be omitted from one point above the upper electrode 7.

[0051] According to the thirteenth modification, the absence of the intermediate insulation layer 2 above the upper electrode 7 allows current flowing in the upper electrode 7 to be emitted directly to the emitter electrode 1. In particular, the voltage drop caused by the current flowing in the upper electrode 7 becomes less significant, thus reducing the stress on the insulation layer caused by this voltage drop. This, in turn, improves the reliability of the insulation layer.

[0052] Although the thirteenth modification in the exemplary case described above is in Fig. The semiconductor device shown in section 3 is used, and the thirteenth modification can be found in the Fig. 1 or Fig. The semiconductor device shown in section 2 can be used. <Vierzehnte Modifikation>

[0053] Fig. Figure 11 is a sectional view of a semiconductor device according to a fourteenth modification of the first preferred embodiment. Fig. 12 is a top view of the in Fig. 11 Semiconductor device shown, photographed from the side of the upper surface. As in Fig. As shown in Figure 11, the dummy active trench 11 has a side contact 20 which has a side surface on one side in contact with the source layer 3 and the base layer 4.

[0054] Using this configuration allows the source layer 3 and the base layer 4 to be electrically connected to the emitter electrode 1 via the side contact 20. This enables a reduction in the width of the next active trench (see, for example, Fig. 16, which is referred to below) (a contact width of a mesa part), thereby realizing a finer cell part size. The finer design of the cell part makes it possible to improve the characteristics of the semiconductor device, such as voltage reduction.

[0055] Although the fourteenth modification in the exemplary case described above is in Fig. The semiconductor device shown in section 3 is used, and the fourteenth modification can be found in the Fig. 1 or Fig. The semiconductor device shown in section 2 can be used. <Fünfzehnte Modifikation>

[0056] Fig. Figure 13 is a sectional view of a semiconductor device according to a fifteenth modification of the first preferred embodiment. As in Fig. As shown in Figure 13, the side contact 20 can have a side surface on one side in contact with the source layer 3 and the base layer 4 and a side surface on the other side in contact with the upper electrode 7.

[0057] In addition to the effect achieved by the fourteenth modification, the use of this configuration allows the upper electrode 7 to be connected to the emitter electrode 1 further from a transverse side via the side contact 20. This increases the contact area of ​​the upper electrode 7, which makes it possible to improve the stability of a potential with respect to the emitter electrode 1.

[0058] Although the fifteenth modification in the exemplary case described above is in Fig. The semiconductor device shown in section 3 is used, and the fifteenth modification can be found in the Fig. 1 or Fig. The semiconductor device shown in section 2 can be used. <Sechzehnte Modifikation>

[0059] Fig. Figure 14 is a sectional view of a semiconductor device according to a sixteenth modification of the first preferred embodiment. As in Fig. As shown in Figure 14, the length SC1 of the side contact 20 in the top-to-bottom direction (the depth direction of the side contact 20) can be greater than the length SS1 of the source layer 3 in the top-to-bottom direction (the depth direction of the source layer 3).

[0060] The use of this configuration allows for an increase in the contact area of ​​the side contact 20 with the source layer 3 and the base layer 4, thereby enabling a reduction in contact resistance.

[0061] Although the sixteenth modification in the exemplary case described above is in the Fig. The semiconductor device shown in section 3 is used, and the sixteenth modification can be found in the Fig. 1 or Fig. The semiconductor device shown in section 2 can be used. <Siebzehnte Modifikation>

[0062] Fig. Figure 15 is a sectional view of a semiconductor device according to a seventeenth modification of the first preferred embodiment. As in Fig. As shown in Figure 15, the upper end of the upper insulating layer 6 can be separated from the upper surface of the semiconductor substrate by a predetermined distance U1. In a sectional view, the upper electrode 7 has a T-shape.

[0063] The use of this configuration allows a reduction in the effective length ratio of the upper electrode 7, which makes it possible to improve the embedding of the upper electrode 7.

[0064] Although the seventeenth modification in the exemplary case described above is in the Fig. The semiconductor device shown in section 3 is used, and the seventeenth modification can be found in the Fig. 1 or Fig. The semiconductor device shown in section 2 can be used. <Achtzehnte Modifikation>

[0065] In the Fig. In the semiconductor devices shown in 1 to 3, the material for the upper electrode 7 can be amorphous silicon.

[0066] According to the eighteenth modification, by using amorphous silicon, which has fewer surface irregularities than polysilicon, as a material for the upper electrode 7, it becomes possible to reduce the electric field strength between the upper electrode 7 and the lower electrode 10, thus improving the reliability of the insulating layer. <Neunzehnte Modifikation>

[0067] In the Fig. In the semiconductor devices shown in 1 to 3, the material for the upper electrode 7 can be an insulator.

[0068] According to the nineteenth modification, by using an insulator as a material for the upper electrode 7, it becomes possible to reduce the electric field strength between the upper electrode 7 and the lower electrode 10, which makes it possible to improve the reliability of the insulating layer. <Zwanzigste Modifikation>

[0069] In the Fig. In the semiconductor devices shown in 1 to 3, the material for the upper electrode 7 can be metal.

[0070] According to the twentieth modification, using metal as the material for the upper electrode 7 reduces its resistance. This allows current flowing in the upper electrode 7 to be emitted directly to the emitter electrode 1. Specifically, the voltage drop caused by the current flowing in the upper electrode 7 becomes less significant, thus reducing the stress on the insulation layer caused by this voltage drop. This, in turn, improves the reliability of the insulation layer. <Zweite bevorzugte Ausführungsform>

[0071] Fig. Figure 16 is a sectional view of a semiconductor device according to a second preferred embodiment. The semiconductor device according to the second preferred embodiment characteristically has a dummy active trench 11 and an active trench 32. The dummy active trench 11 is the same as the dummy active trench 11 described in Figure 16. Fig. Figure 3 is shown, so the detailed description of it is omitted here.

[0072] A semiconductor substrate is provided with a dummy active trench 11 and an active trench 32. The active trench 32 has an active part 31 and an insulating layer 30, which is configured to cover the active part 31, both of which are provided in a trench of the semiconductor substrate. The active part 31 is connected to a gate electrode.

[0073] In addition to the effects achieved by the first preferred embodiment, according to the second preferred embodiment, by providing the active trench 32 it is possible to cause a current to flow in the semiconductor device.

[0074] Although the exemplary configuration in Fig. 16 den in Fig. The dummy active trench 11 shown in 3 can be configured as described in Fig. 1 or Fig. The 2 dummy active trenches shown comprise 11. <Erste Modifikation>

[0075] Fig. Figure 17 is a sectional view of a semiconductor device according to a first modification of the second preferred embodiment. A dummy active trench 11 is the same as the one in Fig. 3 dummy active trenches 11 are shown, so the detailed description of them is omitted here.

[0076] As in Fig. As shown in Figure 17, the semiconductor substrate is provided with the dummy active trench 11 and an active trench 45. The active trench 45 has an upper active part 41 and a lower active part 44, each located in an upper and lower part of a trench in the semiconductor substrate. The upper active part 41 and the lower active part 44 are connected to a gate electrode.

[0077] The active trench 45 has an upper insulating layer 40 formed on a side surface of the upper active part 41, a lower insulating layer 43 formed on a side surface of the lower active part 44, and a boundary insulating layer 42 formed between the upper active part 41 and the lower active part 44. The upper active part 41 and the lower active part 44 are electrically separated from each other by means of the boundary insulating layer 42. The thickness of the upper insulating layer 40 in the right-to-left direction is greater than the thickness of the lower insulating layer 43 in the right-to-left direction.

[0078] According to the first modification, by providing the boundary insulation layer 42 in the active trench 45, it becomes possible to reduce the area of ​​an electrode that is electrically connected to the gate electrode by the area where the boundary insulation layer 42 is formed, thereby enabling a reduction of a gate capacitance.

[0079] Although the exemplary configuration in Fig. 17 den in Fig. The dummy active trench 11 shown in 3 can be configured as described in Fig. 1. Dummy active trench 11 shown. In this case, the position and size of the upper active part 41 can be the same as the position and size of the part shown in 1. Fig. 1 upper electrode shown 7. <Zweite Modifikation>

[0080] Fig. Figure 18 is a sectional view of a semiconductor device according to a second modification of the second preferred embodiment. A dummy active trench 11 is the same as the one in Fig. 2 dummy active trenches 11 are shown, so the detailed description of them is omitted here.

[0081] As in Fig. As shown in Figure 18, in the active trench 45, the thickness of the upper insulation layer 40 in the right-to-left direction can be the same as the thickness of the lower insulation layer 43 in the right-to-left direction. Alternatively, the thickness of the upper insulation layer 40 in the right-to-left direction can be greater than the thickness of the lower insulation layer 43 in the right-to-left direction.

[0082] Implementing this configuration allows for a reduction in channel resistance, which in turn allows for a reduction in ON voltage. <Dritte Modifikation>

[0083] Fig. Figure 19 is a sectional view of a semiconductor device according to a third modification of the second preferred embodiment. A dummy active trench 11 is the same as the one in Fig. The 3 dummy active trenches 11 shown, and an active trench 32 is the same as the one in Fig. 16 active trenches 32 are shown, so the detailed descriptions of them are omitted here.

[0084] As in Fig. As shown in Figure 19, a material for the upper electrode 7 is an insulator 50, and the insulator 50 can be a chemical vapor deposition (CVD) layer. In another case, the impurity concentration in the insulator 50 can be higher than the impurity concentration in the lower insulating layer 9.

[0085] When the insulator 50 is used as a material for the upper electrode 7, the application of a CVD layer prepared by the CVD process, such as a layer of high-temperature oxide (HTO), tetraethoxysilane (TEOS), or boron phosphosilicate glass (BPSG), which has a lower formation temperature than a thermal oxide layer, allows the formation temperature of the insulating layer to be reduced. This makes it possible to suppress thermal expansion, thus reducing the stress caused during the formation of the insulating layer. Generally, the CVD layer has the property of exhibiting a higher impurity concentration than the thermal oxide layer.

[0086] Although the exemplary configuration in Fig. 19 den in Fig. The dummy active trench 11 shown in 3 can be configured as described in Fig. 1 or Fig. 2 dummy active trench 11 shown. Although the exemplary configuration in Fig. 19 den in Fig. The active trench 32 shown in 16 can be configured in Fig. 17 or Fig. 18 shown active trenches 45. <Vierte Modifikation>

[0087] Fig. Figure 20 is a sectional view of a semiconductor device according to a fourth modification of the second preferred embodiment. A dummy active trench 11 is the same as the one in Figure 20. Fig. The 3 dummy active trenches 11 shown, and an active trench 32 is the same as the one in Fig. 16 active trenches 32 are shown, so the detailed descriptions of them are omitted here.

[0088] As in Fig. As shown in Figure 20, a corner at a lower end of the upper electrode 7 can have a curvature. Using this configuration makes it possible to relax a concentration of an electric field at the corner of the upper electrode 7.

[0089] Although the exemplary configuration in Fig. 20 den in Fig. The dummy active trench 11 shown in 3 can be configured as described in Fig. 1 or Fig. 2 dummy active trench 11 shown. Although the exemplary configuration in Fig. 20 den in Fig. The active trench 32 shown in 16 can be configured in Fig. 17 or Fig. 18 shown active trenches 45. Fifth modification>

[0090] Fig. 21 is a sectional view of a semiconductor device according to a fifth modification of the second preferred embodiment. A dummy active trench 11 is the same as the one in Fig. The 3 dummy active trenches 11 shown, and an active trench 32 is the same as the one in Fig. 16 active trenches 32 are shown, so the detailed descriptions of them are omitted here.

[0091] As in Fig. As shown in Figure 21, an upper end of the upper electrode 7 can be separated from the upper surface of the semiconductor substrate by a predetermined distance R1.

[0092] Using this configuration reduces the length ratio of the upper electrode 7, which makes it possible to improve the embedding of the upper electrode 7.

[0093] Although the exemplary configuration in Fig. 21 den in Fig. The dummy active trench 11 shown in 3 can be configured as described in Fig. 1 or Fig. 2 dummy active trench 11 shown. Although the exemplary configuration in Fig. 21 den in Fig. The active trench 32 shown in 16 can be configured in Fig. 17 or Fig. 18 shown active trenches 45. <Sechste Modifikation>

[0094] Fig. Figure 22 is a top view of a semiconductor device according to a sixth modification of the second preferred embodiment. Fig. 23 is a sectional view of the Fig. 22 Semiconductor device shown, recorded along Y1 - Y2.

[0095] As in Fig. 22 and Fig. As shown in Figure 23, the dummy active trench 11, which has the upper electrode 7 and the lower electrode 10, can be connected via a trench to the active trench 32, which has the active part 31. The dummy active trench 11 and the active trench 32 are partially connected to each other via the trench.

[0096] According to the sixth modification, by electrically connecting the dummy active trench 11 and the active trench 32, it becomes possible to stabilize an electrical connection with a gate electrode. <Siebte Modifikation>

[0097] Fig. Figure 24 is a top view of a semiconductor device according to a seventh modification of the second preferred embodiment. Fig. 25 is a sectional view of the in Fig. 24 Semiconductor device shown, recorded along Y3 - Y4.

[0098] As in Fig. 24 and Fig. As shown in Figure 25, the dummy active trench 11, which has the upper electrode 7 and the lower electrode 10, can be connected via a trench to the active trench 32, which has the active part 31. The active part 31 is provided in the trench that forms the connection between the dummy active trench 11 and the active trench 32.

[0099] According to the seventh modification, electrically connecting the dummy active trench 11 and the active trench 32 makes it possible to stabilize an electrical connection with a gate electrode. Furthermore, by placing the active part 31 in the trench that forms the connection between the dummy active trench 11 and the active trench 32, the contact area between the dummy active trench 11 and the active trench 32 is increased, thus enabling the connection to be established with reduced resistance. <Achte Modifikation>

[0100] Fig. Figure 26 is a sectional view of a semiconductor device according to an eighth modification of the second preferred embodiment. A dummy active trench 11 is the same as the one in Fig. The 3 dummy active trenches 11 shown, and an active trench 32 is the same as the one in Fig. 16 active trenches 32 are shown, so the detailed descriptions of them are omitted here.

[0101] As in Fig. As shown in Figure 26, the upper insulation layer 6 and the boundary insulation layer 8 in the dummy active trench 11 can be CVD layers 60.

[0102] The insulating layer to be formed can be either a thermal oxide layer or a CVD layer. By forming a thermal oxide layer, which exhibits excellent electrical stability (the lower insulating layer 9), and by forming CVD layers, such as layers of HTO, TEOS, or BPSG, which have lower formation temperatures than the thermal oxide layer, through the CVD process (the thick upper insulating layer 6 and the thick boundary insulating layer 8), it is possible to reduce the formation temperature of the insulating layer. This reduces the stress caused during the formation of the insulating layer. Generally, the CVD layer has the property of containing a higher impurity concentration than the thermal oxide layer.

[0103] The thermal oxide layer, which exhibits excellent electrical properties, and the CVD layer can be used in combination. More precisely, as shown in Fig. As shown in Figure 27, a thermal oxidation layer 61 can be formed in a first layer, and the CVD layer 60 can be formed in a second layer. By forming the thermal oxidation layer 61 at a trench junction where excellent electrical properties are required, preferred gate characteristics are obtained. Furthermore, thermal stress can be reduced by the CVD layer 60. In another case, stress occurring at the trench junction can be reduced by forming a CVD layer 60 in the first layer corresponding to the trench junction subjected to the highest stress, and by forming the thermal oxidation layer 61 in the second layer.

[0104] Although in the representation in Fig. 26. If the upper insulation layer 6 and the boundary insulation layer 8 are configured as CVD layers 60, at least one of the upper insulation layer 6 and the boundary insulation layer 8 can be configured as the CVD layer 60. Furthermore, at least one impurity concentration in the upper insulation layer 6 and one impurity concentration in the boundary insulation layer 8 can be higher than one impurity concentration in the lower insulation layer 9.

[0105] Although the exemplary configuration in Fig. 26 den in Fig. The dummy active trench 11 shown in 3 can be configured as described in Fig. 1 or Fig. 2 dummy active trench 11 shown. Although the exemplary configuration in Fig. 26 den in Fig. The active trench 32 shown in 16 can be configured in Fig. 17 or Fig.18 shown active trenches 45.

[0106] Within the scope of protection of the disclosure, the preferred embodiments of the present disclosure may be freely combined, and each preferred embodiment may be suitably modified or omitted. <appendizes>

[0107] The disclosure described above is summarized in appendices. (Appendix 1)

[0108] Semiconductor device comprising: a semiconductor substrate; an emitter electrode formed on the semiconductor substrate; a gate electrode that is formed on the semiconductor substrate; a drift layer of a first conductivity type that is formed in the semiconductor substrate; a source layer of the first conductivity type, which is formed in an upper surface side of the semiconductor substrate; a base layer of a second conductivity type, which is formed in the upper surface side of the semiconductor substrate; a collector electrode formed below the semiconductor substrate; and a dummy active trench comprising an upper electrode and a lower electrode, each provided in an upper part and a lower part in a trench of the semiconductor substrate, wherein the upper electrode is connected to the gate electrode or the emitter electrode or is at an unconnected potential, wherein the lower electrode is connected to the gate electrode or the emitter electrode or is at an unconnected potential, wherein the dummy active trench has an upper insulating layer formed on a side surface of the upper electrode, a lower insulating layer formed on a side surface of the lower electrode, and a boundary insulating layer formed between the upper electrode and the lower electrode. the thickness of the upper insulation layer is greater in a right-to-left direction than the thickness of the lower insulation layer in a right-to-left direction, and In a cross-sectional view, the area of ​​the upper electrode is smaller than the area of ​​the lower electrode. (Appendix 2)

[0109] Semiconductor device comprising: a semiconductor substrate; an emitter electrode formed on the semiconductor substrate; a gate electrode that is formed on the semiconductor substrate; a drift layer of a first conductivity type that is formed in the semiconductor substrate; a source layer of the first conductivity type, which is formed in an upper surface side of the semiconductor substrate; a base layer of a second conductivity type, which is formed in the upper surface side of the semiconductor substrate; a collector electrode formed beneath the semiconductor substrate; and a dummy active trench comprising an upper electrode and a lower electrode, each provided in an upper part and a lower part in a trench of the semiconductor substrate, wherein the upper electrode is connected to the gate electrode or the emitter electrode or is at an unconnected potential, wherein the lower electrode is connected to the gate electrode or the emitter electrode or is at an unconnected potential, wherein the dummy active trench has an upper insulating layer formed on a side surface of the upper electrode, a lower insulating layer formed on a side surface of the lower electrode, and a boundary insulating layer formed between the upper electrode and the lower electrode. the thickness of the boundary insulation layer in a top-to-bottom direction is greater than the thickness of the lower insulation layer in a right-to-left direction, and In a cross-sectional view, the area of ​​the upper electrode is smaller than the area of ​​the lower electrode. (Appendix 3)

[0110] Semiconductor device according to Appendix 1 or 2, wherein The thickness of the upper insulation layer in the right-to-left direction, the thickness of the boundary insulation layer in a top-to-bottom direction, and the thickness of the lower insulation layer in the right-to-left direction have a ratio such that: the thickness of the boundary insulation layer in the top-to-bottom direction > the thickness of the upper insulation layer in the right-to-left direction > the thickness of the lower insulation layer in the right-to-left direction. (Appendix 4)

[0111] Semiconductor device according to one of Appendices 1 to 3, wherein The boundary insulation layer is arranged above the center of the dummy active trench in a direction from top to bottom. (Appendix 5)

[0112] Semiconductor device according to any one of Appendices 1 to 4, wherein a length from the upper surface of the semiconductor substrate to an upper end of the lower electrode is greater than the length from the upper surface of the semiconductor substrate to a lower end of the base layer. (Appendix 6)

[0113] Semiconductor device according to any one of Appendices 1 to 5, further comprising: a charge carrier accumulation layer of the first conductivity type, which is provided between the base layer and the drift layer. (Appendix 7)

[0114] Semiconductor device according to Appendix 6, wherein the boundary insulation layer is arranged above a lower end of the charge carrier accumulation layer. (Appendix 8)

[0115] Semiconductor device according to Appendix 6, wherein the boundary insulation layer is arranged above the center of the charge carrier accumulation layer. (Appendix 9)

[0116] Semiconductor device according to Appendix 6, wherein The boundary insulation layer is located above a maximum value position of a contaminant concentration in the charge carrier accumulation layer. (Appendix 10)

[0117] Semiconductor device according to any one of Appendices 1 to 9, wherein the length of the lower electrode in a top-to-bottom direction is greater than the length of the upper electrode in a top-to-bottom direction. (Appendix 11)

[0118] Semiconductor device according to any one of Appendices 1 to 10, wherein the length of the upper electrode in a top-to-bottom direction is shorter than the length from the top surface of the semiconductor substrate to a lower end of the base layer. (Appendix 12)

[0119] Semiconductor device according to any one of Appendices 1 to 11, wherein the length of the upper electrode in a top-to-bottom direction is shorter than the length of the upper electrode in a right-to-left direction. (Appendix 13)

[0120] Semiconductor device according to any one of Appendices 1 to 12, wherein The material for the lower electrode is amorphous silicon. (Appendix 14)

[0121] Semiconductor device according to any one of Appendices 1 to 13, wherein a length ratio of the length of the upper electrode in a top-to-bottom direction relative to the length of the upper electrode in a right-to-left direction is smaller than a length ratio of the length of the lower electrode in a top-to-bottom direction relative to the length of the lower electrode in a right-to-left direction. (Appendix 15)

[0122] Semiconductor device according to any one of Appendices 1 to 14, wherein An intermediate insulation layer is missing at one point above the upper electrode. (Appendix 16)

[0123] Semiconductor device according to any one of Appendices 1 to 15, wherein The dummy active trench further exhibits a lateral contact, which has a side surface on one side in contact with the source layer and the base layer. (Appendix 17)

[0124] Semiconductor device according to Appendix 16, wherein The side contact has a side surface on the other side in contact with the upper electrode. (Appendix 18)

[0125] Semiconductor device according to Appendix 16, wherein the length of the side contact in a top-to-bottom direction is greater than the length of the source layer in a top-to-bottom direction. (Appendix 19)

[0126] Semiconductor device according to any one of Appendices 1 to 18, wherein an upper end of the upper insulation layer is separated from the upper surface of the semiconductor substrate by a predetermined distance. (Appendix 20)

[0127] Semiconductor device according to any one of Appendices 1 to 19, wherein The material for the upper electrode is amorphous silicon. (Appendix 21)

[0128] Semiconductor device according to any one of Appendices 1 to 19, wherein a material for the upper electrode is an insulator. (Appendix 22)

[0129] Semiconductor device according to any one of Appendices 1 to 19, wherein The material for the upper electrode is metal. (Appendix 23)

[0130] Semiconductor device according to any one of Appendices 1 to 22, further comprising: an active trench which has an active part that is provided in a trench of the semiconductor substrate. (Appendix 24)

[0131] Semiconductor device according to Appendix 23, wherein the active part is divided into an upper active part and a lower active part via a boundary insulation layer. (Appendix 25)

[0132] Semiconductor device according to Appendix 21, wherein The insulator is a chemical vapor deposition (CVD) layer. (Appendix 26)

[0133] Semiconductor device according to Appendix 21, wherein a contamination concentration in the insulator is higher than a contamination concentration in the lower insulation layer. (Appendix 27)

[0134] Semiconductor device according to any one of Appendices 1 to 26, wherein one corner at the lower end of the upper electrode has a curvature. (Appendix 28)

[0135] Semiconductor device according to any one of Appendices 1 to 27, wherein an upper end of the upper electrode is separated from the upper surface of the semiconductor substrate by a predetermined distance. (Appendix 29)

[0136] Semiconductor device according to Appendix 23, wherein The dummy active trench and the active trench are connected to each other via a trench. (Appendix 30)

[0137] Semiconductor device according to Appendix 29, wherein the active part is formed in the trench. (Appendix 31)

[0138] Semiconductor device according to any one of Appendices 1 to 30, wherein at least one of the upper insulation layer and the boundary insulation layer is a chemical vapor deposition (CVD) layer. (Appendix 32)

[0139] Semiconductor device according to any one of Appendices 1 to 31, wherein at least one contamination concentration in the upper insulation layer and one contamination concentration in the boundary insulation layer is higher than one contamination concentration in the lower insulation layer.

[0140] Although the revelation has been shown and described in detail, the foregoing description is descriptive in all aspects and not limiting. It is therefore understood that numerous modifications and variations can be devised. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2022-78755 [0003, 0004]< / appendizes>

Claims

[1] Semiconductor device comprising: a semiconductor substrate; an emitter electrode (1) formed on the semiconductor substrate; a gate electrode that is formed on the semiconductor substrate; a drift layer (12) of a first conductivity type formed in the semiconductor substrate; a source layer (3) of the first conductivity type formed in an upper surface side of the semiconductor substrate; a base layer (4) of a second conductivity type formed in the upper surface side of the semiconductor substrate; a collector electrode (15) formed beneath the semiconductor substrate; and a dummy active trench (11) comprising an upper electrode (7) and a lower electrode (10), each provided in an upper part and a lower part in a trench of the semiconductor substrate, wherein the upper electrode is connected to the gate electrode or the emitter electrode (1) or is at an unconnected potential, wherein the lower electrode is connected to the gate electrode or the emitter electrode (1) or is at an unconnected potential, wherein the dummy active trench (11) has an upper insulating layer (6) formed on a side surface of the upper electrode (7), a lower insulating layer (9) formed on a side surface of the lower electrode (10), and a boundary insulating layer (8) formed between the upper electrode (7) and the lower electrode (10), the thickness of the upper insulation layer (6) in a right-to-left direction is greater than the thickness of the lower insulation layer (9) in a right-to-left direction, and In a sectional view, the area of ​​the upper electrode (7) is smaller than the area of ​​the lower electrode (10). [2] Semiconductor device comprising: a semiconductor substrate; an emitter electrode (1) formed on the semiconductor substrate; a gate electrode that is formed on the semiconductor substrate; a drift layer (12) of a first conductivity type formed in the semiconductor substrate; a source layer (3) of the first conductivity type formed in an upper surface side of the semiconductor substrate; a base layer (4) of a second conductivity type formed in the upper surface side of the semiconductor substrate; a collector electrode (15) formed beneath the semiconductor substrate; and a dummy active trench (11) comprising an upper electrode (7) and a lower electrode (10), each provided in an upper part and a lower part in a trench of the semiconductor substrate, wherein the upper electrode is connected to the gate electrode or the emitter electrode (1) or is at an unconnected potential, wherein the lower electrode is connected to the gate electrode or the emitter electrode (1) or is at an unconnected potential, wherein the dummy active trench (11) has an upper insulating layer (6) formed on a side surface of the upper electrode (7), a lower insulating layer (9) formed on a side surface of the lower electrode (10), and a boundary insulating layer (8) formed between the upper electrode (7) and the lower electrode (10), the thickness of the boundary insulation layer (8) in a top-to-bottom direction is greater than the thickness of the lower insulation layer (9) in a right-to-left direction, and In a sectional view, the area of ​​the upper electrode (7) is smaller than the area of ​​the lower electrode (10). [3] Semiconductor device according to claim 1 or 2, wherein the thickness of the upper insulating layer (6) in the right-to-left direction, the thickness of the boundary insulating layer (8) in a top-to-bottom direction and the thickness of the lower insulating layer (9) in the right-to-left direction have a ratio such that: the thickness of the boundary insulating layer (8) in the top-to-bottom direction > the thickness of the upper insulating layer (6) in the right-to-left direction > the thickness of the lower insulating layer (9) in the right-to-left direction. [4] Semiconductor device according to any one of claims 1 to 3, wherein the boundary insulation layer (8) is arranged over the center of the dummy active trench (11) in a top-to-bottom direction. [5] Semiconductor device according to any one of claims 1 to 4, wherein the length from the upper surface of the semiconductor substrate to an upper end of the lower electrode (10) is greater than the length from the upper surface of the semiconductor substrate to a lower end of the base layer (4). [6] Semiconductor device according to any one of claims 1 to 5, further comprising: a charge carrier accumulation layer (5) of the first conductivity type, which is provided between the base layer (4) and the drift layer (12). [7] Semiconductor device according to claim 6, wherein the boundary insulation layer (8) is arranged over a lower end of the charge carrier accumulation layer (5). [8] Semiconductor device according to claim 6, wherein the boundary insulation layer (8) is arranged over the center of the charge carrier accumulation layer (5). [9] Semiconductor device according to claim 6, wherein the boundary insulation layer (8) is arranged above a maximum value position of an impurity concentration in the charge carrier accumulation layer (5). [10] Semiconductor device according to any one of claims 1 to 9, wherein the length of the lower electrode (10) in a top-to-bottom direction is greater than the length of the upper electrode (7) in a top-to-bottom direction. [11] Semiconductor device according to any one of claims 1 to 10, wherein the length of the upper electrode (7) in a top-to-bottom direction is shorter than the length from the top surface of the semiconductor substrate to a lower end of the base layer (4). [12] Semiconductor device according to any one of claims 1 to 11, wherein the length of the upper electrode (7) in a top-to-bottom direction is shorter than the length of the upper electrode (7) in a right-to-left direction. [13] Semiconductor device according to any one of claims 1 to 12, wherein the material for the lower electrode (10) is amorphous silicon. [14] Semiconductor device according to any one of claims 1 to 13, wherein a length ratio of the length of the upper electrode (7) in a top-to-bottom direction relative to the length of the upper electrode in the right-to-left direction is smaller than a length ratio of the length of the lower electrode (10) in a top-to-bottom direction relative to the length of the lower electrode in the right-to-left direction. [15] Semiconductor device according to any one of claims 1 to 14, wherein an intermediate insulating layer (2) is not present at a location above the upper electrode (7). [16] Semiconductor device according to any one of claims 1 to 15, wherein the dummy active trench (11) further comprises a side contact (20) having a side surface on one side in contact with the source layer (3) and the base layer (4). [17] Semiconductor device according to claim 16, wherein the side contact (20) has a side surface on the other side in contact with the upper electrode (7). [18] Semiconductor device according to claim 16, wherein the length of the side contact (20) in a top-to-bottom direction is greater than the length of the source layer (3) in a top-to-bottom direction. [19] Semiconductor device according to any one of claims 1 to 18, wherein an upper end of the upper insulating layer (6) is separated from the upper surface of the semiconductor substrate by a predetermined distance. [20] Semiconductor device according to any one of claims 1 to 19, wherein a material for the upper electrode (7) is amorphous silicon. [21] Semiconductor device according to any one of claims 1 to 19, wherein a material for the upper electrode (7) is an insulator. [22] Semiconductor device according to any one of claims 1 to 19, wherein a material for the upper electrode (7) is metal. [23] Semiconductor device according to any one of claims 1 to 22, further comprising: an active trench (32) comprising an active part (31) provided in a trench of the semiconductor substrate. [24] Semiconductor device according to claim 23, wherein the active part (31) is divided into an upper active part (41) and a lower active part (44) via a boundary insulation layer (42). [25] Semiconductor device according to claim 21, wherein the insulator is a chemical vapor deposition (CVD) layer. [26] Semiconductor device according to claim 21, wherein the impurity concentration in the insulator is higher than the impurity concentration in the lower insulating layer (9). [27] Semiconductor device according to any one of claims 1 to 26, wherein a corner at a lower end of the upper electrode (7) has a curvature. [28] Semiconductor device according to any one of claims 1 to 27, wherein an upper end of the upper electrode (7) is separated from the upper surface of the semiconductor substrate by a predetermined distance. [29] Semiconductor device according to claim 23, wherein the dummy active trench (11) and the active trench (32) are connected to each other via a trench. [30] Semiconductor device according to claim 29, wherein the active part (31) is formed in the trench. [31] Semiconductor device according to any one of claims 1 to 30, wherein at least one of the upper insulating layer (6) and the boundary insulating layer (8) is a chemical vapor deposition (CVD) layer. [32] Semiconductor device according to any one of claims 1 to 31, wherein at least one impurity concentration in the upper insulation layer (6) and one impurity concentration in the boundary insulation layer (8) is higher than one impurity concentration in the lower insulation layer (9).

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