REDUCING SOLDER-INDICATED SHIFTS IN CIRCUIT CHARACTERISTICS IN INTEGRATED CIRCUITS

Abstract

Solder drift reduction for packaged integrated circuits is disclosed. In certain embodiments, a packaged integrated circuit includes a paddle, a main semiconductor die having a bottom surface attached to the paddle and a top surface having a voltage-sensitive circuit fabricated thereon, and a voltage-suppression die attached to the top surface of the main semiconductor die. The voltage-suppression die operates to provide voltage suppression that places the voltage-sensitive circuit at or near a voltage-neutral region of the package subject to deformation caused by the soldering process.

Description

Area of ​​Revelation

[0001] The field concerns electronics in general and packaged integrated circuits in particular. BACKGROUND

[0002] Integrated circuits are typically packaged for coupling to a larger electronic system by attaching an integrated circuit (IC) die to a package substrate and encapsulating the IC die with a molding material. Some electronic circuits within the IC die may be sensitive to voltage, temperature, humidity, and / or other factors that can adversely affect the performance of the electronic circuit. A package is designed to protect IC dies and facilitate their connection to larger systems. However, in some situations, the package can adversely affect the performance of sensitive electronic circuits. SUMMARY OF REVELATION

[0003] Aspects of the disclosure relate to suppressing package stresses caused by the soldering process of packaged integrated circuits. In certain embodiments, a packaged integrated circuit includes a paddle, a main semiconductor die having a bottom surface attached to the paddle and a top surface having stress-sensitive circuitry fabricated thereon, and a stress-suppression die attached to the top surface of the main semiconductor die. The stress-suppression die operates to provide stress suppression that places the stress-sensitive circuitry at or near a stress-neutral region of the package subject to deformation caused by the soldering process.Such solder stress suppression techniques provide a cost-effective way to reduce and / or eliminate performance degradation of packaged integrated circuits due to the soldering process.

[0004] According to one aspect, an IC package includes a paddle, a main semiconductor die having a first side attached to the paddle and a second side including voltage-sensitive circuitry, and a voltage suppression die attached to the second side of the main semiconductor die. The voltage suppression die operates to provide voltage suppression resulting from soldering the IC package to a circuit board.

[0005] According to another aspect, an electronic system includes a circuit board and an IC package soldered to the circuit board. The IC package includes a paddle, a main semiconductor die having a first side attached to the paddle and a second side including voltage-sensitive circuitry, and a voltage suppression die attached to the second side of the main semiconductor die. The voltage suppression die operates to provide voltage suppression resulting from soldering the IC package to the circuit board.

[0006] According to another aspect, a method of packaging an integrated circuit comprises attaching a bottom surface of a main semiconductor die to a paddle, attaching a voltage suppression die to a top surface of the main semiconductor die, the top surface comprising voltage sensitive circuitry, and providing voltage suppression resulting from soldering the paddle to a circuit board using the voltage suppression die. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1A is a schematic cross-sectional view of an example packaged integrated circuit. Fig. Figure 1B is a schematic cross-sectional view of an example of the packaged integrated circuit of Fig. 1A after soldering. Fig. 2A is a schematic cross-sectional view of a packaged integrated circuit according to one embodiment. Fig. Figure 2B is a schematic cross-sectional view of an example of the packaged integrated circuit of Fig. 2A after soldering. Fig. 3 is a schematic top view of a packaged integrated circuit according to one embodiment. Fig. 4 is a schematic diagram of a voltage sensitive circuit according to one embodiment. Fig. Figure 5 is a graph of an example of measured solder displacement versus simulated solder voltage. Fig. 6A is a schematic cross-sectional view of an electronic system according to an embodiment. Fig. Figure 6B is a graph of an example of a reference voltage shift versus board stretch or bend. Fig. 7 is a schematic cross-sectional view of a packaged integrated circuit according to another embodiment. DETAILED DESCRIPTION

[0007] The following detailed description of embodiments presents various descriptions of specific embodiments of the invention. However, the invention may be embodied in many different ways. In this description, reference is made to the drawings, in which like reference numerals may indicate identical or functionally similar elements. It is understood that the elements illustrated in the figures are not necessarily to scale. Furthermore, it is understood that certain embodiments may include more elements than illustrated in any one drawing and / or a subset of the elements illustrated in the drawing. Further, some embodiments may include any suitable combination of features from two or more drawings.

[0008] The mechanical stress of soldering a packaged integrated circuit (also referred to herein as a package) to a printed circuit board can cause package stress, which leads to deformation.

[0009] For example, a packaged integrated circuit may comprise a semiconductor die and various package structures, each with different rates of thermal expansion and contraction. Furthermore, package distortion may occur after such a package is exposed to the extreme heat of soldering (for example, a lead-free infrared reflow profile with a peak temperature of 260°C or higher). Particularly in low-cost packages such as Quad Flat No-Lead (QFN) packages, severe package warpage occurs due to mechanical deformation after the soldering process.

[0010] Package distortion can affect the performance of packaged integrated circuits that include voltage-sensitive circuits, such as voltage references. For example, warpage in a packaged integrated circuit that includes a voltage reference (such as a bandgap reference circuit) can cause the output reference voltage to shift after soldering.

[0011] Various embodiments disclosed herein relate to suppressing package stresses caused by the soldering process of packaged integrated circuits. In certain embodiments, a packaged integrated circuit includes a paddle, a main semiconductor die having a bottom surface attached to the paddle and a top surface having stress-sensitive circuitry fabricated thereon, and a stress-suppression die attached to the top surface of the main semiconductor die. The stress-suppression die operates to provide stress suppression that places the stress-sensitive circuitry at or near a stress-neutral region of the package subject to deformation caused by the soldering process.

[0012] In certain implementations, the voltage suppression die is implemented as a thick dummy die that is much thicker than a thin main die containing voltage-sensitive circuitry. The stack of the paddle, the thin main die, and the thick dummy die can cause the voltage-sensitive circuitry to be closer to the voltage-neutral region.

[0013] For example, the stress-neutral region may correspond to one or more points and / or an axis where tensile and compressive stresses cancel each other in a deformed beam. Additionally, the dummy die and the main die may form a complex that approximates the behavior of a single beam. If the dummy die and the main die are formed from a common material (e.g., a semiconductor such as silicon), both have the same coefficient of thermal expansion (CTE). Furthermore, the dummy die protects the main die from global and local stresses in the molding compound, while local stress is primarily due to particles (e.g., silicon dioxide particles) in the molding compound.

[0014] The solder stress suppression techniques herein provide a cost-effective way to reduce and / or eliminate performance degradation of packaged integrated circuits due to the soldering process.

[0015] Fig. 1A is a schematic cross-sectional view of an example of a packaged integrated circuit 20. The packaged integrated circuit 20 includes a paddle 1, a semiconductor die 5, a mold material or encapsulant 7, a paddle solder region 8, a bond wire 9, a die attach 11, a die pad 16, a package lead 17, and a package lead solder region 18.

[0016] As in Fig. As shown in Figure 1A, the semiconductor die 5 has a voltage-sensitive circuit 15 fabricated thereon.

[0017] Fig. 1B is a schematic cross-sectional view of an example of the packaged integrated circuit 20 of Fig. 1A after soldering.

[0018] As in Fig. 1B, the extreme heat of the soldering process has resulted in deformation or warpage of the packaged integrated circuit 20.

[0019] The deformation of the packaged integrated circuit 20 may arise from the semiconductor die 5 and various package structures (for example, the paddle 1 and / or the mold material 7), each with different thermal expansion and contraction rates.

[0020] The varying thermal expansion and contraction rates may result in a compressive force 21 near the top of the semiconductor die 5 and a tensile force 22 near the bottom of the semiconductor die 5.

[0021] As in Fig. As shown in Figure 1B, a voltage-neutral region 23 is spaced apart from the voltage-sensitive circuit 15. In one example, the voltage-sensitive circuit 15 is a bandgap reference circuit that outputs an absolute voltage. The distortion experienced by such a bandgap reference circuit can result in unacceptable shifts in the output voltage, degrading the overall performance of the packaged integrated circuit 20.

[0022] Fig. 2A is a schematic cross-sectional view of a packaged integrated circuit 50 according to one embodiment. The packaged integrated circuit 50 includes a paddle 31, a main semiconductor die 35, a stress suppression die 36, a mold material 37, a paddle solder region 38, a bond wire 39, a first die attach 41, a second die attach 42, a die pad 46, a package lead 47, and a package lead solder region 48.

[0023] As in Fig. As shown in Figure 2A, the main semiconductor die 35 includes a voltage-sensitive circuit 45 fabricated on a top, or active, side of the die 35. Furthermore, a bottom, or inactive, side of the main semiconductor die 35 is attached to the paddle 31 via the first die attach 41, which may be, for example, a conductive or non-conductive epoxy. The paddle 31 may be, for example, an exposed copper paddle. The paddle 31 helps ensure heat dissipation during operation.

[0024] With further reference to Fig. 2A, the voltage suppression die 36 is attached to the top of the main semiconductor die 35 via a second die attach 42. The second die attach 42 may be any suitable material for providing the die attach and may be the same or a different material than the first die attach 41.

[0025] As in Fig. As shown in Figure 2A, the mold material 37 is formed over the stack of the paddle 31, the main semiconductor die 35, and the stress suppression die 36. The mold material 37 helps protect the semiconductor die during use. In certain implementations, the mold material 37 may comprise a plastic material including an epoxy molding compound, for example, a resin.

[0026] In the embodiment of Fig. 2A, die pad 46 of main semiconductor die 35 is electrically coupled to package lead 47 via bond wire 39. Bond wire 39 may be made of any suitable conductive material, such as gold or copper. Although only one attachment between main semiconductor die 35 and the package lead frame is shown, typically multiple bond wires are used to attach multiple die pads to lead frame leads.

[0027] Although the main semiconductor die 35 in Fig. 2A, it should be understood that the main semiconductor die 35 may be electrically connected in other ways. For example, in some embodiments (such as those using a printed circuit board for a package substrate), the main semiconductor die 35 may be attached (e.g., soldered) to the package substrate, and internal conductive traces within the package substrate may provide electrical communication between the main semiconductor die 35 and an external printed circuit board. The main semiconductor die 35 may also be flip-chip mounted and coupled to the package substrate in some embodiments. In still other arrangements, the main semiconductor die 35 may be electrically coupled to the package substrate using NCP (non-conductive paste) or ACF (anisotropic conductive film) technologies.

[0028] Thus, the teachings herein are applicable to a variety of package types. Thus, the teachings herein are applicable not only to QFN packages, but also to other package types, such as low-profile quad flat pack (LQFP) packages, ball grid array (BGA) packages, and other package types, including those using flip-chip technologies.

[0029] Other stacking configurations are also possible. In one embodiment, the paddle 31 is located above the main semiconductor die 35, and the main semiconductor die 35 is located above the voltage suppression die 36.

[0030] In Fig. 2A, the voltage-sensitive circuit 45 is schematically illustrated. However, one skilled in the art would appreciate that the voltage-sensitive circuit 45 may also be fabricated from layers of the main semiconductor die 35. The voltage-sensitive circuit 45 may be a precision component with performance affected by voltages, as opposed to a circuit that outputs or measures relative voltages and is not voltage-sensitive. Examples of the stress-sensitive circuit 45 include, but are not limited to, a reference circuit (a current reference or a voltage reference, such as a bandgap reference circuit), an oscillator, a sensor, a data converter (e.g., a digital-to-analog converter or an analog-to-digital converter), and / or an amplifier.Such a voltage-sensitive circuit arrangement may comprise one or more voltage-sensitive components, such as voltage-sensitive transistors, resistors, capacitors and / or trimming structures.

[0031] In certain implementations, the main semiconductor die 35 is a BMS (battery management system integrated circuit) IC that includes battery management circuitry that utilizes the voltage-sensitive circuit 45 for operation. For example, the voltage-sensitive circuit 45 may include a bandgap reference circuit that provides a bandgap reference voltage to the battery management circuitry of the BMS IC.

[0032] As in Fig. 2A, solder is placed along a bottom surface of the packaged integrated circuit 50 and is used to make electrical connections to a printed circuit board (in Fig. 2A (not shown) to which the packaged integrated circuit 50 can be attached for operation in a larger electronic system. For example, the paddle solder region 38 is provided for the paddle 31, while the package lead solder region 48 is provided for the package lead 47 and other leads of the lead frame.

[0033] The mechanical stress of soldering the packaged integrated circuit 50 to a circuit board (e.g., a printed circuit board or PCB) may cause package stress, which leads to deformation of the packaged integrated circuit 50.

[0034] As in Fig. As shown in Figure 2A, the voltage suppression die 36 is placed over the top of the main semiconductor die 35. The stack of the paddle 31, the main semiconductor die 35, and the voltage suppression die 36 may result in the position of the voltage-sensitive circuit 45 after soldering being closer to a voltage-neutral region. In certain implementations, the voltage suppression die 36 is chosen to comprise the same material (e.g., a semiconductor such as silicon) as the main semiconductor die 35 so that both dies have the same CTE.

[0035] Although the voltage suppression die 36 may be a semiconductor die, the teachings herein also apply to implementations in which the voltage suppression die 36 is not a semiconductor.

[0036] In the illustrated embodiment, the stress-suppression die 36 also completely covers the stress-sensitive circuit 45, preventing the molding material 37 from contacting the top surface of the main semiconductor die 35 near the location where the stress-sensitive circuit 45 is fabricated. Since particles (e.g., silicon dioxide particles) in the molding material 37 can cause local stresses, implementing the stress-suppression die 36 to completely cover the stress-sensitive circuit 45 ensures improved performance by reducing the impact of local stresses on the performance of the stress-sensitive circuit 45.

[0037] Various thickness dimensions of components of the packaged integrated circuit 50 were Fig. 2A schematically illustrated. For example, the paddle 31 has a thickness d1, the main semiconductor die 35 has a thickness d2, the stress suppression die 36 has a thickness d3, the first die attach 41 has a thickness d4, the second die attach 42 has a thickness d5, the solder has a thickness d6, and the mold material 37 has a thickness d7.

[0038] The thicknesses may have any suitable values. In certain implementations, the thickness d1 is chosen to be in the range from 100 µm to 400 µm (or in particular, in the range from 160 µm to 240 µm), for example, 200 µm. In some implementations, the thickness d2 is chosen to be in the range from 80 µm to 120 µm, for example, 100 µm. In various implementations, the thickness d3 is chosen to be in the range from 80 µm to 700 µm (or in particular, in the range from 200 µm to 300 µm), for example, 250 µm. In certain implementations, the thicknesses d4 and d5 are selected to be less than 50 µm, for example, 20 µm. In some implementations, the thickness d6 is selected to be in the range of 50 µm to 75 µm, for example, 63 µm. In various implementations, the thickness d7 is selected to be in the range of 600 µm to 900 µm, for example, 750 µm.

[0039] Although example thickness ranges have been provided, other thickness values ​​may also be used.

[0040] In certain implementations, the voltage suppression die 36 is implemented as a thick dummy die, and the main semiconductor die 35 is implemented as a thin main die that includes the voltage-sensitive circuitry 45. For example, in some implementations, the voltage suppression die 36 is between 0.5 and 10 times (or more particularly, between 1.5 and 5 times) as thick as the main semiconductor die 35.

[0041] In implementations where the voltage suppression die 36 is a dummy die, the voltage suppression die 36 includes no operating circuitry. In other implementations, the voltage suppression die 36 includes circuitry that works in combination with the circuitry of the main semiconductor die 35 (including the voltage-sensitive circuit 45) to achieve a desired overall functionality of the packaged integrated circuit 50.

[0042] In some embodiments, the stress suppression die 36 has a thickness approximately equal to that of the paddle 31. For example, in certain implementations, the thickness of the stress suppression die 36 is within approximately 50% to 150% of the thickness of the paddle 31.

[0043] Although a main semiconductor die 35 is attached to the paddle 31 in Fig. 2A, in other embodiments, one or more additional main semiconductor dies may also be attached to the paddle 31. Such additional main semiconductor dies may be implemented with or without one or more voltage suppression dies for voltage suppression.

[0044] Fig. 2B is a schematic cross-sectional view of an example of the packaged integrated circuit 50 of Fig. 2A after soldering.

[0045] As in Fig. As shown in Figure 2B, the extreme heat of the soldering process has resulted in deformation or warpage of the packaged integrated circuit 50. For example, the varying thermal expansion and contraction rates may result in a compressive force 51 near the top of the stress-suppression die 36 and a tensile force 52 near the bottom of the main semiconductor die 35.

[0046] Compared to the warped packaged integrated circuit 20 of Fig. 1B, in which the voltage-neutral region 23 is far away from the voltage-sensitive circuit 15, the warped packaged integrated circuit 50 of Fig. 2B, however, has a voltage-neutral region 53 located at or near the voltage-sensitive circuit 45.

[0047] In certain implementations, the voltage suppression die 36 provides voltage suppression that results in the voltage neutral region 23 not being located exactly at the location of the voltage sensitive circuit 45 and only reduces the voltage level at the voltage sensitive circuit 45.

[0048] In some embodiments, the voltage difference due to the soldering process is significantly minimized by moving a voltage neutral point closer to the sensitive circuitry. Additionally or alternatively, in certain embodiments, the voltage suppression die positions a voltage neutral region after soldering to within 100 µm of the voltage-sensitive circuit.

[0049] Thus, the stress-suppression die 36 and the main semiconductor die 35 can form a complex that approximates the behavior of a single carrier. Furthermore, in implementations where the stress-suppression die 36 and the main semiconductor die 35 are formed from a common material (e.g., a semiconductor such as silicon), they both have the same CTE. Furthermore, the stress-suppression die 36 protects the main semiconductor die 35 from global and local stresses of the mold material 37, while local stresses are primarily due to particles (e.g., silicon dioxide particles) in the mold material 37.

[0050] Fig. 3 is a schematic top view of a packaged integrated circuit 80 according to one embodiment. The packaged integrated circuit 80 is implemented as a QFN package having a lead frame including leads 47. Additionally, a main semiconductor die 31 is attached to a paddle 31 (e.g., an exposed copper paddle), while a voltage suppression die 36 is attached over the main semiconductor die 31. The main semiconductor die 31 has pads 46 attached to the leads 47 of the lead frame via bond wires 39. The main semiconductor die 31 includes voltage-sensitive circuitry, such as a bandgap reference voltage.

[0051] As in Fig. 3, the leads 47 may surround and be electrically insulated from the paddle 31 (or fused to the paddle 31 in another implementation). The pads 46 may be formed around the perimeter of the main semiconductor die 35, and the stress suppression die 36 may leave the pads 46 exposed to allow wire bonding of the bond wires 39 to the leads 47. In some implementations, the stress suppression die 36 covers about 50% to about 90% of the top surface of the main semiconductor die 35. In certain implementations, the stress suppression die 36 completely covers the stress-sensitive circuitry of the main semiconductor die 35 to protect the stress-sensitive circuitry from global and local stresses of a mold material (for clarity, Fig. 3 not shown).

[0052] Fig. Figure 4 is a schematic diagram of a voltage-sensitive circuit 110 according to one embodiment. The voltage-sensitive circuit 110 corresponds to a bandgap reference circuit in this embodiment.

[0053] Although stress-sensitive circuitry 110 represents one example of a stress-sensitive circuitry that may be included in a packaged integrated circuit, packaged integrated circuits herein may include other types of stress-sensitive circuitry. For example, examples of stress-sensitive circuitry include, but are not limited to, a reference circuitry (a current reference or a voltage reference, such as a bandgap reference circuitry), an oscillator, a sensor, a data converter (e.g., a digital-to-analog converter or an analog-to-digital converter), and / or an amplifier.

[0054] In the illustrated embodiment, voltage-sensitive circuit 110 includes a pair of ratioed bipolar transistors 100, a first resistor 101, a second resistor 102, a third resistor 103, a fourth resistor 104, and an amplifier 105. Voltage-sensitive circuit 110 receives a first voltage V+ and a second voltage V-, which in some implementations correspond to a power supply voltage and a ground voltage, respectively. Voltage-sensitive circuit 110 also outputs a bandgap voltage V BGAP which should remain essentially constant even in the presence of housing distortion caused by soldering.

[0055] With further reference to Fig. 4, the pair of ratioed bipolar transistors 100 includes a first NPN bipolar transistor A and a second NPN bipolar transistor B, which are electrically coupled to an inverted input and a non-inverted input of amplifier 105, respectively. For example, the first NPN bipolar transistor A has a collector connected to the inverted input of amplifier 105, while the second NPN bipolar transistor B has a collector connected to the non-inverted input of amplifier 105.

[0056] As in Fig. 4, the output of amplifier 105 represents the bandgap voltage V BGAPand is also connected to the base of the first NPN bipolar transistor A and to the base of the second NPN bipolar transistor B. The inverted input of the amplifier 105 is also connected to the first voltage V+ via the third resistor 103, while the non-inverted input of the amplifier 105 is also connected to the first voltage V+ via the fourth resistor 104. The emitter of the first NPN bipolar transistor A is connected to the second voltage V- via the series connection of the first resistor 101 and the second resistor 102, while the emitter of the second NPN bipolar transistor B is connected to the second voltage V- via the second resistor 102.

[0057] With further reference to Fig. 4, the first NPN bipolar transistor A has a larger area than the second NPN bipolar transistor B. For example, as illustrated, the ratio of emitter areas of the first NPN bipolar transistor A to the second NPN bipolar transistor may be BN:1, where N may be at least 2, for example.

[0058] The stability of the band gap voltage V BGAP may depend on the electrical properties associated with a precise ratio of the emitter area of ​​the first NPN bipolar transistor A to the emitter area of ​​the second NPN bipolar transistor B. However, electrical properties of the first and second NPN bipolar transistors A and B may be influenced by mechanical stresses resulting from package deformation.

[0059] Thus, voltages to which the voltage-sensitive circuit 110 is exposed may cause an unacceptable voltage shift in the bandgap voltage V BGAPthat affect the performance of an electronic system based on the band gap voltage V BGAP works, reduces.

[0060] Fig. Figure 5 is a graph of an example of measured solder displacement versus simulated solder voltage. The graph compares a variation in solder displacement versus bandgap voltage for a 9x9mm QFN package according to an implementation of the packaged integrated circuit 20 of Fig. 1A after soldering versus a 9x9mm QFN package according to an implementation of the packaged integrated circuit 50 of Fig. 2A after soldering.

[0061] As in Fig. As shown in Figure 5, the use of a thick dummy die to provide voltage suppression results in statistically much less solder shift in the bandgap voltage.

[0062] Fig. Figure 6A is a schematic cross-sectional view of an electronic system 140 according to one embodiment. The electronic system 140 includes a circuit board 141 and a packaged integrated circuit 50 attached to the circuit board 141.

[0063] The electronic system 150 from Fig. 6A illustrates an example of the packaged integrated circuit 50 of Fig. 2A after soldering to the circuit board 141. The packaged integrated circuit 50 exhibits better reference stability when bending the circuit board 141 due to the inclusion of the stress suppression die 36. For example, bending the circuit board 141 deforms the packaged integrated circuit 50, but the deformation plays a less significant role when the reference is in a stress-neutral position.

[0064] Fig. Figure 6B is a graph of an example of a reference voltage shift versus board stretching or bending. As shown in Fig. As shown in Figure 6B, the reference voltage shift for a packaged integrated circuit with a voltage suppression die is compared to a packaged integrated circuit without a voltage suppression die. The packaged integrated circuit with the voltage suppression die exhibits better reference stability during board flexion.

[0065] Fig. 7 is a schematic cross-sectional view of a packaged integrated circuit 150 according to another embodiment. The packaged integrated circuit 150 of Fig. 7 is similar to the packaged integrated circuit 50 of Fig.2A, except that the packaged integrated circuit 150 further includes a third die attach 43 and an additional main semiconductor die 49, which in this example does not include a voltage suppression semiconductor die. However, in another embodiment, a voltage suppression die is also included above the additional main semiconductor die 49.

[0066] Any number of semiconductor dies may be included in the packaged integrated circuits disclosed herein. Concluding remarks

[0067] The foregoing description may refer to elements or features as being "connected" or "coupled" to one another. As used herein, unless expressly stated otherwise, "connected" means that one element / feature is directly or indirectly connected to another element / feature, and not necessarily mechanically. Likewise, unless expressly stated otherwise, "coupled" means that one element / feature is directly or indirectly coupled to another element / feature, and not necessarily mechanically. While the various schematics shown in the figures represent example arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the illustrated circuits is not adversely affected).

[0068] While certain embodiments have been described, these embodiments have been presented merely by way of example and are not intended to limit the scope of the disclosure. Indeed, the novel devices, methods, and systems described herein may be embodied in a variety of other forms; further, various omissions, substitutions, and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, although the disclosed embodiments are presented in a given arrangement, alternative embodiments may perform similar functionality with different components and / or circuit topologies, and some elements may be removed, moved, added, subdivided, combined, and / or modified. Each of these elements may be implemented in a variety of different ways.Any suitable combination of the elements and acts of the various embodiments described above may be combined to provide further embodiments. Accordingly, the scope of the present invention is defined only by reference to the appended claims.

[0069] Although the claims set forth herein are set forth in a simple reference-back format for filing with the USPTO, it is understood that any claim may be referenced back to any prior claim of the same type unless it is obviously technically impracticable to do so.

Claims

[1] IC package comprising: a paddle; a main semiconductor die having a first side attached to the paddle and a second side having a voltage-sensitive circuit; and a voltage suppression die attached to the second side of the main semiconductor die, the voltage suppression die operative to provide voltage suppression resulting from soldering the IC package to a circuit board. [2] The IC package of claim 1, wherein the voltage suppression die positions a voltage neutral region after soldering to within 100 µm of the voltage sensitive circuit. [3] The IC package of claim 1, wherein a voltage difference due to a soldering process is substantially minimized by moving a voltage neutral point closer to the voltage sensitive circuit. [4] The IC package of claim 1, further comprising a molding material over the voltage suppression die, the main semiconductor die, and the paddle. [5] The IC package of claim 1, wherein the voltage suppression die completely covers a portion of the main semiconductor die including the voltage sensitive circuitry. [6] The IC package of claim 1, wherein the stress suppression die exposes a plurality of pads of the main semiconductor die for wire bonding. [7] The IC package of claim 6, further comprising a lead frame having a plurality of leads, and a plurality of bond wires electrically coupling the plurality of leads to the plurality of pads of the main semiconductor die. [8] The IC package of claim 1, wherein the voltage sensitive circuit comprises a bandgap reference circuit. [9] The IC package of claim 1, wherein the stress suppression die has a thickness that is 0.5 to 10 times a thickness of the main semiconductor die. [10] The IC package of claim 1, wherein the stress suppression die has a thickness in a range of 80 µm to 700 µm and the main semiconductor die has a thickness in a range of 80 µm to 120 µm. [11] The IC package of claim 10, wherein the paddle has a thickness in a range of 100 µm to 400 µm. [12] The IC package of claim 1, wherein the voltage suppression die is a dummy die or comprises operating circuitry. [13] The IC package of claim 1, wherein the main semiconductor die and the stress suppression die are formed from a common material to ensure a common coefficient of thermal expansion (CTE). [14] The IC package of claim 13, wherein the common material is silicon. [15] The IC package of claim 1, implemented in a Quad-Flat-No-Lead (QFN) package. [16] The IC package of claim 1, further comprising at least one additional main semiconductor die on the paddle. [17] The IC package of claim 16, wherein the at least one additional main semiconductor die is not stacked with a voltage suppression die. [18] Electronic system comprising: a circuit board; and an IC package soldered to the circuit board, the IC package comprising: a paddle; a main semiconductor die having a first side attached to the paddle and a second side having a voltage-sensitive circuit; and a voltage suppression die attached to the second side of the main semiconductor die, the voltage suppression die operative to provide voltage suppression resulting from soldering the IC package to the circuit board. [19] The electronic system of claim 18, wherein the stress suppression provided by the stress suppression die counteracts a stress effect due to bending of the circuit board. [20] A method of packaging an integrated circuit, the method comprising: Attaching a bottom surface of a main semiconductor die to a paddle; Attaching a voltage suppression die to a top surface of the main semiconductor die, the top surface having a voltage-sensitive circuit; and Providing voltage suppression resulting from soldering the paddle to a circuit board using the voltage suppression die.

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