Failure protection energy management to prevent short circuits due to water damage in solid-state drives using a conductivity detector

Abstract

Methods and devices are provided for detecting the presence of electrically conductive liquids in a data storage device, such as an M.2 solid-state drive (SSD), and for triggering a failsafe mode. In an illustrative example, the SSD includes a non-volatile memory array (NVM) and a data storage controller. A linear resistive strip or other resistance sensor is mounted next to the NVM array and the data storage controller. A conductivity detector uses the linear resistive strip to detect the presence of an electrically conductive liquid. In response to the detection of the electrically conductive liquid, a power management unit (PMU) activates a failsafe processing mode. In failsafe mode, power to the NVM array and the data storage controller is disabled to prevent corrosion and short circuits.A signal is also sent to a laptop or other host in which the SSD is installed to request that the laptop be shut down.

Description

AREA

[0001] The subject matter described here relates to data storage devices and controllers. In particular, some examples refer to techniques for preventing a short circuit in a solid-state device due to water damage. INTRODUCTION

[0002] Data storage devices (DSDs), such as solid-state drives (SSDs), can be damaged by water, leading to short circuits, corrosion, and damage to the metal layer within the DSD. For example, condensation of water inside an SSD containing a NAND die or a data storage controller can cause these problems. More specifically, condensation of water on ball grid arrays (BGAs) (e.g., for the NAND die or the data storage controller) implemented on a printed circuit board (PCB) of a NAND-based SSD can cause corrosion between the NAND die and its BGA pins, or between a data storage processor and its BGA pins. Similar problems can occur with other surface-mount devices (SMPs). This increases the risk of hardware damage and data loss. This can be a significant issue for integrated M.2 SSDs installed as components in laptops.M.2 is a specification for internally mounted computer expansion cards and associated connectors, and M.2 SSDs are native PCIe (Peripheral Component Interconnect Express) devices and were originally designed to connect to the internal M.2 slots of a laptop or desktop PC. Such laptops often have numerous vents for cooling and airflow around the motherboard, processor, and circuitry of the laptop, which can allow water or humid air to enter the built-in M.2 SSD and cause corrosion within the SSD.

[0003] In many cases, the data stored on the SSD is far more valuable to the user than the SSD itself. Modern SSDs, for example, can store terabytes of data, including millions of project files, financial documents, or other confidential and valuable information. Protecting SSDs from water damage is therefore particularly important to safeguard the stored data. Such protection is especially challenging for M.2 form factor SSDs due to their small size and thin profile. At least some aspects of this disclosure aim to reduce the risk of water-related damage and data loss in such devices, or to achieve other objectives. SUMMARY

[0004] The following is a simplified summary of some aspects of Revelation, intended to provide a basic understanding of these aspects. This summary does not constitute a comprehensive overview of all features of Revelation under consideration, nor is it intended to identify key or critical elements of all aspects of Revelation, nor to delimit the scope of any single or all aspects of Revelation. Its sole purpose is to present various concepts of some aspects of Revelation in a simplified form as a prelude to the more detailed description that follows.

[0005] One aspect of the disclosure provides a data storage device (DSD) comprising: a non-volatile memory array (NVM) mounted on a printed circuit board (PCB) using a first surface-mount package (SMP); one or more processors mounted on the PCB using a second SMP and communicating with the NVM array; a sensor mounted adjacent to the first and / or second SMP; a detector configured to use the sensor to detect an electrically conductive liquid; and wherein the one or more processors are configured, individually or in combination, to activate a fail-safe processing mode in response to the detection of the electrically conductive liquid.

[0006] Another aspect of the disclosure provides a DSD comprising: an NVM array mounted on a printed circuit board (PCB); a resistive strip mounted on the PCB; a conductivity detector coupled to the resistive strip; and one or more processors configured individually or in combination to: receive signals from the conductivity detector indicating whether the amount of metal ions in a liquid contacting the resistive strip exceeds a contamination threshold; disable power to the data storage device in response to the amount of metal ions in the liquid exceeding the contamination threshold; and re-enable power in response to the amount of metal ions in the liquid no longer exceeding the contamination threshold.

[0007] Another aspect of the disclosure provides a data storage device that includes: means for detecting aqueous metal ions within the data storage device; means for determining whether the aqueous metal ions exceed a contamination threshold; means for disabling a power supply to the data storage device in response to the aqueous metal ions exceeding the contamination threshold; and means for reactivating the power supply in response to the aqueous metal ions no longer exceeding the contamination threshold. BRIEF DESCRIPTION OF THE DRAWINGS Fig.Figure 1 is a schematic block diagram illustrating an exemplary data storage device (DSD) designed as a solid-state device (SSD) and including one or more resistive strip sensors and other components for detecting the presence of an electrically conductive liquid within the DSD using the resistive strips according to some aspects of the disclosure. Fig. Figure 2 illustrates selected components of an exemplary M.2 SSD according to some aspects of the revelation. Fig. Figure 3 illustrates a physical configuration of an exemplary M.2 SSD according to some aspects of the revelation. Fig. Figure 4 illustrates a NAND array die with a Ball Grid Array (BGA) and shows resistor strips mounted next to the BGA of the NAND die according to some aspects of the revelation. Fig. 5A and Fig.5B illustrates an exemplary procedure that can be performed by an SSD to detect and respond to an electrically conductive fluid within the SSD according to some aspects of the disclosure. Fig. Figure 6 illustrates an exemplary procedure that can be performed by an SSD to convert electrical resistance signals into conductivity values ​​and compare them with conductivity thresholds in order to detect electrically conductive liquids within the SSD according to some aspects of the disclosure. Fig. Figure 7 is a schematic block diagram showing an exemplary data storage device configured according to some aspects of the disclosure. Fig. Figure 8 is a schematic block diagram showing another exemplary data storage device configured according to some aspects of the disclosure. Fig.Figure 9 is a schematic block diagram showing yet another exemplary data storage device configured according to some aspects of the revelation. Fig. Figure 10 is a flowchart illustrating a method or procedure for use by a DSD or an SSD according to some aspects of the disclosure. DETAILED DESCRIPTION

[0008] The following detailed description refers to the accompanying drawings, which form an integral part thereof. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become clear by reference to the drawings and the following detailed description. The description of elements in each figure may refer to elements in the preceding figures. Identical numbers may refer to identical elements in the figures, including alternative embodiments of the same elements.

[0009] The examples given herein refer to data storage devices (DSDs) and DSD data storage controllers. In the main examples described here, data is stored in non-volatile memory arrays (NVMs). DSDs with NVM arrays can be referred to as solid-state devices (SSDs) or flash drives. Some SSDs use NAND memory, referred to hereafter as "NANDs." NAND is a type of non-volatile memory technology that does not require power to store data. It uses negative AND logic, or NAND logic. For brevity, in the description of various embodiments, an SSD with one or more NAND dies is used as a non-restrictive example of a DSD. In particular, an M.2 form factor NAND SSD is used as an example. It is understood that at least some of the aspects described herein may also apply to other forms of DSDs.For example, at least some of the aspects described herein may be applicable to DSDs with phase-change memory (PCM) arrays, magnetoresistive random-access memory (MRAM) arrays, and resistive random-access memory (ReRAM) arrays. In still other examples, data may be stored on hard disk drives (HDDs). overview

[0010] As explained above, SSDs can be damaged by water, which can lead to short circuits, corrosion, and damage to the metal layer inside the SSD. For example, condensation of water in ball grid arrays (BGAs) of a printed circuit board (PCB) inside an SSD can cause corrosion between the NAND array die and its BGA pins, or between the data storage controller and its BGA pins, increasing the risk of hardware damage and resulting data loss. Similar problems can occur with other surface-mount devices (SMPs). This is a particular concern with built-in M.2 SSDs used as components in laptops.

[0011] There are several relatively expensive techniques for protecting printed circuit boards from water damage, such as the use of conformal coatings, water-resistant layers, manual spraying, immersion processes, or enclosed housings. These methods can have various drawbacks. For example, coatings and enclosures incur additional costs based on the PCB area, which may require special materials, selective spraying, selective flow, protective measures, or vapor deposition. Coatings on SSD components are very difficult to remove, which significantly complicates cleaning and repair in the event of rework, further increasing the manual costs of rework and recoating. If the entire routing is coated, significant problems can arise when component failures occur and need to be addressed. Environmental and safety regulations must also be considered for SSDs.Coating chemicals may only be used in accordance with local regulations. If the SSD is not classified as environmentally safe, the necessary licenses for import / export or sale may not be granted.

[0012] This document provides a failover power management mechanism for use in M.2 SSDs or other DSDs. In illustrative examples, the failover mechanism includes an intelligent power management device (which may be referred to as the "PMU IP" or simply the "PMU"), a programmable power relay, a linear resistive strip sensor, and a conductivity detector to detect electrically conductive liquids around one or more SMPs of the SSD. The PMU cuts off power to the NAND die and the data storage controller when electrically conductive liquids are detected.

[0013] Not all liquids are electrically conductive. Only electrically conductive liquids pose a significant risk of corrosion or short circuits within the SSD. Such liquids contain metal ions or other impurities that conduct electricity. Accordingly, the conductivity detector is configured to detect the presence of metal ions or other impurities in the liquid to distinguish a non-conductive (and non-harmful) liquid from a potentially harmful, electrically conductive one. In some cases, the failsafe mechanism is only activated when an electrically conductive liquid with sufficient conductivity to pose a significant risk of damage is detected. In other cases, the failsafe mechanism can be activated upon detection of any amount of liquid.

[0014] In some aspects, the conductivity detector collects and analyzes various parameters to detect electrically conductive fluid within the SSD and sends a signal to the PMU to switch a programmable power relay on or off, which in turn powers specific modules, such as the NAND array die and the data storage controller. In other aspects, the procedure involves coordinating and synchronizing the PMU with the data storage controller to send and receive requests and acknowledgments to and from the laptop (or other host), allowing the PMU sufficient time to interrupt the reception of data packets and request a safe shutdown of the laptop by sending an Interrupt Request (IRQ). This protects the NAND array die and the data storage controller from damage or short circuits, thereby safeguarding the data stored in the NAND array.The SSD can also be equipped with an internal lithium-ion battery that powers the failover mode circuit, thus restoring the power output of the NAND and controller.

[0015] These and other functions are described in more detail below. Example M.2 SSD and failover procedures

[0016] Fig.Figure 1 is a schematic block diagram illustrating an exemplary DSD implemented as an SSD (e.g., an M.2 SSD) and including one or more resistive strip sensors, a conductivity detector, and a power management unit (PMU) configured to activate and control a fail-safe mode in response to the detection of electrically conductive liquid (e.g., ionized water) within the SSD, according to some aspects of the disclosure. System 100 includes a host 102 and the SSD 104 (or another DSD, referred to here as an SSD for simplicity) coupled to the host 102. The host 102 provides commands to the SSD 104 to transfer data between the host 102 and the SSD 104.For example, Host 102 can issue a write command to SSD 104 to write data to SSD 104, or issue a read command to SSD 104 to read data from SSD 104. Host 102 can be any system or device that requires data storage or retrieval and a compatible interface to communicate with SSD 104. For example, Host 102 could be a computing device, a personal computer, a laptop, a workstation, a server, a personal digital assistant, a digital camera, or a digital phone, to name just a few. In the main examples given here, the host is a laptop in which the SSD is installed.

[0017] The SSD 104 includes a host interface 106, a data storage controller 108, a memory 110 (such as dynamic RAM (DRAM) or other volatile memory), a physical storage interface (PS) 112 (e.g., Flash Interface Module (FIM)), and an NVM array 114 with one or more NAND dies for storing data. The host interface 106 is coupled to the data storage controller 108 and facilitates communication between the host 102 and the data storage controller 108. The data storage controller 108 is coupled to the memory 110 and the NVM array 114 via the PS interface 112.The host interface 106 can be any suitable communication interface, such as an NVMe (Non-Volatile Memory Express) interface, a USB (Universal Serial Bus) interface, an SP (Serial Peripheral) interface, an ATA (Advanced Technology Attachment) or SATA (Serial Advanced Technology Attachment) interface, a SCSI (Small Computer System Interface), a FireWire (IEEE 1394) interface, or the like. In some embodiments, the host 102 includes the SSD 104. In other embodiments, the SSD 104 is located remotely from the host 102 or is contained in a remote computer system that is communicatively connected to the host 102. For example, the host 102 can communicate with the SSD 104 via a wireless communication link. The NVM array 114 can include multiple dies.

[0018] Although in the Fig.Although the illustrated example in Figure 1 shows the SSD 104 including a single channel between the data storage controller 108 and the NVM array 114 via the PS interface 112, the subject matter described herein is not limited to a single storage channel. For example, in some NAND storage system architectures, two, four, eight, or more NAND channels connect the controller and the NAND storage device, depending on the controller's functions. In all embodiments described herein, more than one channel can be used between the controller and the storage die, even though only a single channel is shown in the drawings. The data storage controller 108 can be implemented on a single integrated circuit chip and communicate with different memory levels in the NVM 114 via one or more command channels.

[0019] The data storage controller 108 manages the operation of the SSD 104. In various aspects, the data storage controller 108 receives commands from the host 102 via the host interface 106 and executes these commands to transfer data between the host 102 and the NVM array 114. Furthermore, the data storage controller 108 can manage reading from and writing to the main memory 110 to perform the various functions executed by the controller and to retrieve and manage cached information in the main memory 110.

[0020] The data storage controller 108 can include any type of processing device, such as a microprocessor, microcontroller, embedded controller, logic circuit, software, firmware, or the like, to control the operation of the SSD 104. In some aspects, some or all of the functions described herein as being performed by the data storage controller 108 can instead be performed by another element of the SSD 104. For example, the SSD 104 can include a microprocessor, microcontroller, embedded controller, logic circuit, software, firmware, ASIC, or any type of processing device to perform one or more of the functions described herein as being performed by the data storage controller 108. In other aspects, one or more of the functions described herein as being performed by the data storage controller 108 are instead performed by the host 102.In yet other aspects, some or all of the functions described herein as being performed by the data storage controller 108 may instead be performed by another element, for example, a controller in a hybrid drive that includes both non-volatile and magnetic storage elements.

[0021] The primary power supply for the SSD 104 is provided by the host 102, which supplies power to the SSD 104 (via a suitable power connector, not shown). A power relay 122 routes the power from the host 102 to various components, such as the data storage controller 108 and the NVM array 114. The SSD 104 includes a power management controller (e.g., PMU) 113, which in this example includes a controller 115 for electrically conductive liquid detection and a failsafe controller 116 for short circuits. The electrically conductive liquid detection controller 115 is configured to receive signals from a conductivity detector 118, which is connected to one or more resistance strip sensors 120 (e.g., linear resistance strips).The electrically conductive liquid detection controller 115 detects the presence of an electrically conductive liquid within the SSD 104 based on information provided by the conductivity detector 118. (In some examples, the conductivity detector 118 is configured to detect the electrically conductive liquid and notify the power management controller 113. In other examples, the power management controller 113 can also receive signals directly from the strip sensor 120.)

[0022] Upon detecting electrically conductive liquid within the SSD, the short-circuit failover controller 116 can interrupt (or lock or disable) the power supply to the host 102 to prevent potential short circuits within the SSD 104. This can be achieved by controlling the power relay 122. When the primary power supply is disconnected, a backup lithium-ion battery 124 can be used as a secondary power supply to continue providing sufficient power so that at least some components of the device (e.g., the power management controller 113 and the conductivity detector 118) can continue to operate in order to detect the subsequent drying of the liquid, allowing the primary power supply to be reactivated.The detector can, for example, be configured to detect when the amount of an electrically conductive liquid falls below a threshold indicating sufficient drying. In some aspects, the power management controller 113 and the conductivity detector 118 can be implemented using any combination of hardware, software, and firmware (e.g., like the implementation options described above for the SSD controller 108).

[0023] The 120 resistance strip sensors are in Fig. 1 is shown in the form of a block diagram; however, it is understood that these components can be placed directly next to certain hardware components of the SSD 104, such as the data storage controller 108 and the NVM array 114. Although in Fig.Not shown in Figure 1, the data storage controller 108 and the NVM array 114 can be mounted on a PCB via BGAs (or other SMPs), with the resistor strips installed next to these BGAs to detect liquid on or near the BGAs that could cause corrosion and / or a short circuit. It should also be noted that the power management controller 113 is shown connected to the host interface 106, because in some examples the power management controller 113 sends signals to the host 102 to request a laptop shutdown if electrically conductive liquids are detected inside the SSD 104 (so that the laptop can be shut down, for example, until the liquid has dried).

[0024] The memory 110 can be any suitable storage device, computing device, or system capable of storing data. For example, the memory 110 can be ordinary RAM, DRAM, DDR-RAM (Double Data Rate), SRAM (Static RAM), SDRAM (Synchronous Dynamic RAM), flash memory, EPROM (Erasable Programmable Read Only Memory), EEPROM (Electrically Erasable Programmable ROM), or similar. In various embodiments, the controller 108 uses the memory 110, or a portion thereof, to store data during data transmission between the host 102 and the NVM array 114. For example, the memory 110, or a portion thereof, can serve as a cache. The NVM array 114 receives data from the controller 108 via the PS interface 112 and stores the data. In some embodiments, the main memory 110 can be replaced by non-volatile memory such as MRAM, PCM, ReRAM, etc.to be replaced in order to serve as a working memory for the entire device.

[0025] The NVM array 114 can be implemented using NAND flash memory. In one aspect, the NVM array 114 can be implemented using any combination of NAND flash, PCM arrays, MRAM arrays, and / or ReRAM. In one example, six NAND flash chips are provided. The PS interface 112 provides an interface to the NVM array 114. For example, if the NVM array 114 is implemented using NAND flash memory, the PS interface 112 can be a flash interface module. In one aspect, the PS interface 112 can be implemented as a component of the SSD controller 108.

[0026] Although in Fig.Not shown in Figure 1, in some examples a temperature sensor is provided in the SSD 104 to enable temperature compensation of the conductivity measurements performed by the conductivity detector 118. Fig. Figure 7 shows a temperature sensor, which is explained further below.

[0027] Although Fig.Although Figure 1 shows an exemplary SSD used throughout this description as an illustrative example, the various disclosed embodiments are not necessarily limited to one SSD application / implementation. For example, the disclosed NVM array and associated processing components can be implemented as part of a package that includes other processing circuitry and / or components. For example, a processor can include an embedded NVM array and associated circuitry, or be otherwise coupled to it. The processor could, for example, offload certain operations to the NVM and associated circuitry and / or components. As another example, the SSD controller 108 can be a controller in a different type of device and still be configured to perform some or all of the other functions described herein.

[0028] Fig.Figure 2 illustrates selected components of an exemplary M.2 SSD 200 configured for communication with an M.2 connector 202 (which can be a component of a laptop in which the SSD 200 is installed), with communication utilizing a PCIe Express Link and NVMe via a PCIe NVMe interface bus (I / F) 204. As shown, the SSD 200 includes a conductivity detector 206 and a linear resistance strip 208. An intelligent power management unit (PMU) 210 is provided, which communicates with the power management controller 113. Fig. 1. The SSD 200 also includes a controller power supply 211 (which can receive power from the host), a programmable relay 212, and a controller and NAND switch 214. Furthermore, the SSD 200 includes a NAND 216 (which corresponds to the NVM array 114). Fig. 1 can correspond) and a storage controller (which corresponds to the data storage controller 108 from Fig.1 can correspond). The components of the SSD 200 are interconnected via various buses, which are shown in the figure but not numbered separately. It should also be noted that in some examples, the conductivity detector 206 is directly connected to the linear resistance strip 208 in order to receive voltage signals directly from the linear resistance strip 208. The linear resistance strip 208 is in Fig. 2 is shown in the form of a block diagram, however, it is understood that the linear resistance strip 208 can be placed directly next to certain hardware components of the SSD 200, such as the NAND 216 and the memory controller 218.

[0029] In this configuration, the conductivity detector 206, using the linear resistive strip 208, detects electrically conductive fluids within the SSD 200 and signals this to the PMU 210, which can then interrupt the power supply (from the power supply unit 211) and / or control the power output to selected components, such as the NAND flash memory 216 and the memory controller 218. To interrupt the power supply, the PMU 210 sends a signal to the programmable relay 212 to disconnect the power supply to specific modules, such as the NAND flash memory 216 and the memory controller 218. The PMU 210 can also send and receive requests and acknowledgments to and from the host via connector 202 to provide sufficient time to pause the reception of data packets and to request a safe shutdown of the host (laptop) by sending an IRQ.In this way, the NAND 216 and the data storage controller 218 can be protected from severe damage or short circuits, thus also protecting the data stored in the NAND. As in . Fig. As shown in Figure 1, the SSD can be equipped with an internal Li-ion battery to power various components such as the PMU 210 and the conductivity detector 206, and to restore the power output of the NAND and the controller once the SSD has dried out. A temperature sensor can also be provided to enable temperature compensation of the conductivity measurements.

[0030] In some examples, the power supply to the NAND 216 and the memory controller 218 can be interrupted when the PMU 210 receives an active signal from the resistor strip 208 indicating a voltage above a programmable threshold voltage to show the presence of liquid (e.g., water near the BGA pins of the NAND 216 and the memory controller 218). In some examples, the PMU 210 also receives signals from the conductivity detector 206 indicating the presence (or absence) of metal ions in the liquid. The power supply is interrupted only if the liquid has a high ion concentration (impurities) indicating a significant short-circuit hazard. For example, signals from the conductivity detector 206 can be compared to appropriate conductivity thresholds.

[0031] In some scenarios, the PMU 210 switches off the NAND 216, activates failover power management procedures, enters a critical or failover mode, and then waits for the water near the BGA pins to dry. In some examples, the PMU 210 (along with the conductivity detector 206 and the resistance strip 208) is always active to make real-time decisions. Continuous voltage changes and measurements can be recorded, with the analog-to-digital converter (ADC) values ​​synchronized with the PMU 210.

[0032] Fig.Figure 3 illustrates an M.2 SSD 300 with selected components. The SSD 300 includes a NAND chip 302 (or NVM array), a conductivity detector 304, a lithium-ion battery 306, a programmable relay 308, a data storage controller 310, other electrical components 312, and a connector 314. A first linear resistive strip 3161 extends along a first edge of the SSD from a distal end (near the NAND 302) to a proximal end (near the data storage controller 310). The linear resistive strip 3161 passes close to a portion of the data storage controller 310 to detect moisture in its vicinity. The linear resistance strip 3161 is also coupled to the conductivity detector 304 to enable the conductivity detector 304 to input and process signals received from the resistance strip to detect water and assess impurities.A second linear resistance strip 3162 extends along an opposite second edge of the SSD and runs close to a section of the NAND 302 to detect moisture in its vicinity. A third linear resistance strip 3163 is coupled between strips 3161 and 3162 and extends along one side of the NAND 302 to detect any moisture along that side of the NAND. Because strip 3163 is coupled to both strip 3161 and strip 3162, signals from strip 3162 can be routed via strip 3161 to the conductivity detector 304. A fourth linear resistance strip 3164 is coupled between strips 3161 and 3162 and extends along one side of the data storage controller 310 to detect any moisture along that side of the data storage controller.A fifth linear resistor strip 3165 is coupled to strip 3162 and extends along another side of the data storage controller 310 to detect any moisture along that side of the file storage controller.

[0033] In other examples, more or fewer strips may be provided. It should be noted that in the example of Fig. There is unused space (318) in the center of the SSD to accommodate additional NAND chips (allowing the SSD to provide additional storage). For example, two additional NAND chips could be installed in the existing space. Additional strips can be provided running alongside these additional NAND chips to enable moisture detection near them.

[0034] Fig.Figure 4 illustrates a side view of a section of an SSD 400 and shows the positioning of resistor strips next to the BGA of a NAND array die. In short, the SSD 400 includes a NAND array die 402 mounted on a PCB 404 via a BGA consisting of solder balls 406. A first resistor strip 408 is mounted on the PCB 404 next to the first side of the NAND array die 402 to detect moisture near the BGA along that side of the NAND array die. A second resistor strip 410 is mounted on the PCB 404 next to the opposite second side of the NAND array die 402 to detect moisture near the BGA along that side of the NAND array die. More or fewer strips can be provided. Although not shown, additional strips can, for example, be provided along the other two sides of the square NAND array die.It should also be noted that if moisture penetrates the BGA under a chip, at least some of this moisture will be located at the chip's edges and can therefore be detected by a resistance strip next to the chip. Therefore, one strip next to the chip is often sufficient. More strips can be provided to ensure more thorough moisture detection.

[0035] Fig. 5A and Fig. Section 5B provides a flowchart illustrating an example procedure 500, which is executed from a suitably equipped SSD such as the M.2 SSD. Fig. 1 or Fig.2. Starting with an M.2 socket in block 502, the M.2 SSD determines whether it is connected to the socket of a host device, such as a laptop. If so, at block 504, the SSD detects whether the host device is providing power. If no power is detected, as indicated by block 506, there is insufficient power for the data storage controller and NAND array die to operate, and processing therefore does not proceed. (Note that the power mentioned here is the power provided by the host, not the power supplied by the additional lithium-ion battery in the SSD to power some SSD components in failover mode.)

[0036] Assuming that power is detected at block 504, the intelligent failover PMU (e.g., PMU 210) is activated at 508. Fig.2) initialized and a current signal is sent at block 510 (e.g., from the PMU 210 to the controller power supply 211 in Fig. 2) to supply power to the data storage controller (e.g., controller 218 in Fig. 2) to control. The data storage controller is initialized at 512, which also activates the NAND chip (e.g., NAND 216 in). Fig. 2) The NAND detection procedure is triggered at 514. NAND detection is used to check and activate the NAND. Connectivity with the laptop is established at 516, and data transfer between the laptop and SSD can be performed at 518.

[0037] Simultaneously, after the PMU is initialized in block 508, current is supplied by the PMU to the conductivity detector / sensor at 520, and at 522 the conductivity and linear resistance sensor components are initialized (e.g., detector 206 is initialized in block 508). Fig.2 initialized). The PMU reads the values ​​from the conductivity detector / sensor at block 524. If no metal ions are detected at block 526 (or if no moisture is detected at all), safe operation is permitted, as indicated by block 528. If metal ions are present in the detected moisture, failover mode is activated at block 530. Note that after block 508, the PMU also activates the Li-ion power supply at block 532 to allow the operation of the PMU and the conductivity detector / sensor during failover mode. It should also be noted that blocks 520-528 may be executed before blocks 510-518 to ensure the safe operation of the data storage controller and the NAND chip. That is, the PMU checks for the absence of electrically conductive liquid before powering on the data storage controller and the NAND chip.

[0038] If failover mode is enabled at block 530, the PMU determines at block 534 whether data is currently being transferred to / from the host. If data is being transferred, the transfer is interrupted at block 536. After this, it is safe to send an IRQ to shut down the laptop. The IRQ is sent to the laptop at block 538 to request a shutdown. Shutting down the laptop is requested because if moisture is detected inside the M.2 SSD, other laptop components may also be affected, necessitating a complete shutdown. When the laptop shuts down automatically, the laptop cuts power to the SSD, as detected at block 540. If power has not yet been cut, the shutdown IRQ request is sent to the laptop again at block 542.Finally, the power supply is deactivated and the laptop shutdown is completed in block 544. In block 546, a signal is sent to the program relay (e.g., relay 212 in ). Fig. 2) sent to cut off power to the data storage controller and NAND. Power to the data storage controller and NAND is then disabled in block 548. Note that even though power from the laptop has already been cut off (as detected in block 540), it is still worthwhile to control relay 212 to also cut power to the data storage controller and NAND. This is done so that when the laptop resumes powering the SSD in failover mode, this power is not passed to the data storage controller and NAND, which could potentially damage these components.

[0039] In block 550, the failover mode continues. During failover mode, in block 554, the PMU and the conductive / resistive detectors / sensors continue to operate, using power from the lithium-ion battery to collect data and determine if any moisture containing metal ions is still present. This means the conductivity detector continues to operate during failover mode. Assuming that liquid containing metal ions is still detected, as determined in block 556, the PMU waits in block 558 until the circuit board is dry. Once the circuit board is dry, it is safe to restart the SSD at block 560. In block 562, power is restored to the data storage controller and the NAND flash memory. In block 564, failover mode is deactivated. Processing returns to block 504 to resume normal operation. Procedure for assessing conductivity

[0040] As explained above, the conductivity detector (e.g., detector 304 in Fig. 3) with at least one resistance strip (e.g. strip 316 in Fig. 3) connected and configured to detect an electrically conductive liquid. In some examples, the conductivity detector can also detect the presence of aqueous metal ions in acids, bases, and salts. For this purpose, the conductivity detector coordinates the timing and sequence of measurements as the resistivity in or around the resistance strip changes. The conductivity detector may also include a built-in data filter to remove noise from the raw analog-to-digital converter data, thus ensuring more accurate measurements. It should be noted that the metal ions can also be referred to as impurities.

[0041] In an example procedure, the conductivity detector receives resistance values ​​(R) from the resistance strips. The resistivity values ​​(ρ) are calculated from the resistance values ​​(R). From the resistivity values ​​(ρ), the conductivity values ​​(σ) are then calculated. The conductivity values ​​(σ) are compared to one or more conductivity thresholds to detect the presence of metal ions or other impurities. More specifically, in some examples, the conductivity values ​​are processed to identify ions originating from salts (such as sodium chloride), acids (such as hydrochloric acid), and bases (such as sodium hydroxide). If the values ​​exceed the threshold(s), metal ions are detected, and the fail-safe mode is activated. Otherwise, normal operation is performed (i.e., the SSD remains in a working state). It should be noted that many aqueous solutions have no conductivity.For example, non-electrolytic solutions like sugar or ethanol do not conduct electricity because they do not contain enough ions. Therefore, the failsafe mode is not only activated when a liquid is detected. It is activated when a potentially harmful metal ion concentration is detected, which could cause corrosion, short circuits, or other problems. (As mentioned earlier, the failsafe can be activated in other ways when water is detected, regardless of the ion concentration in the water.)

[0042] In some examples, the following impurities can be analyzed: Salt NaCl → Na + + Cl - Acid HCl → H + + Cl - Base NaOH → Na + + OH - Water H2O ⇄ H + + OH -

[0043] The detection procedure can be programmed so that the conductivity detector automatically compensates for temperature variations by adjusting either the conductivity values ​​or the thresholds. After manufacturing a test SSD, verification procedures can be performed to check that the SSD's sensor is correctly calibrated to detect metal ions. The threshold(s) or temperature compensation parameter(s) can be adjusted as needed.

[0044] Conductivity processing can include the following processes and features: - Power supply: The intelligent PMU activates and powers the resistance strip and conductivity detector as soon as the SSD is connected to a laptop, ensuring that the system is ready for measurement. - Continuous measurement: The conductivity detector continuously monitors the resistance changes of the resistance strip and detects deviations that are due to the presence of ions in the liquid, which are detected near BGAs and passive components. - ADC value conversion: The analog values ​​of the resistance strip are converted into digital values ​​and further processed using an ADC built into the conductivity detector. - Noise filtering: The conductivity detector uses digital signal processing (DSP) techniques to filter out noise from the raw data of the ADC, thus ensuring more accurate resistance and conductivity measurements. - Conductivity calculation: The conductivity detector determines the conductivity (σ) of the fluid inside the SSD using the formula σ = 1 / ρ. The resistivity (ρ) is calculated using the formula ρ = R*A / L, where R is the resistivity, A is the cross-sectional area of ​​the resistive strip, and L is its length. This procedure utilizes the precise geometric calibration of the resistive strip and the cell constant, which is performed during SSD design and manufacturing. - Temperature compensation: Since the conductivity of liquids increases with temperature, a temperature coefficient constant is used for accurate conductivity measurements: Adapted conductivity = (σ / (1 / +tc*(temperature−25,0))) where tc = temperature coefficient constant per degree Celsius and Temperature = values ​​read from the integrated temperature sensors. - Ion analysis: The conductivity detector analyzes conductivity values ​​to identify the presence of specific ions from salts, acids, and bases. This is achieved by comparing the measured values ​​with pre-programmed (integrated) thresholds stored in the conductivity detector's memory to enable the detection of substances such as sodium chloride, hydrochloric acid, acetic acid, and sodium hydroxide. - Threshold comparison: The conductivity values ​​are compared with predefined threshold values ​​stored in the conductivity detector's memory. This comparison determines whether the solution is sufficiently conductive to pose a risk to SSD operation. The results of the conductivity measurements and ion analysis are stored in the conductivity detector's NVM for further processing. The sensor then sends a control signal to the PMU, which activates the programmable relay to cut off power to the NAND array die and the data storage controller, ensuring safe SSD operation as soon as liquid is detected.

[0045] Regarding cell constants, the cell constant K (known as conductivity probes or electrodes) refers to the ratio of the distance between the two conductive plates to their surface area. These constants are calculated for various liquids during the calibration procedure as part of product development and then stored in SSD memory for use by the conductivity detector. A cell constant uses the unit per centimeter (e.g., 1 / cm), where the value represents the ratio of the distance between the electrode plates (d) to the surface area of ​​the plates (A). The cell constant can be measured as follows: 1. Conductivity probes are calibrated using standard solutions with known conductivity values. 2. The distance between the probes (d) and the surface (A) is measured using the formula K=d / A. 3. The measured values ​​are stored in the SSD memory and used by the conductivity detector.

[0046] Fig.Figure 6 illustrates some of these features. In Block 602, the conductivity detector uses the linear resistive strips to acquire analog resistance values ​​(R), converts the analog values ​​to digital values ​​using an ADC, and smooths the digital values ​​using a DSP noise processing filter. In Block 604, the conductivity detector calculates or determines the resistivity values ​​(ρ) from the resistance values ​​(R) based on the cross-sectional area (A) and length (L) of the resistive strip, as described above. In Block 606, the conductivity detector calculates or determines conductivity values ​​(σ) from the resistivity values ​​(ρ) in a different manner, as described above. In Block 608, the conductivity detector adjusts the conductivity values ​​(σ) to compensate for temperature using the temperature measured by the SSD and a temperature coefficient, as described above.In Block 610, the conductivity detector compares the temperature-adjusted conductivity values ​​(σ) against one or more conductivity thresholds to detect metal ions and, in some examples, identify the specific metal ions. (The conductivity thresholds can also be referred to as impurity thresholds.) In Block 612, the conductivity detector sends a signal to the PMU to activate the failover mode if the temperature-adjusted conductivity values ​​(σ) exceed at least one of the thresholds. Note that in some examples, a single threshold is used, and the failover mode is activated when the conductivity values ​​exceed this threshold. In other examples, multiple thresholds can be defined so that the sensor can distinguish between different types of metal ions, as described above.The detected metal ion type can be stored in memory.

[0047] The specific threshold values ​​programmed into the SSD's conductivity detector can be determined during SSD design by applying liquids containing known amounts of metal ions to the resistance strips within a test fixture and to the test fixture's BGAs. This allows for the determination of the extent of corrosion or short circuits while simultaneously reading the corresponding conductivity values. Subsequently, threshold values ​​can be set based on these conductivity readings to trigger the fail-safe mode, thus preventing any significant risk of corrosion or short circuits. It should be noted that the calibration procedure can also be modified by applying known amounts of different types of metal ions (bases, acids, etc.).This can be done to set different threshold values ​​for the different metal ions, if necessary, so that the device can identify the different types of metal ions. It should also be noted that conductivity is given in Siemens per meter (S / m), while resistivity, the inverse of conductivity, is given in ohmmeters (Ω·m).

[0048] Table I provides exemplary conductivity and resistivity values ​​for various liquids, which can be used to set thresholds for detecting and differentiating various metal ions. For example, threshold pairs can be programmed into the SSD's conductivity detector, with each threshold pair encompassing corresponding conductivity values ​​from the table, enabling the conductivity detector to detect and identify the respective liquid. For example, an initial threshold pair can be set to encompass σ = 0.0000055 S / m. If the measured conductivity falls within this initial threshold pair, ultrapure water will be detected (which is non-corrosive and therefore does not trigger the failsafe mode). In a specific example, the specified conductivity value can be narrowed down using thresholds set to +10% and -10% of the specified value (or +20% and -20%, etc.).The lower threshold is set below the lower conductivity value, and the upper threshold is set above the upper conductivity value. For liquids where a range of values ​​is listed in the table, the lower threshold can be set below the lower conductivity value and the upper threshold above the upper conductivity value. In cases where the thresholds for different liquids may overlap, the detector may not be able to distinguish between them, but would still determine whether the conductivity value justifies triggering the failsafe mode. Table i liquid Conductivity (σ) Specific resistance (ρ) Ultrapure water 0.0000055 S / m 180,000 Ω·m drinking water 0.005 - 0.05 S / m 200 - 20 Ω·m Seawater 4 S / m 0.25 Ω·m Acetic acid (0.1 M) 0.0029 S / m 345 Ω·m Sulfuric acid (0.1 M) 0.07 S / m 14.3 Ω·m Sodium chloride (NaCl, 0.1 M) 1.0 S / m 1.0 Ω·m copper 59,600,000 S / m 0.0000000168 Ω·m aluminum 37,700,000 S / m 0.0000000265 Ω·m Silicon (Intrinsic) 0.00156 S / m 641 Ω·m Silver 63,000,000 S / m 0.0000000159 Ω·m graphite 10,000-100,000 S / m 0.00001-0.0001 Ω·m Example data storage device

[0049] Fig.Figure 7 illustrates an embodiment of an exemplary device 700 configured according to one or more aspects of the disclosure. The device 700 or its components could embody or be implemented in an M.2 SSD comprising one or more temperature sensors 750, one or more linear resistive strips 752, and a NAND die 701 or another type of NVM array for data storage.In various implementations, the Device 700 or its components could be a component of a processor, controller, computing device, personal computer (laptop), portable device, workstation, server, PDA, digital camera, digital phone, entertainment device, medical device, autonomous vehicle control device, edge device, or any other electronic device that stores, processes, or uses data. Specifically, the Device could be an M.2 SSD installed in a laptop computer.

[0050] The device 700 includes a communication interface 702 and is coupled to the NVM 701 (e.g., a NAND die). The NVM 701 comprises the physical memory array 704. The communication interface 702 is further coupled to one or more temperature sensors 750 and one or more linear resistor strips 752. These components can be coupled to each other and / or electrically connected via suitable components, generally represented by the connection line in Fig. Figure 7 is shown. Although not shown, other circuits such as clock sources, peripherals, voltage regulators, and power management circuits may be provided, which are not described further. It should also be noted that the linear resistor strips, as explained above, may be placed next to a BGA of a NAND die and / or a BGA of a DSD data storage controller and / or next to other SSD components.

[0051] The 702 communication interface of the 700 device provides a means of communication with other devices via a transmission medium. In some implementations, the 702 communication interface includes circuitry and / or programming (e.g., a program) suitable for facilitating bidirectional communication of information relating to one or more devices in a system. In some implementations, the 702 communication interface may be configured for wired communication. For example, the 702 communication interface could be a bus interface, a transmit / receive interface, or another type of signaling interface that includes circuitry for outputting and / or receiving signals (e.g., outputting signals from and / or receiving signals in a DSD).

[0052] The physical memory array 704 can include one or more NAND blocks 740. The processing components 710 can access the physical memory array 704. Some of the processing components 710 can be part of a data storage controller of the DSD; others can be separate components, such as the conductivity detector described above, the PMU, etc.

[0053] In one aspect, the 700 device can also include volatile memory for storing instructions and other information to support the operation of the 710 processing components.

[0054] The device 700 includes various processing components 710 arranged or configured to receive, process, and / or send data, control data access and storage, issue or respond to commands, and control other desired operations. For example, the processing components 710 may be implemented as one or more processors, one or more controllers, and / or other structures configured to perform functions. According to one or more aspects of the disclosure, the processing components 710 may be adapted to perform some or all of the features, processes, functions, operations, and / or routines described herein relating to DSDs and SSDs. For example, the processing components 710 may be configured to perform all steps, functions, and / or processes relating to Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5A, Fig. 5B, Fig. 6, Fig. 8, Fig. 9 and Fig. 10 are described. The term “adapted” in connection with the processing components 710 herein may refer to one or more of the components that are configured, deployed, implemented, and / or programmed to perform a specific process, function, operation, and / or routine according to the various characteristics described herein. The circuits may include a specialized processor, such as an ASIC, which serves as a means (e.g., structure) for performing one of the operations that, for example, are associated with Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5A, Fig. 5B, Fig. 6, Fig. 8, Fig. 9 and Fig.10 were described. The processing components 710 serve as an example of a means of processing. In various implementations, the processing components 710 can at least partially fulfill the requirements described above for the components of the conductivity detector 206. Fig. 2 and the PMU 210 in Fig. 2. Provide and / or integrate the described functionality.

[0055] According to at least one example of the device 700, the processing components 710 may include one or more of the following: circuits / modules 719 configured to detect an electrically conductive liquid (or to control the detection of an electrically conductive liquid performed by other components); circuits / modules 720 configured to detect resistance signals from the strips 752; circuits / modules 722 configured to convert resistance signals into specific resistance values; circuits / modules 724 configured to convert specific resistance values ​​into conductivity values; circuits / modules 726 configured to adjust the conductivity values ​​to compensate for the temperature (as detected by the temperature sensors 750);Circuits / modules 728 configured to compare conductivity values ​​with threshold values ​​to detect, for example, the presence of aqueous metal ions or other contaminants indicating the presence of liquid in the DSD that could damage it; circuits / modules 730 to activate a failsafe mode (e.g., when conductivity values ​​exceed one or more threshold values); circuits / modules 732 configured to deactivate the failsafe mode (e.g., once conductivity values ​​no longer exceed the threshold values); circuits / modules 734 configured to request that the laptop be shut down (e.g., upon entering failsafe mode);and circuits / modules 736 configured to identify metal ion types in electrically conductive liquids (when the device is programmed with different conductivity thresholds to differentiate between different types of metal ions or other impurities). It should be noted that circuits / modules 720, 722, 724, 726, and 728 may be components of circuits / modules 719 used to detect the electrically conductive liquid (or they may operate under the control of circuits / modules 719).

[0056] In at least some examples, means for carrying out the in Fig.The functions illustrated in section 7 and / or other functions shown or described herein may be provided. For example, the means may include one or more of the following: means, such as circuits / modules 719, for detecting an electrically conductive liquid (or for controlling the detection of an electrically conductive liquid performed by other components); means, such as circuits / modules 720, for detecting resistance signals from the strips 752; means, such as circuits / modules 722, for converting resistance signals into resistance values; means, such as circuits / modules 724, for converting specific resistance values ​​into conductivity values; means, such as circuits / modules 726, for adjusting the conductivity values ​​to compensate for temperature (as detected by the temperature sensors 750);Means, such as circuits / modules 728, for comparing conductivity values ​​with threshold values ​​to detect, for example, the presence of aqueous metal ions or other contaminants indicating the presence of liquid in the DSD that could damage the DSD; means, such as circuits / modules 730, for activating a failsafe mode (e.g., when conductivity values ​​exceed one or more threshold values); means, such as circuits / modules 732, for deactivating the failsafe mode (e.g., once conductivity values ​​no longer exceed the threshold values); means, such as circuits / modules 734, for requesting the shutdown of the laptop (e.g., upon entering failsafe mode);and means, such as circuits / modules 736, for identifying the metal ion type in electrically conductive liquids (when the device is programmed with different conductivity thresholds that distinguish between different metal ion types). Other exemplary institutions

[0057] Fig. Figure 8 essentially illustrates a data storage device 800 configured according to one or more aspects of the disclosure. The data storage device 800 includes an NVM array 802 mounted on a PCB using a first surface-mount package (SMP). The NVM array 802 can, for example, be mounted on the PCB of the data storage device using a first BGA. The NVM array can, for example, include the NAND 216 in Fig.2. The data storage device 800 also includes one or more processors mounted on the PCB using a second SMP and communicating with the NVM array. The one or more processors 804 are configured to activate a fail-safe mode, individually or in combination, in response to the detection of an electrically conductive liquid. A sensor 806 (for example, a resistance strip for detecting electrical resistance values) is mounted next to the first and / or second SMP. A detector 808 (such as a conductivity detector) is configured to detect the electrically conductive liquid using the sensor. For example, the detector 808 detects an electrically conductive liquid at the first and / or second SMP. In some examples, one of the processors 804 can activate the intelligent PMU 210 in Fig. 2. Another of the 804 processors can be the 218 data storage controller in Fig.It should be noted that the second SMP can include one or more SMPs, including one or more BGAs.

[0058] As explained above, the fail-safe mode prevents damage to the BGAs or other SMPs that may occur due to the presence of electrically conductive liquids on the BGAs or other SMPs, such as liquids containing aqueous metal ions or other conductive contaminants.

[0059] Fig.Figure 9 essentially illustrates a data storage device 900 configured according to one or more aspects of the disclosure. The data storage device 900 includes an NVM array 902 mounted on a printed circuit board. A resistive strip 904 is also mounted on the printed circuit board (it can, for example, be mounted next to the NVM array 902). A conductivity detector 906 is coupled to the resistive strip 904.One or more 908 processors are configured individually or in combination to: receive signals from the conductivity detector indicating whether the amount of metal ions in a liquid contacting the resistive strip exceeds a contamination threshold (indicating, for example, that the liquid is electrically conductive); disable power to the data storage device in response to the amount of metal ions in the liquid exceeding the contamination threshold; and re-enable power in response to the amount of metal ions in the liquid no longer exceeding the contamination threshold.

[0060] The data storage device 900 can also include various other components, such as a data storage controller, with the resistor strip 904 also mounted alongside such other devices to detect metal ions in liquids in or around these devices. Interrupting the power supply prevents damage to the NVM array 902 and other devices that could occur due to the presence of the liquid containing metal ions (e.g., corrosion or short circuit).

[0061] Fig.Section 10 essentially illustrates a method 1000 according to one or more aspects of the disclosure for use by a data storage device. In block 1002, a component of the data storage device (e.g., a conductivity detector) detects the presence of aqueous metal ions within the data storage device (e.g., near a NAND chip or a data storage controller). In block 1004, a component of the data storage device (e.g., the conductivity detector) determines whether the amount (e.g., concentration) of aqueous metal ions exceeds a contamination threshold. In block 1006, a component of the data storage device (e.g., a failover PMU) disables a power supply to the data storage device in response to the amount of aqueous metal ions exceeding the contamination threshold.Later, in block 1008, a component of the data storage device (e.g., the failover PMU) reactivates the power supply in response to the fact that the amount of aqueous metal ions no longer exceeds the contamination threshold.

[0062] In some aspects, a device can be provided that includes components for carrying out the operations of Fig. 10 includes. For example, a device may be provided which includes: means for detecting the presence of aqueous metal ions in the data storage device (e.g., the resistance strip 208 in Fig. 2); Means for determining whether the amount of aqueous metal ions exceeds an impurity threshold (e.g. the conductivity detector 206 in Fig.2); Means of disabling power supply to the data storage device in response to the amount of aqueous metal ions exceeding the contamination threshold (e.g., relay 212 in Fig. 2); and means for reactivating the power supply in response to the fact that the amount of aqueous metal ions no longer exceeds the contamination threshold (e.g. the PMU 210 in Fig. 2).

[0063] In summary, some examples provide systems and procedures for: - Activate a fail-safe power management mechanism that protects M.2 SSD NAND dies and data storage controller BGAs from water damage using various processing circuits (e.g., firmware), relays, PMUs, conductive detectors, and linear resistance strips. - Measuring water contaminants such as metal ions, salt, acids and bases, which can cause corrosion or damage to the BGA pins. - Determine whether the level of water contamination (e.g., metal ion content) exceeds a threshold and, if so, protect the SSD from short circuits by interrupting the main power supply until the water is completely removed or the contamination has dropped to a safe level. - Maintaining the power supply when using deionized or distilled water, as this water does not cause corrosion or short circuits. - Maintaining emergency power supply via a built-in lithium battery, so that the presence or absence of liquids can be detected in time to, for example, switch on the power supply as soon as the SSD is dry, even if the SSD is not connected to the laptop or the laptop is switched off. - Managing the sending of an IRQ signal to the laptop during a safe shutdown. Other aspects

[0064] At least some of the processing circuits described herein can be generally adapted for processing, including the execution of program code stored on a storage medium. The terms "code" or "programming" as used herein are to be interpreted in the broadest sense and include, without limitation, instructions, instruction sets, data, code, code segments, program code, programs, programming, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, execution threads, procedures, functions, etc., regardless of whether they are described as software, firmware, middleware, microcode, hardware description language, or otherwise.

[0065] At least some of the processing circuits described herein can be configured to retrieve, process, and / or send data, control data access and storage, issue commands, and control other desired operations. The processing circuits can include circuits configured to implement, in at least one example, the desired programming provided by suitable media. For instance, the processing circuits can be implemented as one or more processors, one or more controllers, and / or another structure configured to execute programs.Examples of processing circuits include a general-purpose processor, a digital signal processor (DSP), an ASIC, a field-programmable gate array (FPGA) or other programmable logic component, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may include a microprocessor as well as any conventional processor, controller, microcontroller, or state machine. At least some of the processing circuits may also be implemented as a combination of computer components, such as a combination of a controller and a microprocessor, a number of microprocessors, one or more microprocessors in conjunction with an ASIC and a microprocessor, or in any number of other different configurations.The various examples of processing circuits listed here serve for illustration purposes, and other suitable configurations are also conceivable within the scope of the disclosure.

[0066] Aspects of the subject matter described herein can be implemented in any suitable NVM, including NAND flash memory such as 3D NAND flash memory. More generally, semiconductor memory devices include working memory devices such as DRAM or SRAM devices, NVM devices, ReRAM, EEPROM, flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (FRAM), and MRAM, as well as other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured in either a NAND or NOR configuration.

[0067] The memory devices can consist of passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistive switching memory element, such as an anti-fuse, a phase-change material, etc., and optionally a control element, such as a diode, etc. As another non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a dielectric charge storage material.

[0068] Multiple memory elements can be configured to be cascaded or to allow individual access to each element. As a non-restrictive example, flash memory devices in a NAND configuration (NAND memory) typically contain cascaded memory elements. A NAND memory array can be configured to consist of multiple memory strings, where a string comprises multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements can be configured to allow individual access to each element, such as a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be configured differently.The semiconductor memory elements, which are located within and / or above a substrate, can be arranged in two or three dimensions, for example as a two-dimensional memory structure or as a three-dimensional memory structure.

[0069] Typically, associated circuitry is required for the operation and communication of memory elements. As non-limiting examples, memory devices may include circuitry used to control and manage memory elements to perform functions such as programming and reading. This associated circuitry may be located on the same substrate as the memory elements and / or on a separate substrate. For example, a memory read / write controller may be located on a separate controller chip and / or on the same substrate as the memory elements. A person skilled in the art will recognize that the subject matter described here is not limited to the two- and three-dimensional exemplary structures described, but covers all relevant memory structures that fall within the scope and meaning of the subject matter described here, as understood by a person skilled in the art.

[0070] The examples set forth herein serve to illustrate certain concepts of the disclosure. The devices, apparatuses, or components illustrated above may be configured to perform one or more of the procedures, functions, or steps described herein. The person skilled in the art will understand that these are merely illustrative and that other examples may fall within the scope of the disclosure and the attached claims. Based on the teachings set forth herein, the person skilled in the art should recognize that one aspect disclosed herein may be implemented independently of all other aspects and that two or more of these aspects may be combined in various ways. For example, a device may be implemented or a procedure may be carried out using any number of the aspects set forth herein.Furthermore, such a facility may be implemented or such a procedure may be carried out using a different structure, functionality or structure and functionality in addition to or in deviation from one or more of the aspects set forth herein.

[0071] The aspects of the present disclosure have been described above with reference to schematic flowcharts and / or schematic block diagrams of processes, facilities, systems, and computer program products according to embodiments of the disclosure. It is understood that each block of the schematic flowcharts and / or schematic block diagrams, and combinations of blocks in the schematic flowcharts and / or schematic block diagrams, can be implemented by computer program instructions.These computer program instructions can be provided to a processor of a computer or other programmable data processing device to create a machine such that the instructions executed through the processor or other programmable data processing device provide means for implementing the functions and / or actions specified in the schematic flowcharts and / or schematic block diagrams.

[0072] The subject matter described herein may be implemented in hardware, software, firmware, or any combination thereof. Therefore, the terms "function," "module," and the like, as used herein, may refer to hardware, which may also include software and / or firmware components for implementing the described feature. In an exemplary implementation, the subject matter described herein may be implemented using a computer-readable medium on which computer-executable instructions are stored, which, when executed by a computer (e.g., a processor), control the computer to perform the functionality described herein.Examples of computer-readable media suitable for implementing the subject matter described herein include non-transitory computer-readable media such as disk storage devices, chip storage devices, programmable logic devices, and application-specific integrated circuits. Furthermore, a computer-readable medium implementing the subject matter described herein may reside on a single device or computer platform, or it may be distributed across multiple devices or computer platforms.

[0073] It should also be noted that the functions specified in the block may occur in a different order in some alternative implementations than shown in the figures. For example, two blocks shown consecutively may actually be executed essentially simultaneously, or the blocks may sometimes be executed in reverse order, depending on the functionality involved. Other steps and procedures are conceivable that correspond in function, logic, or effect to one or more blocks or parts thereof in the figures shown. Although different arrow and line types may be used in the flowcharts and / or block diagrams, it should be assumed that these do not restrict the scope of the corresponding embodiments. For example, an arrow may indicate a waiting or monitoring period of indefinite duration between the enumerated steps of the embodiment shown.

[0074] The various features and processes described above can be used independently or combined in various ways. All possible combinations and subcombinations are said to fall within the scope of this disclosure. Furthermore, in some implementations, certain procedure, event, state, or process blocks may be omitted. The procedures and processes described herein are also not restricted to a specific order, and the associated blocks or states may be executed in other suitable sequences. For example, described tasks or events may be executed in a different order than expressly stated, or several of them may be combined in a single block or state. The exemplary tasks or events may be executed serially, in parallel, or in any other suitable manner.Tasks or events can be added to or removed from the disclosed exemplary embodiments. The example systems and components described here can be configured differently than described. For example, elements can be added, removed, or rearranged compared to the disclosed exemplary embodiments.

[0075] Experts will recognize that information and signals can be represented using a wide variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips, as referred to in the description above, can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0076] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Each aspect described herein as "exemplary" is not necessarily to be interpreted as preferential or advantageous over other aspects. Likewise, the term "aspects" does not require that all aspects include the discussed feature, advantage, or mode of operation.

[0077] Although the above descriptions contain many specific embodiments of the invention, these should not be interpreted as limitations on the scope of the invention, but rather as examples of specific embodiments thereof. Accordingly, the scope of the invention should not be determined by the embodiments described, but by the appended claims and their equivalents. Furthermore, reference in this specification to “an embodiment,” “in one aspect,” or similar expressions means that a particular feature, structure, or property described in connection with the embodiment is included in at least one embodiment of the present disclosure.Therefore, the occurrences of the expressions “in one embodiment”, “in one aspect” and similar formulations in this specification may all refer to the same embodiment, but need not, but mean “one or more, but not all, embodiments”, unless expressly stated otherwise.

[0078] The terminology used here serves solely to describe certain aspects and is not intended to limit them. The singular forms "a," "an," "a," and "the" are used here to include the plural forms (i.e., one or more) unless the context clearly indicates otherwise. An enumeration of elements does not imply that some or all of the elements are mutually exclusive and / or mutually inclusive unless explicitly stated otherwise. It is further understood that the terms "comprises," "comprehensive," "includes," "including," "showing," and variations thereof, when used herein, mean "including but not limited to," unless explicitly stated otherwise.This means that these terms can specify the presence of certain features, integers, steps, operations, elements, or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Furthermore, it is understood that the word "or" has the same meaning as the Boolean operator "OR," that is, it includes the possibilities of "either" and "both" and is not limited to "exclusively or" ("XOR") unless explicitly stated otherwise. It is also understood that the symbol " / " between two adjacent words has the same meaning as "or" unless explicitly stated otherwise. In addition, expressions such as "associated with," "coupled with," or "in communication with" are not limited to direct connections unless explicitly stated otherwise.

[0079] Any reference to an element herein using a designation such as "first," "second," etc., does not generally limit the set or order of those elements. Rather, these designations may be used here as a convenient method for distinguishing between two or more elements or instances of an element. A reference to first and second elements does not mean that only two elements may be used therein, or that the first element must in any way precede the second element. Unless otherwise specified, a set of elements may also include one or more elements. Furthermore, the terminology used in the description or claims of the form "at least one of A, B, or C," or "A, B, C, or any combination thereof," or "one or more of A, B, or C" means "A, B, or C, or any combination thereof."This terminology can include, for example, A, B, C, A and B, A and C, A and B and C, 2A, 2B, 2C, 2A and B, etc. As another example, "at least one of: 'A, B or C'" or "one or more of A, B or C" should cover A, B, C, AB, AC, BC and ABC, as well as multiples of the same members (e.g., all lists that include AA, BB, or CC). Similarly, "at least one of: A, B and C" or "one or more of A, B or C" should cover A, B, C, AB, AC, BC and ABC, as well as multiples of the same members. Likewise, a phrase such as the one used here, referring to a list linked by "and / or," refers to any combination of the elements. For example, "A and / or B" should cover A alone, B alone, or A and B together. As another example, “A, B and / or C” should cover A alone, B alone, C alone, A and B together, A and C together, B and C together or A, B and C together.

[0080] The term "determine" as used here encompasses a wide variety of actions. For example, "determine" can include calculating, arithmetic, processing, deriving, investigating, looking up (e.g., looking up in a table, a data store, or another data structure), ascertaining, and the like. Furthermore, "determine" can include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), and the like. Additionally, "determine" can include solving, selecting, choosing, setting, and the like.

Claims

[1] Data storage device comprising: a non-volatile memory array (NVM) mounted on a printed circuit board (PCB) using a first surface-mount package (SMP); one or more processors mounted on the circuit board using a second SMP and communicating with the NVM array; a sensor that is mounted next to the first and / or second SMP; a detector configured to detect an electrically conductive liquid using the sensor; and wherein one or more processors are configured to activate a fail-safe processing mode individually or in combination in response to the detection of the electrically conductive liquid. [2] Data storage device according to claim 1, wherein the sensor comprises at least one linear resistive strip; and wherein the detector comprises a conductivity detector coupled to at least one linear resistance strip. [3] Data storage device according to claim 2, wherein the at least one linear resistance strip has a first section next to the first SMP and a second section next to the second SMP. [4] Data storage device according to claim 2, wherein the conductivity detector is configured to detect the electrically conductive liquid by further being configured to detect aqueous metal ions based on electrical resistance signals received from the at least one linear resistance strip. [5] Data storage device according to claim 4, wherein the conductivity detector is configured to detect the aqueous metal ions by further being configured to: the electrical resistance signals received from the at least one linear resistance strip; converts the electrical resistance signals into resistance values; converts the specific resistance values ​​into conductivity values; and compares the conductivity values ​​with one or more conductivity threshold values ​​that indicate the presence of aqueous metal ions. [6] Data storage device according to claim 5, further comprising a temperature sensor, and wherein the conductivity detector is further configured to adjust the conductivity values ​​based on the temperature values ​​measured by the temperature sensor. [7] Data storage device according to claim 1, wherein the one or more processors are further configured to disable a power supply that powers the NVM array in response to the activation of the failover processing mode. [8] Data storage device according to claim 7, wherein the one or more processors are further configured to reactivate the power supply in response to the detector recognizing that an amount of the electrically conductive liquid falls below a threshold indicating sufficient drying. [9] Data storage device according to claim 7, wherein the power supply is provided by a host. [10] Data storage device according to claim 1, wherein the one or more processors are further configured to send a signal to a host in response to the activation of the failover processing mode to request the shutdown of the host. [11] Data storage device according to claim 10, wherein the one or more processors are further configured to send a signal to the host to request the reactivation of the host in response to the detector recognizing that the amount of electrically conductive liquid falls below a threshold indicating sufficient drying. [12] Data storage device according to claim 1, further comprising a secondary power supply which remains active during the failover processing mode to supply power to at least the detector. [13] Data storage device according to claim 1, wherein the data storage device comprises a solid-state device (SSD) in the M.2 form factor. [14] Data storage device according to claim 1, wherein the first and / or the second SMP comprises a Ball Grid Array (BGA). [15] Data storage device comprising: a non-volatile memory array (NVM) mounted on a printed circuit board (PCB); a resistor strip mounted on the circuit board; a conductivity detector coupled to the resistance strip; and one or more processors configured individually or in combination to: To receive signals from the conductivity detector indicating whether the amount of metal ions in a liquid contacting the resistance strip exceeds a contamination threshold; to disable the power supply to the data storage device in response to the amount of metal ions in the liquid exceeding the contamination threshold; and to reactivate the power supply in response to the fact that the amount of metal ions in the liquid no longer exceeds the contamination limit. [16] Data storage device according to claim 15, wherein the conductivity detector is configured to detect the metal ions by further being configured to: receives electrical resistance signals from the resistance strip; converts the electrical resistance signals into resistance values; converts the specific resistance values ​​into conductivity values; and the conductivity values ​​with one or more compares conductivity threshold values ​​that indicate the presence of metal ions in the liquid. [17] Data storage device according to claim 16, further comprising a temperature sensor, and wherein the conductivity detector is further configured to adjust the conductivity values ​​based on the temperature values ​​measured by the temperature sensor. [18] Data storage device according to claim 15, wherein the resistance strip has a section adjacent to the NVM array. [19] Data storage device according to claim 15, further comprising a data storage controller, and wherein the resistance strip has a section adjacent to the data storage controller, and the data storage device comprises a solid-state device (SSD) in the M.2 form factor. [20] Data storage device comprising: Means for detecting aqueous metal ions in the data storage device; Means for determining whether the aqueous metal ions exceed a contamination threshold; Means of disabling power supply to the data storage device in response to aqueous metal ions exceeding the contamination threshold; and Means to reactivate the power supply in response to the aqueous metal ions no longer exceeding the contamination threshold.

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