ENERGY STATE MANAGEMENT IN A DATA STORAGE DEVICE

Abstract

The disclosure relates in some aspects to the management of power states in a data storage device. A data storage device can receive a request from a host device to switch to a specific power state. Such a request can be used to cause the data storage device to switch to a corresponding internal power state. In some scenarios, the host device might not support the same internal power states supported by the data storage device. In this case, the data storage device can switch to an internal power state that is lower than the internal power state supported by the host device in conjunction with the request.

Description

AREA

[0001] In some embodiments, the disclosure relates to data storage devices such as non-volatile memory (NVM), as well as storage controllers and host devices for use with them. More specifically, but not exclusively, the disclosure relates to the management of energy states in a data storage device. INTRODUCTION

[0002] In consumer electronics, solid-state drives (SSDs) or other data storage devices (DSDs) using non-volatile memory (NVM), such as flash NAND flash memory, frequently replace or supplement traditional rotating hard disk drives for mass storage in many consumer or industrial electronics devices and computers. In a typical SSD-based product (e.g., a solid-state drive), a host device includes or communicates with an NVM device controller, which in turn controls access to one or more NVM devices (e.g., NVM arrays). For example, the host device can send write and read commands to an NVM device controller to write data to and read data from an SSD.

[0003] A host device can control the power state of a data storage device (such as an SSD) to reduce power consumption in certain situations. For example, if the host device has no pending write or read commands to send to a data storage device, it can instruct the data storage device to enter a lower power state. In some cases, entering a lower power state might involve temporarily disabling one or more components of the data storage device.

[0004] EP 2 048 571 B1 relates to a method for network interfaces to improve latency when exiting the L1 layer of the Active Power Management System (ASPM) of PCI Express (PCI-E) by speculatively initiating an early L1 exit based on a network incentive. DE 10 2021 114 459 A1 relates generally to data storage devices and, in particular, to a controller of a data storage device that is configured to predict when a host device will send a command to enter a low-power state, to prepare the data storage device to enter the low-power state, and to receive a command to enter the low-power state after prediction and preparation. SUMMARY

[0005] According to the invention, data storage devices and a method for controlling at least one energy state of a data storage device with the features of the independent claims are provided; dependent claims relate to preferred embodiments.

[0006] The following is a simplified summary of some aspects of Revelation, intended to provide a basic understanding of these aspects. This summary does not constitute a comprehensive overview of all features of Revelation under consideration, nor is it intended to identify key or critical elements of all aspects of Revelation, nor to limit the scope of any single aspect or all aspects of Revelation. Its sole purpose is to present various concepts of some aspects of Revelation in a simplified form as a prelude to the more detailed description that will follow.

[0007] One embodiment of the disclosure provides a data storage device that includes a non-volatile memory array, a PCI (Peripheral Component Interconnect) interface, and at least one processor coupled to the non-volatile memory array and the PCI interface. In one example, the at least one processor is configured to: receive, via the PCI interface, a request from a host device to switch to a PCI-D3 power state; determine that the host device does not support an L1.2 interconnect state; and, in response to receiving the request and determining that the host device does not support the L1.2 interconnect state, set an initial power state of the data storage device to a non-operational power state.

[0008] One embodiment of the disclosure provides a method for controlling at least one energy state of a data storage device. In an example, the method includes: receiving a request from a host device to enter a PCI-D3 (Peripheral Component Interconnect) energy state, determining that the host device does not support an L1.2 interconnect state, and setting a first energy state of the data storage device to a non-operational energy state in response to receiving the request and determining that the host device does not support the L1.2 interconnect state.

[0009] One embodiment of the disclosure provides a data storage device. In an example, the data storage device includes: means for receiving a request from a host device to enter a PCI-D3 (Peripheral Component Interconnect) power state, means for determining that the host device does not support an L1.2 interconnect state, and means for setting an initial power state of the data storage device to a non-operational power state in response to receiving the request and determining that the host device does not support the L1.2 interconnect state.

[0010] One embodiment of the disclosure provides a non-volatile, computer-readable medium that stores computer-executable code for storing data. In one example, the computer-readable medium includes code for: receiving a request from a host device to enter a PCI-D3 (Peripheral Component Interconnect) power state, determining that the host device does not support an L1.2 interconnect state, and setting an initial power state of the data storage device to a non-operational power state in response to receiving the request and determining that the host device does not support the L1.2 interconnect state.

[0011] These and other aspects of Revelation will be better understood by reading the following detailed description. Other aspects, features, and implementations of Revelation will become apparent to experts when reading the following description of specific implementations of Revelation in conjunction with the accompanying figures. While features of Revelation may be discussed below in relation to certain implementations and figures, all implementations of Revelation may include one or more of the beneficial features discussed here. In other words, even if one or more implementations are said to have certain beneficial features, one or more of these features may also be used according to the various implementations of Revelation discussed herein.Similarly, while certain implementations may be discussed below as device, system or process implementations, it is understood that such implementations can be implemented in various devices, systems and processes. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] A more detailed description with reference to the specific embodiments illustrated in the accompanying drawings is included below. Since these drawings naturally only represent certain embodiments of the disclosure and therefore may not be considered as limiting its scope of protection, the disclosure is described and explained with additional specificity and detail using the accompanying drawings, in which: Fig.1 An example of a data storage device (DSD) implemented as a solid-state drive (SSD) and configured according to one or more aspects of the disclosure is illustrated. Fig. Figure 2 illustrates an example of conventional energy state management processes. Fig. 3. An example of signal timing for the energy state management processes of Fig. 2 illustrated. Fig. 4 illustrates an example of energy state management operations according to one or more aspects of the disclosure. Fig. 5 an example of signal timing for the energy state management processes of Fig. 4 illustrated according to one or more aspects of the revelation. Fig.6 illustrates an exemplary hardware implementation for a data storage device (e.g., an SSD) that includes various components to support power state management according to one or more aspects of the disclosure. Fig. 7. An exemplary SSD that supports power state management, as described in one or more aspects of the revelation. Fig. 8 an exemplary hardware implementation for a Data storage device (e.g., an SSD) that supports power state management, illustrated according to one or more aspects of the disclosure. Fig. 9 illustrates an example of energy state management operations according to one or more aspects of the disclosure. Fig. 10 illustrates another example of energy state management operations according to one or more aspects of the revelation. Fig. 11 illustrates another example of energy state management operations according to one or more aspects of the revelation. Fig. 12 illustrates another example of energy state management operations according to one or more aspects of the disclosure. DETAILED DESCRIPTION

[0013] The following detailed description refers to the accompanying drawings, which form an integral part thereof. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description. The description of elements in each figure may refer to elements in the preceding figures. Identical reference numbers may refer to identical elements in the figures, including alternative embodiments of the same elements.

[0014] The disclosure relates in some aspects to various devices, systems, procedures, and media for managing energy states in a data storage device. A data storage device can receive a request from a host device to switch to a specific energy state. Such a request can be used to cause the data storage device to switch to a corresponding internal energy state. In some scenarios, the host device may not support the same internal energy states supported by the data storage device. In this case, the data storage device can switch to an internal energy state that is lower than the internal energy state supported by the host device in conjunction with the request.

[0015] To illustrate, various aspects of the disclosure are described in the context of a storage system that incorporates NAND memory technology. A NAND device may be referred to here as NAND flash memory, NAND storage device, NAND flash, or simply NAND. In general, a NAND device is a non-volatile memory with high storage density, fast access time, low power consumption during operation, and advantageous shock resistance compared to more conventional storage platforms. Raw NAND devices can be equipped (e.g., configured) with a serial interface such as Open NAND Flash Interface (ONFi), Common Flash Memory Interface (CFI), and the like. NAND devices can be configured as discrete memory chips or packaged with a controller to form an SD (Secure Digital) memory card, a MultiMediaCard (MMC), or a solid-state drive.A NAND device can be configured with a single flash chip or multiple chips. In addition to memory cells, a NAND device can include other components, such as control / address logic components, I / O components, and data register components. It is understood that the teachings contained herein are also applicable to other memory forms (e.g., NVM other than NAND devices). For example, at least some of the aspects described herein may be applicable to a data storage or memory device, including phase-change memory (PCM) arrays, magnetoresistive random-access memory (MRAM) arrays, memory class memory, and resistive random-access memory (ReRAM) arrays. Example of a storage system

[0016] Fig.Figure 1 illustrates an embodiment of a storage system 100 that includes a host device 102 and a solid-state drive (SSD) or other data storage device (DSD) 104 that is communicatively coupled to the host device 102. For brevity, the SSD / DSD 104 may be referred to here as SSD 104. The host device (e.g., a host computer) 102 provides commands to the SSD 104 for transferring data between the host device 102 and the SSD 104. For example, the host device 102 may provide a write command to the SSD 104 to write data to the SSD 104 or send a read command to the SSD 104 to read data from the SSD 104. The host device 102 may be any system or device that requires data storage or retrieval and has a compatible interface for communicating with the SSD 104.For example, the host device 102 could be a computing device, a personal computer, a portable computer or workstation, a server, a PDA, a digital camera, a digital telephone, or the like.

[0017] The SSD 104 includes a host interface 106, an SSD / DSD controller 108, a memory module 110, and a non-volatile memory (NVM) module 112. For brevity, the SSD / DSD controller 108 can be referred to here as the SSD controller 108. The host interface 106 is connected to the SSD controller 108 and facilitates communication between the host device 102 and the SSD controller 108. Furthermore, the SSD controller 108 is connected to the memory module 110 and the NVM module 112. Host interface 106 can be any type of communication interface, such as a PCI (Peripheral Component Interconnect), PCIe (PCI Express), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), SP (Serial Peripheral), ATA (Advanced Technology Attachment), SCSI (Small Computer System Interface), IEEE 1394 (Firewire), or similar.PCIe, for example, is a high-speed serial computer expansion bus standard published by the PCI Special Interest Group (PCI-SIG) that specifies an interface used by expansion cards (e.g., graphics cards, SSDs, etc.) that are plugged into the expansion slots on the motherboard of a PC.

[0018] In some embodiments, the host device 102 includes the SSD 104 (e.g., the host device 102 and the SSD 104 are implemented as a single component). In other embodiments, the SSD 104 is located remotely from the host device 102 or is contained in a remote computing system that is communicatively coupled to the host device 102. For example, the host device 102 can communicate with the SSD 104 via a wireless communication link.

[0019] The SSD controller 108 manages the operation of the SSD 104. In various embodiments, the SSD controller 108 receives commands from the host device 102 via the host interface 106 and executes these commands to transfer data between the host device 102 and the NVM 112. Furthermore, the SSD controller 108 performs internal operations such as garbage collection, data integrity, and wear leveling. In some examples, the SSD controller 108 can execute the aforementioned operations and / or other operations as processing threads (usually referred to simply as threads), where a specific thread can correspond to a specific set of instructions whose execution can be scheduled independently. The SSD controller 108 can execute such threads serially and / or in parallel.The SSD controller 108 can include any type of processing device, such as a microprocessor, microcontroller, embedded controller, logic circuit, software, firmware, hardware or the like, to control the operation of the SSD 104.

[0020] In some embodiments, some or all of the functions described herein as being performed by the SSD controller 108 may instead be performed by another element of the SSD 104. For example, the SSD 104 may include a microprocessor, a microcontroller, an embedded controller, a logic circuit, an application-specific integrated circuit (ASIC), software, firmware, or any other type of processing device to perform one or more of the functions described herein as being performed by the SSD controller 108. In some embodiments, one or more of the functions described herein as being performed by the SSD controller 108 are instead performed by the host device 102.In some embodiments, some or all of the functions described herein as being performed by the SSD controller 108 may instead be performed by another element, such as a controller in a hybrid drive that includes both non-volatile memory elements and magnetic memory elements.

[0021] The memory 110 can be any storage device, computing device, or system capable of storing data. For example, the memory 110 can be random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), flash memory, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or the like. In various embodiments, the SSD controller 108 uses the memory 110, or a portion thereof, to store data during data transfer between the host device 102 and the NVM 112. For example, the memory 110, or a portion thereof, can be a cache memory.

[0022] The host device 102 includes a module (e.g., hardware and / or software) for managing power states 114. In certain situations, the power state management module 114 can send a request to the SSD 104 to change a power state 116. For example, the power state management module 114 can send a message over a PCI bus that configures a register (not shown) on the SSD 104 to indicate a specific power state of the device (e.g., D0, D1, D2, or D3).

[0023] The SSD 104 includes a module (e.g., hardware and / or software) for managing power states 118. In response to a change in the power state specified by the register discussed above, the power state management module 118 can control one or more components of the SSD 104 to change the power consumption of the component(s). For example, if the register is set to indicate a D3 power state (lowest power state), the power state management module 118 can turn off (e.g., disable, power down, etc.) one or more processing cores, memory circuits, and / or phase-locked loops (PLLs). PCI power states

[0024] The PCI Power Management Specification defines several device power states (Dx): D0, D1, D2, D3hot, and D3cold. As described in Table 1 below, power state D0 corresponds to device operation at full power, power states D1 and D2 correspond to medium power consumption, and power state D3 corresponds to lowest power consumption. Power state D3 is further divided into two separate and distinct substates, D3hot and D3cold. The lower power states can be used, for example, in conjunction with putting a device into a sleep state. Table 1 Conditions Description D0 uninitialisiert When a device emerges from a conventional reset or a Functional Level Reset (FLR), it is in D0 by default. uninitialisiert -Condition D0 aktiv After completion of the enumeration and configuration process (e.g., device identification and address assignment), the device enters the D0 aktiv -State, the fully operational state. In this state, one of the following is possible: the memory space enable bit, the I / O space enable bit, or the bus master enable bit has been activated. D1 Optional D2 Optional D3 hot D3 hot This is a power-saving state in which the device's main power supply is not interrupted. Upon exiting this state, the device could transition to state D0 (uninitialized or unactive state). D3 cold D3 hot This is a state in which the main power supply to the device is interrupted. After exiting this state, a complete reinitialization must be performed, e.g., to D0. uninitialisiert -Condition PCI connection states

[0025] The PCI power management specification also defines several link states: L0, L1, L2, and L3. These link states can refer to the power state of components communicating over a PCIe (PCI Express) link. Depending on the link state, the device's power consumption can vary. As described in Table 2 below, link state L0 corresponds to normal operation of a device at full power, link state L1 corresponds to a low-power state, such as with intermittent power savings, link state L2 corresponds to a lower power state (e.g., lower power than link states L1 and L0), and link state L3 corresponds to a completely off state. In some aspects, the link states can correspond to the device power states discussed above.For example, the connection state L0 can correspond to the energy state of device D0, the connection state L1 to the energy state of device D1, D2, or D3hot, and the connection state L2 to the energy state of device D3cold. In some examples, devices in device energy state D0 can autonomously switch between the connection states L0, L0s, and L1. Table 2 Conditions Description L0 Normal, fully operational connection state L0 S Low-power connection state; Exhibits the shortest exit latency back to the L0 state; Access is controlled exclusively by the hardware. L1 Low power connection state; can be triggered by: - ​​Active State Power Management (ASPM) - Device power management (PM) when the device switches to state D1, D2 or D3hot L1.1 In the L1.1 state, the common-mode voltages of the connection are maintained. L1.2 In the L1.2 state, the common-mode voltages of the connection do not need to be maintained. L2 Low power connection state; The connection is put into the L2 state when the device is put into the D3 cold state. L3 Full power-off state NVMe energy states

[0026] The NVMe (Non-Volatile Memory Express) architecture defines several active power states that can be used to manage the performance of SSDs. In one example, six NVMe power states are defined: PS0, PS1, PS2, PS3, PS4, and PS5. In this example, PS0, PS1, and PS2 can be active power states, and PS3, PS4, and PS5 can be inactive power states. Other examples may use a different number of NVMe power states.

[0027] An operating power state can be used, for example, to throttle an SSD to a specific TDP (Thermal Design Power) to manage platform temperature (e.g., device temperature) and overall power consumption. A non-operational power state can be used, for example, in portable SSDs to improve battery life. While the device is inactive, its power consumption can be close to zero. In some examples, the NVMe architecture utilizes PCIe's low-power states to achieve reduced power consumption.

[0028] Table 3 shows a series of examples of device power consumption at different link energy levels and different NVMe energy levels. Other examples may show different power consumption values. Connection status NVMe power status Average (30 seconds) power output (watts) L1.2 PS5 0,0023 PS4 0,003 PS3 0,0053 PS2 0,2049 PS1 0,2059 PS0 0,2062 L1 PS5 0,0106 PS4 0,0109 PS3 0,0135 PS2 0,4673 PS1 0,4706 PS0 0,4719 L0 PS5 1,0982 PS4 1,1108 Table 3 PS3 1,1157 PS2 1,0563 PS1 1,056 PS0 1,057 L3hot(L1.2) PS5 0,0027 Conventional energy state management

[0029] As mentioned above, a host can change the power state of a PCI peripheral device, such as a data storage device (which includes a PCI interface), by setting bits in a register of the device. For example, a Power Management Control / Status Register (PMCSR) might include two bits to specify a device power state, such as D0, D1, D2, or D3. Typically, D3hot is specified by setting each of these two bits to one (1). A host can also specify a D3cold power state to the data storage device by issuing a shutdown request via a power management event signal. In some examples, an interrupt is generated on the data storage device after a host write operation to the PMCSR. This allows the data storage device to immediately detect that its power state needs to be changed.

[0030] When a host sets the bits of a PMCSR of a data storage device (operating in an active state) to indicate D3, a D3 hot transition occurs on the data storage device. If the host supports the L1.2 link state, the data storage device transitions to its lowest non-operational power state upon receiving the D3 hot request. In the example in Table 3, this corresponds to the last entry in the table, where the NVMe power state is PS5 and the data storage device's power consumption is approximately 3 milliwatts (mW) or less.

[0031] If, however, the host does not support the L1.2 connection state (e.g., the host might be a legacy host that only supports the L1 connection state), the data storage device remains in a ready power state, and the connection state is set to the L1 connection state according to the PCI specification requirements. In the example in Table 3, this corresponds to the bold NVMe power states PS0, PS1, or PS2. In this example, the power consumption of the data storage device is approximately 470 mW. Therefore, the power consumption of the data storage device is significantly higher in D3hot scenarios where the host does not support the L1.2 connection state.

[0032] Fig. Figure 2 shows an example of operations that can be performed on a data storage device (e.g., a PCI-based SSD) in conjunction with the conventional processing of a D3hot request from a host device. At #202, a D3hot interrupt occurs on the data storage device. At #204, the data storage device determines whether the L1.2 link state is supported by the host. If so, at #206, the data storage device triggers a transition to the L1.2 link state. Additionally, at #208, the data storage device triggers a non-operational low-power sequence (e.g., a transition to a non-operational low-power state). For example, the data storage device might set the NVMe power state to PS5 and power off one or more components of the data storage device.At # 210, the activation source for the data storage device is configured to CLK_REQ (e.g., the CLK_REQ signal) according to the requirements of the PCI specification.

[0033] CLK_REQ is a dedicated signal between a host and a specific device. It is used, for example, to inform a device in the D3cold state that it needs to be activated to receive commands from the host. CLK_REQ is configured as an open-drain signal, meaning the host and the device can independently set (activate) the signal to the active low state. When a device is in a non-operational state, both the host and the device disable the CLK_REQ signal. If the host subsequently needs to send a command to the device, the host activates the CLK_REQ signal (sets it low). This tells the device, for example, that it needs to enter an operational state.

[0034] Fig. Figure 3 shows an example of PCIe bus signaling, which is used with some of the operations of Fig. 2 can be linked. In some aspects, this figure illustrates that the CLK_REQ signal can be controlled by the host and / or by the logic on the device side. In response to a D3hot request, a data storage device in the L1 link state stops setting CLK_REQ to a low state. In other words, the data storage device disables the CLK_REQ signal (302). Furthermore, the host stops operating CLK_REQ (disables 304). Consequently, the CLK_REQ signal is in an inactive (disabled) high state when the data storage device link state changes to L1.2 (306). After a 2-microsecond abort window, the data storage device link state is inactive at L1.2 (308).After a 4 microsecond shutdown window of the physical PCI interface (PHY), the data storage device can shut down components such as a host interface module (HIM) and the PCI-PHY 310.

[0035] With renewed reference to Fig. 2: If the data storage device detects at #204 that the host does not support the L1.2 connection state, the operational flow proceeds to #212 (instead of #206), with the data storage device ignoring the D3hot request. In this case, the data storage device remains in the L1 connection state and updates its power state to the previous operational power state (e.g., PS0, PS1, or PS2). The data storage device then sends a response to the host indicating the current power state of the data storage device. As discussed above, the power consumption at the data storage device is much higher in this scenario because the host does not support the L1.2 connection state. Exemplary energy state management

[0036] Given the aforementioned problems with conventional power state management, the disclosure relates in some aspects to various techniques for managing power states in a scenario where a host does not support certain power states (e.g., link state L1.2). In some examples, a data storage device receiving a D3hot request in a scenario where the host does not support link state L1.2 may nevertheless enter link state L1.2 and a non-operational power mode (e.g., PS5). In some aspects, this action may be described as a pseudo- (or fake) L1.2 mode.

[0037] Fig. Figure 4 illustrates an example of operations that can be performed on a data storage device (such as a PCI-based SSD) in conjunction with processing a D3hot request from a host device, as taught herein. At #402, a D3hot interrupt occurs on the data storage device. At #404, the data storage device determines whether the L1.2 connection state is supported by the host. For example, the data storage device can read a host capability register on the data storage device that the host has configured to indicate whether the host supports the L1.2 connection state.

[0038] If the host supports the L1.2 connection state, the data storage device triggers a transition to the L1.2 connection state at #406. Additionally, at #408, the data storage device triggers a non-operational low-power sequence (e.g., a transition to a non-operational low-power state). For example, the data storage device might set the NVMe power state to PS5 and power down one or more components of the data storage device (e.g., disable, shut down, etc.).

[0039] If, however, the data storage device detects at #404 that the host does not support the L1.2 link state, the operation proceeds to #410 (instead of #406), causing the data storage device to enter a pseudo (fake) L1.2 mode. In this case, the data storage device can rewrite the PMCSR to indicate the L1.2 link state. Additionally, the data storage device can update its power state to D3hot. The operation then continues with #408, as discussed above.

[0040] In some examples, the non-operational low-power sequence of #408 can include the hibernation of one or more computer threads and / or processing cores. Here, control can be delegated to a power management module (PM module) (e.g., a PM IC) to activate only one primary core and its associated XRAM. Therefore, all other cores and memory can be turned off along with one or more PLLs.

[0041] Before entering the non-operational power state, the data storage device can configure its wake-up source as an EIB (Electrical Idle Broken) signal. In some examples, using the EIB signal as the wake-up source involves the data storage device monitoring (detecting) an electrical disturbance on the PCI bus (e.g., because the host sends a command or other signal) to determine when to wake from power-saving mode. In some examples, a host interface module can perform EIB detection (e.g., by determining whether a PCI PHY of the data storage device has received a signal on a PCI bus signal path).

[0042] At #410, the data storage device determines whether the L1.2 mode is a true L1.2 mode or a pseudo (fake) L1.2 mode. If the L1.2 mode is a true L1.2 mode, the activation source for the data storage device at #412 is CLK_REQ, as required by the PCI specification.

[0043] However, if the L1.2 mode is a pseudo (fake) L1.2 mode, the data storage device configures its wake-up source as EIB at #416. Instead of relying on CLK_REQ (which is unavailable in this case because the host has not disabled CLK_REQ), the data storage device monitors the PCI bus for electrical disturbances (such as the host sending a command or other signal) to determine when to wake it from sleep mode.

[0044] If a data storage device detects that a host does not support PCIe L1.2 power-saving mode, the data storage device can enter a pseudo-L1.2 mode by switching the connection from the data storage device side to L1.2 mode and configuring EIB as the wake-up source. With EIB configured as the wake-up source, a disturbance on the PCIe connection can wake the data storage device (e.g., generating a corresponding interrupt) and put the connection into L0 mode. For example, the firmware on the data storage device can be configured in a polling mode, with the firmware initiating wake-up mode in response to the interrupt.

[0045] Fig. Figure 5 shows an example of PCIe bus signaling, which is associated with some of the operations of Fig. 4 can be linked. In response to a D3hot request, a data storage device in the connection state L1 502 CLK_REQ is disabled. Unlike Fig. However, in this case, the host does not disable CLK_REQ because the host does not expect a change to the L1.2 connection state on port 504 (e.g., the host assumes the connection state is L1), and CLK_REQ is only used for the L1.2 connection state according to the PCI specification. After a 2-microsecond abort window, the connection state for the data storage device is inactive at L1.2 on port 506. After a 4-microsecond PHY shutdown window, the data storage device can shut down components such as one or more host interface modules (HIMs), a PCI physical interface (PHY) on port 508, processing cores, memory, PLLs, or other SSD components.

[0046] In the example of Fig. 4. Power consumption at the data storage device can be much lower if the host does not support the L1.2 connection state, compared to the example of Fig. 2. For example, the power consumption of the data storage device in pseudo (fake) L1.2 mode (D3hot, L1.2, and PS5) can be around 11 mW in some cases. Pseudo (fake) L1.2 mode may require more power than true L1.2 mode, for example, due to the use of EIB monitoring.

[0047] Since the power consumption of the data storage device is lower, the battery life of the entire computing system (e.g., a laptop) can be longer. Furthermore, because the power consumption of the data storage device is lower, the temperature of the electronic components (e.g., ASICs and NAND devices) is also lower, which can improve performance and / or extend the lifespan of the components.

[0048] In light of the foregoing, the disclosure relates in a first aspect to setting a first energy state (e.g., an NVMe energy state) of the data storage device to a non-operational energy state (e.g., PS5) as a result of receiving a D3hot request and a finding that the host device does not support the L1.2 connection state.

[0049] In a second aspect, the disclosure relates to entering the PCIe D3hot energy state as a result of receiving a D3hot request and determining that the host device does not support the L1.2 link state.

[0050] In a third aspect, the disclosure relates to setting a PMCSR (Power Management Control and Status Register) to indicate the L1.2 connection state when a D3hot request is received and it is determined that the host device does not support the L1.2 connection state.

[0051] In a fourth aspect, the disclosure relates to the configuration of an activation circuit for detecting an EIB (Electrical Idle Broken) signal as a result of receiving a D3hot request and determining that the host device does not support the L1.2 connection state.

[0052] In a fifth aspect, the disclosure relates to the monitoring of an EIB (Electrical Idle Broken) signal as a result of receiving a D3hot request and the finding that the host device does not support the L1.2 connection state.

[0053] In a sixth aspect, the disclosure relates to the transition of the data storage device's first energy state to an operating energy state as a result of the detection of an EIB signal.

[0054] In a seventh aspect, the disclosure relates to the transition of an NVMe energy state of the data storage device to an operating energy state as a result of the detection of an EIB signal.

[0055] In an eighth aspect, the disclosure refers to entering a PCI-D0 energy state as a result of detecting an EIB signal.

[0056] In a ninth aspect, the disclosure relates to configuring at least one component of the data storage device to switch from a first energy state to a second energy state, which is associated with lower power consumption than the first energy state, as a result of receiving a D3hot request and determining that the host device does not support the L1.2 connection state.

[0057] In a tenth aspect, the disclosure relates to configuring the at least one component for switching from the second power state to the first power state as a result of detecting an EIB signal.

[0058] In an eleventh aspect, the disclosure relates to the shutdown of at least one processing core, memory circuit or phase-locked loop (PLL) as a result of receiving a D3hot request and determining that the host device does not support the L1.2 interconnect state.

[0059] In a twelfth aspect, the disclosure relates to the switching on (e.g., activating, turning on, etc.) of the processing core, the memory circuit, or the PLL as a result of the detection of an EIB signal.

[0060] These and other aspects of the revelation are now discussed in connection with the Fig. Sections 6 to 12 are described in more detail. Exemplary components of a data storage device

[0061] Fig. Figure 6 shows an embodiment of a data storage device 602 that can support the power state management taught herein. The data storage device 602 includes a controller 604 that writes data to and reads data from an NVM 606 and performs other related data storage operations (e.g., as discussed herein).

[0062] The data storage device 602 includes a physical PCI interface (PCI PHY) 608 for communication with other devices via a PCI bus 610. The PCI bus can be a legacy PCI bus, a PCI Express bus (PCIe), or another form of PCI bus (e.g., as defined by future standards).

[0063] The data storage device 602 includes a host interface module (HIM) 612 for communication with a host device (not shown) via the PCI-PHY 608. In some examples, the HIM 612 can process commands (e.g., data write / read, register write / read, etc.) from the host device and take appropriate actions (e.g., forward data commands to the controller 604, forward read data to the host device, write to registers, etc.).

[0064] In the example of Fig. In section 6, a bus 614 is used to enable communication between different components of the data storage device 602. Such communication between components can also be implemented in other ways in various examples (e.g., some components can communicate via a dedicated bus).

[0065] The data storage device 602 includes several processing cores 616. The processing cores 616 can include one primary processing core 618 and one or more secondary processing cores 620. In some examples, different memory circuits (not shown) can be assigned to each processing core. In some examples, some or all of the processing cores 616 can be located in the controller 604, in an ASIC (in Fig. 6 not shown) or implemented in an ASIC that includes the 604 controller.

[0066] The data storage device 602 includes one or more storage devices 622. The storage device(s) 622 can be used by various components (e.g., the HIM 612, the controller 604, the processing cores 616, etc.) of the data storage device 602 to store volatile and / or non-volatile data. In some examples, some or all of the storage device(s) 622 can be located in the controller 604, in an ASIC (in Fig. 6 not shown) or implemented in an ASIC that includes the 604 controller.

[0067] The data storage device 602 includes several registers 624 that can be accessed by various components of the data storage device 602. For example, the registers 624 may include a PMCSR 626 and / or a host capability register 628, as discussed herein. In some examples, the registers 624 may include special function registers (e.g., implemented in an ASIC) used to control (e.g., via I / O signaling 630) one or more components (e.g., PLLs 632, etc.) of the data storage device 602. In some examples, some or all of the registers 624 and / or PLLs 632 may be implemented in the controller 604, in an ASIC (in Fig. 6 not shown) or implemented in an ASIC containing the 604 controller.

[0068] The data storage device 602 includes a power management module (PM module) (e.g., a PM IC) 634, which is used, for example, to control the power states of the data storage device 602. In some examples, some or all of the functions of the power management module 634 can be implemented in the controller 604, in an ASIC (in Fig. 6 not shown) or implemented in an ASIC containing the 604 controller.

[0069] In some examples, the 634 power management module can take action in response to a change in the PMCSR's Dx bits. For instance, in response to an interrupt related to a D3hot request, the 634 power management module can perform one or more of the following actions.

[0070] In some examples, the power management module 634 can send a message or signal 636 instructing one or more of the processing cores 616 (e.g., processing cores 620) or another component to suspend all pending activities (e.g., program threads) and prepare to shut down. In doing so, one or more of the processing cores 616 (e.g., processing core 618) may remain operational (i.e., not shut down), so that at least one core is available to retrieve the data storage device 602 from a non-operational state and / or perform other critical functions.

[0071] In some examples, the power management module 634 can send a message or signal 638 that turns off or suspends one or more of the storage device(s) 622. In some examples, the power management module 634 can set a bit in one of the registers 624 that controls an I / O signal that turns off or suspends one or more of the storage device(s) 622.

[0072] In some examples, the power management module 634 can send a message or signal that turns off or suspends one or more of the PLLs 632. In some examples, the power management module 634 can set a bit in one of the registers 624 that controls an I / O signal that turns off or suspends one or more of the PLLs 632.

[0073] In some examples, the power management module 634 can send a message or signal 640 that turns off or suspends one or more of the components (e.g., a transmission chain, a PCI connection, etc.) of the PCI-PHY 608. In some examples, the power management module 634 can set a bit in one of the registers 624 that controls an I / O signal that turns off or suspends one or more components of the PCI-PHY 608.

[0074] In some examples, the power management module 634 can send a message or signal 642 that informs one or more of the components (e.g.,

[0075] The HIM 612's message processing, etc., is switched off or suspended. In some examples, the power management module 634 can set a bit in one of the registers 624 that controls an I / O signal which switches off or suspends one or more components of the HIM 612.

[0076] In some examples, the power management module 634 can send a message or signal that turns off or suspends one or more SSD components (e.g., the controller 604). In some examples, the power management module 634 can set a bit in one of the registers 624 that controls an I / O signal that turns off or suspends one or more SSD components.

[0077] The operations described above can be performed by different components in various examples. Furthermore, in some examples, one or more of these operations can be performed by one processor, and other operations by at least one other processor. In some examples, the operations described above can be performed by a single device (e.g., an ASIC, a CPU, etc.). In accordance with the teachings presented herein, other means of implementing these functions are also possible. Example SSD

[0078] Fig. Figure 7 shows an embodiment of an SSD / DSD 702 that can support the power state management described herein. The SSD / DSD 702 includes an SSD / DSD controller 704 that writes data to and reads from a storage device 706 (e.g., an NVM) and performs other related data storage operations. For brevity, the SSD / DSD 702 and the SSD / DSD controller 704 are referred to herein as SSD 702 and SSD controller 704, respectively.

[0079] The SSD controller 704 and the storage device 706 communicate with each other via appropriate interfaces. The SSD controller 704 includes an input / output (I / O) interface 708 for storage devices for sending commands to the storage device (e.g., via a command bus), for sending and receiving data from the storage device 706 (e.g., via a data bus), and for sending and receiving other signals, as applicable (e.g., a read / busy indicator (RBx) generated by the storage device 706). Likewise, the storage device 706 includes a controller interface 710 for receiving commands from the SSD controller 704 (e.g., via a command bus), for sending and receiving data from the SSD controller 704 (e.g., via a data bus), and for sending and receiving other signals, as applicable (e.g., RBx).

[0080] The storage device 706 includes an NVM core array 712 for storing data, data latches 714 for outputting stored data to the controller interface 710 and for receiving data to be stored from it, as well as for storing operational data used by the storage device 706. The storage device 706 also includes a read circuit 718 for reading data from the multi-stage NVM core array 712, a programming circuit 720 for writing data to the multi-stage NVM core array 712, and an erase circuit 722 for erasing data in the multi-stage NVM core array 712.

[0081] According to the teachings herein, the SSD controller 704 can include a power state management module 724, which can be configured to perform one or more of the operations described herein. For example, the power state management module 724 can implement a function for receiving a message or signal indicating that one or more components or operations of the SSD should be turned off or suspended. Upon receiving such a message or signal, the power state management module 724 can perform the requested action (e.g., suspend a read or write operation, turn off one or more PLLs, turn off one or more memory circuits (e.g., volatile memory), etc.). Example data storage device

[0082] Fig. Figure 8 illustrates an embodiment of a data storage device 800 configured to communicate, according to one or more aspects of the disclosure. The data storage device 800 could embody or be implemented in an SSD, a storage controller, a solid-state drive, a host device, an NVM device, a NAND chip, or any other type of device that supports data storage. In various implementations, the data storage device 800 could embody or be implemented in a computing device, a PC, a laptop, a portable device or workstation, a server, a PDA, a digital camera, a digital telephone, an entertainment device, a medical device, or any other electronic device that stores data.

[0083] The data storage device 800 includes a communication interface 802, a storage medium 804, at least one storage device (e.g., an NVM device) 808, and at least one processor 810 (e.g., at least one processor and / or other suitable circuitry). These components can be coupled to one another and / or electrically connected to one another via a signal bus or other suitable component, generally represented by the connection lines in Fig. Figure 8 illustrates this. Depending on the specific application of the at least one processor 810 and the general design constraints, the signal bus can include any number of interconnect buses and bridges. The signal bus connects various circuits such that the communication interface 802, the storage medium 804, and the storage device(s) 808 are each coupled to and / or electrically connected with the at least one processor 810. The signal bus can also connect various other circuits (not shown), such as timer sources, peripheral devices, voltage regulators, and power management circuits, which are known in the prior art and are therefore not described further.

[0084] The 802 communication interface provides a means of communication with other devices via a transmission medium. In some implementations, the 802 communication interface includes switching logic and / or programming (e.g., a program) suitable for facilitating bidirectional communication of information with respect to one or more devices in a system. In some implementations, the 802 communication interface may be configured for wired communication. For example, the 802 communication interface could be a bus interface, a transmit / receive interface, or another type of signaling interface, including drivers, buffers, or other switching logic for outputting and / or receiving signals (e.g., outputting signals from and / or receiving signals in an integrated circuit).The 802 communication interface serves as an example of a means to receive and / or transmit. In some implementations, the 802 communication interface may be configured for wireless communication. In some implementations, the communication interface includes a host interface 814 (e.g., a PCI-based interface). In some implementations, the communication interface may include at least one other 816 interface. For example, the 802 communication interface may include at least one radio frequency (RF) receiver and / or RF transmitter (e.g., together an RF transceiver).

[0085] The storage device(s) 808 can represent one or more storage devices. As indicated, the storage device(s) 808 can store energy state information as well as other information used by the data storage device 800. In some implementations, the storage device(s) 808 and the storage medium 804 are implemented as a common storage component. The storage device(s) 808 can also be used to store data that is processed by at least one processor 810 or another component of the data storage device 800.

[0086] The storage medium 804 can be one or more computer-readable, machine-readable, and / or processor-readable devices for storing programming, such as processor-executable code or instructions (e.g., software, firmware), electronic data, databases, or other digital information. The storage medium 804 can also be used to store data that is processed by the one or more processors 810 when executing programming. The storage medium 804 can be any available medium accessible to a general-purpose or special-purpose processor, including portable or fixed storage devices, optical storage devices, and various other media capable of storing, containing, or transmitting programming.

[0087] For example, and without limitation, Storage Medium 804 can include a magnetic storage device (e.g., hard disk, floppy disk, magnetic stripe), an optical disc (e.g., a compact disc (CD) or a digital versatile disc (DVD)), a chip card, a flash storage device (e.g., a card, a flash drive, or a key drive), random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), a register, a removable disk, and any other suitable medium for storing software and / or instructions that a computer can access and read. Storage Medium 804 can be embodied in a product (e.g., a computer program product). For example, a computer program product can contain a computer-readable medium in packaging materials.In light of the foregoing, the 804 storage medium may, in some implementations, be a non-transitory (e.g., physical) storage medium. For example, the 804 storage medium may be a non-transitory, computer-readable medium that stores computer-executable code, including code for performing the operations described herein.

[0088] The storage medium 804 can be coupled to the at least one processor 810 so that the at least one processor 810 can read information from and write information to the storage medium 804. That is, the storage medium 804 can be coupled to the at least one processor 810 so that at least the at least one processor 810 can access the storage medium 804, including examples where at least one storage medium is integrated into the at least one processor 810 and / or examples where at least one storage medium is separate from the at least one processor 810 (e.g., arranged in data storage device 800, arranged outside the data storage device 800, distributed over several units, etc.).

[0089] The programming stored on the storage medium 804, when executed by the at least one processor 810, causes the at least one processor 810 to perform one or more of the various functions and / or processes described herein. For example, the storage medium 804 may include operations configured to control operations on one or more hardware blocks of the at least one processor 810, as well as to use the communication interface 802 for wireless communication using its respective communication protocols.

[0090] The at least one 810 processor is generally adapted for processing, including the execution of, such programming stored on the 804 storage medium. The terms "code" or "programming" as used herein are to be interpreted in the broadest sense and include, without limitation, instructions, instruction sets, data, code, code segments, program code, programs, programming, subroutines, software modules, applications, software applications, software packages, routines, subroutines, objects, executable files, execution threads, procedures, functions, etc., regardless of whether they are described as software, firmware, middleware, microcode, hardware description language, or otherwise.

[0091] The at least one Processor 810 is configured to receive, process, and / or send data, control data access and storage, issue commands, and control other desired operations. The at least one Processor 810 may include switching logic configured to implement, in at least one example, the desired programming provided by suitable media. For example, the at least one Processor 810 may be implemented as one or more processors, one or more controllers, and / or other structures configured to execute executable programming.Examples of the at least one Processor 810 may include a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic component, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may include a microprocessor as well as any conventional processor, controller, microcontroller, or state machine. The at least one Processor 810 may also be implemented as a combination of computing components, such as a combination of a controller and a microprocessor, a number of microprocessors, one or more microprocessors in conjunction with an ASIC and a microprocessor, or in any other number of varying configurations.These examples of the at least one 810 processor serve for illustration and other suitable configurations within the scope of protection of the disclosure are considered.

[0092] According to one or more aspects of the disclosure, the at least one processor 810 can be adapted to perform some or all of the features, processes, functions, operations, and / or routines for some or all of the devices described herein. For example, the at least one processor 810 can be configured to perform each of the steps, functions, and / or processes relating to Fig. 1 to 7 and 9 to 12 are described herein. The term "adapted" may refer, in relation to the at least one Processor 810, to the at least one Processor 810 that is configured, deployed, implemented and / or programmed to perform a specific process, function, operation and / or routine according to the various characteristics described herein.

[0093] The at least one 810 processor can be a special-purpose processor, such as an application-specific integrated circuit (ASIC), which serves as a means (e.g., structure) for executing one of the functions associated with Fig. The operations described in sections 1 to 7 and 9 to 12 are used. The at least one 810 processor serves as an example of a means of sending and / or receiving. In various implementations, the at least one 810 processor can perform the operations described above for the SSD controller 108 or the SSD 104. Fig. 1 or the SSD controller 704 or the SSD 702 from Fig. 7. Provide and / or integrate at least some of the described functionality.

[0094] According to at least one example of the data storage device 800, the at least one processor 810 can include one or more of a receive and / or monitor circuit / module 820 (e.g., receiving a request, monitoring an EIB signal, etc.), a determine circuit / module 822 (e.g., determining whether a host device supports a particular power state), a set and / or clear circuit / module 824 (e.g., setting a power state, setting a register, setting a bit, clearing a bit, etc.), an enter power state circuit / module 826, a configure circuit / module 828 (e.g., configuring an activation circuit, configuring a component, etc.), and a switch on and / or off circuit / module 830 (e.g.,Switching off a processing core, memory circuit, or PLL; switching on a processing core, memory circuit, or PLL, etc.) or a circuit / module for suspending 832 (e.g., suspending a processing thread). In various implementations, the circuit / module for receiving and / or monitoring 820, the circuit / module for determining 822, the circuit / module for setting and / or erasing 824, the circuit / module for entering a power state 826, the circuit / module for configuring 828, the circuit / module for turning on and / or off 830, or the circuit / module for suspending 832 may be the above for the SSD controller 108 or the SSD 104. Fig. 1 or the SSD controller 704 or the SSD 702 from Fig. 7. Provide and / or integrate at least some of the described functionality.

[0095] As mentioned above, when executed by the at least one processor 810, the programming stored on the storage medium 804 causes the at least one processor 810 to perform one or more of the various functions and / or processes described herein. For example, the programming can cause the at least one processor 810 to perform the various functions, steps, and / or processes described herein with respect to Fig. 1 to 7 and 9 to 12 are described in different implementations. As in Fig. As shown in Figure 8, the storage medium 804 can contain one or more receive and / or monitor codes 840, determine code 842, set and / or erase code 844, enter power state code 846, configure code 848, turn on and / or off code 850 or suspend code 852.In various implementations, the receive and / or monitor code 840, the determine code 842, the set and / or erase code 844, the power-change code 846, the configure code 848, the power-on and / or power-off code 850, or the suspend code 852 can be executed or otherwise used to provide the functionality described herein for the receive and / or monitor circuit / module 820, the determine circuit / module 822, the set and / or erase circuit / module 824, the power-change circuit / module 826, the configure circuit / module 828, the power-on and / or power-off circuit / module 830, or the suspend circuit / module 832. First example process

[0096] Fig. Figure 9 illustrates a Process 900 for communicating according to some aspects of the revelation. Process 900 can be implemented in at least one processor (e.g., the Processor(s) 810 from Fig. 8) take place, which may be located in an ASIC, a controller, an SSD, an NVM device, a NAND chip, or any other suitable device. Of course, Process 900 can be implemented in various aspects within the scope of this disclosure by any suitable device capable of supporting memory-related operations.

[0097] At block 902, a data storage device can receive a request from a host device to enter a PCI-D3 power state via a PCI interface. For example, the data storage device can receive a message (such as a configuration write) that configures a PMCSR register. In some examples, the PCI-D3 power state is a PCI Express (PCIe) D3hot power state.

[0098] At block 904, the data storage device can determine that the host device does not support an L1.2 connection state. For example, the data storage device can read a host capability register to determine that the host device does not support an L1.2 connection state.

[0099] In block 906, in response to receiving the request and determining that the host device does not support the L1.2 connection state, the data storage device can set its initial power state to a non-operational power state. In some examples, the initial power state is an NVMe (Non-Volatile Memory Express) power state. In other examples, the non-operational power state is an NVMe PS5 power state.

[0100] In some examples, the at least one processor includes a power management module configured to turn off at least one processing core, memory circuit, or phase-locked loop (PLL) in response to receiving the request and determining that the host device does not support the link state L1.2.

[0101] In some aspects, a process according to the teachings set forth herein may include any combination of the aforementioned processes. Second example process

[0102] Fig. Figure 10 illustrates a Process 1000 for communicating according to some aspects of Revelation. In some examples, the processes of Process 1000 can be used in conjunction with (e.g., in addition to and / or as part of) the processes of Process 900. Fig. 9. Process 1000 can be executed in at least one processor (e.g., processor(s) 810). Fig. 8) take place, which may be located in an ASIC, an SSD, a controller, an NVM device, a NAND chip, or any other suitable data storage device. Of course, Process 1000 can be implemented in various aspects within the scope of this disclosure by any suitable data storage device capable of supporting memory-related operations.

[0103] At block 1002, a data storage device can receive a request from a host device via a PCI interface to transition to a PCI-D3 power state. In some aspects, the operations of block 1002 may differ from those of block 902. Fig. 9 correspond.

[0104] At block 1004, the data storage device can detect that the host device does not support an L1.2 connectivity state. In some aspects, the operations of block 1004 may differ from the operations of block 904. Fig. 9 correspond.

[0105] At block 1006, in response to receiving the request and determining that the host device does not support the L1.2 connection state, the data storage device can perform at least one of the following actions: enter the PCIe D3hot power state, set a PMCSR (Power Management Control and Status Register) to indicate the L1.2 connection state, or configure an activation circuit for the detection of an EIB (Electrical Idle Broken) signal. In some examples, the at least one processor includes a host interface module containing the activation circuit.

[0106] In some aspects, a process according to the teachings set forth herein may include any combination of the aforementioned processes. Third example process

[0107] Fig. Figure 11 illustrates a Process 1100 for communicating according to some aspects of Revelation. In some examples, the processes of Process 1100 can be used in conjunction with (e.g., in addition to and / or as part of) the processes of Process 900. Fig. 9. Process 1100 can be executed in at least one processor (e.g., processor(s) 810). Fig. 8) take place, which may be located in an ASIC, a controller, an SSD, or another suitable data storage device. Of course, Process 1100 can be implemented in various aspects within the scope of the disclosure by any suitable data storage device capable of supporting storage-related operations.

[0108] In optional Block 1102, a data storage device can receive a request from a host device via a PCI interface to enter a PCI-D3 power state. In some aspects, the operations of Block 1102 may differ from those of Block 902. Fig. 9 correspond.

[0109] At block 1104, the data storage device can detect that the host device does not support an L1.2 connection state. In some aspects, the operations of block 1104 may differ from the operations of block 904. Fig. 9 correspond.

[0110] At block 1106, in response to receiving the request and determining that the host device does not support the link state L1.2, the data storage device may perform at least one of the following: suspend at least one data storage thread (e.g., suspend a processing thread associated with a data operation), configure at least one component of the data storage device to transition from a first energy state to a second energy state associated with lower power consumption than the first energy state (e.g., set or clear at least one bit in at least one register that controls the at least one component), or turn off at least one processing core, memory circuit, or phase-locked loop (PLL) (e.g., set or clear at least one bit in at least one register that controls the processing core, memory circuit, or PLL).

[0111] In some aspects, a process according to the teachings set forth herein may include any combination of the aforementioned processes. Fourth example process

[0112] Fig. Figure 12 illustrates a Process 1200 for communicating according to some aspects of Revelation. In some examples, the processes of Process 1100 can be used in conjunction with (e.g., in addition to and / or as part of) the processes of Process 900. Fig. 9. Process 1200 can be executed in at least one processor (e.g., processor(s) 810). Fig. 8) take place, which may be located in an ASIC, a controller, an SSD, or another suitable data storage device. Of course, Process 1200 can be implemented in various aspects within the scope of the disclosure by any suitable data storage device capable of supporting memory-related operations.

[0113] At block 1202, a data storage device can be used in response to receiving the request (e.g., at block 902 of Fig. 9) and the finding that the host device does not support the L1.2 connection state (e.g., at block 904 of Fig. 9) monitor for an EIB (Electrical Idle Broken) signal. In some examples, a Host Interface Module (HIM) may be configured to detect an EIB signal.

[0114] At block 1204, the data storage device can set its initial energy state to an operational energy state in response to the detection of an EIB signal. For example, the data storage device can set an NVMe energy state to PS5.

[0115] At block 1206, the data storage device can switch to a PCI-D0 power state in response to the detection of the EIB signal.

[0116] In block 1208, the data storage device can be at least one component (e.g., from block 1106 of Fig. 11) configure it so that it switches from the second energy state to the first energy state in response to the detection of an EIB (Electrical Idle Broken) signal.

[0117] In block 1210, the data storage device can, in response to the detection of an EIB (Electrical Idle Broken) signal, activate at least one processing core, storage circuit, or PLL (e.g., from block 1106 of Fig. 11) switch on.

[0118] In some aspects, a process according to the teachings set forth herein may include any combination of the aforementioned processes. Other aspects

[0119] The examples set forth herein serve to illustrate certain concepts of the disclosure. The devices, apparatuses, or components illustrated above may be configured to perform one or more of the methods, features, or steps described herein. The person skilled in the art will understand that these are merely illustrative and that other examples may fall within the scope of the disclosure and the attached claims. Based on the teachings set forth herein, the person skilled in the art should appreciate that one aspect disclosed herein may be implemented independently of all other aspects and that two or more of these aspects may be combined in various ways. For example, a device may be implemented or a method practiced using any number of the aspects set forth herein.In addition, such a facility may be implemented or such a procedure may be practiced using other structures, functionality or structures and functionality in addition to one or more of the aspects set out herein or others.

[0120] Aspects of the present disclosure have been described above with reference to schematic flowcharts and / or schematic block diagrams of processes, facilities, systems, and computer program products according to embodiments of the disclosure. It is understood that each block of the schematic flowcharts and / or schematic block diagrams, and combinations of blocks in the schematic flowcharts and / or schematic block diagrams, can be implemented by computer program instructions.These computer program instructions can be provided to a processor of a computer or other programmable data processing device to create a machine such that the instructions executed through the processor or other programmable data processing device create means for implementing the functions and / or actions specified in the schematic flowcharts and / or schematic block diagrams, block or blocks.

[0121] The subject matter described herein may be implemented in hardware, software, firmware, or any combination thereof. Therefore, the terms "function," "module," and the like, as used herein, may refer to hardware, which may also include software and / or firmware components for implementing the described feature. In an exemplary implementation, the subject matter described herein may be implemented using a computer-readable medium on which computer-executable instructions are stored. When executed by a computer (e.g., a processor), these instructions control the computer to perform the functionality described herein.Examples of computer-readable media suitable for implementing the subject matter described herein include non-transitory computer-readable media such as disk storage devices, chip storage devices, programmable logic devices, and application-specific integrated circuits. Additionally, a computer-readable medium implementing the subject matter described herein may reside on a single device or computing platform, or it may be distributed across multiple devices or computing platforms.

[0122] It should also be noted that the functions specified in the block may occur in a different order in some alternative implementations than shown in the figures. For example, two blocks shown consecutively may actually be executed essentially simultaneously, or the blocks may sometimes be executed in reverse order, depending on the functionality involved. Other steps and procedures are conceivable that correspond in function, logic, or effect to one or more blocks or parts thereof in the figures shown. Although various types of arrows and lines may be used in the flowcharts and / or block diagrams, it is understood that these do not limit the scope of the corresponding embodiments. For example, an arrow may indicate a waiting or monitoring period of indefinite duration between the enumerated steps of the embodiment shown.

[0123] The various features and processes described above can be used independently or combined in various ways. All possible combinations and subcombinations are said to fall within the scope of this disclosure. Furthermore, in some implementations, certain procedure, event, state, or process blocks may be omitted. The procedures and processes described herein are also not restricted to a particular sequence, and the associated blocks or states may be executed in other suitable sequences. For example, described tasks or events may be performed in a different order than expressly disclosed, or several of them may be combined in a single block or state. The exemplary tasks or events may be executed serially, in parallel, or in any other suitable manner.Tasks or events can be added to or removed from the disclosed embodiments. The example systems and components described here can be configured differently than described. For example, elements can be added, removed, or rearranged compared to the disclosed embodiments.

[0124] Experts will recognize that information and signals can be represented using a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced in the description above can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0125] The word "exemplary / example" is used here to mean "serving as an example, instance, or illustration." Each instance described here as The aspect described as "exemplary / example" is not necessarily to be interpreted as preferential or advantageous over other aspects. Likewise, the term "aspects" does not require that all aspects include the discussed feature, advantage, or method of operation.

[0126] Although the above descriptions contain many specific embodiments of the invention, these should not be interpreted as limitations on the scope of the invention, but rather as examples of specific embodiments thereof. Accordingly, the scope of the invention should not be determined by the embodiments described, but by the appended claims and their equivalents. Furthermore, reference in this patent specification to "an embodiment," "embodiments," or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure.Therefore, the occurrences of the expressions “in one embodiment”, “in embodiments” and similar formulations in this patent specification may all refer to the same embodiment, but need not, but mean “one or more, but not all embodiments”, unless expressly stated otherwise.

[0127] The terminology used herein serves solely to describe particular aspects and is not intended to limit them. The singular forms "a," "a," and "the" used herein are also intended to include the plural forms (i.e., one or more) unless the context clearly indicates otherwise. Unless expressly stated otherwise, an enumeration of elements does not imply that some or all of the elements are mutually exclusive and / or inclusive. It is further understood that the terms "comprises," "comprehensive," "includes," "including," "exhibiting," and variations thereof, when used herein, mean "including but not limited to," unless expressly stated otherwise.This means that these terms can specify the presence of named features, integers, steps, operations, elements, or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Furthermore, it is understood that the word "or" has the same meaning as the Boolean operator "OR," that is, encompassing possibilities of "either" and "both," and is not limited to "exclusively or" ("XOR") unless explicitly stated otherwise. It is also understood that the symbol " / " between two adjacent words has the same meaning as "or" unless explicitly stated otherwise. Moreover, expressions such as "connected with," "coupled with," or "in communication with / communicating" are not limited to direct connections unless explicitly stated otherwise.

[0128] Any reference to an element herein using a designation such as "first," "second," etc., does not generally limit the set or order of such elements. Rather, these designations herein may be used as a practical method for distinguishing between two or more elements or instances of an element. A reference to first and second elements therefore does not mean that only two elements may be used therein, or that the first element must in any way precede the second element. Unless otherwise specified, a set of elements may also include one or more elements. Additionally, the terminology of the form "at least one of a, b, or c" or "a, c, c, or any combination thereof" used in the description or claims means "a or b or c, or any combination thereof."This terminology can include, for example, a, b, c, a and b, a and c, a and b and c, 2a, 2b, 2c, 2a and b, etc.

[0129] As used herein, the term "determine" encompasses a wide variety of actions. For example, "determine" can include calculating, arithmetic, processing, deducing, investigating, looking up (e.g., looking up in a table, database, or other data structure), ascertaining, and the like. Furthermore, "determine" can include receiving (e.g., receiving information), accessing (e.g., accessing data in a memory), and the like. Additionally, "determine" can include solving, selecting, choosing, creating, and the like.

Claims

[1] Data storage device (104), comprising: a non-volatile memory array (112); a PCI (Peripheral Component Interconnect) interface (106); and at least one processor coupled and configured with the non-volatile memory array (112) and the PCI interface (106) to: to receive a request (116) from a host device (102) via the PCI interface (106) to switch to a PCI-D3 power state; to determine that the host device (102) does not support an L1.2 connectivity state; and to set a first energy state of the data storage device (104) to a non-operational energy state in response to receiving the request (116) and the finding that the host device does not support the link state L1.2, wherein the first energy state is a Non-Volatile Memory Express (NVMe) energy state and the non-operational energy state is an NVMe PS3, PS4 or PS5 energy state. [2] Data storage device according to claim 1, wherein the PCI-D3 energy state is an energy state of PCI Express (PCIe) D3hot. [3] Data storage device according to claim 2, wherein the at least one processor is further configured to: to switch to the PCIe-D3hot power state in response to receiving the request (116) and determining that the host device (102) does not support the L1.2 link state. [4] Data storage device according to claim 1, wherein the at least one processor is further configured to: to set up a PMCSR (Power Management Control and Status Register) to indicate the L1.2 link state in response to receiving the request (116) and determining that the host device (102) does not support the L1.2 link state. [5] Data storage device according to claim 1, wherein the at least one processor is further configured to: to configure an activation circuit to detect the EIB (Electrical Idle Broken) signal in response to receiving the request (116) and the finding that the host device (104) does not support the L1.2 connection state. [6] Data storage device according to claim 5, wherein the at least one processor is further configured to: to establish the first energy state of the data storage device (104) as an operational energy state in response to the detection of an EIB signal. [7] Data storage device according to claim 1, wherein the at least one processor is further configured to: to configure at least one component of the data storage device (104) to switch from a first energy state to a second energy state, which is associated with lower power consumption than the first energy state, in response to receiving the request (116) and determining that the host device (102) does not support the connection state L1.

2. [8] Data storage device according to claim 7, wherein the at least one processor is further configured to: to configure at least one component so that it switches from the second to the first energy state in response to the detection of an EIB (Electrical Idle Broken) signal. [9] Data storage device according to claim 1, wherein the at least one processor is further configured to: in response to receiving the request (116) and determining that the host device (102) does not support the link state L1.2, at least one processing core, one memory circuit or to switch off a phase control loop (PLL). [10] Data storage device according to claim 9, wherein, to turn off the processing core, the memory circuit or the PLL, the at least one processor is further configured to: to set or clear at least one bit in at least one register that controls at least one of the processing core, memory circuitry or PLL. [11] Data storage device according to claim 9, wherein the at least one processor is further configured to: to switch on at least one processor core, the memory circuit or the phase-locked loop (PLL) in response to the detection of an EIB (Electrical Idle Broken) signal. [12] Method for controlling at least one energy state of a data storage device (104), comprising: Receiving (902) a request (116) from a host device (102) to enter a PCI-D3 (Peripheral Component Interconnect) power state; Determine (904) that the host device (102) does not support an L1.2 connectivity state; and Setting (906) a first energy state of the data storage device (104) as a non-operational energy state in response to receiving the request (116) and determining that the host device (102) does not support the link state L1.2, wherein the first energy state is a Non-Volatile Memory Express (NVMe) energy state and the non-operational energy state is an NVMe PS3, PS4 or PS5 energy state. [13] The method of claim 12, further comprising: Monitoring for an EIB (Electrical Idle Broken) signal in response to receiving the request (116) and determining that the host device (102) does not support the L1.2 connection state. [14] The method of claim 13, further comprising: Setting the first energy state of the data storage device (104) as an operational energy state in response to the detection of an EIB signal. [15] The method of claim 13, further comprising: Switching to a PCI-D0 power state in response to the detection of the EIB signal. [16] The method of claim 12, further comprising: Suspending at least one data store thread in response to receiving the request (116) and determining that the host device (102) does not support the link state L1.

2. [17] Data storage device (104), comprising: Means of receiving a request (116) from a host device (102) to switch to a PCI-D3 (Peripheral Component Interconnect) power state; Means to determine that the host device (102) does not support an L1.2 connectivity state; and Means of setting a first energy state of the data storage device (104) as a non-operational energy state in response to receiving the request (116) and determining that the host device (102) does not support the link state L1.2, wherein the first energy state is a Non-Volatile Memory Express (NVMe) energy state and the non-operational energy state is an NVMe PS3, PS4 or PS5 energy state.

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