Semiconductor through-hole plating as a well-tap structure

Abstract

Techniques are provided for forming one or more well-tap semiconductor through-hole structures (TSV structures) between conductive back-side and front-side layers. The well-tap / TSV structures can be formed during the same fabrication process used to form other TSVs and can be located in the same general area of ​​the device layer. The well-tap / TSV structures can be nanoscale structures that extend partially or completely through the device layer. One or more initial wells through the device layer feature TSVs for routing power or ground between the conductive back-side layer below the device layer and a conductive front-side layer above the device layer without contacting the device layer.One or more secondary recesses through the device layer feature power tap / TSV structures that can provide routing from the front to the back and also conductively couple a semiconductor material of the device layer to power and / or ground terminals or rails on the back.

Description

BACKGROUND

[0001] As the size of integrated circuits continues to decrease, a number of challenges arise. With increasing device density, the available space on a given die diminishes rapidly. Some structures require a certain amount of space to operate effectively, but the limited available footprint on a die makes arranging these structures challenging. Consequently, a number of non-trivial challenges remain regarding the fabrication of certain structures within an integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a cross-sectional view illustrating an exemplary section of an integrated circuit configured with an interconnection area over a plurality of semiconductor devices and a well-tap connected to a backside interconnect, according to some embodiments of the present disclosure. Fig. Figure 2 is a cross-sectional view of various semiconductor through-hole vias (TSVs) and well-taps coupled with a backside interconnect, according to some embodiments of the present disclosure. Fig. Figures 3A - 3L illustrate cross-sectional views of a process for forming both TSVs and well-taps through an area of ​​a semiconductor device layer according to some embodiments of the present disclosure. Fig. Figure 4 illustrates a cross-sectional view of a chip package containing one or more semiconductor die(s) according to some embodiments of the present disclosure. Fig. Figure 5 is a flowchart of a method for forming both TSVs and well-taps through a region of a semiconductor device layer according to some embodiments of the present disclosure. Fig. Figure 6 illustrates a computing system comprising one or more integrated circuit(s), as described herein in various ways, according to some embodiments of the present disclosure.

[0002] Although the following detailed description continues with reference to illustrated embodiments, many alternatives, modifications, and variations thereof become apparent in light of the present disclosure. Furthermore, it is understood that the figures are not necessarily drawn to scale, nor is the present disclosure intended to limit it to the specific configurations shown. For example, although some figures generally indicate perfectly straight lines, right angles, and smooth surfaces, an actual implementation of an integrated circuit structure may not have perfectly straight lines and right angles (e.g., some features may have tapered side walls and / or rounded corners), and some features may have a surface topology or otherwise be uneven due to real limitations of the machining equipment and techniques used. DETAILED DESCRIPTION

[0003] Techniques for forming one or more well-tap semiconductor through-hole plating (TSV) structures between a conductive backside layer and a conductive frontside layer are provided here. The combined well-tap / TSV structures can be formed during the same fabrication process used to create other pure TSV structures and can be located in the same general area of ​​the device layer. For example, the combined well-tap / TSV structures can be nanoscale structures extending through the entire device layer of a die (e.g., height of less than 1000 nm or less than 500 nm), although microscale configurations can also utilize the techniques. In one example, a plurality of wells are formed through the entire thickness of a given region of a semiconductor device layer.The semiconductor device layer can host any number of transistors in another region of the device layer. One or more first wells have a dielectric lining along all sidewalls of the first wells and a conductive infill on the dielectric lining to provide one or more pure TSV structure(s). One or more second wells have a conductive layer (e.g., silicide) on the sidewalls of the second wells and a conductive infill on the conductive layer to provide one or more combination well-tap / TSV structure(s). The top surfaces of the conductive infill in both the first and second wells can be coupled to any number of conductive front-side layers as part of a front-side interconnect network.The substrate (or a portion thereof) can be removed from the backside, and the exposed lower surfaces of the conductive infill in both the first and second wells can be coupled to any number of conductive backside layers as part of a backside interconnect network. The first well(s) may contain pure TSV structures, for example, for routing signals, power, or ground between the conductive backside layer below the device layer and a conductive frontside layer above the device layer, without contacting the device layer.The one or more second recess(s) feature combined power tap / TSV structures that can also provide routing of power and / or ground, but can also conductively couple the given area of ​​the device layer to the backside power or ground connection. The term TSV is commonly used to refer to silicon vias, but in the present disclosure it is used more broadly to include a via that passes through any semiconductor material, not just silicon. Numerous configurations and variations become apparent in light of this disclosure. General overview

[0004] As previously noted, effectively utilizing the space on a given die can be challenging. Numerous structures beyond the active devices (e.g., transistors) must also be placed on the die, including interconnects and well-tap structures. Well-tap structures are used to connect n-doped or p-doped sections of the semiconductor device layer to a power or ground rail to prevent voltage drift and latch-up problems. Multiple TSV structures and separate well-tap structures may be necessary on a given die, thus reducing the footprint available for the active devices.

[0005] Techniques for forming nanoscale TSV structures, also known as well-tap structures, are described here. The TSV structures feature a conductive core material extending through the entire thickness of a semiconductor device layer and between a conductive backside layer and a conductive topside layer. According to some embodiments, the sidewalls of one or more of the TSV structures penetrating the device layer have a conductive material layer instead of a dielectric lining. The conductive material layer can, for example, comprise a silicide or other low-resistance contact material to conductively couple the conductive core of the TSV to the semiconductor device layer. In some examples, the combined TSV / well-tap structure is coupled to an n-doped or p-doped region of the device layer.

[0006] According to one embodiment, an integrated circuit comprises a plurality of semiconductor devices in a first region of a device layer, a dielectric layer below the device layer, and a conductive via in a second region of the device layer, which extends through at least a section of the device layer's thickness and through the entire thickness of the dielectric layer. Furthermore, a conductive layer is located below the dielectric layer, and this layer contacts a section of the conductive via. A conductive material layer is located between a sidewall of the device layer and the conductive via. The conductive material layer directly contacts the conductive via and also directly contacts a semiconductor material in the second region of the device layer.

[0007] According to another embodiment, an electronic device comprises a chip package containing one or more dies. At least one of the dies has a device layer comprising a plurality of semiconductor devices in a first region of the device layer, a dielectric layer below the device layer, and a conductive via in a second region of the device layer, which extends through at least a section of the device layer's thickness and through the entire thickness of the dielectric layer. Furthermore, a conductive layer is located below the dielectric layer, and this layer contacts a section of the conductive via. A conductive material layer is located between a sidewall of the device layer and the conductive via.The conductive material layer directly contacts the conductive via and directly contacts a semiconductor material in the second area of ​​the device layer.

[0008] According to another embodiment, an integrated circuit comprises a semiconductor region including one or more semiconductor layers, a dielectric layer beneath the semiconductor region, a conductive via extending through the entire thickness of the semiconductor region and the entire thickness of the dielectric layer, a conductive layer beneath the dielectric layer contacting a portion of the conductive via, and a conductive material layer between a sidewall of the semiconductor region and the conductive via. The conductive material layer directly contacts the conductive via and directly contacts the semiconductor region.

[0009] According to another embodiment, a method for forming an integrated circuit comprises: forming a well through a semiconductor region above a semiconductor substrate; forming a dielectric lining on exposed surfaces within the well; forming a sacrificial filling at a lower section of the well; removing an exposed section of the dielectric lining above the sacrificial filling; removing the sacrificial filling; forming a conductive material layer on exposed surfaces of the semiconductor region within the well; forming a conductive filling within the well and on the conductive material layer; removing at least a section of the semiconductor substrate; forming a dielectric layer below the semiconductor region and forming a conductive layer below the dielectric layer, wherein the conductive layer contacts at least a section of the conductive filling.

[0010] These techniques can be used with any type of planar and non-planar transistor, including FinFETs (sometimes called dual-gate or tri-gate transistors), nanowire and nanoband transistors (sometimes called gate-all-around transistors), and thin-film transistors, to name a few. The source and drain regions can be, for example, epitaxial regions deposited during an etch-and-replacement process to form the source / drain, or doped regions of a given substrate. The type of dopant in the source and drain regions depends on the polarity of the corresponding transistor. The gate structure can be implemented using a gate-first process or a gate-last process (sometimes called a removal metal gate or RMG process).Any number of semiconductor materials can be used in forming the transistors, which are supplied with power via a rear-side power rail, such as group IV materials (e.g. silicon, germanium, silicon germanium) or group III-V materials (e.g. gallium arsenide, indium gallium arsenide).

[0011] The use of the techniques and structures provided here may be detectable using tools such as electron microscopy, including scanning / transmission electron microscopy (SEM / TEM), scanning transmission electron microscopy (STEM), nanobeam electron diffraction (NBD or NBED), and reflection electron microscopy (SEM); composition mapping, X-ray crystallography or diffraction (XRD); energy-dispersive X-ray spectroscopy (EDX); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atom probe imaging or tomography; local electrode atom probe techniques (LEAP techniques); 3D tomography; or high-resolution physical or chemical analysis, to name a few suitable example analytical tools.For example, in some exemplary embodiments, such tools may specify the presence of TSVs extending through the device layer and having a conductive material on their sidewalls that electrically couples the conductive core of the TSVs to the semiconductor material of the device layer. In some examples, such tools may specify that the conductive material is a silicide (e.g., including titanium and silicon). Other examples may show a germanide (e.g., including titanium and germanium) or a III-V ide (e.g., including titanium and gallium arsenide or tungsten on indium gallium nitride or indium aluminum nitride).

[0012] It should be clear that the meanings of "above" and "over" in this disclosure should be interpreted as broadly as possible, so that "above" and "over" do not only mean "directly on" something, but also encompass the meaning of "over" something with an intervening feature or layer. Furthermore, spatial terms such as "below," "under," "lower," "over," "upper," and the like may be used here to simplify the description and to describe a relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatial terms are to be understood as encompassing various orientations of the device in use or operation in addition to the orientation shown in the figures.The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatial descriptors used here may also be interpreted accordingly.

[0013] As used here, the term "layer" refers to a section of material that has a region of thickness. A monolayer is a layer consisting of a single layer of atoms of a given material. A layer may extend over the entirety of an underlying or overlying structure, or it may have a lesser extent than the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or inhomogeneous continuous structure, where the layer has a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between or on top of an upper surface and a lower surface of the continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface.A layer can conform to a given surface (whether flat or curved) with a relatively uniform thickness across the entire layer.

[0014] Materials that are “different in composition” or “different in composition,” as used here, refer to two materials that have different chemical compositions. This difference in composition might consist, for example, of an element being present in one material but not the other (e.g., SiGe differs in composition from silicon), or of one material containing all the same elements as another, but at least one of these elements being intentionally provided in a different concentration relative to the other material (e.g., SiGe with 70 atomic percent germanium differs in composition from SiGe with 25 atomic percent germanium). In addition to such a difference in chemical composition, the materials might also contain different dopants (e.g.,Gallium and magnesium) or the same dopants, but in different concentrations. In further embodiments, different materials in composition can also refer to two materials that have different crystallographic orientations. For example, (110) silicon is different in composition from (100) silicon. Creating a stack with different orientations could be achieved, for example, by transferring an unstructured wafer layer. If two materials are elementally different, then one of the materials has an element that is not present in the other material. architecture

[0015] Fig. Figure 1 is a cross-sectional view illustrating an exemplary section of an integrated circuit having an interconnection region above a plurality of semiconductor devices, according to an embodiment of the present disclosure. The semiconductor devices in this example are non-planar metal-oxide-semiconductor transistors (MOS transistors), such as tri-gate or gate-all-around (GAA) transistors, although other transistor topologies and types can also be used in conjunction with the techniques provided herein (e.g., planar transistors, fork-sheet transistors, thin-film transistors, or any other transistors).

[0016] According to some embodiments, the integrated circuit has a device area 101 (sometimes referred to as a device layer) and an interconnection area 103 above the device area 101. The device area 101 may have a plurality of semiconductor devices 104 together with one or more other layers or structures associated with the semiconductor devices 104. For example, the device area 101 may also have one or more dielectric layer(s) 106 surrounding active sections or contacts of the semiconductor devices 104. The device area 101 may also have one or more conductive contact(s) 108 providing electrical contact to transistor elements, such as gate structures, drain regions, or source regions.The conductive contacts 108, for example, feature tungsten, although other metal or metal alloy materials can also be used. Conductive contacts can also be part of something sometimes referred to as a local interconnect, which can be considered part of the device area and is usually formed prior to any backend processing, or otherwise feature something of the sort. In some examples, the device area 101 features a semiconductor device layer from which the semiconductor channels of the transistors are formed.

[0017] As further in Fig. As shown in Figure 1, the device area 101 is located above a backside interconnection area 105. In one example, backside processing can be used to remove the substrate from below the device area 101 and form any number of backside interconnection layers that constitute the interconnection area 105. According to some embodiments, a conductive backside layer 107 can be provided to carry power rail signals or a ground signal (e.g., VDD, VSS, or GND). Any number of backside interconnection layers, including dielectric material with structured conductor tracks and vias, can be formed.

[0018] The interconnection region 103 has a plurality of interconnection layers 110a–110e stacked on top of each other. Each interconnection layer can have a dielectric material 112 together with one or more different conductive feature(s). The dielectric material 112 can be any dielectric, such as silicon oxide, silicon oxycarbide, silicon nitride, or silicon oxynitride. The dielectric material 112 can be deposited using any known dielectric deposition technique, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), flowable CVD, spin-deposition of dielectric, or atomic layer deposition (ALD).The one or more conductive feature(s) may include conductor tracks 114 and conductive vias 116 arranged in any structure across the interconnection layers 110a–110e to carry signal and / or power voltages to / from the various semiconductor devices 104. A conductive via, such as the conductive via 116, may extend through an interconnection layer to connect conductor tracks on an upper interconnection layer to a lower interconnection layer. In other cases, a via 116 may extend only partially through a given interconnection layer. Although the interconnection area 103 is illustrated with only five interconnection layers, any number of interconnection layers may be used within the interconnection area 103.Furthermore, this example shows vias and traces in different interconnection layers, in both single and dual Damascene configurations. In other examples, vias and traces may also be present within the same interconnection layer, as in the case of some dual Damascene configurations.

[0019] Any of the conductor tracks 114 and conductive vias 116 can have any number of conductive materials, some examples being copper, ruthenium, tungsten, cobalt, molybdenum, and alloys thereof. In some cases, any of the conductor tracks 114 and conductive vias 116 can have a relatively thin lining or barrier, such as titanium nitride or tantalum nitride.

[0020] It should be noted that the various conductive vias 116 and conductive contacts 108 are each shown with tapered profiles to indicate a more natural appearance resulting from the etching process used to form the openings. Depending on the etching parameters used and the thickness (depth) of the etched dielectric layer, any degree of tapering can be observed. Furthermore, conductive vias can be stacked on top of each other through different dielectric layers of the interconnection region 103. In some examples, however, a single via recess can be formed through more than one dielectric layer, resulting in a taller, more tapered conductive via that extends through two or more dielectric layers.

[0021] The various interlinking layers of the interlinking region 103 may not all have the same thickness. According to some embodiments, the thickness of the interlinking layers increases upwards towards the top of the interlinking region 103. Therefore, the uppermost interlinking layer may have the greatest thickness, while the lowermost interlinking layer may have the smallest thickness. In some examples, the uppermost interlinking layer may have a thickness in the range of several micrometers (e.g., 1–4 µm), while the lowermost interlinking layer may have a thickness of less than 50 nm.

[0022] According to some embodiments, the semiconductor devices 104 are formed within a first section of the device area 101, and a second section 118 of the device area 101 comprises at least one TSV structure 120. As shown in this example, the TSV structure 120 extends through the entire thickness of the device area 101 between a conductive front layer 121 and a conductive back layer 107. Accordingly, the TSV structure 120 provides a conductive connection between the conductive front layer 121 and the conductive back layer 107. Additionally, the TSV structure 120 is electrically coupled to the semiconductor material of the device area 101.For example, a conductive material layer 122 is provided on or otherwise between the semiconductor material sidewalls of the device area 101 and the sidewalls of the TSV structure 120 to support an ohmic contact between the TSV structure 120 and the semiconductor material of the device area 101. The semiconductor material within the second section 118 of the device area 101 may, for example, be n-doped, p-doped, or undoped. Accordingly, the TSV structure 120 also acts as a well-tap to connect the doped or undoped semiconductor material of the device area 101 to power or ground provided by the conductive backside layer 107 (or by the conductive frontside layer 121).

[0023] The TSV structure 120 can be any suitable conductive material, such as tungsten, ruthenium, molybdenum, or cobalt. The conductive material layer 122 can be, for example, silicide, germanide, or any other suitable conductive material to improve the ohmic contact between the semiconductor material of the device layer and a metal or metal alloy.

[0024] Fig. Figure 2 illustrates a cross-sectional view through a region of a device layer 202, which has any number of TSV / Tap structures 204 and any number of TSV structures 206 (without conductive contact to the device layer 202), according to some embodiments. Each of the TSV / Tap structures 204 and TSV structures 206 extends through a thickness of the device layer 202, which in some examples may comprise one or more arbitrarily suitable semiconductor material(s), such as silicon, SiGe, germanium, or any III-V-based materials. In this example, the device layer 202 can have a total thickness of less than 1000 nm or less than 500 nm, such as between 50 nm and 300 nm. Other regions of the device layer 202 can host any number of semiconductor devices, such as planer transistors, thin-film transistors (TFTs), tri-gate transistors, gate-all-around transistors, or forksheet transistors.

[0025] The TSV / Tap structures 204 and the TSV structures 206 both have a conductive core that can extend through the entire thickness of at least the device layer 202. In some embodiments, the conductive core of the TSV / Tap structures 204 and TSV structures 206 also extends through a front-side dielectric layer 208 above the device layer 202 and a back-side dielectric layer 210 below the device layer 202. Each of the front-side dielectric layer 208 and the back-side dielectric layer 210 can be any suitable dielectric material. In some examples, the front-side dielectric layer 208 and the back-side dielectric layer 210 comprise silicon dioxide, silicon nitride, or silicon oxynitride.

[0026] According to some embodiments, the conductive core of the TSV / Tap structures 204 is conductively coupled to the device layer 202 by a conductive material layer 212 formed on the sidewalls of the device layer 202 and / or TSV / Tap structures 204. The conductive material layer 212 can be, for example, silicide (for a silicon-based device layer 202), germanide (for a germanium-based device layer 202), a III-V ide (for a III-V semiconductor-based device layer 202), or any other suitable conductive material to improve the ohmic contact between the device layer 202 and the TSV / Tap structures 204. The conductive material layer 212 can, for example, have a lateral thickness of less than 5 nm, such as between 1 nm and 3 nm.In contrast, the TSV structures 206 are electrically insulated from the device layer 202 by means of a dielectric lining 214 on the side walls of the TSV structures 206. The dielectric lining 214 can be any suitable dielectric material, such as silicon nitride. In some examples, the dielectric lining 214 has a different dielectric material compared to at least the front-side dielectric layer 208 in order to provide a degree of etch selectivity between the dielectric lining 214 and the front-side dielectric layer 208.

[0027] In some embodiments, a conductive backside layer 216 is provided below the backside dielectric layer 210. The conductive backside layer 216 contacts the lower surfaces of any number of TSV / Tap structures 204 and TSV structures 206. In some examples, the conductive backside layer 216 provides a power rail (e.g., VDD) or a ground rail (e.g., VSS) for the circuit. In the illustrated example, the TSV / Tap structures 204 provide conductive paths between the conductive backside layer 216 and any number of conductive frontside layers 218, which are provided above the frontside dielectric layer 208. Likewise, the TSV structures 206 provide conductive paths between the conductive backside layer 216 and any number of conductive frontside layers 220 provided above the frontside dielectric layer 208.The TSV / Tap structures 204 additionally provide a conductive path between the conductive backside layer 216 and the device layer 202, and between the conductive frontside layers 218 and the device layer 202 according to some embodiments. It is understood that the illustrated arrangement of the conductive topside layers 218 / 220, TSV / Tap structures 204, and TSV structures 206 is only an exemplary arrangement and that any arrangement of such elements along the device layer 202 can be used. In some embodiments, the TSV / Tap structures 204 extend upwards from the conductive backside layer 216 through only a portion of the total height of the device layer 202.In such examples, the TSV / Tap structures 204 act as tap structures to conductively connect the device layer 202 to the conductive backside layer 216, but they are not connected to conductive frontside layers. The conductive frontside layers 218 / 220 and the conductive backside layer 216 can comprise any suitable conductive material, such as those previously described above (e.g., copper, tungsten, ruthenium, molybdenum, or cobalt). Manufacturing methodology

[0028] Fig. Figures 3A-3L are cross-sectional views that together illustrate an exemplary process for forming a section of an integrated circuit according to an embodiment of the present disclosure. Each figure shows an exemplary structure resulting from the process flow up to that point, such that the depicted structure evolves as the process flow continues, as shown in the Fig. The structure shown in 3L ends, which is in Fig. The structure is similar to the one illustrated in Figure 2. Such a structure can be part of a larger integrated circuit (such as a processor or a memory chip) that includes, for example, digital logic cells and / or memory cells and an analog mixed-signal circuit arrangement. Therefore, the illustrated integrated circuit structure can be part of a larger integrated circuit that includes other, not shown, integrated circuit arrangements. Exemplary materials and process parameters are given; however, it is understood that the present disclosure is not intended to be limited to any specific such materials or parameters.

[0029] Fig. Figure 3A is a cross-sectional view taken through a section of substrate 302. Substrate 302 can be, for example, a bulk substrate containing a group IV semiconductor material (such as silicon, germanium, or silicon germanium), a group III-V semiconductor material (such as gallium arsenide, indium gallium arsenide, or indium phosphide), and / or any other suitable material on which transistors can be formed. Alternatively, the substrate can be a semiconductor-on-insulator substrate containing a desired semiconductor layer over a buried insulator layer (e.g., silicon over silicon dioxide). Alternatively, the substrate can be a multilayer substrate or superlattice suitable for forming nanowires or nanoribbons (e.g., alternating layers of silicon and SiGe or alternating layers of indium gallium arsenide and indium phosphide). Any number of substrates can be used.

[0030] According to some embodiments, a device layer 304 is provided above the substrate 302. The illustrated portion of the device layer 304 can be located away from the semiconductor devices and can comprise any one or more suitable semiconductor materials. In one example, the device layer 304 comprises a single layer of silicon, germanium, or silicon germanium, suitable for forming FinFET devices. In some examples, the device layer 304 comprises alternating layers of silicon and silicon germanium, suitable for fabricating gate-all-around transistors (GAA transistors). In still other examples, the device layer 304 comprises one or more layers of III-V semiconductor materials (e.g., gallium arsenide or indium gallium arsenide), suitable for fabricating amplifiers, filters, and power transistors.Although the dimensions can vary from one example to the next, in one example the device layer 304 has a total thickness of less than 500 nm, such as between 30 nm and 150 nm. In some embodiments, the device layer 304 has the same semiconductor material as the substrate 302.

[0031] According to some embodiments, a front-side dielectric layer 306 is provided on an upper surface of the device layer 304. The front-side dielectric layer 306 can comprise any suitable dielectric material, such as silicon dioxide, silicon nitride, silicon carbide, or silicon oxynitride.

[0032] According to some embodiments, any number and arrangement of depressions 308 is etched through an entire thickness of the front-side dielectric layer 306 and through an entire thickness of the device layer 304. A reactive ion etching (RIE) process can be used together with suitable lithography techniques to pattern and etch the depressions 308 using the front-side dielectric layer 306 as a hard mask material. According to some embodiments, the depressions 308 can be trenches extending in and out of the side or can have a circular or square basic cross-sectional shape. According to some embodiments, the depressions 308 extend into at least one section of the substrate 302. Fig. 3A is the boundary between the substrate 302 and the device layer 304 indicated by a dashed line, wherein the recesses 308 extend into the substrate 302 below the dashed line.

[0033] Fig. 3B is a cross-sectional view of the in Fig. The structure shown in Figure 3A is formed after the formation of a dielectric lining 310 over the structure according to some embodiments. The dielectric lining 310 can be any suitable dielectric material, such as silicon dioxide, silicon nitride, or silicon oxynitride. In some examples, the dielectric lining 310 has a different material composition compared to the front-side dielectric layer 306. The dielectric lining 310 can be conformally deposited along all surfaces of the recesses 308 using CVD or ALD, to name a few examples. The dielectric lining 310 can have a thickness between, for example, about 3 nm and about 10 nm.

[0034] Fig. 3C is a cross-sectional view of the in Fig. The structure shown in Figure 3B is after the formation of the sacrificial filling 312 and the mask structure 314 according to some embodiments. The sacrificial filling 312 can be any suitable material that can be easily removed at a later time without damaging surrounding structures. In one example, the sacrificial filling 312 has a hard carbon mask (CHM). Other suitable materials include titanium nitride or aluminum oxide. According to some embodiments, the sacrificial filling 312 is first deposited within all the recesses 308 and then deepened to a final height at the bottom of the recesses 308 using a suitable isotropic etching process.The sacrificial filling 312 can be recessed to a final height such that its upper surface is located near the boundary between the device layer 304 and the substrate 302 (as indicated by a dashed line), such as within 10 nm, within 5 nm or within 2 nm of the boundary.

[0035] After the formation of the sacrificial filling 312, the mask structure 314 can be deposited over the structure and lithographically patterned to be removed from some wells while remaining in others. According to some embodiments, wells still containing the mask structure 314 are ultimately pure TSV structures, and wells free of the mask structure 314 are ultimately combination TSV / Tap structures. The mask structure 314 can be a photoresist or a suitable hard mask structure that can be safely patterned without damaging the dielectric lining 310. In some examples, the mask structure 314 and the sacrificial filling 312 are the same material (e.g., CHM), which is lithographically patterned and selectively removed to form the structure in Fig. to provide 3C.

[0036] Fig. 3D is a cross-sectional view of the Fig. The structure shown in Figure 3C is visible after the removal of exposed sections of the dielectric lining 310 according to some embodiments. Any sections of the dielectric lining 310 not protected by the mask structures 312 and 314 can be removed using a suitable isotropic etching process.

[0037] Fig. 3E is a cross-sectional view of the in Fig. The 3D structure is shown after the removal of the sacrificial filler 312 and the mask structure 314. Any suitable isotropic etching process can be used to remove the sacrificial filler 312 and the mask structure 314. In some examples, the sacrificial filler 312 and the mask structure 314 are removed during the same isotropic etching process as during the same ashing process.

[0038] Fig. 3F is a cross-sectional view of the in Fig. The structure shown in Figure 3E is determined after the formation of a conductive material layer 316 on the well sidewalls, where the semiconductor material of the device layer 304 is exposed. The conductive material layer 316 can, for example, comprise silicide (metal + silicon) to provide improved ohmic contact with exposed silicon regions of the device layer 304. In another example, the conductive material layer 316 can comprise germanicide (metal + germanium) to provide improved ohmic contact with exposed germanium regions of the device layer 304. In yet another example, the conductive material layer 316 can comprise III-V-ide (metal + III-V material, such as gallium arsenide, indium phosphide, or indium gallium arsenide) to provide improved ohmic contact with exposed III-V material regions of the device layer 304.The metal can be, for example, titanium, nickel, tungsten, gold, aluminum, or an alloy thereof. The conductive material layer 316 can be formed in various ways. In one example, a layer of titanium is deposited over the entire structure and then annealed in a nitrogen-rich environment. In areas where the titanium is deposited on silicon (e.g., on the device layer 304), titanium disilicide (TiSi₂) is formed, while titanium nitride is formed everywhere else. The excess titanium nitride can then be selectively removed using a suitable isotropic etching process, leaving only the titanium disilicide. In another example, silicide can be grown epitaxially on the exposed silicon surfaces along the sidewalls of the recesses 308.The growth process is selective in that, according to some embodiments, silicide growth occurs only on the exposed silicon surfaces, thus forming the silicide only in these areas. A similar selective growth of germanide or III-V-ide can be used with other semiconductor materials. In any such case, the conductive material layer 316 does not form within the depressions 308, which still retain the dielectric lining 310 along the entire sidewall height. Any number of deposition processes, such as CVD and ALD, can be used to provide a conductive material layer 316, along with thermal annealing to initiate the reaction between the contact metal and the semiconductor materials. The conductive material layer 316 can be formed to a lateral thickness of, for example, less than 5 nm, such as between 1 nm and 3 nm. Other examples may have different thicknesses.

[0039] Fig. 3G is a cross-sectional view of the in Fig. The structure shown in Figure 3F is obtained after the formation of a conductive filling 318, which substantially fills each of the wells 308, according to some embodiments. The conductive filling 318 can be any suitable conductive material, such as copper, tungsten, molybdenum, cobalt, or ruthenium. In some examples, a conductive lining is first conformally deposited (e.g., via CVD or ALD), followed by a conductive filling to substantially fill the wells 308. The conductive filling 318 can be deposited using any of the following processes: electroplating, electroless plating, CVD, ALD, or PECVD, to name a few.

[0040] Fig. 3H is a cross-sectional view of the in Fig. The structure shown in Figure 3G is shown after a polishing process for removing excess conductive filler 318 from above the front-side dielectric layer 306, according to some embodiments. Chemical-mechanical polishing (CMP) can be used to remove the excess conductive filler 318 and also any portions of the dielectric lining 310 above the front-side dielectric layer 306. According to some embodiments, the polishing process results in TSV / Tap structures 320 having a conductive material layer 316 on their sidewalls between the conductive filler material and the device layer 304, and TSV structures 322 having a dielectric lining 310 on their sidewalls between the conductive filler material and the device layer 304.The polishing process results in the upper surfaces of the TSV / Tap structures 320 and the TSV structures 322 being essentially coplanar with an upper surface of the front-side dielectric layer 306.

[0041] Fig. 3I is a cross-sectional view of the in Fig. The structure shown in Figure 3H is formed after the formation of any number of conductive front face layers 324 and 325 according to some embodiments. The conductive front face layers 324 / 325 can be formed by one or more dielectric layers to contact the upper surfaces of any number of TSV / Tap structures 320 or TSV structures 322. In the illustrated example, the conductive front face layers 324 contact the upper surfaces of the TSV / Tap structures 320, and the conductive front face layer 325 contacts the upper surfaces of the TSV structures 322. The conductive front face layers 324 / 325 can be part of a front face interconnect network comprising any number of interconnect layers for routing signals and power across the circuit.The conductive front face layers 324 / 325 can comprise any suitable conductive material, such as copper, tungsten, molybdenum, cobalt or ruthenium.

[0042] Fig. 3J is a cross-sectional view of the in Fig. The structure shown in Figure 3I is obtained after the removal of a back-side portion of the substrate 302 according to some embodiments. The back side of the substrate 302 can be removed using any number or combination of techniques, such as dry etching, wet etching, polishing, or grinding. In some examples, the back side of the substrate 302 is polished or ground down until the lower surface of the conductive filler 318 (or the dielectric lining 310) is exposed. Further deepening of the substrate 302 (which may expose a lower surface of the device layer 304) can then be carried out using any suitable etching process, such that the lower ends of the TSV / Tap structures 320 and the TSV structures 322 protrude from the lower surface of the device layer 304.

[0043] Fig. 3K is a cross-sectional view of the in Fig. The structure shown in Figure 3J is formed after the formation of a backside dielectric layer 326 according to some embodiments. The backside dielectric layer 326 can be formed on the lower surface of the device layer 304 and around the ends of the TSV / Tap structures 320 and the TSV structures 322. The backside dielectric layer 326 can be any suitable dielectric material, such as silicon dioxide, silicon nitride, or silicon oxynitride. According to some embodiments, the lower surface of the backside dielectric layer 326 can be polished until it is substantially coplanar with the lower surface of the conductive filling 318 within the TSV / Tap structures 320 and the TSV structures 322.

[0044] Fig. 3L is a cross-sectional view of the in Fig. The structure shown in Figure 3K is formed after the formation of a conductive backside layer 328 below the backside dielectric layer 326 according to some embodiments. The conductive backside layer 328 can be part of a backside interconnect structure consisting of any number of backside interconnect layers. The conductive backside layer 328 can contact the exposed lower surface of the conductive fill 318 within the TSV / Tap structures 320 and the TSV structures 322. In some examples, more than one conductive backside layer is structured to make contact with any number of TSV / Tap structures 320 and / or TSV structures 322. In the illustrated example, the conductive backside layer 328 extends to contact the lower surface of each TSV / Tap structure 320 and each TSV structure 322.The conductive backside layer 328 can comprise any suitable conductive material, such as copper, tungsten, ruthenium, molybdenum, or cobalt. The conductive backside layer 328 can be arranged to supply rail power or ground to the circuit.

[0045] In the illustrated example, the TSV structures 322 provide a conductive path between the conductive backside layer 328 and the conductive frontside layer 325. The TSV / Tap structures 320 provide conductive paths between the conductive backside layer 328 and the conductive frontside layers 324. Additionally, according to some embodiments, the TSV / Tap structures 320 provide a conductive path between the conductive backside layer 328 and the device layer 304.

[0046] Fig. Figure 4 illustrates an exemplary embodiment of a chip package 400 according to an embodiment of the present disclosure. As can be seen, the chip package 400 comprises one or more dies 402. One or more dies 402 may comprise at least one integrated circuit with a structure as described in any of the embodiments mentioned above. In some exemplary configurations, one or more dies 402 may comprise any other circuit arrangement used to form an interface with other devices formed on the dies or other devices connected to the chip package 400.

[0047] As can be further seen, the chip package 400 has a housing 404 bonded to a housing substrate 406. The housing 404 can be any standard or proprietary package and can, for example, provide electromagnetic shielding and environmental protection for the components of the chip package 400. The one or more dies 402 can be conductively coupled to a housing substrate 406 using interconnects 408, which can be implemented with any number of standard or proprietary interconnection mechanisms, such as solder pads, a ball-and-pin assembly (BGA), pins, or wire bonds, to name a few examples. The housing substrate 406 can be any standard or proprietary package substrate, but in some cases, it has a dielectric material with conductive paths (e.g.,including conductive vias and conductors) extending through the dielectric material between the faces of the housing substrate 406 or between different locations on each face. In some embodiments, the housing substrate 406 may have a thickness of less than 1 millimeter (e.g., between 0.1 millimeters and 0.5 millimeters), although any number of housing geometries may be used. Additional conductive contacts 412 may be arranged on an opposite face of the housing substrate 406 for conductive contacting, for example, a printed circuit board (PCB). One or more vias 410 extend through a thickness of the housing substrate 406 to provide conductive paths between one or more junctions 408 and one or more contact(s) 412.For the sake of simplicity, the vias 410 are illustrated as single straight pillars extending through the housing substrate 406, although other configurations can be used (e.g., damascene, dual damascene, silicon through-hole plating, or an intermediate interconnect structure that meanders through the thickness of the substrate 406 to make contact with one or more intermediate positions therein). In still other embodiments, the vias 410 are made by multiple smaller stacked vias or are staggered at various locations across the housing substrate 406. In the illustrated embodiment, the contacts 412 are solder balls (e.g., for contact-hill-based connections or a ball-grid arrangement), but any suitable housing bonding mechanism can be used (e.g., pins in a pin-grid arrangement or contact spots in a contact-spot grid arrangement).In some embodiments, a solder mask is arranged between the contacts 412 to prevent a short circuit.

[0048] In some embodiments, a potting compound 414 can be arranged around one or more dies 402 contained within the housing 404 (e.g., between the dies 402 and the housing substrate 406 as an underfill material, and between the dies 402 and the housing 404 as an overfill material). Although the dimensions and properties of the potting compound 414 may vary from one embodiment to another, in some embodiments the thickness of the potting compound 414 is less than 1 millimeter. Suitable materials for the potting compound 414 include epoxy potting compounds. In some cases, the potting compound 414 is also thermally conductive, in addition to being electrically insulating. methodology

[0049] Fig. Figure 5 is a flowchart of a method 500 for forming at least one section of an integrated circuit according to one embodiment. Various operations of the method 500 can be shown in Fig. Figures 3A-3L illustrate the process. However, the correlation of the various operations of Process 500 with the specific components illustrated in the aforementioned figures is not intended to imply any structural and / or application-related restrictions. Instead, the aforementioned figures provide an exemplary embodiment of Process 500. Other operations may be performed before, during, or after any of the operations of Process 500. Some of the operations of Process 500 may be performed in a different order than the one illustrated.

[0050] Method 500 begins with step 502, in which a depression is formed through a semiconductor region and partially through a substrate beneath the semiconductor region. A RIE process can be used together with suitable lithography techniques to pattern and etch the depression. In some embodiments, a front-side dielectric layer over the semiconductor region is used as a hard mask material to pattern the position of the depression. According to some embodiments, the depression can have an elongated trench shape or can have a circular or square basic cross-sectional shape.

[0051] Method 500 continues with step 504, in which a dielectric lining is formed within the well. The dielectric lining can be any suitable dielectric material, such as silicon dioxide, silicon nitride, or silicon oxynitride. In some examples, the dielectric lining has a different material composition compared to the front-side dielectric layer. The dielectric lining can be conformally deposited along all surfaces of the wells to a thickness, for example, between about 3 nm and about 10 nm, using CVD or ALD.

[0052] Method 500 continues with step 506, in which a sacrificial filling is formed at the bottom of the well. The sacrificial filling can be any suitable material that can be easily removed at a later time without damaging surrounding structures. For example, the sacrificial filling can be CHM, titanium nitride, or aluminum oxide, to name just a few. According to some embodiments, the sacrificial filling is first deposited within the well and then deepened to a final height at the bottom of the well using a suitable isotropic etching process. According to some exemplary embodiments, the sacrificial filling can be deepened to a final height such that its top surface is close to the boundary between the semiconductor region and the substrate, such as within 10 nm, within 5 nm, or within 2 nm of the boundary.

[0053] Method 500 continues with step 508, in which exposed portions of the dielectric lining not protected by the sacrificial filling are removed from the well. The dielectric lining can be removed using any suitable isotropic etching process. Removal of the dielectric lining exposes the semiconductor region along the sidewalls of the well, according to some embodiments.

[0054] Procedure 500 continues with step 510, in which the sacrificial filling is removed and a conductive material layer is formed on the exposed semiconductor region within the well. The sacrificial material can be removed using any suitable isotropic etching process. The conductive material layer can be, for example, a silicide, a germanide, a III-V ide, or another suitable conductive material to improve the ohmic contact with the semiconductor region.

[0055] In one example, a layer of titanium is deposited over the entire structure and subsequently annealed. In areas where the titanium is deposited on the semiconductor domain, titanium disilicide is formed (in examples where the semiconductor domain contains silicon), while titanium nitride is formed everywhere else. The excess titanium nitride can then be selectively removed using a suitable isotropic etching process, leaving only the silicide on the well walls. In another example, silicide can be epitaxially grown on the exposed portions of the semiconductor domain along the well walls. According to some embodiments, the growth process occurs only on the exposed silicon surfaces, thus forming the silicide only in these regions.In another example, germanide can be epitaxially grown on the exposed portions of the semiconductor region along the sidewalls of the depressions. According to some embodiments, the growth process occurs only on the exposed germanium surfaces, thus forming the germanide only in these areas. In yet another example, III-V ide can be epitaxially grown on the exposed portions of the semiconductor region along the sidewalls of the depressions. Again, according to some embodiments, the growth process occurs only on the exposed III-V semiconductor material surfaces, thus forming the III-V ide only in these areas. The conductive material layer can be formed to a lateral thickness, for example, less than 5 nm, such as between 1 nm and 3 nm.

[0056] Procedure 500 continues with step 512, in which a conductive fill is formed within the cavity and on top of the conductive material layer. The conductive fill can be any suitable conductive material, such as copper, tungsten, molybdenum, cobalt, or ruthenium. The conductive fill can be deposited using any of the following processes: electroplating, electroless plating, CVD, ALD, or PECVD, to name a few. As noted above, a conductive liner can first be deposited on the exposed surfaces of the cavity, followed by a conductive fill on top of the conductive liner.

[0057] Procedure 500 continues with Operation 514, in which at least a portion of the substrate is removed from the back side. The back side of the substrate can be removed using any number or combination of techniques, such as dry etching, wet etching, polishing, or grinding. In some examples, the back side of the substrate is polished or ground down until the lower surface of the conductive infill is exposed. Further recession of the substrate can then be performed around the end of the conductive infill (potentially exposing a lower surface of the semiconductor region).

[0058] Method 500 continues with step 516, in which a backside dielectric layer is formed below the semiconductor region. According to some embodiments, the backside dielectric layer is also formed around the lower end of the conductive fill, extending outward from below the semiconductor region. The backside dielectric layer can be any suitable dielectric material, such as silicon dioxide, silicon nitride, or silicon oxynitride. According to some embodiments, a lower surface of the backside dielectric layer can be polished until it is substantially coplanar with a lower surface of the conductive fill.

[0059] Method 500 continues with step 518, in which a conductive backside layer is formed below the backside dielectric layer. In some embodiments, the conductive backside layer contacts a lower surface of the conductive fill. The conductive backside layer can be part of a backside interconnect structure consisting of any number of backside interconnect layers. The backside interconnect layer can comprise any suitable conductive material, such as copper, tungsten, ruthenium, molybdenum, or cobalt. In some embodiments, the conductive backside layer is arranged to supply rail power or ground to the circuit.

[0060] It should be noted that the conductive infill provides a well-tap structure to couple between the semiconductor region and the conductive back layer. A conductive front layer can also be formed above the conductive infill, so that it also acts as a TSV between the conductive front layer and the conductive back layer. Exemplary system

[0061] Fig.Figure 6 is an exemplary computing system implemented with one or more of the integrated circuit structures disclosed herein, according to some embodiments of the present disclosure. As can be seen, the computing system 600 includes a mainboard 602. The mainboard 602 can have a number of components, including, but not limited to, a processor 604 and at least one communication chip 606, each of which can be physically and electrically coupled to the mainboard 602 or otherwise integrated therein. It is understood that the mainboard 602 can, for example, be any printed circuit board (PCB), whether a mainboard, a daughterboard mounted on a mainboard, or the only board of the system 600, etc.

[0062] Depending on its applications, the Computing System 600 may include one or more other components, which may or may not be physically and electrically coupled to the Mainboard 602. These other components may, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), a graphics processor, a digital signal processor, a cryptoprocessor, a chipset, an antenna, a display, a touchscreen display, a touchscreen control, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a loudspeaker, a camera, and a mass storage device (such as a hard disk drive, a compact disc (CD), a digital versatile disc (DVD), and the like).Any of the components included in the computing system 600 may comprise one or more integrated circuit structure(s) or device(s) configured according to any of the embodiments disclosed herein (e.g., a module comprising an integrated circuit having semiconductor through-hole vias (TSVs) and well-taps coupled by a backside interconnect). In some embodiments, several functions may be integrated into one or more chips (e.g., the communication chip 606 may be part of the processor 604 or otherwise integrated into it).

[0063] The 606 communication chip enables wireless communication for the transmission of data to and from the 600 computer system. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data through a non-solid medium by using modulated electromagnetic radiation. The term does not imply that the associated devices do not contain wires, although in some embodiments they may not. The 606 communication chip can implement any number of wireless standards or protocols, including, but not limited to, WiFi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.11, and IEEE 802.11.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols designated as 3G, 4G, 5G, and higher. The Computing System 600 can incorporate multiple Communication Chips 606. For example, a first Communication Chip 606 can be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second Communication Chip 606 can be dedicated to longer-range wireless communications, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0064] The processor 604 of the computing system 600 comprises an integrated circuit die that is packaged within the processor 604. In some embodiments, the integrated circuit die of the processor includes an onboard circuit arrangement implemented with one or more semiconductor devices, as described herein in various ways. The term "processor" can refer to any device or any section of a device that, for example, processes electronic data from registers and / or a memory to transform such electronic data into other electronic data that can be stored in registers and / or a memory.

[0065] The communication chip 606 can also include an integrated circuit die that is housed within the communication chip 606. According to some such exemplary embodiments, the integrated circuit die of the communication chip includes one or more semiconductor devices, as described herein in various ways. As is understood from this disclosure, it should be noted that multi-standard wireless capability can be directly integrated into the processor 604 (e.g., by integrating functionality from any chip 606 into the processor 604 instead of having separate communication chips). It should also be noted that the processor 604 can be a chipset with such wireless capability. In summary, any number of the processor 604 and / or the communication chips 606 can be used. Likewise, any chip or chipset can have multiple functions integrated therein.

[0066] In various implementations, the Computing System 600 can be a laptop, a netbook, a notebook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra-mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music playback device, a digital video recorder, or any other electronic device that processes data or uses one or more integrated circuit structure(s) or device(s) formed using the disclosed techniques as described herein in various ways.

[0067] It is understood that in some embodiments the various components of the Computing System 600 can be combined with or integrated into a system-on-a-chip (SoC) architecture. In some embodiments, the components can be hardware components, firmware components, software components, or any suitable combination of hardware, firmware, or software. Further exemplary embodiments

[0068] The following examples represent further embodiments, from which numerous implementations and configurations can be seen.

[0069] Example 1 is an integrated circuit comprising a device layer with a plurality of semiconductor devices in a first region of the device layer and with semiconductor material in a second region of the device layer, a dielectric layer below the device layer, a conductive via in the second region of the device layer extending through at least a section of a thickness of the device layer and through the entire thickness of the dielectric layer, a conductive layer below the dielectric layer contacting a section of the conductive via, and a conductive material layer between a side wall of the conductive via and a side wall of the semiconductor material in the second region of the device layer. The conductive material layer directly contacts the conductive via and directly contacts the semiconductor material in the second region of the device layer.

[0070] Example 2 features the integrated circuit of Example 1, wherein the conductive material layer comprises silicon and titanium.

[0071] Example 3 features the integrated circuit of Example 1, wherein the conductive material layer comprises germanium and titanium.

[0072] Example 4 features the integrated circuit of Example 1, wherein the conductive material layer comprises silicon and a metal.

[0073] Example 5 features the integrated circuit of Example 1, wherein the conductive material layer comprises germanium and metal.

[0074] Example 6 features the integrated circuit of Example 1, wherein the conductive material layer comprises a Group III V semiconductor material and a metal.

[0075] Example 7 features the integrated circuit of one of Examples 1-6, wherein the conductive material layer has a lateral thickness between about 2 nm and about 5 nm.

[0076] Example 8 features the integrated circuit of one of Examples 1 - 7, wherein the conductive via comprises tungsten, molybdenum, cobalt or ruthenium.

[0077] Example 9 comprises the integrated circuit of one of Examples 1-8, wherein the dielectric layer is a first dielectric layer and the conductive layer is a first conductive layer. The integrated circuit further comprises a second dielectric layer above the device layer and a second conductive layer above the second dielectric layer. The conductive via contacts a portion of the second conductive layer.

[0078] Example 10 features the integrated circuit of Example 9, wherein the conductive via extends through the entire thickness of the device layer and the entire thickness of the second dielectric layer.

[0079] Example 11 features the integrated circuit of one of Examples 1-10, wherein the conductive via extends through the entire thickness of the device layer.

[0080] Example 12 features the integrated circuit of one of Examples 1 - 11, wherein the conductive material layer along the side wall extends only between the conductive via and the semiconductor material.

[0081] Example 13 features the integrated circuit of one of Examples 1-12, wherein the semiconductor material comprises silicon, germanium, silicon and germanium, or a Group III-V semiconductor material.

[0082] Example 14 features the integrated circuit of one of Examples 1-13, wherein a lower surface of the conductive via is essentially coplanar with a lower surface of the dielectric layer.

[0083] Example 15 is a printed circuit board that incorporates the integrated circuit from one of Examples 1 - 14.

[0084] Example 16 is an electronic device comprising a chip package containing one or more dies. At least one of the one or more dies has a device layer comprising a plurality of semiconductor devices in a first region of the device layer, a dielectric layer below the device layer, a conductive via in a second region of the device layer extending through at least a section of a thickness of the device layer and through the entire thickness of the dielectric layer, a conductive layer below the dielectric layer contacting a section of the conductive via, and a conductive material layer on a sidewall of the conductive via. The conductive material layer directly contacts the conductive via and directly contacts a semiconductor material in the second region of the device layer.

[0085] Example 17 features the electronic device of Example 16, wherein the conductive material layer comprises silicon and titanium.

[0086] Example 18 features the electronic device of Example 16 or 17, wherein the conductive material layer has a lateral thickness between about 2 nm and about 5 nm.

[0087] Example 19 includes the electronic device of one of Examples 16-18, wherein the conductive via comprises tungsten, molybdenum, cobalt or ruthenium.

[0088] Example 20 comprises the electronic device of one of Examples 16-19, wherein the dielectric layer is a first dielectric layer and the conductive layer is a first conductive layer. The at least one of the one or more dies further comprises a second dielectric layer above the device layer and a second conductive layer above the second dielectric layer. The conductive via contacts a section of the second conductive layer.

[0089] Example 21 features the electronic device of Example 20, wherein the conductive via extends through the entire thickness of the second dielectric layer.

[0090] Example 22 features the electronic device of one of Examples 16 - 21, wherein the conductive via extends through the entire thickness of the device layer.

[0091] Example 23 features the electronic device of one of Examples 16-22, wherein the conductive material layer along the side wall extends only between the conductive via and the semiconductor material.

[0092] Example 24 includes the electronic device of one of Examples 16-23, wherein the semiconductor material comprises silicon.

[0093] Example 25 features the electronic device of one of Examples 16-24, wherein a lower surface of the conductive via is substantially coplanar with a lower surface of the dielectric layer.

[0094] Example 26 comprises the electronic device of one of Examples 16-25, which further comprises a printed circuit board, wherein the chip package is attached to the printed circuit board.

[0095] Example 27 is a method for forming an integrated circuit. The method comprises: forming a well through a semiconductor region above a semiconductor substrate; forming a dielectric lining on exposed surfaces within the well; forming a sacrificial fill on a lower portion of the well; removing an exposed portion of the dielectric lining above the sacrificial fill; removing the sacrificial fill; forming a conductive layer on exposed surfaces of the semiconductor region within the well; forming a conductive fill within the well and on the conductive layer; removing at least a portion of the semiconductor substrate; forming a dielectric layer below the semiconductor region; and forming a conductive layer below the dielectric layer, the conductive layer contacting at least a portion of the conductive fill.

[0096] Example 28 exhibits the procedure of Example 27, wherein the formation of the conductive material layer includes the formation of a layer comprising silicon and titanium.

[0097] Example 29 includes the procedure of Example 28, wherein forming the conductive material layer comprises: depositing a layer comprising titanium over exposed surfaces within the well and annealing the layer comprising titanium to form the conductive material layer on the exposed surfaces of the semiconductor region.

[0098] Example 30 exhibits the method of one of Examples 27-29, wherein the formation of the dielectric layer comprises forming the dielectric layer around a lower end of the conductive filling and polishing the dielectric layer to expose a lower surface of the conductive filling.

[0099] Example 31 is an integrated circuit comprising a semiconductor region comprising one or more semiconductor layers, a dielectric layer below the semiconductor region, a conductive via extending through the entire thickness of the semiconductor region and the entire thickness of the dielectric layer, a conductive layer below the dielectric layer contacting a portion of the conductive via, and a conductive material layer between a sidewall of the semiconductor region and the conductive via.

[0100] Example 32 features the integrated circuit of Example 31, wherein the conductive material layer comprises silicon and titanium.

[0101] Example 33 features the integrated circuit of Example 31, wherein the conductive material layer comprises germanium and titanium.

[0102] Example 34 features the integrated circuit of Example 31, wherein the conductive material layer comprises silicon and a metal.

[0103] Example 35 features the integrated circuit of Example 31, wherein the conductive material layer comprises germanium and metal.

[0104] Example 36 features the integrated circuit of Example 31, wherein the conductive material layer comprises a Group III V semiconductor material and a metal.

[0105] Example 37 features the integrated circuit of one of Examples 31-36, wherein the conductive material layer has a lateral thickness between about 2 nm and about 5 nm.

[0106] Example 38 features the integrated circuit of one of Examples 31-37, wherein the conductive via comprises tungsten, molybdenum, cobalt or ruthenium.

[0107] Example 39 features the integrated circuit of one of Examples 31–38, wherein the dielectric layer is a first dielectric layer and the conductive layer is a first conductive layer. The integrated circuit further features a second dielectric layer over the semiconductor region and a second conductive layer over the second dielectric layer. The conductive via contacts a portion of the second conductive layer.

[0108] Example 40 features the integrated circuit of Example 39, wherein the conductive via extends through the entire thickness of the second dielectric layer.

[0109] Example 41 features the integrated circuit of one of Examples 31-40, where the thickness of the semiconductor region is between about 50 nm and about 200 nm.

[0110] Example 42 features the integrated circuit of one of Examples 31-41, wherein the conductive material layer along the side wall extends only between the conductive via and the semiconductor region.

[0111] Example 43 features the integrated circuit of one of Examples 31-42, wherein the semiconductor domain comprises silicon, germanium, silicon and germanium, or a Group III-V semiconductor material.

[0112] Example 44 features the integrated circuit of one of Examples 31-43, wherein a lower surface of the conductive via is essentially coplanar with a lower surface of the dielectric layer.

[0113] Example 45 is a printed circuit board that incorporates the integrated circuit from one of Examples 31 - 44.

[0114] The foregoing description of the embodiments of the disclosure is presented for illustrative and descriptive purposes. It is not intended to be exhaustive or to limit the disclosure to the exact forms disclosed. Many modifications and variations are possible in light of this disclosure. It is intended that the scope of the present disclosure is not limited by this detailed description, but instead by the claims attached thereto.

Claims

[1] Integrated circuit comprising: a device layer comprising a plurality of semiconductor devices in a first region of the device layer and semiconductor material in a second region of the device layer; a dielectric layer below the device layer; a conductive via in the second region of the device layer, which extends through at least one section of a thickness of the device layer and extends through an entire thickness of the dielectric layer; a conductive layer below the dielectric layer that contacts a section of the conductive via; and a conductive material layer between a side wall of the conductive via and a side wall of the semiconductor material in the second region of the device layer, such that the conductive material layer directly contacts the conductive via and directly contacts the semiconductor material in the second region of the device layer. [2] Integrated circuit according to claim 1, wherein the conductive material layer comprises silicon and titanium. [3] Integrated circuit according to claim 1, wherein the conductive material layer comprises germanium and titanium. [4] Integrated circuit according to claim 1, wherein the conductive material layer comprises silicon and a metal. [5] Integrated circuit according to claim 1, wherein the conductive material layer comprises germanium and metal. [6] Integrated circuit according to claim 1, wherein the conductive material layer comprises a group III-V semiconductor material and a metal. [7] Integrated circuit according to any one of claims 1 to 6, wherein the conductive material layer has a lateral thickness between about 2 nm and about 5 nm. [8] Integrated circuit according to any one of claims 1 to 7, wherein the conductive via comprises tungsten, molybdenum, cobalt or ruthenium. [9] Integrated circuit according to any one of claims 1 to 8, wherein the dielectric layer is a first dielectric layer and the conductive layer is a first conductive layer, the integrated circuit further comprising: a second dielectric layer above the device layer and a second conductive layer above the second dielectric layer; where the conductive via contacts a section of the second conductive layer. [10] Integrated circuit according to claim 9, wherein the conductive via extends through an entire thickness of the device layer and an entire thickness of the second dielectric layer. [11] Integrated circuit according to any one of claims 1 to 10, wherein the conductive via extends through the entire thickness of the device layer. [12] Integrated circuit according to any one of claims 1 to 11, wherein the conductive material layer extends along the side wall only between the conductive via and the semiconductor material. [13] Printed circuit board comprising the integrated circuit according to any one of claims 1 to 12. [14] Electronic device comprising: a chip package comprising one or more dies, wherein at least one of the one or more of these. This includes a device layer comprising a plurality of semiconductor devices in a first region of the device layer; a dielectric layer below the device layer; a conductive via in a second region of the device layer, which extends through at least one section of a thickness of the device layer and extends through an entire thickness of the dielectric layer; a conductive layer below the dielectric layer that contacts a section of the conductive via; and a conductive material layer on a side wall of the conductive via, so that the conductive material layer directly contacts the conductive via and directly contacts the semiconductor material in the second area of ​​the device layer. [15] Electronic device according to claim 14, wherein the conductive material layer comprises silicon and titanium. [16] Electronic device according to claim 14 or 15, wherein the conductive material layer has a lateral thickness between about 2 nm and about 5 nm. [17] Electronic device according to any one of claims 14 to 16, wherein the dielectric layer is a first dielectric layer and the conductive layer is a first conductive layer, wherein the at least one of the one or more die(s) further comprises: a second dielectric layer above the device layer and a second conductive layer above the second dielectric layer, where the conductive via contacts a section of the second conductive layer. [18] Electronic device according to any one of claims 14 to 17, wherein the conductive via extends through the entire thickness of the device layer. [19] Electronic device according to any one of claims 14 to 18, wherein the conductive material layer along the side wall extends only between the conductive via and the semiconductor material. [20] Integrated circuit comprising: a semiconductor area comprising one or more semiconductor layer(s); a dielectric layer below the semiconductor region; a conductive via that extends through the entire thickness of the semiconductor region and through the entire thickness of the dielectric layer; a conductive layer below the dielectric layer that contacts a section of the conductive via; and a conductive material layer that directly contacts the conductive via and directly contacts the semiconductor area. [21] Integrated circuit according to claim 20, wherein the conductive material layer comprises silicon and titanium or germanium and titanium. [22] Integrated circuit according to claim 20 or 21, wherein the dielectric layer is a first dielectric layer and the conductive layer is a first conductive layer, the integrated circuit further comprising: a second dielectric layer over the semiconductor area and a second conductive layer above the second dielectric layer, where the conductive via contacts a section of the second conductive layer. [23] Integrated circuit according to claim 22, wherein the conductive via extends through the entire thickness of the second dielectric layer. [24] Integrated circuit according to one of claims 20 to 23, wherein the thickness of the semiconductor region is between about 50 nm and about 200 nm. [25] Integrated circuit according to one of claims 20 to 24, wherein the conductive material layer along the side wall extends only between the conductive via and the semiconductor material.

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