ASYMMETRIC TRANSMITTER POWER COMBINATOR

Abstract

An exemplary device described herein comprises a first contact surface, a second contact surface, and a transmission line having a first end configured to be coupled to a circuit arrangement, the transmission line having a second end. The exemplary device also comprises a first switch coupled to the first contact surface, the first switch being coupled to the transmission line between its first end and second end. The exemplary device further comprises a second switch coupled to the second contact surface and to the second end of the transmission line, the impedance of the first switch being greater than the impedance of the second switch.

Description

TECHNICAL AREA

[0001] This description refers generally to power combiners and in particular to asymmetric transmission line power combiners. BACKGROUND

[0002] A millimeter-wave radar sensor (mmWave radar sensor) can incorporate a multi-input / multi-output transmitter / receiver (MIMO transmitter / receiver) with an internal loopback system to support calibration, monitoring, and / or operational safety requirements. The loopback system connects the multiple transmit power outputs of the MIMO transmitter / receiver to the receiver of the MIMO transmitter / receiver. Such a loopback system allows attenuated versions of the output signals generated at the transmit power outputs to be fed back to the receiver. The receiver receives these feedback signals and makes them available to one or more circuits for various purposes. For example, a monitoring circuit coupled to or otherwise contained within the receiver can use the feedback signals to verify the functionality of individual transmit power outputs during operation and to monitor characteristics such as...To ensure reliable transmitter performance, it is necessary to measure the average power output, peak power output, gain mismatch between power outputs, phase mismatch between power outputs, and so on. Some such loop-circuit systems use a transmission line power combiner that couples the multiple transmit power outputs of the MIMO transmitter / receiver to a common transmission line. This combines the power from the multiple transmit power outputs and feeds it back to the receiver of the MIMO transmitter / receiver. In some examples, the feedback signals can be used to generate an auxiliary oscillator signal in the receiver. SUMMARY

[0003] For methods and devices for implementing asymmetric transmission line power combiners, an exemplary device described herein includes a first contact surface, a second contact surface, and a transmission line having a first end configured to be coupled to a monitoring circuit arrangement, the transmission line having a second end. The exemplary device also includes a first switch coupled to the first contact surface, the first switch being coupled to the transmission line between the first end and the second end. The exemplary device further includes a second switch coupled to the second contact surface and to the second end of the transmission line, the impedance of the first switch being greater than the impedance of the second switch.

[0004] For methods and devices for implementing asymmetric transmission line power combiners, another exemplary device described herein includes a transmission line with a first end and a second end, wherein the first end is coupled to a circuit arrangement to monitor multiple transmit power outputs of the device. The exemplary device also includes switches for coupling the transmit power outputs to the transmission line, wherein a first switch couples a first transmit power output between the first and second ends of the transmission line to the transmission line, a second switch couples a second transmit power output to the second end of the transmission line, and the second switch has a lower impedance than the first switch.

[0005] For methods and devices for implementing asymmetric transmission line power combiners, an exemplary transitive computer-readable medium described herein contains computer-readable instructions to cause at least one processor circuit to at least cause several transmit power outputs of a device to be sequentially activated for respective time intervals in a monitoring period, wherein the transmit power outputs are each connected to several switches coupled to a transmission line at respective positions spaced apart along the transmission line, wherein the transmission line has a termination and an output, the output being coupled to a circuit arrangement to monitor the transmit power outputs.Furthermore, the computer-readable instructions for a first of the time intervals in which a first of the transmit power outputs is active and other of the transmit power outputs are inactive, also cause one or more of the at least one processor circuit (i) to cause a first of the switches connected to the first of the transmit power outputs to be deactivated, the first of the switches being coupled to the transmission line at a first of the positions, and (ii) to cause a second of the switches being coupled to the transmission line at a second of the positions between the first of the positions and the termination of the transmission line to be activated. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a block diagram of an exemplary device containing an exemplary transmission line power combiner. Fig. Figure 2 illustrates a first exemplary implementation of the transmission line power combiner according to Fig. 1. Fig. Figure 3 illustrates a second exemplary implementation of the transmission line power combiner according to Fig. 1. Fig. Figure 4 illustrates a third exemplary implementation of the transmission line power combiner according to Fig. 1. Fig. Figure 5 illustrates exemplary performance results for the third exemplary implementation of the in Fig. 4 illustrated transmission line power combiners. Fig. Figure 6 illustrates a fourth exemplary implementation of the transmission line power combiner according to Fig. 1, which corresponds to an exemplary small-area, loss-balanced asymmetric transmission line power combiner, as described herein. Fig. Figure 7 illustrates an exemplary operation of the asymmetric transmission line power combiner according to Fig. 6. Fig. Figure 8 illustrates an exemplary equivalence circuit for modeling the impedance in the asymmetric transmission line power combiner according to Fig. 6. Fig. Figure 9 illustrates exemplary performance results for the asymmetric transmission line power combiner according to Fig. 6. Fig. Figures 10-11 illustrate exemplary performance results for alternative switch configurations used in the asymmetric transmission line power combiner according to Fig. 6 can be used. Fig. Figure 12 illustrates an exemplary use of the equivalent circuit according to Fig. 8 for modeling the impedance of a transmission line, which in the asymmetric transmission line power combiner according to Fig. 6 is included. Fig. 13 is a flowchart representing exemplary machine-readable instructions or exemplary operations that can be performed using an implementation of an exemplary programmable circuit arrangement of the device according to Fig. 1, which connects the asymmetric transmission line power combiner to Fig. 6 contains at least one of which can be performed, instantiated or executed. Fig. Figure 14 is a block diagram of an exemplary processing platform containing a programmable circuit arrangement structured to execute, instantiate, or perform the exemplary machine-readable instructions or the exemplary operations according to Fig. 13 to execute in order to move the device to Fig. 1, which connects the asymmetric transmission line power combiner to Fig. 6 contains, to implement. Fig. Figure 15 is a block diagram of an exemplary implementation of the programmable circuit arrangement according to Fig. 14. Fig. Figure 16 is a block diagram of another exemplary implementation of the programmable circuit arrangement according to Fig. 14. Fig. Figure 17 is a block diagram of an exemplary software / firmware / instruction distribution platform (e.g., one or more servers) for distributing software, instructions, or firmware (e.g., according to the exemplary machine-readable instructions according to Fig. 13) to client devices that are assigned to end users or consumers (e.g. for licensing, sale or use), retailers (e.g. for sale, resale, licensing or sublicensing) or original equipment manufacturers (OEMs) (e.g. for inclusion in products to be distributed to retailers or other end users such as direct purchase customers).

[0006] The drawings are not necessarily to scale. In general, identical reference symbols in one or more drawings and in this description refer to (functionally and / or structurally) identical or similar features and / or parts. Although the drawings show areas with clean lines and boundaries, some or all of these lines and boundaries may be idealized. In reality, the boundaries or lines may be unobservable, mixed, or irregular. DETAILED DESCRIPTION

[0007] This section describes exemplary techniques for implementing a small-area, loss-balanced, asymmetric transmission line power combiner. As mentioned above, some MIMO transmitters / receivers incorporate a loop-connected system that uses a transmission line power combiner to couple the multiple transmit power outputs of a MIMO transmitter / receiver to a common transmission line. The transmission line combines the power from the multiple transmit power outputs and feeds it back to the receiver of the MIMO transmitter / receiver. Such transmission line power combiners can use a symmetrical design, so that the loop paths for the different transmit power outputs have similar lengths, resulting in similar attenuation for the different transmit power outputs.Symmetrical transmission line power combiners can work well for relatively small numbers of transmit power outputs (e.g., two to four transmitters). However, for MIMO transmitters / receivers with a larger number of transmit power outputs (e.g., eight or sixteen transmitters), such as those used in modern radar systems, a symmetrical combiner can occupy a relatively large die area due to the relatively large transmission line size. Furthermore, such a MIMO transmitter / receiver can experience relatively high attenuation losses due to the relatively large transmission line size and consequently require additional amplifier stages to compensate for the extra loss, resulting in increased power consumption.

[0008] Transmission line power combiners employing an asymmetric design can significantly reduce the combiner die area compared to symmetric transmission line implementations. However, some asymmetric transmission line power combiners exhibit significant attenuation loss variations across their different transmit power outputs. In contrast, the exemplary asymmetric transmission line power combiners described here compensate for the attenuation loss between the multiple transmit power outputs and consequently provide smaller attenuation differences compared to other asymmetric transmission line power combiners.Furthermore, the exemplary asymmetric transmission line power combiners described here reduce the overall attenuation loss compared to other implementations of symmetric transmission line power combiners, thereby reducing the number of amplifiers used to amplify the feedback signal and the associated power consumption compared to these symmetric transmission line power combiners. For example, an asymmetric transmission line power combiner described here may exhibit a 7-9 dB lower overall attenuation loss compared to a symmetric transmission line power combiner and consequently save 20-40 milliamperes of power consumption. Furthermore, the asymmetric transmission line power combiners described here exhibit a significantly lower overall attenuation loss compared to other symmetric transmission line power combiners (e.g.,The die area is reduced by at least a factor of four because the total length of the transmission lines described here is shorter.

[0009] The characters are Fig. 1 A block diagram of an exemplary device 100, which includes an exemplary transmission line power combiner 105. According to the in Fig. In the illustrated example, the device 100 can implement at least a portion of a MIMO transmitter / receiver of a mmWave radar sensor used in automotive applications, industrial applications, imaging radar, building automation, consumer electronics, etc. For example, the device 100 can be used to implement a front radar for a motor vehicle, a corner radar for a motor vehicle, etc., used in an advanced driver assistance system (ADAS). However, according to other examples, the device 100 can correspond to any device containing multiple transmitters. For example, the device 100 can correspond to a mobile communications device with multiple transmitting antennas (e.g., an antenna array), an industrial detection and imaging radar, etc. Although the combiner 105 is described here as a combiner in a transmitter system, the same techniques can be implemented in a splitter circuit.

[0010] The device 100 as such includes several exemplary antennas 110A-H and corresponding exemplary power amplifiers (PAs) 115A-H to generate several transmit signals to be output by the device 100. The antennas 110A-H can be implemented using any suitable technology and can be external antennas, internal antennas, etc., or any combination thereof. The antennas 110A-H are coupled to corresponding exemplary transmit power outputs 120A-H of the PAs 115A-H. The PAs 115A-H can be implemented using any suitable amplifier technology to generate output signals at the transmit power outputs 120A-H, which drive the respective antennas 110A-H to generate the transmit signals to be output by the device 100. According to some examples, the antennas 110A-110H may be integrated into the device 100, while according to other examples, the antennas 110A-110H may be located outside the device 100.

[0011] In the Fig. In the illustrated example, the device includes an exemplary loop circuit system implemented by the transmission line power combiner 105, an exemplary monitoring circuit arrangement 125, and an exemplary control circuit arrangement 130. According to some examples, the monitoring circuit arrangement 125 and / or the control circuit arrangement 130 can be further specified. Fig. 1. instantiated by a programmable circuit arrangement, such as a central processing unit (CPU), which executes initial instructions (e.g., creating an instance, creating for a certain duration, materializing, implementing, etc.). Additionally or alternatively, the monitoring circuit arrangement 125 and / or the control circuit arrangement 130 can be Fig. 1. instantiated (e.g., by creating an instance, creating for some duration, materializing, implementing, etc.) by (i) an application-specific integrated circuit (ASIC) or (ii) a field-programmable gate array (FPGA) that is structured or configured in response to the execution of second instructions to perform the operations corresponding to the first instructions. Some or all of the monitoring circuit arrangement 125 and / or the control circuit arrangement 130 according to Fig. 1 can therefore be instantiated at the same or different times. Some or all of the monitoring circuit arrangement 125 and / or the control circuit arrangement 130 according to Fig. 1. They can be instantiated, for example, in one or more threads that are executed concurrently on hardware or sequentially on hardware. Furthermore, according to some examples, some or all of the monitoring circuit arrangement 125 and / or the control circuit arrangement 130 can be executed according to Fig. 1. be implemented by a microprocessor circuit arrangement that executes instructions, or by an FPGA circuit arrangement that performs operations to implement one or more virtual machines or containers.

[0012] According to the illustrated example, the transmission line power combiner 105 of the device 100 includes an exemplary transmission line 135, exemplary contact pads 140A-H, and exemplary switches 145A-H. The transmission line power combiner 105 uses the contact pads 140A-H and the switches 145A-H to couple the transmit power outputs 120A-H of the PAs 115A-H to the transmission line 135. The transmission line 135 of the illustrated example has an exemplary termination end 150 and an exemplary output end 155. According to the illustrated example, the output end 155 of the transmission line 135 is coupled to the monitoring circuit arrangement 125.

[0013] As illustrated in the example, the transmission line power combiner 105 combines the power from the transmit power outputs 120A-H of the PAs 115A-H and feeds the combined power back to the monitoring circuit 125. The monitoring circuit 125 processes the feedback signal provided at the output end 155 of the transmission line to check the functionality of the transmit power outputs 120A-H of individual transmitters in operation and to measure characteristics such as average power output, peak power output, gain mismatch between the transmit power outputs 120A-H, phase mismatch between the transmit power outputs 120A-H, etc. According to some examples, the monitoring circuit 125 uses the measured characteristics to ensure reliable transmitter performance, identify one or more disturbances, implement one or more safe operating modes, etc.

[0014] To facilitate individual monitoring of the transmit power outputs 120A-H, the control circuit arrangement 130 of the illustrated example defines monitoring periods that are triggered or otherwise activated, enabled, etc., intermittently (e.g., periodically, aperiodically, etc.) or activated, released, etc., during the operation of the device 100. A monitoring period may, for example, have a duration of 10 milliseconds (ms) or any other duration and be triggered at periodic intervals of 10 seconds (s) or any other periodic interval. The control circuit arrangement 130 further defines several time intervals within the monitoring period and assigns each time interval to the transmit power outputs 120A-H. Consequently, according to some examples, the number of time intervals in a monitoring period is equal to the number of transmit power outputs 120A-H. For example,If there are eight (8) transmit power outputs 120A-H, then the control circuit arrangement 130 can define eight (8) time intervals within a given monitoring period.

[0015] According to the illustrated example, the control circuit arrangement 130 causes the transmit power outputs 120A-H of the PAs 115A-H to be activated sequentially for respective time intervals within a monitoring period. For example, in the first time interval of a monitoring period, the control circuit arrangement 130 can cause the transmit power output 120A of the PA 115A to be active and the other transmit power outputs 120B-H of the PAs 115B-H to be inactive. Then, in a second interval of the monitoring period, the control circuit arrangement 130 can cause the transmit power output 120B of the PA 115B to be active and the other transmit power outputs 120A,CH of the PAs 115A,CH to be inactive.According to this example, the control circuit arrangement 130 continues to perform similar operations until the last time interval of the monitoring period, during which the control circuit arrangement 130 causes the transmit power output 120H of the PA 115H to be active and the other transmit power outputs 120A-C of the PAs 115A-C to be inactive. According to some examples, during normal operation outside of a monitoring period, the control circuit arrangement 130 controls or otherwise causes one, more, or all of the transmit power outputs 120A-H of the PAs 115A-H to be activated.

[0016] To facilitate the control of the PAs 115A-H, as described above, the control circuit arrangement 130 of the illustrative example includes exemplary transmit control outputs 160 coupled to the respective control inputs 165A-H of the PAs 115A-H. According to the illustrated example, the control circuit arrangement 130 uses the transmit control outputs 160 to selectively determine that the control inputs 165A-H of the PAs 115A-H individually enable (or release, turn on, etc.) or disable (or lock, turn off, etc.) the PAs 115A-H and consequently their transmit power outputs 120A-H. The PAs 115A-H can be, for example, B. be configured so that a first logic value (e.g. a logic 1 value, a logic 0 value, a logic HIGH value, a logic LOW value, etc.) applied to the control input 165A-H of a specific PA 115A-H causes the transmit power output 120A-H to activate (or enable, turn on, etc.) this PA.) whereas another second logic value (e.g., a logic 0, a logic 1, a logic LOW, a logic HIGH, etc.) applied to the control input 165A-H of this particular PA 115A-H causes the transmit power output 120A-H of the PA to be disabled (or locked, turned off, etc.). According to some examples, the transmit control outputs 160 of the control circuit arrangement 130 are implemented by one or more terminal pins, one or more lines, one or more traces, one or more buses, etc.

[0017] As illustrated in the example, the control circuit arrangement 130 also includes exemplary switch control outputs 170, which are coupled to respective control inputs 175A-H of the switches 145A-H. The control circuit arrangement 130 uses the switch control outputs 170 to selectively set the control inputs 175A-H of the switches 145A-H in order to individually couple (or connect to, etc.) or decouple (or disconnect, etc.) the respective contact pads 140A-H and consequently the respective transmit power outputs 120A-H to the transmission line 135. The switches 145A-H can be configured to, for example, B. be configured such that a first logic value (e.g., a logic 1 value, a logic 0 value, a logic HIGH value, a logic LOW value, etc.) applied to the control input 175A-H of a specific switch 145A-H causes that switch to be activated (or enabled, closed, etc.), whereas another second logic value (e.g.,A logical 0 value, a logical 1 value, a logical LOW value, a logical HIGH value, etc., applied to the control input 175A-H of this particular switch 145A-H causes the switch to be deactivated (or locked, opened, etc.). According to some examples, the switch control outputs 170 of the control circuit arrangement 130 are implemented by one or more terminal pins, one or more lines, one or more traces, one or more buses, etc. According to some examples, during normal operation outside of a monitoring period, the control circuit arrangement 130 controls or otherwise causes one or more or all of the switches 145A-H to be activated (or enabled, closed, etc.) or otherwise decouple (e.g., disconnect) their respective transmit power outputs 120A-H from the transmission line 135.Further details concerning how the control circuit arrangement 130 works to selectively control the switches 145A-H during a monitoring period are provided below.

[0018] According to the illustrated example, the contact pads 140A-H couple the transmit power outputs 120A-H of the PAs 115A-H to the antennas 110A-H and the switches 145A-H of the transmission line power combiner 105. The contact pads 140A-H can be implemented by any conductive material, conductive structure, etc., in any suitable arrangement. According to some examples, the contact pads 140A-H are implemented by ground-signal-ground (GSG) contact pads. According to some examples, such as... B. in the examples where the antennas 110A-H are located inside the device 100, the contact surfaces 140A-H are omitted, since the transmit power outputs 120A-H of the Pas 115A-H can be internally coupled to the antennas 110A-H and the switches 145A-H of the transmission line power combiner 105.

[0019] As illustrated in the example, the 145A-H switches can be implemented using any type of switching technology. According to some examples, the 145A-H switches can be implemented using one or more exemplary 145A-H transistor switches. The 145A-H transistor switches can be, for example, n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs). According to some examples, one or more of the 145A-H transistor switches can be n-channel field-effect transistors (n-channel FETs), n-channel insulated-gate bipolar transistors (n-channel IGBTs), n-channel junction field-effect transistors (n-channel JFETs), NPN bipolar transistors (NPN-BJTs), or, with minor modifications, equivalent p-type devices, or any combination thereof. According to some examples, one or more of the transistor switches can be 145A-H p-channel MOSFETs.According to some examples, one or more of the 145A-H transistor switches can be p-channel FETs, p-channel IGBTs, p-channel JFETs, PNP BJTs, or, with minor modifications, equivalent N-type devices, or any combination thereof. According to some examples, one or more of the 145A-H transistor switches can be depletion-operated devices, drain-extended devices, enhancement-operated devices, natural transistors, or another type of device-structure transistor. According to some examples, one or more of the 145A-H transistor switches can be implemented in / over a silicon (Si), silicon carbide (SiC), gallium nitride (GaN), or gallium arsenide (GaAs) substrate. According to some examples, the 145A-H switches are shunt switches.

[0020] According to the examples where the switches are transistor switches 145A-H, the impedance of a given transistor switch 145A-H is proportional to its channel length (also referred to as the length of the transistor switch) and inversely proportional to its channel width (also referred to as the width of the transistor switch). Furthermore, according to some examples, the widths of the transistor switches 145A-H are limited to a set of available widths. For example, the transistor switches 145A-H may have widths limited to a set of available widths that includes 16 micrometers (µm), 32 µm, 50 µm, and so on. According to some examples, the widths of the transistor switches 145A-H are the same. However, according to some examples, one or more of the transistor switches 145A-H may have widths that differ from the widths of the other transistor switches 145A-H.

[0021] Fig. Figure 2 illustrates a first exemplary implementation 105A of the transmission line power combiner 105 according to Fig. 1. The exemplary 105A transmission line power combiner according to Fig. 2 supports two (2) transmitters and therefore contains two (2) contact pads 140A-B and two (2) switches 145A-B, which have been described above. The transmission line power combiner 105A also contains a first exemplary implementation 135A of the transmission line 135, which is implemented in the transmission line power combiner 105 according to Fig. 1 is included. The example transmission line 135A in Fig. 2 is an example of a symmetrical transmission line 135A, where consequently the transmission line power combiner 105A is an example of a symmetrical transmission line power combiner 105A.

[0022] According to the illustrated example, the combination of contact surface 140A and switch 145A assigned to the first transmitter is connected to a first position 205 on the transmission line 135A (which is in Fig. 2 is labelled “TX1”), while the combination of contact surface 140B and switch 145B assigned to the second transmitter is connected to a second position 210 on the transmission line 135A (which is in Fig. 2 (designated with "TX2") is coupled. Furthermore, the second position 210 (TX2) corresponds to the termination end 150A of the transmission line 135A. As in Fig. As illustrated in Figure 2, the transmission line 135A is structured such that the feedback path from the first position 205, assigned to the first transmitter (TX1), to the output 155A of the transmission line 135A, and the feedback path from the second position 210, assigned to the second transmitter (TX2), to the output 155A of the transmission line 135A, have the same or substantially similar lengths. Such a structure results in the feedback signals assigned to the first and second transmitters experiencing the same or substantially similar attenuation, thus imparting little to no mismatch to the two feedback signals. Consequently, the monitoring circuit arrangement 125 can apply the same gain factor to both feedback signals and, consequently, use the same number of one or more amplifiers for both feedback paths.

[0023] Fig. Figure 3 illustrates a second exemplary implementation 105B of the transmission line power combiner 105 according to Fig. 1. The exemplary transmission line power combiner 105B according to Fig. 3 supports eight (8) transmitters and therefore contains eight (8) contact pads 140A-H and eight (8) switches 145A-H, as described above. The transmission line power combiner 105B also contains a second exemplary implementation 135B of the transmission line 135, which is implemented in the transmission line power combiner 105 according to Fig. 1 is included. The exemplary transmission line 135B in Fig. Figure 3 is another example of a symmetrical 135B transmission line, where, consequently, the 105B transmission line power combiner is another example of a symmetrical 105B transmission line power combiner. Furthermore, the 135B transmission line shows, according to Fig. 3 regarding the transmission line 135A to Fig. 2 potential disadvantages of using symmetrical transmission lines in power combiners.

[0024] According to the in Fig. The illustrated example 3 shows the combination of contact surface 140A and switch 145A assigned to the first transmitter at a first position 305 on the transmission line 135B (which is shown in Fig. 3, designated “TX1”), is coupled to the second transmitter, the combination of contact surface 140B and switch 145B is connected to a second position 310 on the transmission line 135B (which is in Fig. 3, designated “TX2”), etc., wherein the combination of contact surface 140H and switch 145H, which is assigned to the eighth transmitter, is connected to an eighth position 340 on transmission line 135B (which is in Fig. 3 (designated with "TX8") is coupled. Furthermore, the eighth position 340 (TX8) corresponds to the termination end 150B of transmission line 135B. As in Fig. As illustrated in Figure 3, the transmission line 135B is structured such that the feedback paths from the various positions 305-340, which are assigned to the first through eighth transmitters (TX1-TX8), to the output 155B of the transmission line 135B have the same or substantially similar lengths. Such a structure results in the feedback signals assigned to the first through eighth transmitters experiencing the same or substantially similar attenuation, thus introducing little to no mismatch to the eight feedback signals. Consequently, the monitoring circuit arrangement 125 can apply the same gain factor to the various feedback signals.

[0025] As in Fig. Figure 3 illustrates how the transmission line 135B uses two layers compared to the transmission line 135A. Fig. Two layers are used, but four (4) layers are required to implement its symmetrical structure. The increased number of layers is due to the increased number of transmitters coupled to the 135B transmission line. According to some examples, a symmetrical transmission line with a structure similar to the 135B transmission line requires a number of layers equal to half the number of transmitters to be coupled to the transmission line.

[0026] According to some examples, the width of a layer of the 135B transmission line is 40 µm. Furthermore, according to some examples, the total length of the 135B transmission line increases with the number of transmitters, since the widths of the 140A-H contact pads (which can be, for example, GSG contact pads) define a minimum distance between adjacent transmitter connections. With these limitations, the 135B transmission line, according to some examples, occupies a die area of ​​approximately 4 (layers) × 40 µm (width) × 4 mm (length) = 0.64 square millimeters (mm²). 2), which in at least some implementations consumes a significant amount of die space. Furthermore, the total length of the feedback paths of the transmission line 135B results in a total passive loss for the combiner 105B, which, according to some examples, can be approximately 29–32 decibels (dB). Consequently, according to some such examples, the monitoring circuit arrangement 125 may require additional amplifiers and, consequently, additional power dissipation to amplify the feedback signals to adequate levels for subsequent processing.

[0027] Fig. Figure 4 illustrates a third exemplary implementation 105C of the transmission line power combiner 105 according to Fig. 1. The exemplary transmission line power combiner 105C according to Fig. 4 supports eight (8) transmitters and therefore contains eight (8) contact pads 140A-H and eight (8) switches 145A-H, as described above. The transmission line power combiner 105C also contains a third exemplary implementation 135C of the transmission line 135, which is implemented in the transmission line power combiner 105 according to Fig. 1 is included. The exemplary transmission line 135C according to Fig. 4 is an example of an asymmetric transmission line 135C, wherein the transmission line power combiner 105B is consequently an example of an asymmetric transmission line power combiner 105C.

[0028] According to the in Fig. The illustrated example 4 shows the combination of contact surface 140A and switch 145A assigned to the first transmitter at a first position 405 on the transmission line 135C (which is shown in Fig. 3, designated “TX1”), is coupled to the second transmitter, the combination of contact surface 140B and switch 145B is connected to a second position 410 on the transmission line 135C (which is in Fig. 3, designated “TX2”), etc., wherein the combination of contact surface 140H and switch 145H assigned to the eighth transmitter is connected to an eighth position 440 on the transmission line 135C (which is in Fig. 3, designated "TX8"), is coupled. Furthermore, the eighth position 440 (TX8) corresponds to the termination end 150C of transmission line 135C. As in Fig. As illustrated in Figure 4, the asymmetric transmission line 135C is implemented with a single layer, whereby the width of the asymmetric transmission line 135C is reduced by a factor of four (4) compared to the symmetric transmission line 135B, although both support eight (8) transmitters. Consequently, the asymmetric transmission line 135C occupies a die area of ​​40 µm (width) × 4 mm (length) = 0.16 mm². 2 , which is four times smaller than the area of ​​the symmetrical 135B transmission line.

[0029] As also in Fig. As illustrated in Figure 4, however, transmission line 135C is structured such that the feedback paths from the various positions 405-440, which are assigned to the first through eighth transmitters (TX1-TX8), to the output 155C of transmission line 135C have different lengths. For example, the feedback path from position 405 (TX1) to output 155C of transmission line 135C may be approximately 10 µm long, whereas the feedback path from position 440 (TX8) to output 155C of transmission line 135C may be approximately 4 millimeters (mm). Such a structure results in the feedback signals assigned to the first through eighth transmitters experiencing different attenuation, potentially leading to significant mismatches between the eight feedback signals.

[0030] Fig. Figure 5 illustrates, for example, exemplary performance results 500 for the asymmetric transmission line power combiner 105C, which is installed in Fig. Figure 4 illustrates this. The performance results 500 demonstrate that the differences in loss between the various feedback paths assigned to the different transmissions can be substantial, such as about 36 dB in the illustrated example. According to some examples, it can be difficult for the monitoring circuit arrangement 125 to compensate for such a large dynamic loss range.

[0031] Fig. Figure 6 illustrates a fourth exemplary implementation 105D of the transmission line power combiner 105 according to Fig. 1. The exemplary transmission line power combiner 105D according to Fig. 6 supports eight (8) transmitters and consequently contains eight (8) switches 145A-H coupled to eight (8) (not shown) contact pads 140A-H, as described above. The transmission line power combiner 105D also contains a fourth exemplary implementation 135D of the transmission line 135, which is implemented in the transmission line power combiner 105 according to Fig. 1 is included. The exemplary transmission line 135D according to Fig. Figure 6 is another example of an asymmetric transmission line 135D, where, consequently, the transmission line power combiner 105D is another example of an asymmetric transmission line power combiner 105D. In contrast to the asymmetric transmission line power combiner 105B according to Fig. 4 is the asymmetric transmission line power combiner 105D according to Fig. 6, however, a small-area, loss-balanced asymmetric transmission line power combiner.

[0032] In the Fig. In the illustrated example 6, the switch 145A assigned to the first transmitter is connected to a first position 605 on the transmission line 135D (which is in Fig. 6, labelled "TX1"), is coupled to the second transmitter, switch 145B is connected to a second position 610 on the transmission line 135D (which is in Fig. 6, designated “TX2”), etc., wherein the switch 145H assigned to the eighth transmitter is connected to an eighth position 640 on the transmission line 135D (which is in Fig. 6, designated "TX8"), is coupled. Furthermore, the eighth position 640 (TX8) corresponds to the termination end 150D of the transmission line 135D. As in Fig. As illustrated in Figure 6, the asymmetric transmission line 135D is implemented with one layer, thus functioning like the asymmetric transmission line 135C. Fig. 4. The width of the asymmetric transmission line 135D is reduced by a factor of four (4) compared to the symmetric transmission line 135B, although both support eight (8) transmitters. Additionally, the length of the transmission line 135D from the first position 605 to the output 155C can be significantly shorter than the length of the transmission line 135B from the first position 305 to the output 155B. Consequently, the asymmetric transmission line 135D occupies, according to Fig. 6 like the asymmetric transmission line 135C after Fig. 4 a die area of ​​40 µm (width) × 4 mm (length) = 0.16 mm 2, which is four times smaller than the area of ​​the symmetrical 135B transmission line. The asymmetrical 135D transmission line can use less metal than the symmetrical 135B transmission line.

[0033] As also in Fig. As illustrated in Figure 6, the transmission line 135D is structured such that the feedback paths from the various positions 605-640, which are assigned to the first to eighth transmitters (TX1-TX8), to the output 155D of the transmission line 135D have different lengths. For example, the feedback path from position 605 (TX1) to the output 155D of the transmission line 135D can be approximately 10 µm long, whereas the feedback path from position 640 (TX8) to the output 155D of the transmission line 135D can be approximately 4 mm long. As described above, such a structure results in the different feedback paths assigned to the first to eighth transmitters experiencing different passive losses along the transmission line 135D. Regarding the asymmetric transmission line power combiner 105C according to Fig. The asymmetric transmission line power combiner 105D achieves 4 after Fig. 6. However, there is a reduced overall damping / loss mismatch between the different feedback paths.

[0034] The asymmetric transmission line power combiner 105D according to Fig. 6 achieves such a reduction in total attenuation / loss mismatch using switches 140A-H with progressive width scaling from output end 155D to termination end 150D of transmission line 135D, as shown in Fig. Figure 6 shows that, due to the inversely proportional relationship between switch width and impedance described above, such progressive width scaling results in the switches 140A-H coupled to the transmission line 135D exhibiting a progressive impedance scaling from the output end 155D to the termination end 150D of the transmission line 135D. In the asymmetric transmission line power combiner 105D according to Fig. For example, switches 140A-D (located closest to the output end 155D of the transmission line 135D) have widths of 16 µm, switches 140E-G (located further from the output end 155D of the transmission line 135D) have widths of 32 µm, and switch 145H (located furthest from the output end 155D of the transmission line 135D) has a width of 50 µm.As a result, switches 140A-D (located closest to the output end 155D of the transmission line 135D) exhibit higher impedances than switches 140E-H (located further away from the output end 155D of the transmission line 135D), while switches 140E-G (located further away from the output end 155D of the transmission line 135D than switches 140A-C, but closer than switch 145H) exhibit lower impedances than switches 140A-C, but higher impedances than switch 145H, with switch 145H (located furthest from the output end 155D of the transmission line 135D) exhibiting a lower impedance than switches 140A-G. A switch with a width of 16 µm exhibits, for example, a lower impedance than switches 140A-G. For example, a switch with a width of 50 µm has an impedance of approximately 35 ohms, whereas it has an impedance of approximately 10 ohms. Of course, the 140A-H switches can have different widths and impedances, as shown in other examples.According to such examples, however, the widths of the switches 140A-H are the same or increase in the direction from the output end 155D to the termination end 150D of the transmission line 135D, causing the impedances of the switches 140A-H to be the same or to increase (e.g., by at least twenty percent or some other amount) in the direction from the output end 155D to the termination end 150D of the transmission line 135D. Furthermore, according to some examples, the lengths of the sections of the transmission line 135D between two adjacent transmitter link positions 605-640 can be designed to be about one-quarter of the lambda length of the transmission line (where the lambda length is about 1.4 mm according to the illustrative example) to obtain the advantage of impedance inversion.

[0035] According to some examples, the channel width of switch 145H is at least two, three, or four times greater than the channel width of switch 145A (i.e., a ratio of at least 2, 3, or 4). Consequently, the impedance of switch 145A is at least two, three, or four times greater than the channel width of switch 145H. The channel width of switch 145E can be at least 1.5, 2.0, or 2.5 times greater than the channel width of switch 145A (i.e., a ratio of at least 1.5, 2.0, or 2.5). The impedance of switch 145A is at least 1.5, 2.0, or 2.5 times greater than the channel width of switch 145E. And the channel width of switch 145H can be at least 1.2, 1.5, or 2.0 times greater than the channel width of switch 145E (i.e., a ratio of at least 1.2, 1.5, or 2.0). The impedance of switch 145E is at least 1.2, 1.5, or 2.0 times greater than the channel width of switch 145H.According to some examples, all switches 145A-145H have the same channel length. These dimensions and parameters are merely examples of how the techniques of this revelation are to be implemented.

[0036] The asymmetric transmission line power combiner 105D according to Fig. 6 also achieves its reduction of the overall attenuation / loss mismatch through a novel operation of the switches 140A-H by the control circuit arrangement 130. In Fig. 1. The control circuit arrangement 130 controls the switches 140A-H to couple different combinations of the transmit power outputs 120A-H to the transmission line 135D, depending on which transmit power output 120A-H is active during a specific time interval of a monitoring period. An exemplary operation 700 of the control circuit arrangement 130 for controlling the switches 140A-H is shown in Fig. 7 illustrates.

[0037] Again in Fig. For an implementation of the device 100 with eight (8) transmitters corresponding to the transmission line 135D, there are eight (8) transmit power outputs 120A-H from eight (8) PAs 115A-H, which are coupled to the transmission line 135D at positions 605-640 (i.e., TX1-8) via the eight (8) contact pads 140A-H and switches 145A-H. As described above, the control circuit arrangement 130 operates to cause the transmit power outputs 120A-H of the PAs 115A-H to be sequentially activated for respective time intervals within a monitoring period. Furthermore, with regard to exemplary operation 700, Fig. 7. The control circuit arrangement 130, during a given time interval in which a specific transmit power output 120A-H is active, causes the specific switch 145A-H connected to the active transmit power output 120A-H to couple that transmit power output 120A-H to the transmission line 135D. Furthermore, the control circuit arrangement 130 causes all the switches 145A-H connected at positions 605-640 on the transmission line 135D between the output end 155D and the position of the switch 145A-H connected to the active transmit power output 120A-H to couple their respective transmit power outputs 120A-H to the transmission line 135.Furthermore, the control circuit arrangement 130 works to cause all of the switches 145A-H, which are coupled at positions 605-640 on the transmission line 135D between the position of the switch 145A-H which is coupled to the active transmit power output 120A-H and the termination end 150D, to decouple their respective transmit power outputs 120A-H from the transmission line 135.

[0038] If the switches 145A-H are, for example, shunt switches, the control circuit arrangement 130 operates during a specific time interval in which a particular transmit power output 120A-H is active, to cause the specific switch 145A-H connected to that transmit power output 120A-H to be deactivated (i.e., opened), thus coupling the active transmit power output 120A-H to the transmission line 135D. Furthermore, the control circuit arrangement 130 operates to cause each of the switches 145A-H coupled at positions 605-640 on the transmission line 135D between the output end 155D and the position of the switch 145A-H coupled to the active transmit power output 120A-H to be deactivated (i.e., opened).Furthermore, the control circuit arrangement 130 works to cause each of the switches 145A-H, which are coupled at positions 605-640 on the transmission line 135D between the position of the switch 145A-H that is coupled to the active transmit power output 120A-H and the termination end 150D, to be activated (i.e., opened), thus decoupling their respective transmit power outputs 120A-H from the transmission line 135D.

[0039] Fig. Figure 7 illustrates such an operation 700 in the case where the control circuit arrangement 130 causes the transmit power output 120D corresponding to switch 145D to be active during a time interval of a monitoring period. According to this example, the control circuit arrangement 130 causes switch 145D to be deactivated (e.g., open). The control circuit arrangement 130 also causes switches 145A-C, located between the output end 155D of the transmission line 135D and switch 145D, to be deactivated (e.g., open). The control circuit arrangement 130 further causes switches 145E-H, located between switch 145D and the termination end 150D of the transmission line 135D, to be activated (e.g., closed). More mathematically expressed, when TX <n>(the nth transmitter) is looped back (e.g. TX4 in Fig. (7 is looped back), the TX<1:n - 1> shunt switches are deactivated (e.g. open), while the TX <n:8>The shunt switches are activated (e.g., closed). Such operation allows the specific transmitter that is looped back to experience a relatively low impedance in the direction towards the output end 155D of the transmission line 135D and a relatively high impedance in the direction towards the termination end 150D of the transmission line 135D, causing the feedback signal to flow towards the output end 155D. This type of operation also improves the intermediate transmitter isolation across the loop path when a specific transmitter is active.

[0040] Fig. Figure 8 illustrates an exemplary equivalent circuit 800 for modeling the impedance in the asymmetric transmission line power combiner 105D according to Fig. 6. The equivalent circuit 800 models the impedance at a specific switching coupling position 605-640 in the direction towards the termination end 150D of the transmission line 135D. In the equivalent circuit 800, the impedance of the transmission line 135D is represented by the variable Z0, while the impedance of the switch 145A-H at the specific switching coupling position 605-640 is represented by the variable Z L is represented. As in Fig. As shown in Figure 8, using the equivalent circuit 800, the impedance at the special switch coupling position 605-640 in the direction to the termination end 150D of the transmission line 135D is given by Equation 1: Zin=Z02ZL

[0041] Fig. Figure 8 also illustrates the evaluation of the equivalent circuit 800 for the exemplary operation 700 according to Fig. 7. In operation 700, the impedance of transmission line 135D is 50 ohms, while the impedance of switch 145D is 35 ohms. Consequently, according to Equation 1, the impedance at switch coupling position 620 (corresponding to switch 145D) towards the termination end 150D of transmission line 135D is 71 ohms. Furthermore, the impedance towards the output end 155D of transmission line 135D is the line impedance of 50 ohms, resulting in a lower impedance towards the output end 155D than towards the termination end 150D.

[0042] Fig. Figure 9 illustrates exemplary performance results for the 900 in Fig. Figure 6 illustrated the asymmetric transmission line power combiner 105D. Performance results 900 represent the loss frequency profiles for the various feedback paths from positions 605-640, assigned to the eight transmitters (TX1-TX8), to output 155B of transmission line 135B. Results 900 show that the differences in loss between the various feedback paths for the asymmetric transmission line power combiner 105D are approximately 5 dB, which is significantly smaller than the approximately 36 dB loss caused by the other asymmetric transmission line power combiner 105C, which is shown in Figure 6. Fig. As illustrated in Figure 4, such a small dynamic loss range can be handled by an amplifier in the monitoring circuit arrangement 125, according to some examples. Furthermore, according to this example, the absolute feedback path loss for the asymmetric transmission line power combiner 105D is 7-9 dB smaller than the loss for the symmetric transmission line power combiner 105B described above. According to some examples, the advantages of the asymmetric transmission line power combiner 105D are even more pronounced for a higher number of transmitters, such as sixteen transmitters, as in an imaging radar.

[0043] The Fig. Figures 10-11 illustrate exemplary performance results for alternative switch configurations used in the 105D asymmetric transmission line power combiner. Fig. 6 can be used. Fig. Figure 10 illustrates exemplary performance results 1000 for an exemplary implementation where all switches 145A-H have widths of 16 µm. Fig. Figure 11 illustrates exemplary performance results 1100 for an exemplary implementation where all switches 145A-H have widths of 50 µm. Performance results 1000 and 1100 demonstrate that using switches 145A-H with the same widths results in greater differences in loss between the various feedback paths than for the asymmetric transmission line power combiner 105D with progressive scaling of the switch widths.

[0044] The performance results 1000 show, for example, that TX7 exhibits a loss 2-2.7 dB higher than the rest of the transmitters when the 145A-H switches have widths of 16 µm. This is because TX7 sees 50 ohms towards the output end 155D and 71 ohms towards the termination end 150D, which is an almost equal power distribution. A switch with a larger width can provide a lower on-resistance (e.g., a 50 µm switch results in an on-resistance of 10 ohms Ron and a 250-ohm post-impedance inversion). The performance results 1100 show that when the 145A-H switches have widths of 50 µm, TX4 exhibits a loss approximately 4 dB higher than the first three transmitters, TX1-TX3. This is because a 50-µm switch has a larger capacitance than a 16-µm switch, and this capacitance connects the signal from the 135D transmission line in parallel.The feedback signals from the more distant transmitters TX4-8 pass through more switches and consequently experience greater attenuation than the feedback signals from the closer transmitters TX1-3.

[0045] A progressive scaling of the switch size can solve the aforementioned problems. Transmitters closer to the output end 155D of the transmission line 135D experience a high impedance towards the termination end 150D and consequently do not require a large switch. Transmitters further from the output end 155D, however, benefit from a larger switch size. According to the illustrated example, transmitter TX7 experiences the worst signal splitting, and a 50-µm switch at position TX8 corrects this problem. The signals from transmitters further from the output end 155D experience less attenuation as they travel towards the output end 155D due to the capacitances of the 16-µm shunt switches assigned to transmitters TX1-4. This scheme provides low loss for all transmitters and aims to compensate for their losses despite the fact that their signals travel approximately four millimeters different signal paths.

[0046] Fig. Figure 12 illustrates an exemplary use of the equivalent circuit 800 according to 1200. Fig. 8 for modeling the impedance in the asymmetric transmission line power combiner 105D according to Fig. 6.

[0047] The following table compares the characteristics of the 105D asymmetric transmission line power combiner according to Fig. 6 regarding the symmetrical transmission line power combiner 105B according to Fig. 3. Table Parameter SymmetrischerKombinierer 105B AsymmetrischerKombinierer 105D Verlust 29-32 dB 18-23 dB Fläche 0,64 mm 2 0,16 mm 2 Zusätzliche Verstärker 2-3 1-2

[0048] Although the exemplary transmission line power combiner 105D has been described in the context of a device containing eight (8) transmitters, the transmission line power combiner 105D is not limited to this. On the contrary, the transmission line power combiner 105D can be used in a device containing fewer or more transmitters, such as 4 transmitters, 12 transmitters, 16 transmitters, etc.

[0049] According to some examples, the device includes 100 means for controlling power outputs and switches. The means for control can be implemented, for example, by a control circuit arrangement 130. According to some examples, the control circuit arrangement 130 can be implemented by a programmable circuit arrangement, such as the exemplary programmable circuit arrangement 1412 according to Fig. 14, be instantiated. The control circuit arrangement 130 can be implemented, for example, by the exemplary microprocessor 1500 according to Fig. 15 be instantiated, the machine-executable instructions, such as those executed by at least blocks 1305-1335 after Fig. 13 are implemented. According to some examples, the control circuit arrangement 130 can be instantiated by a hardware logic circuit arrangement implemented by an ASIC, an XPU, or the FPGA circuit 1600. Fig. 16 can be implemented by means of a control circuit arrangement 130 that is structured to execute the operations corresponding to the machine-readable instructions. Alternatively, the control circuit arrangement 130 can be instantiated by any other combination of hardware, software, or firmware. For example, the control circuit arrangement 130 can be implemented by at least one or more hardware circuits (e.g., a processor circuit arrangement, a discrete or integrated analog or digital circuit arrangement, an FPGA, an ASIC, an XPU, a comparator, an operational amplifier (op-amp), a logic circuit, etc.) that are configured or structured to execute some or all of the machine-readable instructions or to perform some or all of the operations corresponding to the machine-readable instructions without executing any software or firmware, although other structures are equally suitable.

[0050] Fig. 13 is a flowchart representing exemplary machine-readable instructions and / or exemplary operations 300 that can be carried out and / or instantiated and / or executed by a programmable circuit arrangement to implement the control circuit arrangement 130, which is implemented in an implementation of the device 100 according to Fig. 1, which the asymmetric transmission line power combiner 105D according to Fig. 6 is included. The exemplary machine-readable instructions and / or the exemplary operations 1300 after Fig. 13 begin in block 1305, in which the control circuit arrangement 130 causes the transmit power outputs 120A-H of the device to be sequentially activated for respective time intervals within a monitoring period, as described above. As also described above, the transmit power outputs 120A-H are coupled to the feedback transmission line 135D via switches 145A-H at respective positions 605-640, which are spaced apart along the transmission line 135D.

[0051] In block 1310, the control circuit arrangement 130 cyclically cycles through the time intervals of a monitoring period, as described above. The control circuit arrangement 130 controls or otherwise causes, for example in block 1315, a specific transmit power output 120A-H, which is assigned to the current time interval, to be active and other transmit power outputs 120A-H to be inactive, as described above. In block 1320, the control circuit arrangement 130 controls or otherwise causes the given switch 145A-H, which is connected to the active transmit power output 120A-H, to be deactivated (e.g., by switching it off).The control circuit arrangement 130 controls or otherwise causes other switches 145A-H (if any) that are coupled to transmission line 135D at one or more positions between position 605-640 of the given switch 145A-H associated with the active transmit power output 120A-H and the output end 155D of the transmission line 135D to be deactivated (e.g., open). In block 1325, the control circuit arrangement 130 controls or otherwise causes other switches 145A-H (if any) that are coupled to transmission line 135D at one or more positions 605-640 between the position of the given switch 145A-H associated with the active transmit power output 120A-H and the termination end of the transmission line 135D to be activated (i.e., closed).

[0052] In block 1330, the control circuit arrangement 130 determines whether any time intervals remain in the current monitoring period. If any time intervals remain (corresponding to the "yes" output of block 1330), the control circuit arrangement 130 sets the next time interval of the monitoring period as the current time interval in block 1335. Processing then returns to block 1310 and the blocks following it, in which the control circuit arrangement 130 controls the power outputs 120A-H and the switches 145A-H for the next time interval of the monitoring period, as described above. However, if no time intervals remain (corresponding to the "no" output of block 1330), then the exemplary machine-readable instructions and / or the exemplary operations 1300 terminate after Fig. 13.

[0053] Fig. Figure 14 is a block diagram of an exemplary programmable circuit arrangement platform 1400, which is structured to include one or more of the exemplary machine-readable instructions or exemplary operations according to Fig. 13 to execute or instantiate and / or to execute and instantiate in combination to execute the device 100 according to Fig. 1 and Fig. 6 to implement. The programmable circuit arrangement 1400 can be, for example, an ADAS, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a cell phone, a smartphone, a tablet such as an iPad™), a personal digital assistant (PDA), an internet device, a DVD player, a CD player, a digital video recorder, a Blu-ray player, a game console, a personal video recorder, a set-top box, a headset (e.g., an augmented reality (AR) headset, a virtual reality (VR) headset, etc.), or any other portable device or any other type of computing or electronic device.

[0054] The programmable circuit arrangement 1400 of the illustrated example contains a programmable circuit arrangement 1412. The programmable circuit arrangement 1412 of the illustrated example is hardware. The programmable circuit arrangement 1412 can be implemented, for example, by one or more integrated circuits, one or more logic circuits, one or more FPGAs, one or more microprocessors, one or more CPUs, one or more GPUs, one or more DSPs, or one or more microcontrollers from any desired family or manufacturer. The programmable circuit arrangement 1412 can be implemented by one or more semiconductor-based (e.g., silicon-based) devices. According to this example, the programmable circuit arrangement 1412 implements the monitoring circuit arrangement 125 and the control circuit arrangement 130.

[0055] The programmable circuit arrangement 1412 of the illustrated example includes a local memory 1413 (e.g., a cache, registers, etc.). The programmable circuit arrangement 1412 of the illustrated example is connected via a bus 1418 to a main memory 1414, 1416, which contains volatile memory 1414 and non-volatile memory 1416. The volatile memory 1414 can be implemented by one or more synchronous dynamic read / write (SDRAM) memories, dynamic read / write (DRAM) memories, dynamic RAMBUS® read / write (RDRAM®) memories, or any other type of RAM device. The non-volatile memory 1416 can be implemented by one or a combination of flash memory or any other desired type of storage device. Access to the main memory 1414, 1416 of the illustrated example is controlled by a memory control unit 1417.According to some examples, the memory control unit 1417 can be implemented by one or more integrated circuits, logic circuits, microcontrollers from any desired family or manufacturer, or by any other type of circuit arrangement to manage the flow of data going to and from the main memory 1414, 1416.

[0056] The programmable circuit assembly platform 1400 of the illustrated example also includes an interface circuit assembly 1420. The interface circuit assembly 1420 can be implemented by hardware according to any type of interface standard, such as an Ethernet interface, a Universal Serial Bus interface (USB interface), a Bluetooth interface, a Near Field Communication (NFC) interface, a Peripheral Component Interconnection (PCI) interface, or a Peripheral Component Interconnection Express (PCIe) interface. According to the illustrated example, the interface circuit assembly implements the antennas 110A-H, the PAs 115A-H, the transmission line 135D, the contact pads 140A-H, and the switches 145A-H.

[0057] As illustrated in the example, one or more input devices 1422 are connected to the interface circuit arrangement 1420. The one or more input devices 1422 enable a user (e.g., a human user, a machine user, etc.) to input one or a combination of data or commands into the programmable circuit arrangement 1412. The one or more input devices 1422 can be implemented, for example, by one or a combination of an audio sensor, a microphone, a camera (still image or video), a keyboard, a button, a mouse, a touchscreen, a keypad, a trackball, an isopoint device, or a speech recognition system.

[0058] Furthermore, one or more output devices 1424 are connected to the interface circuit arrangement 1420 of the illustrated example. The one or more output devices 1424 can be implemented, for example, by one or a combination of display devices (e.g., a light-emitting diode (LED), an organic light-emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube display (CRT), an in-plane switching display (IPS), a touchscreen, etc.), a tactile output device, a printer, or a loudspeaker. The interface circuit arrangement 1420 of the illustrated example therefore includes one or a combination of a graphics driver card, a graphics driver chip, or a graphics processing unit (GPU) circuit arrangement.

[0059] The interface circuit arrangement 1420 of the illustrated example also includes a communication device, such as one or a combination of a transmitter, a receiver, a transmitter / receiver, a modem, a home gateway, a wireless access point, or a network interface, to facilitate the exchange of data with external machines (e.g., computing devices of any kind) through a network 1426. Communication may take place, for example, through an Ethernet connection, a digital subscriber line (DSL) connection, a telephone line connection, a coaxial cable system, a satellite system, a wireless out-of-line system, a wireless line-of-sight system, a cellular telephone system, an optical link, etc.

[0060] The programmable circuit arrangement platform 1400 of the illustrated example also includes one or more mass storage disks or devices 1428 for storing one or more pieces of firmware, software, or data. Examples of such mass storage disks or devices 1428 include one or more magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray discs, CDs, DVDs, etc.), RAID systems, or solid-state storage disks or devices such as flash memory devices and SSDs.

[0061] The machine-readable instructions 1432, which are provided by the machine-readable instructions according to Fig. 13 can be implemented, can be stored in one or a combination of the mass storage device 1428, in the volatile memory 1414, in the non-volatile memory 1416 or in at least one non-transient computer-readable storage medium, such as a CD or DVD, which may be removable.

[0062] Fig. Figure 15 is a block diagram of an exemplary implementation of the programmable circuit arrangement 1412 according to Fig. 14. According to this example, the programmable circuit arrangement 1412 is according to Fig. 14 is implemented by a microprocessor 1500. The microprocessor 1500 can be, for example, a general-purpose microprocessor (e.g., a general-purpose microprocessor circuit arrangement). The microprocessor 1500 executes some or all of the machine-readable instructions of the flowchart. Fig. 13 out to the control circuit arrangement 130 after Fig. 1 effectively instantiate as logic circuits to perform operations corresponding to these machine-readable instructions. According to some such examples, the control circuit arrangement 130 is implemented according to Fig. 1 is instantiated by the hardware circuitry of the microprocessor 1500 in combination with the machine-readable instructions. The microprocessor 1500 can be implemented, for example, by a multi-core hardware circuit arrangement, such as a CPU, DSP, GPU, XPU, etc. Although it can contain any number of exemplary cores 1502 (e.g., 1 core), the microprocessor 1500 in this example is a multi-core semiconductor device containing N cores. The cores 1502 of the microprocessor 1500 can operate independently or work together to execute machine-readable instructions. The machine code corresponding to a firmware program, an embedded software program, or a software program can, for example, be executed by one of the cores 1502 or can be executed by several of the cores 1502 at the same or different times.According to some examples, the machine code corresponding to the firmware program, the embedded software program, or the software program is divided into threads and executed in parallel by two or more of the 1502 cores. The software program may correspond to a portion or all of the machine-readable instructions or operations defined by the flowchart. Fig. 13 will be represented.

[0063] The 1502 cores can communicate via a first exemplary bus 1504. According to some examples, the first bus 1504 can be implemented as a communication bus to enable communication between one or more of the 1502 cores. The first bus 1504 can be implemented, for example, as at least one of an integrated circuit bus (I2C bus), a serial peripheral interface bus (SPI bus), a PCI bus, or a PCIe bus. Alternatively, or in addition, the first bus 1504 can be implemented as any other type of computational or electrical bus. The 1502 cores can receive data, instructions, and signals from one or more external devices through an exemplary interface circuit arrangement 1506. The 1502 cores can output data, instructions, and signals to the one or more external devices through the interface circuit arrangement 1506.Although the 1502 cores of this example contain a local memory 1520 (e.g., a Level 1 cache (L1 cache), which can be partitioned into an L1 data cache and an L1 instruction cache), the 1500 microprocessor also contains an example shared memory 1510 that can be shared by the cores (e.g., a Level 2 cache (L2 cache)) for high-speed access to data and instructions. The data and instructions can be transferred by one or a combination of writing to or reading from the shared memory 1510. The local memory 1520 of each of the 1502 cores and the shared memory 1510 can be part of a hierarchy of memory devices that includes multiple levels of cache memory and main memory (e.g., main memory 1414, 1416). Fig. 14). Typically, higher levels of memory in the hierarchy have lower access times and smaller storage capacities than lower levels. Changes at the various levels of the cache hierarchy are managed (e.g., coordinated) by a cache coherence strategy.

[0064] Each Core 1502 can be referred to as a CPU, DSP, GPU, etc., or as any other type of hardware circuit assembly. Each Core 1502 contains a Control Unit Circuit Assembly 1514, an Arithmetic and Logic Circuit Assembly (AL Circuit Assembly) (sometimes referred to as an ALU) 1516, multiple registers 1518, local memory 1520, and a second exemplary bus 1522. Other structures may be present. For example, each Core 1502 may contain a Vector Unit Circuit Assembly, a Single Instruction Multiple Data Unit Circuit Assembly (SIMD Unit Circuit Assembly), a Load / Store Unit Circuit Assembly (LSU Circuit Assembly), a Branch / Jump Unit Circuit Assembly, a Floating Point Unit Circuit Assembly (FPU Circuit Assembly), etc.The control unit circuit arrangement 1514 contains semiconductor-based circuits structured to control (e.g., coordinate) the movement of data within the corresponding core 1502. The AL circuit arrangement 1516 contains semiconductor-based circuits structured to perform one or more mathematical or logical operations on the data within the corresponding core 1502. In some examples, the AL circuit arrangement 1516 performs integer-based operations. In other examples, the AL circuit arrangement 1516 also performs floating-point operations. In still other examples, the AL circuit arrangement 1516 may contain a first AL circuit arrangement that performs integer-based operations and a second AL circuit arrangement that performs floating-point operations. In some examples, the AL circuit arrangement 1516 may be referred to as an arithmetic logic unit (ALU).

[0065] The 1518 registers are semiconductor-based structures for storing data and instructions, such as the results of one or more of the operations performed by the AL circuit arrangement 1516 of the corresponding 1502 core. The 1518 registers can include, for example, one or more vector registers, one or more SIMD registers, one or more general-purpose registers, one or more marker registers, one or more segment registers, one or more machine-specific registers, one or more instruction pointer registers, one or more control registers, one or more error-finding registers, one or more memory management registers, one or more machine check registers, etc. The 1518 registers can be arranged in a bank, as shown in Fig. Figure 15 shows the following. Alternatively, the registers 1518 can be organized in any other arrangement, format, or structure, such as by being distributed throughout the core 1502 to reduce access time. The second bus 1522 can be implemented by at least one I2C bus, SPI bus, PCI bus, or PCIe bus.

[0066] Each Core 1502, or more generally, the Microprocessor 1500, may contain additional or alternative structures to those shown and described above. For example, it may contain one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more converged / common mesh stops (CMSs), one or more shifters (e.g., one or more barrel shifters), or some other circuit arrangement. The Microprocessor 1500 is a semiconductor device manufactured to contain many interconnected transistors to implement the structures described above in one or more integrated circuits (ICs) contained in one or more assemblies.

[0067] The Microprocessor 1500 can include or work in conjunction with one or more accelerators (e.g., an accelerator circuit arrangement, hardware accelerators, etc.). In some examples, the accelerators are implemented by a logic circuit arrangement to perform certain tasks faster and more efficiently than a general-purpose processor can. Examples of accelerators include ASICs and FPGAs, such as those discussed here. A GPU, DSP, or other programmable device can also be an accelerator. The accelerators can be located on the Microprocessor 1500 board, in the same chip assembly as the Microprocessor 1500, or in one or more assemblies separate from the Microprocessor 1500.

[0068] Fig. Figure 16 is a block diagram of another exemplary implementation of the programmable circuit arrangement 1412 according to Fig. 14. According to this example, the programmable circuit arrangement 1412 is implemented by an FPGA circuit arrangement 1600. The FPGA circuit arrangement 1600 can, for example, be implemented by an FPGA. The FPGA circuit arrangement 1600 can, for example, be used to perform the operations that would otherwise be performed by the exemplary microprocessor 1500 according to Fig. 15 could be executed, which executes the corresponding machine-readable instructions. However, once configured, the FPGA 1600 circuit assembly instantiates the operations and functions corresponding to the machine-readable instructions in hardware and can therefore often execute the operations / functions faster than they could be executed by a general-purpose microprocessor running the corresponding software.

[0069] Specifically, unlike the microprocessor described above, it contains 1500 according to Fig. 15 (which is a universal device that can be programmed to execute some or all of the steps specified by one or more of the flowcharts) Fig. 13 represented machine-readable instructions, but its interconnections and logic circuit arrangement are fixed once it is manufactured) the FPGA circuit arrangement 1600 of the example according to Fig. 16 interconnections and a logic circuit arrangement which, after manufacture, can be configured, structured, programmed and interconnected in different ways, for example to instantiate some or all of the operations / functions corresponding to the machine-readable instructions provided by one or more flowcharts according to Fig. 13. In particular, the FPGA circuit arrangement 1600 can be viewed as an arrangement of logic gates, interconnects, and switches. The switches can be programmed to change how the logic gates are interconnected by the interconnects, effectively forming one or more dedicated logic circuits (except and until the FPGA circuit arrangement 1600 is reprogrammed). The configured logic circuits allow the logic gates to work together in different ways to perform different operations on the data received by the input circuit arrangement. These operations may correspond to some or all of the instructions (e.g., of the software and / or firmware) provided by the one or more flowcharts according to Fig. 13 can be represented. As such, the FPGA circuit arrangement 1600 can be configured and / or structured to include some or all of the operations / functions that correspond to the machine-readable instructions of one or more flowcharts. Fig. 13 correspond to being effectively instantiated as dedicated logic circuits to execute the operations / functions corresponding to these software instructions in a dedicated manner analogous to an ASIC. Therefore, the FPGA circuit arrangement 1600 can perform the operations / functions corresponding to some or all of the machine-readable instructions according to Fig. 13, execute faster than the universal microprocessor can execute the same.

[0070] According to the example Fig. 16. The FPGA circuit arrangement 1600 is configured and / or structured in response to being programmed (and / or reprogrammed one or more times) based on a binary file. According to some examples, the binary file can be compiled and / or generated based on instructions in a hardware description language (HDL), such as Lucid, the hardware description language (VHDL) for very fast integrated circuits (VHSIC), or Verilog. A user (e.g., a human user, a machine user, etc.) can, for example, write code or a program corresponding to one or more operations / functions in an HDL; the code / program can be translated into a low-level language as needed; and the code / program (e.g., the code / program in the low-level language) can be translated into the binary file (e.g., by a compiler, a software application, etc.).According to some examples, the FPGA circuit arrangement can be 1600 according to . Fig. 16 access and / or load the binary file to cause the FPGA circuitry 1600 to Fig. 16 is configured and / or structured to execute one or more operations / functions. The binary file can be implemented, for example, by one or a combination of a bitstream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), or machine-readable instructions, as specified for the FPGA circuit arrangement 1600 according to Fig. 16 are accessible to the FPGA circuit arrangement 1600 according to Fig. 16 or to configure and / or structure one or more sections thereof.

[0071] According to some examples, the binary file is compiled, generated, transformed, and / or otherwise output by a unified software platform used to program FPGAs. The unified software platform might, for example, translate first instructions (e.g., code or a program) corresponding to one or more operations / functions into a higher-level language (e.g., C, C++, Python, etc.) into second instructions corresponding to the one or more operations / functions in an HDL. According to some such examples, the binary file is then compiled, generated, and / or otherwise output by the unified software platform based on these second instructions. According to some examples, the FPGA circuit arrangement 1600 can be... Fig. 16 access and / or load the binary file to cause the FPGA circuit arrangement to 1600 after Fig. 16 is configured and / or structured to execute one or more operations / functions. The binary file can be implemented, for example, by one or a combination of a bitstream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), or machine-readable instructions, as specified for the FPGA circuit arrangement 1600 according to Fig. 16 are accessible to the FPGA circuit arrangement 1600 according to Fig. 16 or to configure or structure one or more sections thereof.

[0072] The FPGA circuit arrangement 1600 according to Fig. Reference 16 contains an exemplary input / output circuit arrangement (I / O circuit arrangement) 1602 for receiving data from and / or outputting data to at least one exemplary configuration circuit arrangement 1604 or external hardware 1606. The configuration circuit 1604 may, for example, be implemented by an interface circuit arrangement capable of receiving a binary file, which may be implemented by one or more bitstreams, data, or machine-readable instructions for configuring the FPGA circuit arrangement 1600 or one or more sections thereof. According to some such examples, the configuration circuit arrangement 1604 may receive the binary file from one or a combination of a user, a machine (e.g., a hardware circuit arrangement), or a FPGA.a programmable or dedicated circuit arrangement) that can implement an artificial intelligence / machine learning (AI / ML) model to generate the binary file, etc.) or any and / or any combination thereof. According to some examples, the external hardware 1606 can be implemented by an external hardware circuit arrangement. The external hardware 1606 can, for example, be implemented by the microprocessor 1500 according to... Fig. 15 will be implemented.

[0073] The FPGA circuit arrangement 1600 also includes an arrangement of an exemplary logic gate circuit arrangement 1608, several exemplary configurable interconnects 1610, and an exemplary memory circuit arrangement 1612. The logic gate circuit arrangement 1608 and the configurable interconnects 1610 are configurable to instantiate one or more operations / functions that perform at least some of the machine-readable instructions according to Fig. 13 and / or other desired operations may correspond to the following. Fig. The 1608 logic gate circuit assembly shown is manufactured in blocks or groups. Each block contains semiconductor-based electrical structures that can be configured into logic circuits. According to some examples, the electrical structures include logic gates (e.g., AND gates, OR gates, NOR gates, etc.) that provide the basic building blocks for logic circuits. Electrically controllable switches (e.g., transistors) are present within each of the 1608 logic gate circuit assemblies to allow the configuration of one or a combination of the electrical structures or logic gates to form circuits that perform desired operations / functions. The 1608 logic gate circuit assembly may also include other electrical structures, such as lookup tables (LUTs), registers (e.g., flip-flops or catch-all registers), multiplexers, etc.

[0074] The configurable interconnections 1610 of the illustrated example are conductive paths, conductor tracks, vias or the like, which may contain electrically controllable switches (e.g. transistors) whose state can be changed by programming (e.g. using an HDL instruction language) to enable or disable one or more connections between one or more of the logic gate circuit arrangement 1608 in order to program desired logic circuits.

[0075] The memory circuit arrangement 1612 of the illustrated example is structured to store one or more results of one or more operations performed by corresponding logic gates. The memory circuit arrangement 1612 can be implemented using registers or the like. According to the illustrated example, the memory circuit arrangement 1612 is distributed among the logic gate circuit arrangement 1608 to facilitate access and increase execution speed.

[0076] The exemplary FPGA circuit arrangement 1600 according to Fig. Reference 16 also includes an exemplary circuit arrangement 1614 for dedicated operations. According to this example, the circuit arrangement 1614 for dedicated operations includes a special-purpose circuit arrangement 1616 that can be called upon to implement frequently used functions, thus avoiding the need to program these functions locally. Examples of such a special-purpose circuit arrangement 1616 include a memory control unit circuit arrangement (e.g., DRAM control unit circuit arrangement), a PCIe control unit circuit arrangement, a clock circuit arrangement, a transmitter / receiver circuit arrangement, a memory, and a multiplier-accumulator circuit arrangement. Other types of special-purpose circuit arrangements may be present. According to some examples, the FPGA circuit arrangement 1600 may also include an exemplary programmable general-purpose circuit arrangement 1618, such as...An example CPU 1620 or an example DSP 1622 may be included. Another programmable universal circuit arrangement 1618, such as a GPU, an XPU, etc., which can be programmed to perform other operations, may also be present, either additionally or alternatively.

[0077] Although the Fig. 15 and Fig. 16 Two exemplary implementations of the programmable circuit arrangement 1412 according to Fig. As illustrated in Figure 14, many other approaches are considered. The FPGA circuit arrangement can, for example, include a CPU on the board, such as one or more of the exemplary CPU 1620 shown in Figure 14. Fig. 15. Therefore, the programmable circuit arrangement 1412 can be according to Fig. 14 also by combining at least the exemplary microprocessor 1500 according to Fig. 15 and the exemplary FPGA circuit arrangement 1600 according to Fig. 16 can be implemented. According to some such hybrid examples, one or more cores can be 1502 after Fig. 15. Execute a first section of the machine-readable instructions, which are determined by one or more flowcharts according to Fig. 13 are represented to perform one or more initial operations / functions, with the FPGA circuit arrangement 1600 following Fig. 16 may be configured and / or structured to execute one or more second operations / functions corresponding to a second section of machine-readable instructions, which are defined by one or more flowcharts according to Fig. 13 may be represented, and / or an ASIC may be configured and / or structured to perform one or more third operations / functions corresponding to a third section of the machine-readable instructions, which are defined by one or more flowcharts according to Fig. 13 will be represented.

[0078] Some or all of the control circuit arrangement 130 according to Fig. 1 can therefore be instantiated at the same or different times. One or more identical and / or different sections of the microprocessor 1500 according to Fig. 15 can be programmed to execute one or more sections of machine-readable instructions at the same and / or different times. According to some examples, one or more identical and / or different sections of the FPGA circuit arrangement 1600 can be executed according to Fig. 16. be configured and / or structured to execute the operations / functions corresponding to one or more sections of machine-readable instructions at the same and / or different times.

[0079] According to some examples, some or all of the control circuit arrangement 130 can be according to Fig. 1. For example, it can be instantiated in one or more threads that are executed simultaneously and / or sequentially. The 1500 microprocessor according to Fig. 15 can, for example, execute machine-readable instructions in one or more threads, which are executed concurrently and / or sequentially. According to some examples, the FPGA circuit arrangement 1600 can be used to... Fig. 16 may be configured and / or structured to execute operations / functions simultaneously and / or sequentially. Furthermore, according to some examples, some or all of the control circuit arrangement 130 may be configured and / or structured to execute operations / functions simultaneously and / or sequentially. Fig. 1. can be implemented within one or more virtual machines or containers running on the 1500 microprocessor. Fig. 15 will be executed.

[0080] According to some examples, the programmable circuit arrangement 1412 can be adapted to Fig. 14 are located in one or more modules. At least one of the microprocessor 1500 after Fig. 15 or the FPGA circuit arrangement 1600 according to Fig. 16 can be located in one or more modules. According to some examples, an XPU can be configured by the programmable circuit arrangement 1412 according to Fig. 14 can be implemented, which may be located in one or more modules. The XPU can, for example, be a CPU (e.g., the 1500 microprocessor). Fig. 15, the CPU 1620 after Fig. 16 etc.) in an assembly, a DSP (e.g. the DSP 1622 according to Fig. 16) in another assembly, a GPU in yet another assembly and an FPGA (e.g. the FPGA circuit arrangement 1600 according to Fig. 16) contained in a further sub-assembly.

[0081] A block diagram illustrating an exemplary software distribution platform 1705 for distributing software, such as the exemplary machine-readable instructions 1432 according to Fig. 14, illustrated by other hardware devices (e.g., one or more hardware devices owned or operated by third parties, by the owner or operator of the software distribution platform), is in Fig. Figure 17 illustrates this. The exemplary software distribution platform 1705 can be implemented by any computer server, data facility, cloud service, etc., capable of storing software and transferring it to other computing devices. The third parties can be the customers of the entity that owns and / or operates the software distribution platform 1705. The entity that owns and / or operates the software distribution platform 1705 can be at least one developer, vendor, or licensor of the software, such as the exemplary machine-readable instructions 1432, according to [reference to relevant document]. Fig. 14. Third parties may be consumers, users, retailers, OEMs, etc., who either purchase or license the software for at least one of the uses, resale, or sublicensing, or a combination thereof. According to the illustrated example, the software distribution platform 1705 includes one or more servers and one or more storage devices. The storage devices store the machine-readable instructions 1432, which correspond to the exemplary machine-readable instructions according to Fig. 13, as described above. The one or more servers of the exemplary software distribution platform 1705 are connected to an exemplary network 1710, which may correspond to any or more of the Internet or to any of the exemplary networks described above. According to some examples, the one or more servers respond to requests to transfer the software to a requesting party as part of a commercial transaction. Payment for at least one of the delivery, sale, or licensing of the software may be processed by the one or more servers of at least one of the software distribution platforms or by a third-party payment entity. The servers enable one or more purchasers or licensors to download the machine-readable instructions 1432 from the software distribution platform 1705.The software, which follows the exemplary machine-readable instructions according to . Fig. 13 can be, for example, downloaded to the exemplary programmable circuit arrangement platform 1400, which is intended to execute the machine-readable instructions 1432 to control the circuit arrangement 130 according to Fig. 1 to implement. According to some examples, one or more servers of the software distribution platform 1705 periodically offer and / or transmit and / or enforce updates to the software (e.g., of the exemplary machine-readable instructions 1432 according to Fig. 14) to ensure that improvements, patches, updates, etc. are distributed and applied to the software on end-user devices. Although referred to above as software, the distributed “software” could alternatively be firmware.

[0082] While in the Fig. 1 and Fig. 6 An exemplary way of implementing the device 100 is illustrated; one or more of the features described in the Fig. 1 and Fig. The elements, processes, or devices illustrated in Section 6 may be combined, divided, rearranged, omitted, eliminated, or implemented in any other way. Furthermore, the monitoring circuit arrangement 125, the control circuit arrangement 130, or, more generally, the exemplary device 100 may be modified according to the following: Fig. 1 and Fig. 6. be implemented by hardware alone or by hardware in combination with software and firmware. Consequently, for example, each of the monitoring circuit arrangement 125 or the control circuit arrangement 130 could be implemented by a programmable circuit arrangement in combination with one or more machine-readable instructions (e.g., firmware or software), a processor circuit arrangement, one or more analog circuits, one or more digital circuits, one or more logic circuits, one or more programmable processors, one or more programmable microcontrollers, one or more graphics processing units (GPUs), one or more digital signal processors (DSPs), one or more ASICs, one or more programmable logic devices (PLDs), or one or more field-programmable logic devices (FPLDs), such as FPGAs.Furthermore, the exemplary device 100 may contain one or more elements, one or more processes, or one or more devices in addition to or instead of those contained in the device 100. Fig. 1 and Fig. 6 are illustrated, or contain more than one of any or all of the illustrated elements, processes and devices.

[0083] One or more flowcharts representing exemplary machine-readable instructions that can be executed by a programmable circuit arrangement to operate the device 100 according to the Fig. 1 and Fig. 6 to implement and / or instantiate, or which represent exemplary operations that can be performed by a programmable circuit arrangement to configure the device 100 according to the Fig. 1 and Fig. 6 to implement and / or instantiate are in Fig. 13 shown. The machine-readable instructions can be one or more executable programs or sections of one or more executable programs for execution by a programmable circuit arrangement, such as the programmable circuit arrangement 1412 shown in the exemplary processor platform 1400, which is discussed below in connection with Fig. 14 is discussed, and can be one or more functions or one or more sections of functions to be performed by the exemplary programmable circuit arrangement (e.g., an FPGA) discussed below in connection with the Fig. 15 or Fig. As discussed in section 16, according to some examples, machine-readable instructions cause an operation, task, etc., to be carried out or performed in an automated manner in the real world. As "automated" is used here, it means without human intervention.

[0084] The program may be embodied in instructions (e.g., software and / or firmware) stored in one or more non-transient computer-readable and / or machine-readable storage media, such as one or a combination of a cache memory, a magnetic storage device or disk (e.g., a floppy disk, a hard disk drive (HDD), etc.), an optical storage device or disk (e.g., a Blu-ray disc, a compact disc (CD), a digital versatile disk (DVD), etc.), a redundant array of independent disks (RAID), a register, a ROM, a solid-state drive (SSD), an SSD memory, non-volatile memory (e.g., an electrically erasable programmable read-only memory (EEPROM), a flash memory, etc.), volatile memory (e.g., a read / write memory (RAM) of any type, etc.), or any other storage device or storage disk.The instructions of the non-transient computer-readable and / or machine-readable medium can program a programmable circuit arrangement or be executed by a programmable circuit arrangement located in one or more hardware devices, but the entire program or parts thereof could alternatively be executed or instantiated by one or more hardware devices that are different from the programmable circuit arrangement or are embodied in dedicated hardware. The machine-readable instructions can be distributed across multiple hardware devices or executed by two or more hardware devices (e.g., a server and a client hardware device). The client hardware device can be, for example, an endpoint client hardware device (e.g., a server).a hardware device assigned to a human and / or machine user) or an intermediate client-hardware device gateway (e.g., a wireless access network (RAN)) that can facilitate communication between a server and an endpoint client-hardware device. Similarly, the non-transient machine-readable storage medium can contain one or more media. Furthermore, although the example program may contain one or more flowcharts, the following may be implemented: Fig. Figure 13 illustrates, and as has been described, there are alternatively many other methods for implementing the exemplary device 100 according to the Fig. 1 and Fig. 6. The execution order of the blocks of one or more flowcharts can be changed, for example, or some of the described blocks can be modified, eliminated, or combined. Furthermore, or alternatively, any or all of the flowchart blocks can be implemented by one or more hardware circuits (e.g., a processor circuit arrangement, a discrete integrated analog and / or digital circuit arrangement, an FPGA, an ASIC, a comparator, an operational amplifier (op-amp), a logic circuit, etc.) that are structured to perform the corresponding operation without executing any software or firmware. The programmable circuit arrangement can be distributed across the network or located locally at one or more hardware devices (e.g., a single-core processor (e.g., a single-core CPU), a multi-core processor (e.g., a multi-core CPU, an XPU, etc.)).The programmable circuit arrangement can be, for example, one or a combination of a CPU or an FPGA located in the same assembly (e.g., the same assembly of an integrated circuit (IC assembly) or in two or more separate packages), one or more processors in a single machine, multiple processors distributed across multiple servers in a server rack, multiple processors distributed across one or more server racks, etc., or any or any combination thereof.

[0085] The machine-readable instructions described here can be stored in one or more compressed, encrypted, fragmented, compiled, executable, or packed formats. Machine-readable instructions, as described here, can be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bitstream (e.g., a computer-readable bitstream, a machine-readable bitstream, etc.) or a data structure (e.g., one or more parts of instructions, code, representations of code, etc.) that can be used to generate, manufacture, or produce machine-executable instructions. The machine-readable instructions can, for example,The data may be fragmented and stored on one or more storage devices, disks, or computing devices (e.g., servers) located in the same or different locations within a network or collection of networks (e.g., in the cloud, on edge devices, etc.). The machine-readable instructions may require one or more of the following operations: installation, modification, adaptation, updating, combining, augmenting, configuring, decryption, decompression, unpacking, distribution, reassignment, compilation, etc., to make them directly readable, interpretable, or executable by a computing device or other machine. For example, the machine-readable instructions might be:be stored in several parts, which are individually compressed, encrypted, or stored in separate computing devices, the parts, when decrypted, decompressed, or combined, forming a set of one or more computer-executable or machine-executable instructions implementing one or more functions or operations which together may form a program, such as the one described herein.

[0086] According to another example, the machine-readable instructions may be stored in a state where they can be read by a programmable circuit arrangement, but require the addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., to execute the machine-readable instructions on a specific computing device or other device. According to yet another example, the machine-readable instructions may need to be configured (e.g., settings saved, data entered, network addresses recorded, etc.) before the machine-readable instructions or the one or more corresponding programs can be executed in whole or in part.Consequently, machine-readable, computer-readable or machine-readable media such as those used here, regardless of the specific format or state of the machine-readable instructions or the one or more programs, may contain one or a combination of instructions and one or more programs.

[0087] The machine-readable instructions described here can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions can be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, HyperText Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0088] As mentioned above, the exemplary operations can be found after Fig. 13. are implemented using executable instructions (e.g., computer-readable and / or machine-readable instructions) stored on one or more non-transient computer-readable or machine-readable media. As used herein, the terms non-transient computer-readable medium, non-transient computer-readable storage medium, non-transient machine-readable medium, and non-transient machine-readable storage medium are expressly defined to include any type of computer-readable storage device or storage disk and to exclude propagating signals and transmission media.Examples of such non-transient computer-readable media, non-transient computer-readable storage media, non-transient machine-readable media, or non-transient machine-readable storage media include one or more optical storage devices, magnetic storage devices, a hard disk drive (HDD), flash memory, read-only memory (ROM), a CD, a DVD, a cache, RAM of any type, a register, or any other storage device or storage disk in which information is stored for any duration (e.g., for extended periods, permanently, for short periods, for temporary buffering, for caching information).As the terms “non-transient computer-readable storage device” and “non-transient machine-readable storage device” are used here, they are defined as including any physical (mechanical, magnetic, electromechanical, or electrical) hardware to retain information for a period of time, but excluding propagating signals and transmission media. Examples of non-transient computer-readable storage devices or non-transient machine-readable storage devices include one or a combination of read / write memory of any type, read-only memory of any type, solid-state memory, flash memory, optical disks, magnetic disks, disk drives, or systems of redundant arrays of independent disks (RAID). As the term “device” is used here, it refers to a physical structure, such as…a mechanical, electromechanical or electrical device, hardware or circuit arrangement that can or cannot be configured by computer-readable instructions, machine-readable instructions, etc., or that is manufactured to execute computer-readable instructions, machine-readable instructions, etc.

[0089] “Contain” and “comprise” (and all forms and tenses thereof) are used here as open terms. Consequently, whenever a claim uses any form of “contain” or “comprise” (e.g., encompasses, contains, encompassing, including, exhibiting, etc.) as a preamble or within any kind of claim description, additional elements, terms, etc., may be present without being outside the scope of protection of the claim or claim description in question. The way the phrase “at least” is used here, when used as a transitional term, e.g., in a preamble to a claim, is open in the same way as the terms “comprehensive” and “containing” are open. The term “and / or,” when used, for example, in a form such as A, B, and / or C, refers to any combination or subset of A, B, C, such as…(1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) B with C, or (7) A with B and with C. As the phrase "at least one of A and B" is used here in the context of describing structures, components, elements, objects, and things, it refers to implementations that contain any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. The phrase "at least one of A or B," as used here in the context of describing structures, components, elements, objects, and things, similarly refers to implementations that contain any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. The phrase "at least one of A and B," as used here in the context of describing the execution or performance of processes, instructions, procedures, activities, etc.The phrase "at least one of A or B" as used here refers to implementations that contain any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, the phrase "at least one of A or B," as used here in the context of describing the execution or performance of processes, instructions, procedures, activities, etc., refers to implementations that contain (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0090] The singular terms (e.g., "one," "a," "first," "second," etc.) used here do not exclude multiple. The term "one" or "an" object, as used here, refers to one or more of these objects. The terms "one" (or "a"), "one or more," and "at least one" are used synonymously here. Furthermore, several means, elements, or processes, although listed individually, may be implemented by, for example, the same entity or object. Although individual features may be included in different examples or claims, they may also potentially be combined, and inclusion in different examples or claims does not imply that a combination of features is not feasible and / or advantageous.

[0091] The term "above," as used here, describes the relationship of two parts with respect to the Earth, unless otherwise specified. A first part is above a second part if the second part has at least one part between the Earth and the first part. As used here, a first part is also "below" a second part if the first part is closer to the Earth than the second part. As mentioned above, a first part can be above or below a second part with one or more of the following: other parts in between, no other parts in between, the first and second parts touching, or the first and second parts not in direct contact.

[0092] Notwithstanding the foregoing, when referring to at least one component of a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, or an assembly of an integrated circuit (IC assembly) containing a semiconductor die, during fabrication or manufacturing, “above” does not refer to the ground, but instead refers to an underlying substrate on which relevant components are fabricated, assembled, attached, supported, or otherwise provided. Consequently, as used here, and unless otherwise specified or implied from the context, a first component within a semiconductor die (e.g., a transistor or other semiconductor device) is “above” a second component within the semiconductor die if, during fabrication / manufacturing, the first component is located further from a substrate (e.g., a substrate) than the second component.a semiconductor wafer) on which the two components are fabricated or otherwise provided. Similarly, unless otherwise stated or implied by the context, a first component within an IC assembly (e.g., a semiconductor die) is located “over” a second component within the IC assembly during fabrication if the first component is located farther away from a printed circuit board (PCB) on which the IC assembly is to be mounted or attached. Semiconductor devices are frequently used in a different orientation than their orientation during fabrication. Consequently, if one or a combination of a semiconductor device (e.g.,When reference is made to a transistor), a semiconductor die containing a semiconductor device, or an assembly of an integrated circuit (IC assembly) containing a semiconductor die, the definition of "over" in the preceding paragraph (i.e., the term "over" describes the relationship of two parts with respect to the earth) is likely to be decisive based on the context of use.

[0093] As used in this patent, the indication that any part (e.g., a layer, a film, an area, a region, or a plate) is in any way located on another part (e.g., positioned, situated, arranged, or formed, etc.) means that the referenced part is either in contact with the other part or that the referenced part is located above the other part with one or more intermediate parts in between.

[0094] As connection references (e.g., attached, coupled, connected, and joined) are used here, they may include intermediate elements between the elements referenced by at least one of the connection references, or a relative movement between those elements, unless otherwise specified. As such, the connection references do not necessarily imply that two elements are directly connected or in a fixed relationship to each other. As used here, stating that any part is in "contact" with another part is defined as meaning that there is no intermediate element between the two parts.

[0095] Unless specifically stated otherwise, descriptors such as "first," "second," "third," etc., are used here without implying or otherwise indicating any significance of priority, physical order, arrangement in a list, or any other order. They are used simply as designations and / or arbitrary names to distinguish elements for the ease of understanding the examples described. According to some examples, the descriptor "first" may be used to refer to an element in the detailed description, while the same element in a claim may be designated by a different descriptor, such as "second" or "third." In such cases, these descriptors are used merely to uniquely identify these elements within the context of the discussion (e.g., within a claim), where the elements are, for example,otherwise they might have the same name.

[0096] As used here, "approximately" and "about" modify their subjects / values ​​to reflect the potential presence of variations that occur in real-world applications. For example, "approximately" and "about" can modify dimensions that may not be exact due to manufacturing tolerances and / or other real-world imperfections. "Approximately" and "about" can also indicate, for example, that such dimensions may fall within a tolerance range of ±10% unless otherwise specified here.

[0097] As used here, "essentially real-time" refers to an occurrence in a near-instantaneous manner, recognizing that real-world delays in processing time, transmission, etc., can occur. Consequently, "essentially real-time" refers to real-time plus one second unless otherwise specified.

[0098] The term “in connection”, including its variations as used here, includes one or a combination of a direct connection or an indirect connection via one or more intermediate components and does not require a direct physical (e.g., wired) connection or permanent connection, but rather also includes a selective connection in at least one of periodic intervals, scheduled intervals, aperiodic intervals or in one-off operations.

[0099] A “programmable circuit arrangement,” as used here, is defined as containing at least one of: (i) one or more specialized electrical circuits (e.g., an application-specific integrated circuit (ASIC)) structured to perform one or more specific operations and containing one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors); or (ii) one or more semiconductor-based general-purpose electrical circuits programmable with instructions to perform one or more specific functions or operations and containing one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of a programmable circuit arrangement include programmable microprocessors, such as…Central processing units (CPUs) that can execute first instructions to perform one or more operations or functions; field-programmable gate arrays (FPGAs) that can be programmed with second instructions to configure or structure the FPGAs to instantiate one or more operations or functions corresponding to the first instructions; graphics processing units (GPUs) that can execute first instructions to perform one or more operations or functions; digital signal processors (DSPs) that can execute first instructions to perform one or more operations or functions; XPUs; network processing units (NPUs); one or more microcontrollers that can execute first instructions to perform one or more operations or functions; or integrated circuits, such as application-specific integrated circuits (ASICs). An XPU, for example, can...be implemented by a heterogeneous computing system that includes several types of programmable circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and any or any combinations thereof) and an orchestration technology (e.g., one or more application programming interfaces (APIs)) that can assign one or more computational tasks to whichever of the several types of programmable circuitry is suitable and available to perform the one or more computational tasks.

[0100] An integrated circuit / circuit assembly, as used here, is defined as one or more semiconductor assemblies containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. An integrated circuit can be implemented, for example, as one or more ASICs, FPGAs, chips, microchips, programmable logic devices, semiconductor substrates coupling multiple circuit elements, systems-on-a-chip (SoCs), etc.

[0101] In this description, the term "couple" can encompass connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if a device A generates a signal to control a device B to perform an operation: (a) in a first example, device A is coupled to device B by a direct connection; or (b) in a second example, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.

[0102] A device that is "configured" to perform a task or function can be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform the function and / or be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration can be achieved through firmware and / or software programming of the device, through the design and / or arrangement of hardware components and interconnections of the device, or a combination thereof.

[0103] The terms "terminal," "node," "interconnection," "terminal pin," and "conduit," as used herein, are synonymous. Unless specifically stated otherwise, these terms are generally used to refer to an interconnection between, or an endpoint of, a device element, circuit element, integrated circuit, appliance, or other electronic or semiconductor component.

[0104] A “circuit arrangement” described in the description and claims may contain one or more circuits. A circuit or device described herein as containing certain components may instead be designed to be coupled to these components to form the described circuit arrangement or device. A structure described as containing one or more semiconductor elements (such as transistors), one or more passive elements (such as one of or a combination of resistors, capacitors, or inductors), or one or more sources (such as voltage and / or current sources) may, for example, instead contain only the semiconductor elements within a single physical device (e.g., a housing).a semiconductor die and / or an integrated circuit (IC) assembly) and may be designed to be coupled to at least some of the passive elements or sources to form the described structure either at the time of manufacture or after a time of manufacture, e.g. by an end user and / or a third party.

[0105] The circuits described here are reconfigurable to include the replaced components in order to provide functionality that is at least partially similar to the functionality available before the component was replaced. Unless otherwise stated, components shown as resistors generally represent one or more elements connected in series and / or parallel to provide an amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described here as a single component may instead be multiple resistors or capacitors connected in parallel between the same nodes.These can be capacitors connected in series between the same two nodes as the single resistor or capacitor. While certain elements of the described examples are contained within an integrated circuit and other elements are located outside the integrated circuit, according to other exemplary embodiments, additional or fewer features may be included in the integrated circuit. Additionally, some or all of the features illustrated as being located outside the integrated circuit may be included within the integrated circuit, while some features illustrated as being located inside the integrated circuit may be included outside the integrated circuit.The term “integrated circuit”, as used herein, means one or more circuits which are at least one of the following: (i) incorporated into / over a semiconductor substrate; (ii) incorporated into a single semiconductor assembly; (iii) incorporated into the same module; or (iv) incorporated into / on the same printed circuit board.

[0106] The uses of the term "mass" in the foregoing description include at least one chassis mass, earth mass, suspended mass, virtual mass, digital mass, common mass, or any other form of ground connection applicable to or suitable for the teachings of this description. Unless otherwise specified, "about," "approximately," or "essentially" before a value means ±10 percent of the stated value or, if the value is zero, a reasonable range of values ​​around zero.

[0107] From the foregoing, it is evident that exemplary systems, devices, articles, and methods implementing asymmetric transmission line power combiners have been described. The described systems, devices, articles, and methods improve the efficiency of a device, such as a radar system. Symmetric transmission line power combiners may be satisfactory for loop-circuit systems with two transmitters, for example. However, some modern radar systems contain eight or sixteen transmitters in a single die. Symmetric transmission line power combiners designed to support this number of transmitters can consume a considerable die area and exhibit high overall losses due to the total length of the symmetric transmission line.In contrast, the exemplary asymmetric transmission line power combiners described here perform well with a high number of transmitters, such as eight or more, and are scalable to even higher numbers of transmitters, while reducing the die area by at least a factor of four and the total loss by 7–9 dB compared to other symmetric transmission line power combiners. Properly dimensioned switches can also reduce the loss across the transmitter feedback paths of the asymmetric transmission line power combiner, so that the paths exhibit similar loss parameters.As such, the exemplary asymmetric transmission line power combiners described here can reduce the number of amplifiers required to amplify the loop-circuit signal, thereby saving 20–40 milliamperes (mA) of current consumption compared to other symmetric transmission line power combiners. Furthermore, such a reduction in die area can lead to smaller assemblies and lower overall costs. Moreover, the exemplary asymmetric transmission line power combiners described here are not limited to use in radar devices but can be used in any device that has multiple transmitters carrying signals that are to be looped back through a transmission line in the device or otherwise transmitted.Consequently, the described systems, devices, manufactured articles and methods are also directed towards one or more improvements in the operation of a machine, such as a computer or other electronic or electromechanical device.

[0108] Modifications to the described embodiments are possible, and other embodiments within the scope of the claims are possible. Further examples and combinations thereof include the following. Example 1 comprises a device comprising a first contact surface, a second contact surface, a transmission line having a first end configured to be coupled to a monitoring circuit arrangement, the transmission line having a second end, a first switch coupled to the first contact surface, the first switch being coupled to the transmission line between the first end and the second end, and a second switch coupled to the second contact surface and to the second end of the transmission line, wherein the impedance of the first switch is greater than the impedance of the second switch.

[0109] Example 2 contains the device of Example 1, wherein the impedance of the first switch is at least twenty percent greater than the impedance of the second switch.

[0110] Example 3 includes the device of Example 1 or Example 2, wherein a channel width of the first switch is smaller than a channel width of the second switch.

[0111] Example 4 includes the device of one of Examples 1 to 3, wherein the distance between the first switch and the first end of the transmission line is less than the distance between the second switch and the first end of the transmission line.

[0112] Example 5 includes the device of one of Examples 1 to 4, comprising a first transmit power output coupled to the first contact surface, a second transmit power output coupled to the second contact surface, and a control circuit arrangement that causes the first switch to be deactivated and the second switch to be activated during a first time interval, wherein the first transmit power output is active during the first time interval and the second transmit power output is inactive during the first time interval.

[0113] Example 6 includes the device of Example 5, wherein the control circuit arrangement causes the first switch to be disabled and the second switch to be disabled during a second time interval, wherein the first transmit power output is inactive and the second transmit power output is active during the second time interval.

[0114] Example 7 includes the device of Example 6, comprising a third contact surface, a third transmit power output coupled to the third contact surface, and a third switch coupled to the third contact surface, wherein the third switch is coupled to the transmission line between the first switch and the second switch, wherein the control circuit arrangement causes the third switch to be activated during the first time interval, with the third transmit power output being inactive during the first time interval, and causes the third switch to be deactivated during the second time interval, with the third transmit power output being inactive during the second time interval.

[0115] Example 8 includes the device of Example 7, wherein the control circuit arrangement causes the first switch to be disabled, the second switch to be enabled, and the third switch to be disabled during a third time interval, wherein the first transmit power output is inactive, the second transmit power output is inactive, and the third transmit power output is active during the third time interval.

[0116] Example 9 contains the device of Example 7, wherein the impedance of the third switch is smaller than the impedance of the first switch and larger than the impedance of the second switch.

[0117] Example 10 contains the device of one of Examples 1 to 9, wherein the first switch and the second switch are shunt switches.

[0118] Example 11 comprises a device comprising a transmission line with a first end and a second end, wherein the first end is coupled to a circuit arrangement to monitor multiple transmit power outputs of the device, and switches to couple the transmit power outputs to the transmission line, wherein a first switch of the switches couples a first transmit power output of the transmit power outputs between the first end and the second end of the transmission line to the transmission line, wherein a second switch of the switches couples a second transmit power output of the transmit power outputs to the second end of the transmission line, and the second switch has a lower impedance than the first switch.

[0119] Example 12 includes the device of Example 11, wherein the circuit arrangement is a first circuit arrangement, and which includes a second circuit arrangement to cause the first switch to be disabled and the second switch to be enabled during a first time interval, wherein the first transmit power output is active during the first time interval and the second transmit power output is inactive during the first time interval.

[0120] Example 13 includes the device of Example 12, wherein the second circuit arrangement causes the first switch to be disabled and the second switch to be disabled during a second time interval, wherein the first transmit power output is inactive and the second transmit power output is active during the second time interval.

[0121] Example 14 includes the device of Example 13, wherein a third switch couples a third transmit power output between the first switch and the second switch to the transmission line, and the second circuit arrangement causes the third switch to be activated during the first time interval, with the third transmit power output being inactive during the first time interval, and causes the third switch to be deactivated during the second time interval, with the third transmit power output being inactive during the second time interval.

[0122] Example 15 includes the device of Example 14, wherein the second circuit arrangement causes the first switch to be disabled, the second switch to be enabled, and the third switch to be disabled during a third time interval, wherein the first transmit power output is inactive, the second transmit power output is inactive, and the third transmit power output is active during the third time interval.

[0123] Example 16 includes the device of Example 14 or Example 15, wherein the first switch has a first impedance, the second switch has a second impedance which is less than the first impedance, and the third switch has a third impedance which is less than the first impedance and greater than the second impedance.

[0124] Example 17 includes a non-transient computer-readable medium comprising computer-readable instructions to cause at least one processor circuit to cause several transmit power outputs of a device to be sequentially activated for respective time intervals in a monitoring period, wherein the transmit power outputs are each connected to several switches coupled to a transmission line at respective positions spaced apart along the transmission line, wherein the transmission line has a termination and an output, the output being coupled to a circuit arrangement to monitor the transmit power outputs, and for a first of the time intervals in which a first of the transmit power outputs is active and the other transmit power outputs are inactive, causes a first of the switches connected to the first of the transmit power outputs todeactivated, with the first of the switches being coupled to the transmission line at a first of the positions, and causes a second of the switches, which is coupled to the transmission line at a second of the positions between the first of the positions and the termination of the transmission line, to be activated.

[0125] Example 18 contains the non-transient computer-readable medium of Example 17, wherein the computer-readable instructions cause one or more of the at least one processor circuit to cause, for the first of the time intervals, a third of the switches coupled to the transmission line between the first of the positions and the output of the transmission line at a third of the positions to be deactivated.

[0126] Example 19 contains the non-transient computer-readable medium of Example 17, wherein the computer-readable instructions cause one or more of the at least one processor circuit to cause, for the first of the time intervals, the switches coupled to the transmission line between the first of the positions and the termination of the transmission line to be activated, and to cause those switches coupled to the transmission line between the first of the positions and the output of the transmission line to be deactivated.

[0127] Example 20 contains the non-transient computer-readable medium of Example 17, wherein the computer-readable instructions cause one or more of the at least one processor circuit to cause the switches to be activated at time intervals outside the monitoring period.

[0128] The following claims are hereby incorporated into this detailed description by reference. Although certain exemplary systems, devices, articles, and processes have been described herein, the scope of protection of this patent is not limited thereto. On the contrary, this patent covers all systems, devices, articles, and processes that fall entirely within the scope of protection of the claims of this patent. < / n>

Claims

[1] Device comprising the following: a first contact surface; a second contact surface; a transmission line containing a first end configured to be coupled to a monitoring circuit arrangement, wherein the transmission line contains a second end; a first switch coupled to the first contact surface, the first switch being coupled to the transmission line between the first end and the second end; and a second switch that is coupled to the second contact surface and to the second end of the transmission line, where the impedance of the first switch is greater than the impedance of the second switch. [2] Device according to claim 1, wherein the impedance of the first switch is at least twenty percent greater than the impedance of the second switch. [3] Device according to claim 1, wherein a channel width of the first switch is smaller than a channel width of the second switch. [4] Device according to claim 1, wherein the distance between the first switch and the first end of the transmission line is smaller than the distance between the second switch and the first end of the transmission line. [5] Device according to claim 1, comprising the following: a first transmit power output coupled to the first contact surface; a second transmit power output coupled to the second contact surface, and a control circuit arrangement which causes the first switch to be deactivated and the second switch to be activated during a first time interval, wherein the first transmit power output is active during the first time interval and the second transmit power output is inactive during the first time interval. [6] Device according to claim 5, wherein the control circuit arrangement causes the first switch to be deactivated and the second switch to be deactivated during a second time interval, wherein the first transmit power output is inactive during the second time interval and the second transmit power output is active during the second time interval. [7] Device according to claim 6, comprising the following: a third contact surface; a third transmit power output coupled to the third contact surface; and a third switch coupled to the third contact surface, wherein the third switch is coupled to the transmission line between the first switch and the second switch, wherein the control circuit arrangement: causes the third switch to be activated during the first time interval, while the third transmit power output is inactive during the first time interval; and causes the third switch to be disabled during the second time interval, with the third transmit power output being inactive during the second time interval. [8] Device according to claim 7, wherein the control circuit arrangement causes the first switch to be deactivated, the second switch to be activated and the third switch to be deactivated during a third time interval, wherein the first transmit power output is inactive during the third time interval, the second transmit power output is inactive during the third time interval and the third transmit power output is active during the third time interval. [9] Device according to claim 7, wherein the impedance of the third switch is smaller than the impedance of the first switch and larger than the impedance of the second switch. [10] Device according to claim 1, wherein the first switch and the second switch are shunt switches. [11] Device comprising the following: a transmission line with a first end and a second end, the first end being coupled to a circuit arrangement to monitor multiple transmit power outputs of the device; and Switches to couple the transmit power outputs to the transmission line, wherein a first switch of the switches couples a first transmit power output of the transmit power outputs between the first end and the second end of the transmission line to the transmission line, wherein a second switch of the switches couples a second transmit power output of the transmit power outputs to the second end of the transmission line and the second switch has a lower impedance than the first switch. [12] Device according to claim 11, wherein the circuit arrangement is a first circuit arrangement, and which comprises a second circuit arrangement to cause the first switch to be deactivated and the second switch to be activated during a first time interval, wherein the first transmit power output is active during the first time interval and the second transmit power output is inactive during the first time interval. [13] Device according to claim 12, wherein the second circuit arrangement causes the first switch to be deactivated and the second switch to be deactivated during a second time interval, wherein the first transmit power output is inactive during the second time interval and the second transmit power output is active during the second time interval. [14] Device according to claim 13, wherein a third switch couples a third transmit power output of the transmit power outputs between the first switch and the second switch to the transmission line and the second circuit arrangement: causes the third switch to be activated during the first time interval, with the third transmit power output being inactive during the first time interval, and causes the third switch to be disabled during the second time interval, with the third transmit power output being inactive during the second time interval. [15] Device according to claim 14, wherein the second circuit arrangement causes the first switch to be deactivated, the second switch to be activated and the third switch to be deactivated during a third time interval, wherein the first transmit power output is inactive during the third time interval, the second transmit power output is inactive during the third time interval and the third transmit power output is active during the third time interval. [16] Device according to claim 14, wherein the first switch has a first impedance, the second switch has a second impedance which is smaller than the first impedance, and the third switch has a third impedance which is smaller than the first impedance and larger than the second impedance. [17] Non-transient computer-readable medium comprising computer-readable instructions to cause at least one processor circuit to: caused several transmit power outputs of a device to be sequentially activated for respective time intervals in a monitoring period, wherein the transmit power outputs are each connected to several switches which are coupled to a transmission line at respective positions spaced apart along a transmission line, wherein the transmission line has a termination and an output, the output being coupled to a circuit arrangement to monitor the transmit power outputs; and for a first of the time intervals in which a first of the transmit power outputs is active and the other transmit power outputs are inactive: causes a first of the switches connected to the first of the transmit power outputs to be deactivated, the first of the switches being coupled to the transmission line at a first of the positions; and causes a second switch, which is coupled to the transmission line at a second of the positions between the first of the positions and the end of the transmission line, to be activated. [18] Non-transient computer-readable medium according to claim 17, wherein the computer-readable instructions cause one or more of the at least one processor circuit to cause, for the first of the time intervals, a third of the switches coupled to the transmission line between the first of the positions and the output of the transmission line at a third of the positions to be deactivated. [19] Non-transient computer-readable medium according to claim 17, wherein the computer-readable instructions cause one or more of the at least one processor circuit to: for the first of the time intervals: to cause the switches coupled to the transmission line between the first of the positions and the end of the transmission line to be activated, and to cause those switches that are coupled to the transmission line between the first of the positions and the output of the transmission line to be deactivated. [20] Non-transient computer-readable medium according to claim 17, wherein the computer-readable instructions cause one or more of the at least one processor circuit to cause the switches to be activated at time intervals outside the monitoring period.

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