Semiconductor device

Abstract

A semiconductor device according to the present disclosure comprises: a semiconductor substrate; a base layer located in the semiconductor substrate on one side of a front face thereof; and a two-stage active dummy trench located in the semiconductor substrate on the side of the front face thereof to extend through the base layer, wherein the two-stage active dummy trench includes in itself a first upper electrode in an upper stage which is connected to an emitter electrode and a first lower electrode in a lower stage which is connected to a gate electrode, wherein the first upper electrode has a projection which extends from at least one of the left and right positions of an end face thereof on one side of a rear face towards the rear face, and wherein a tip of the projection is located closer to the rear face than the base layer.

Description

Background Technical field

[0001] The present disclosure relates to a semiconductor device in which a line is controlled by a gate signal. Description of the state of the art

[0002] In a semiconductor device containing a two-stage active dummy trench, which includes an upper electrode in an upper stage connected to an emitter electrode and a lower electrode in a lower stage connected to a gate electrode, a change in voltage over time (dV / dt) which can cause noise and dielectric breakdown of a motor can be reduced by increasing a gate-collector capacitance (see, for example, Japanese patent application disclosure no. 2023-37881).

[0003] Depending on a very fast switching condition, such as rapid turn-on, the potential of the holes around the trench varies, and a displacement current flows into the lower electrode as a gate potential. This leads to a problem with regard to an increase in gate voltage, which causes an increase in dV / dt. Summary

[0004] It is an objective of the present disclosure to provide a semiconductor device in which dV / dt can be reduced by suppressing an increase in a gate voltage.

[0005] A semiconductor device according to the present disclosure comprises: a semiconductor substrate; a base layer located in the semiconductor substrate on one side of a front face thereof; and a two-stage active dummy trench located in the semiconductor substrate on the side of the front face thereof to extend through the base layer, wherein the two-stage active dummy trench includes in itself a first upper electrode in an upper stage which is connected to an emitter electrode and a first lower electrode in a lower stage which is connected to a gate electrode, wherein the first upper electrode has a projection which extends from at least one of the left and right positions of an end face thereof on one side of a rear face towards the rear face, and wherein a tip of the projection is located closer to the rear face than the base layer.

[0006] According to the present disclosure, dV / dt can be reduced by suppressing an increase in a gate voltage.

[0007] These and other tasks, features, aspects and advantages of the present revelation will become clearer based on the following detailed description of the present revelation in conjunction with the accompanying figures. Brief description of the characters Fig. Figure 1 is a cross-sectional view of a semiconductor device according to embodiment 1; Fig. Figure 2 is a cross-sectional view of a semiconductor device according to a modification 1 of embodiment 1; Fig. Figure 3 is a cross-sectional view of a semiconductor device according to a modification 2 of embodiment 1; Fig. Figure 4 is a cross-sectional view of a semiconductor device according to a modification 3 of embodiment 1; Fig. Figure 5 is a cross-sectional view of a semiconductor device according to a modification 4 of embodiment 1; Fig. Figure 6 is a cross-sectional view of a semiconductor device according to a modification 5 of embodiment 1; Fig. Figure 7 is a cross-sectional view of a semiconductor device according to a modification 6 of embodiment 1; Fig. Figure 8 is a cross-sectional view of a semiconductor device according to a modification 7 of embodiment 1; Fig. Figure 9 is a cross-sectional view of a semiconductor device according to a modification 8 of embodiment 1; Fig. Figure 10 is a cross-sectional view of a semiconductor device according to a modification 9 of embodiment 1; Fig. Figure 11 is a cross-sectional view of a semiconductor device according to a modification 10 of embodiment 1; Fig. Figure 12 is a cross-sectional view of a semiconductor device according to a modification 11 of embodiment 1; Fig. Figure 13 is a cross-sectional view of a semiconductor device according to a modification 11 of embodiment 1; Fig. Figure 14 is a cross-sectional view of a semiconductor device according to a modification 11 of embodiment 1; Fig. Figure 15 is a cross-sectional view of a semiconductor device according to a modification 12 of embodiment 1; and Fig. Figure 16 is a cross-sectional view of a semiconductor device according to a modification 14 of embodiment 1. Description of preferred embodiments<Ausführungsform 1>

[0008] Below is a description of a semiconductor device according to one embodiment with reference to the figures. The semiconductor device is an insulated-gate bipolar transistor (IGBT). Identical or corresponding components bear the same reference numerals, and repeated descriptions are sometimes omitted. In the description given below, N and P denote conductivity types of a semiconductor. These conductivity types may be inversely proportional.

[0009] Fig. Figure 1 is a cross-sectional view of a semiconductor device according to embodiment 1. Fig. 1. A semiconductor substrate lies in a region from a base layer 3 to a collector layer 6. In Fig. 1. The upper end of the base layer 3 is referred to as a front face of the semiconductor substrate, and the lower end of the collector layer 6 is referred to as a back face of the semiconductor substrate. The front face and the back face are oriented towards each other.

[0010] As in Fig. As illustrated in Figure 1, the P-type base layer 3 is provided on one side of the front surface of an N-type drift layer 4.

[0011] The semiconductor substrate has a two-stage active dummy trench 8 extending through the base layer 3 to the drift layer 4. The two-stage active dummy trench 8 is located in the semiconductor substrate on one side of its front face and comprises a first upper electrode 9 in an upper stage, which is connected to an emitter electrode 1, and a first lower electrode 11 in a lower stage, which is connected to a gate electrode (not shown). The first upper electrode 9 has a projection 10 on each of its right and left portions of an end face on one side of its rear face, projecting towards the rear face. A tip 15 of the projection 10 is located closer to the rear face than the base layer 3.While the projection 10 is located at the left and right positions of the end face of the side of the rear surface of the first upper electrode 9 in an example of . Fig. If 1 is provided, the advantage of 10 can be provided from the left and right positions.

[0012] The two-stage active dummy trench 8 comprises a first upper insulating layer 12, which is provided on a side wall of the first upper electrode 9, a first lower insulating layer 13, which is provided on a side wall of the first lower electrode 11, and a first boundary insulating layer 14, which is provided between the first upper electrode 9 and the first lower electrode 11. The first upper electrode 9 and the first lower electrode 11 are electrically separated from each other by the first boundary insulating layer 14.

[0013] An intermediate insulating layer 2 is provided above the two-stage active dummy trench 8. The emitter electrode 1 is provided above the base layer 3 and the intermediate insulating layer 2.

[0014] An N-type buffer layer 5, which has a higher concentration of N-type impurities than the drift layer 4, is provided on one side of the back surface of the drift layer 4. The P-type collector layer 6 is provided on one side of the back surface of the buffer layer 5. A collector electrode 7 is provided on one side of the back surface of the collector layer 6.

[0015] A displacement current is generated by holes, which vary the potential around a trench. This displacement current is generated in a region closer to the back face than the base layer 3, where the holes are stored. According to embodiment 1, the first upper electrode 9 includes the projection 10, which extends towards the back face, and the tip 15 of the projection 10 is located closer to the back face than the base layer 3, so that the displacement current flows to the projection 10 as an emitter potential, which is a low potential. The number of holes flowing into the first lower electrode 11 as a gate potential decreases due to the displacement current flowing to the projection 10, thus reducing the increase in gate voltage. That is, according to embodiment 1, dV / dt can be reduced by suppressing the increase in gate voltage.

[0016] The displacement current generated by the potential variation through the holes has a significant influence, particularly in the IGBT, which is a bipolar device using holes as charge carriers. According to embodiment 1, a synergistic effect can be achieved using the IGBT and the configuration mentioned above to reduce the displacement current. <Modifikation 1>

[0017] Fig. Figure 2 is a cross-sectional view of a semiconductor device according to modification 1 of embodiment 1. As in Fig. As illustrated in Figure 2, in the semiconductor device according to modification 1, the projection 10 of the first upper electrode 9 and the first lower electrode 11 are oriented towards each other in a lateral direction (transverse direction) of the two-stage active dummy trench 8.

[0018] According to modification 1, the projection 10 of the first upper electrode 9 and the first lower electrode 11 are arranged such that they face each other in a lateral direction of the two-stage active dummy trench 8, so that the projection 10 shields the first lower electrode 11 to reduce the flow of displacement current into the first lower electrode 11. Thus, dV / dt can be reduced by suppressing the increase in gate voltage. <Modifikation 2>

[0019] Fig. Figure 3 is a cross-sectional view of a semiconductor device according to modification 2 of embodiment 1. As in Fig. As illustrated in Figure 3, the first lower electrode 11 has a portion with a first width G1 on the front surface and a portion with a second width G2, which is wider than the first width G1, on the rear surface. The portion with the first width G1 faces the projection 10 in the lateral direction of the two-stage active dummy trench 8. The portion with the second width G2 does not face the projection 10 in the lateral direction of the two-stage active dummy trench 8.

[0020] According to modification 2, the portion (the portion with the first width G1) of the first lower electrode 11 facing the projection 10 of the first upper electrode 9 has a smaller width (the first width G1), thus creating a space into which the projection 10 can extend towards the first lower electrode 11, and allowing the projection 10 to be lengthened. This can reduce the increase in displacement current flowing into the projection 10 and the displacement current flowing into the first lower electrode 11, thereby suppressing the increase in gate voltage.

[0021] Fig. Figure 3 illustrates an example in which the first lower insulating layer 13 has a greater thickness than the first upper insulating layer 12. Such a combination can be applied to embodiment 1 and modification 1. <Modifikation 3>

[0022] Fig. Figure 4 is a cross-sectional view of a semiconductor device according to modification 3 of embodiment 1. As in Fig. As illustrated in Figure 4, the semiconductor device according to modification 3 further comprises an N-type source layer 16, which is provided on one side of the front surface of the base layer 3, and a two-stage active trench 17, which extends through the source layer 16 and the base layer 3 to the drift layer 4.

[0023] The two-stage active trench 17 is located in the semiconductor substrate on the side of the front surface and has within it a second upper electrode 18 in an upper stage which is connected to the gate electrode and a second lower electrode 19 in a lower stage which is connected to the gate electrode.

[0024] The two-stage active trench 17 has a second upper insulating layer 20, which is provided on a side wall of the second upper electrode 18, a second lower insulating layer 21, which is provided on a side wall of the lower electrode 19, and a second boundary insulating layer 22, which is provided between the second upper electrode 18 and the second lower electrode 19. The second upper electrode 18 and the second lower electrode 19 are electrically separated from each other by the second boundary insulating layer 22.

[0025] According to modification 3, the two-stage active trench 17 includes the second upper electrode 18 as the gate potential and the source layer 16, so that a channel can be formed in the base layer 3 to enable operation of the semiconductor device.

[0026] Although the displacement current flows into the second upper electrode 18 of the two-stage active trench 17 when the second upper electrode 18 is connected to the gate electrode, the two-stage active trench 17 and the two-stage active dummy trench 8 are arranged side by side, so that a synergistic effect is achieved to enable operation while allowing the displacement current to flow through the first upper electrode 9 of the two-stage active dummy trench 8.

[0027] The shapes of the first lower electrode 11 and the second lower electrode 19 are similar to those in modifications 1 and 2 (see Fig. 2 and Fig. 3) in an example of Fig. 4, but they are not limited to these shapes. The shapes of the first lower electrode 11 and the second lower electrode 19 can be similar to those in embodiment 1 (see Fig. 1) be. <Modifikation 4>

[0028] Fig. Figure 5 is a cross-sectional view of a semiconductor device according to modification 4 of embodiment 1. As in Fig. As illustrated in Figure 5, the semiconductor device according to modification 4 further comprises a charge carrier storage layer 23. The charge carrier storage layer 23 is provided on one side of the back face of the base layer 3 (on one side of the front face of the drift layer 4).

[0029] According to modification 4, the charge carrier storage layer 23 is included to increase the number of stored holes, thereby increasing the displacement current. By means of such a configuration, a synergistic effect can be achieved between the charge carrier storage layer 23 and embodiment 1, and in particular, the effect of reducing the displacement current is enhanced.

[0030] The projection 10 of the first upper electrode 9 and the charge carrier storage layer 23 can be arranged such that they face each other in the lateral direction of the two-stage active dummy trench 8. By means of such a configuration, the influence of the displacement current due to a densification of holes in the charge carrier storage layer 23 can be reduced by the projection 10.

[0031] The entire region of the projection 10 of the first upper electrode 9 and the charge carrier storage layer 23 can be arranged such that they face each other in the lateral direction of the two-stage active dummy trench 8. By means of such a configuration, the displacement current can be further reduced.

[0032] The projection 10 of the first upper electrode 9 and a concentration peak value of the charge carrier storage layer 23 can be arranged such that they face each other in the lateral direction of the two-stage active dummy trench 8. As described above, the projection 10 is positioned so that it faces a portion of the charge carrier storage layer 23 that is affected by the displacement current due to a densification of holes, thus reducing the influence of the displacement current.

[0033] The charge carrier storage layer 23 according to modification 4 is applicable to embodiment 1 and the other modifications. <Modifikation 5>

[0034] Fig. Figure 6 is a cross-sectional view of a semiconductor device according to modification 5 of embodiment 1. As in Fig. As illustrated in Figure 6, in the semiconductor device according to modification 5, the layer thickness T2 of the first lower insulating layer 13 is greater than the layer thickness T1 of the first upper insulating layer 12.

[0035] According to modification 5, the layer thickness T2 of the first lower insulating layer 13 is greater than the layer thickness T1 of the first upper insulating layer 12, so that the space into which the projection 10 of the first upper electrode 9 can protrude towards the first lower electrode 11 is formed, and the projection 10 can be extended. This can reduce the increase in displacement current flowing into the projection 10 and the displacement current flowing into the first lower electrode 11, thus suppressing the increase in gate voltage.

[0036] While the projection 10 and the first lower electrode 11 align with each other in the lateral direction of the two-stage active dummy trench 8 in an example of Fig. The positional relationship between the 6 electrodes is not limited to this positional relationship. The projection 10 and the first lower electrode 11 cannot face each other in the lateral direction of the two-stage active dummy trench 8. <Modifikation 6>

[0037] Fig. Figure 7 is a cross-sectional view of a semiconductor device according to modification 6 of embodiment 1. As in Fig. As illustrated in Figure 7, in the semiconductor device according to modification 6, a length U2 of the projection 10 is greater than a length U1 from an end face of the first upper electrode 9 on one side of the front face to an origin 24 of the projection 10.

[0038] According to modification 6, the length U2 of the projection 10 is greater than the length U1 from the end face of the first upper electrode 9 on the side of the front face to the origin 24 of the projection 10, so that the projection 10 can be extended. This can reduce the increase in displacement current flowing into the projection 10 and the displacement current flowing into the first lower electrode 11, thus suppressing the increase in gate voltage.

[0039] The first lower electrode 11 can be extended towards the front surface, so that a wiring resistance of the first lower electrode 11 can be reduced, and an increase with respect to the gate potential, which is determined by the product of the wiring resistance and the displacement current, can be suppressed.

[0040] While the projection 10 and the first lower electrode 11 align with each other in the lateral direction of the two-stage active dummy trench 8 in an example of Fig. The positional relationship between the 7 electrodes is not limited to this positional relationship. The projection 10 and the first lower electrode 11 cannot face each other in the lateral direction of the two-stage active dummy trench 8. <Modifikation 7>

[0041] Fig. Figure 8 is a cross-sectional view of a semiconductor device according to a modification 7 of embodiment 1. As in Fig. As illustrated in Figure 8, in the semiconductor device according to modification 7, the origin 24 of the projection 10 of the first upper electrode 9 is located closer to the rear surface than the base layer 3 (one position away from the front surface of the semiconductor substrate around B1).

[0042] In a layer that is closer to the back face than the base layer 3, holes are stored, and displacement current tends to be generated. According to modification 7, the origin 24 of the protrusion 10 is located closer to the back face than the base layer 3, so that the displacement current flowing into the protrusion 10 can be increased, and the displacement current flowing into the first lower electrode 11 can be reduced, thus suppressing the increase in gate voltage.

[0043] While the projection 10 and the first lower electrode 11 align with each other in the lateral direction of the two-stage active dummy trench 8 in an example of Fig. The positional relationship between the 8 electrodes is not limited to this positional relationship. The projection 10 and the first lower electrode 11 cannot face each other in the lateral direction of the two-stage active dummy trench 8.

[0044] The shape of the first lower electrode 11 is similar to that in modifications 1 and 2 (see Fig. 2 and Fig. 3) in the example of Fig. 8, but it is not limited to this form. The shape of the first lower electrode 11 can be similar to that in embodiment 1 (see Fig. 1). <Modifikation 8>

[0045] Fig. Figure 9 is a cross-sectional view of a semiconductor device according to a modification 8 of embodiment 1. As in Fig. As illustrated in Figure 9, in the semiconductor device according to modification 8, the origin 24 of the projection 10 of the first upper electrode 9 is located closer to the front face than it is to an end face of the base layer 3 on one side of the rear face (the position away from the front face of the semiconductor substrate around B1). The tip 15 of the projection 10 is located closer to the rear face than it is to the base layer 3 in embodiment 1.

[0046] According to modification 8, the origin 24 of the projection 10 is located closer to the front surface than the end surface of the base layer 3 on the side of the rear surface, so that the displacement current flowing into the projection 10 can be increased and the displacement current flowing into the first lower electrode 11 can be reduced, while a region of the first lower electrode 11 can be extended towards the front surface to reduce a wiring resistance of the first lower electrode 11, and thus the increase in gate voltage can be suppressed.

[0047] While the projection 10 and the first lower electrode 11 align with each other in the lateral direction of the two-stage active dummy trench 8 in an example of Fig. The positional relationship between the 9 electrodes is not limited to this positional relationship. The projection 10 and the first lower electrode 11 cannot face each other in the lateral direction of the two-stage active dummy trench 8.

[0048] The shape of the first lower electrode 11 is similar to that in modifications 1 and 2 (see Fig. 2 and Fig. 3) in the example of Fig. 9, but it is not limited to this form. The shape of the first lower electrode 11 can be similar to that in embodiment 1 (see Fig. 1). <Modifikation 9>

[0049] Fig. Figure 10 is a cross-sectional view of a semiconductor device according to a modification 9 of embodiment 1. As in Fig. As illustrated in Figure 10, in the semiconductor device according to modification 9, the two-stage active dummy trench 8 is arranged next to the two-stage active trench 17 on opposite sides of the two-stage active trench 17. While the two-stage active dummy trenches 8 are located on opposite sides of the two-stage active trench 17 in an example of Fig. While 10 are arranged, the number of two-stage active dummy trenches 8 is not limited to two.

[0050] According to modification 9, the two-stage active dummy trench 8 is arranged next to the two-stage active trench 17 on opposite sides of the two-stage active trench 17, so that the displacement current flowing into the second upper electrode 18 of the two-stage active trench 17 is allowed to flow to the first upper electrode 9 of the two-stage active dummy trench 8, and thus the increase in gate voltage due to the displacement current can be suppressed.

[0051] The number of two-stage active dummy trenches 8 can be greater than the number of two-stage active trenches 17. By means of such a configuration, the effect of reducing the displacement flow can be further increased.

[0052] While the projection 10 and the first lower electrode 11 in the two-stage active dummy trench 8 align with each other in the lateral direction of the two-stage active dummy trench 8 in the example of Fig. The positional relationship between the two-stage active dummy trench 8 is not limited to this positional relationship, even though the projection 10 and the first lower electrode 11 cannot face each other in the lateral direction of the two-stage active dummy trench 8. The same applies to the two-stage active trench 17.

[0053] The shape of the first lower electrode 11 is similar to that in modifications 1 and 2 (see Fig. 2 and Fig. 3) in the example of Fig. 10, but it is not limited to this shape. The shape of the first lower electrode 11 can be similar to that in embodiment 1 (see Fig. 1) The same applies to the two-stage active trench 17. <Modifikation 10>

[0054] Fig. Figure 11 is a cross-sectional view of a semiconductor device according to a modification 10 of embodiment 1. As in Fig. As illustrated in Figure 11, in the semiconductor device according to modification 10, the first upper electrode 9 has a smaller cross-sectional area than the first lower electrode 11 in the two-stage active dummy trench 8. Furthermore, the second upper electrode 18 has a smaller cross-sectional area than the second lower electrode 19 in the two-stage active trench 17.

[0055] The cross-sectional area of ​​the first lower electrode 11 and the second lower electrode 19 is increased, so that the wiring resistance of the first lower electrode 11 and the second lower electrode 19 can be reduced, and therefore the increase in gate voltage can be suppressed.

[0056] While the projection 10 and the first lower electrode 11 in the two-stage active dummy trench 8 align with each other in the lateral direction of the two-stage active dummy trench 8 in an example of Fig. The positional relationship between the two-stage active dummy trench 8 is not limited to this positional relationship. The projection 10 and the first lower electrode 11 cannot face each other in the lateral direction of the two-stage active dummy trench 8. The same applies to the two-stage active trench 17.

[0057] The shape of the first lower electrode 11 is similar to that in modifications 1 and 2 (see Fig. 2 and Fig. 3) in the example of Fig. 11, but it is not limited to this shape. The shape of the first lower electrode 11 can be similar to that in embodiment 1 (see Fig. 1) The same applies to the two-stage active trench 17. <Modifikation 11>

[0058] Fig. Figure 12 is a cross-sectional view of a semiconductor device according to a modification 11 of embodiment 1. As in Fig. As illustrated in Figure 12, the semiconductor device according to modification 11 is a reverse-conducting IGBT (RC-IGBT) comprising an IGBT region 26 including the collector layer 6 and a diode region 27 comprising a cathode layer 25, which is provided in the semiconductor substrate on one side of the rear face thereof. The two-stage active trench 17 and the two-stage active dummy trench 8 are arranged in the IGBT region 26, and the two-stage active dummy trenches 8 are arranged in the diode region 27.

[0059] A similar effect to that achieved in embodiment 1 can be achieved in an RC-IGBT as in modification 11. In particular, the two-stage active dummy trenches 8 are arranged in the diode region 27, where no gate is required, so that the displacement current generated in the IGBT region 26 can be drawn to the two-stage active dummy trenches 8, and thus the increase in gate voltage can be suppressed.

[0060] A configuration of the semiconductor device according to modification 11 is not applicable to the one described in Fig. The 12 illustrated configurations are limited and can be as shown in Fig. 13 or Fig. 14 illustrated configurations.

[0061] In the semiconductor device, which is in Fig. As illustrated in Figure 13, two-stage dummy trenches 28 are arranged in the diode region 27. Each two-stage dummy trench 28 is located in the semiconductor substrate on the front surface and each comprises a third upper electrode 29 in an upper stage, which is connected to the emitter electrode 1, and a third lower electrode 30 in a lower stage, which is also connected to the emitter electrode 1. The two-stage dummy trench 28 also includes a third upper insulating layer 31, which is provided on a side wall of the third upper electrode 29, a third lower insulating layer 32, which is provided on a side wall of the third lower electrode 30, and a third boundary insulating layer 33, which is provided between the third upper electrode 29 and the third lower electrode 30.The third upper electrode 29 and the third lower electrode 30 are electrically separated from each other by the third boundary insulating layer 33.

[0062] In a semiconductor device that is in Fig. As illustrated in Figure 14, single-stage dummy trenches 34 are arranged in the diode region 27. The single-stage dummy trenches 34 are each located in the semiconductor substrate on the side of the front surface and each contains a dummy electrode 35 and a dummy insulating layer 36, which is provided on a side wall of the dummy electrode 35.

[0063] The semiconductor device exhibits the in Fig. 13 or Fig. Figure 14 illustrates a configuration that reduces the displacement current flowing into the first lower electrode 11 in the two-stage active dummy trench 8 and the second lower electrode 19 in the two-stage active trench 17 located in the IGBT region 26.

[0064] In diode region 27, the Fig. 12 illustrated two-stage active trench 8, which is in Fig. 13 illustrated two-stage active dummy trench 28, and the one in Fig. Figure 14 illustrated single-stage dummy trenches 34 being combined in a suitable manner for an arrangement.

[0065] While the projection 10 and the first lower electrode 11 in the two-stage active dummy trench 8 align with each other in the lateral direction of the two-stage active dummy trench 8 in the respective examples of the Fig. The positional relationship between electrodes 12 to 14 is not limited to this positional relationship. The projection 10 and the first lower electrode 11 cannot face each other in the lateral direction of the two-stage active dummy trench 8. The same applies to the two-stage active trench 17 and the two-stage active dummy trench 28.

[0066] The shape of the first lower electrode 11 is similar to that in modifications 1 and 2 (see Fig. 2 and Fig. 3) in the respective examples of Fig. 12 to 14, but it is not limited to this form. The shape of the first lower electrode 11 can be similar to that in embodiment 1 (see Fig. 1) The same applies to the two-stage active trench 17 and the two-stage active dummy trench 28. <Modifikation 12>

[0067] Fig. Figure 15 is a cross-sectional view of a semiconductor device according to a modification 12 of embodiment 1. As in Fig. As illustrated in Figure 15, in the semiconductor device according to modification 12, a part of the first upper insulating layer 12, which faces the projection 10, has a smaller layer thickness than the other part of the first upper insulating layer 12 and the first lower insulating layer 13.

[0068] According to modification 12, the part of the first upper insulating layer 12 which faces the projection 10 has a smaller layer thickness than the other part of the first upper insulating layer 12 and the first lower insulating layer 13, so that the displacement current can preferentially flow into the projection 10, and thus the influence of the displacement current on the gate voltage can be reduced.

[0069] The portion of the first upper insulating layer 12 facing the projection 10 can have a greater thickness than the other portion of the first upper insulating layer 12. Such a configuration reduces the total displacement current while maintaining a simple flow of displacement current into the projection 10. A large amount of displacement current flowing into the first upper electrode 9 causes a voltage drop and can affect the gate potential of the first lower electrode 11. Modification 12 reduces the total displacement current, thus minimizing the variation in the gate potential.

[0070] The shape of the first lower electrode 11 is similar to that in modifications 1 and 2 (see Fig. 2 and Fig. 3) in an example of Fig. 15, but it is not limited to this form. The shape of the first lower electrode 11 can be similar to that in embodiment 1 (see Fig. 1). <Modifikation 13>

[0071] In a semiconductor device according to modification 13, the semiconductor substrate comprises a wide-bandgap semiconductor. Examples of wide-bandgap semiconductors include SiC (silicon carbide), GaN (gallium nitride), and Ga₂O₃ (gallium oxide).

[0072] A similar effect to that in embodiment 1 can be obtained even in a configuration where the semiconductor substrate comprises a wide-bandgap semiconductor, as in modification 13. In particular, the wide-bandgap semiconductor enables faster switching compared to Si, so that the displacement current increases due to an increase in dV / dt. The semiconductor device according to the present disclosure features the two-stage active dummy trench 8 with the first upper electrode 9, which contains the projection 10, allowing the displacement current to flow to the first upper electrode 9. Thus, in particular, in the wide-bandgap semiconductor where the displacement current increases, the increase in gate voltage can be suppressed. <Modifikation 14>

[0073] Fig. Figure 16 is a cross-sectional view of a semiconductor device according to a modification 14 of embodiment 1. As in Fig. As illustrated in Figure 16, the semiconductor device according to modification 14 is a metal-oxide-semiconductor field-effect transistor (MOSFET) which has a drain layer 37 provided in the semiconductor substrate on one side of the back face and a drain electrode 38 provided on one side of the back face of the drain layer 37. The further configuration is similar to that in embodiment 1 (see Figure 16). Fig. 1).

[0074] The MOSFET is a unipolar device in which holes do not contribute to operation, so the influence of the displacement current due to holes is small. On the other hand, the absence of holes allows the MOSFET to switch faster, thus increasing dV / dt. The displacement current is determined by the product of dV / dt and Cgd (a gate-drain capacitance) and therefore increases in the MOSFET during high-frequency operation. According to modification 14, the two-stage active dummy trench 8, which includes the first upper electrode 9 and has a projection 10, is incorporated so that the displacement current can flow to the first upper electrode 9 and the increase in gate voltage can be suppressed.

[0075] The shape of the first lower electrode 11 is similar to that in embodiment 1 (see Fig. 1) in an example of Fig. 16, but it is not limited to this form. The shape of the first lower electrode 11 can be similar to that in modifications 1 and 2 (see Fig. 2 and Fig. 3).

[0076] The embodiment may be suitably modified or omitted within the scope of protection of the present disclosure. Attachments

[0077] The following sections describe different aspects of the present revelation together as appendices. Appendix 1

[0078] comprising a semiconductor device: a semiconductor substrate; a base layer located on one side of a front surface of the semiconductor substrate; and a two-stage active dummy trench located in the semiconductor substrate on the side of its front surface to extend through the base layer, wherein the two-stage active dummy trench comprises a first upper electrode in an upper stage, which is connected to an emitter electrode, and a first lower electrode in a lower stage, which is connected to a gate electrode, wherein the first upper electrode has a projection which extends from at least one of the left and right positions of an end face thereon on one side of a rear surface in the direction of the rear surface, and where the tip of the projection is closer to the back surface than the base layer. Appendix 2

[0079] Semiconductor device according to Appendix 1, wherein The projection and the first lower electrode are oriented towards each other in a lateral direction of the trench. Appendix 3

[0080] Semiconductor device according to Appendix 1 or 2, wherein the first lower electrode has a part with a first width on the side of the front surface and a part with a second width, which is greater than the first width, on the side of the rear surface, the part with the first width faces the projection in the width direction of the trench, and the part with the second width is not facing the projection in the width direction of the trench. Appendix 4

[0081] Semiconductor device further comprising one of Appendices 1 to 3 a two-stage active trench located in the semiconductor substrate on the side of the front face thereof to extend through the base layer, wherein the two-stage active trench has a second upper electrode in an upper stage which is connected to the gate electrode and a second lower electrode in a lower stage which is connected to the gate electrode. Appendix 5

[0082] Semiconductor device according to one of Appendices 1 to 4, wherein The semiconductor device is an insulated gate bipolar transistor (IGBT) which has a collector layer located in the semiconductor substrate on the side of the rear surface thereof. Appendix 6

[0083] Semiconductor device further comprising one of Appendices 1 to 5 a charge carrier storage layer located on one side of the rear surface of the base layer. Appendix 7

[0084] Semiconductor device according to any one of Appendices 1 to 6, wherein The two-stage active dummy trench has a first upper insulating layer located on a side wall of the first upper electrode and a first lower insulating layer located on a side wall of the first lower electrode, and The first lower insulating layer has a greater thickness than the first upper insulating layer. Appendix 8

[0085] Semiconductor device according to any one of Appendices 1 to 7, wherein The projection has a greater length in a part of the first upper electrode, starting from an end face thereon on the side of the front face to the front face of the origin of the projection. Appendix 9

[0086] Semiconductor device according to one of Appendices 1 to 8, wherein the origin of the protrusion is located closer to the rear surface than the base layer. Appendix 10

[0087] Semiconductor device according to one of Appendices 1 to 8, wherein where the origin of the projection is located closer to the front surface than where it is an end surface on the side of the rear surface of the base layer. Appendix 11

[0088] Semiconductor device according to Appendix 4, wherein The two-stage active dummy trench is arranged next to the two-stage active trenches on opposite sides of the two-stage active trench. Appendix 12

[0089] Semiconductor device according to any one of Appendices 1 to 11, wherein the first upper electrode has a smaller cross-sectional area than the first lower electrode. Appendix 13

[0090] Semiconductor device according to any one of Appendices 1 to 12, wherein The semiconductor device is a backward-conducting IGBT (an RC-IGBT) which has an IGBT region comprising a collector layer located in the semiconductor substrate on the rear face and a diode region comprising a cathode layer located in the semiconductor substrate on the rear face. Appendix 14

[0091] Semiconductor device according to any one of Appendices 1 to 13, wherein The two-stage active dummy trench has a first upper insulating layer located on a side wall of the first upper electrode and a first lower insulating layer located on a side wall of the first lower electrode, and A part of the first upper insulating layer, which faces the projection, has a smaller layer thickness than the other part of the upper insulating layer and the first lower insulating layer. Appendix 15

[0092] Semiconductor device according to any one of Appendices 1 to 14, wherein the semiconductor substrate has a semiconductor with a wide band gap. Appendix 16

[0093] Semiconductor device according to one of Appendices 1 to 3, wherein The semiconductor device is a metal-oxide-semiconductor field-effect transistor (MOSFET) which has a drain layer located in the semiconductor substrate on the side of the back surface.

[0094] While the revelation has been shown and described in detail, the preceding description is illustrative in all aspects and not limiting. It is therefore understood that numerous modifications and variations can be conceived. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2023-37881

[0002]

Claims

[1] comprising a semiconductor device: • a semiconductor substrate; • a base layer (3) located in the semiconductor substrate on one side of a front face thereof; and • a two-stage active dummy trench (8) located in the semiconductor substrate on the side of its front surface to extend through the base layer (3), wherein the two-stage active dummy trench (8) comprises a first upper electrode (9) in an upper stage, which is connected to an emitter electrode (1), and a first lower electrode (11) in a lower stage, which is connected to a gate electrode, wherein • the first upper electrode (9) has a projection (10) which extends from at least one of the left and right positions of an end face thereon on one side of a rear surface in the direction of the rear surface, and • a tip (15) of the projection (10) is closer to the rear surface than the base layer (3). [2] Semiconductor device according to claim 1, wherein the projection (10) and the first lower electrode (11) are oriented towards each other in a lateral direction of the trench. [3] Semiconductor device according to claim 1 or 2, wherein • the first lower electrode (11) includes a part which has a first width on the side of the front surface and a part which has a second width, which is greater than the first width, on the side of the rear surface, • the part which has the first width, is facing the projection (10) in the width direction of the trench, and • the part which has the second width, is not facing the projection (10) in the width direction of the trench. [4] Semiconductor device according to one of claims 1 to 3 further comprising a two-stage active trench (17) located in the semiconductor substrate on one side of the front surface thereof to extend through the base layer (3), wherein the two-stage active trench (17) comprises a second upper electrode (18) in an upper stage which is connected to the gate electrode and a second lower electrode (19) in a lower stage which is connected to the gate electrode. [5] Semiconductor device according to any one of claims 1 to 4, wherein the semiconductor device is an insulated gate bipolar transistor (IGBT) having a collector layer (6) located in the semiconductor substrate on the side of the rear surface thereof. [6] Semiconductor device according to one of claims 1 to 5 further comprising a charge carrier storage layer (23) located on one side of the rear surface of the base layer (3). [7] Semiconductor device according to any one of claims 1 to 6, wherein • the two-stage active trench (8) comprises a first upper insulating layer (12) located on a side wall of the first upper electrode (9) and a first lower insulating layer (13) located on a side wall of the first lower electrode (11), and • the first lower insulating layer (13) has a greater layer thickness than the first upper insulating layer (12). [8] Semiconductor device according to any one of claims 1 to 7, wherein the projection (10) has a greater length than a part of the first upper electrode (9) extending from an end face thereof on the side of the front face to an origin (24) of the projection (10). [9] Semiconductor device according to any one of claims 1 to 8, wherein an origin (24) of the projection (10) is located closer to the rear surface than the base layer (3). [10] Semiconductor device according to any one of claims 1 to 8, wherein an origin (24) of the projection (10) is located closer to the front surface than an end surface on the side of the rear surface of the base layer (3). [11] Semiconductor device according to claim 4, wherein the two-stage active dummy trench (8) is arranged next to the two-stage active trench (17) on opposite sides of the two-stage active trench (17). [12] Semiconductor device according to any one of claims 1 to 11, wherein the first upper electrode (9) has a smaller cross-sectional area than the first lower electrode (11). [13] Semiconductor device according to any one of claims 1 to 12, wherein the semiconductor device is a backward-conducting IGBT (an RC-IGBT) which has an IGBT region (26) containing a collector layer (6) located in the semiconductor substrate on the side of the back face and a diode region (27) containing a cathode layer (25) located in the semiconductor substrate on the side of the back face. [14] Semiconductor device according to any one of claims 1 to 13, wherein • the two-stage active trench (8) comprises a first upper insulating layer (12) located on a side wall of the first upper electrode (9) and a first lower insulating layer (13) located on a side wall of the first lower electrode (11), and • a part of the first upper insulating layer (12), which faces the projection (10), has a lesser layer thickness than the other part of the first upper insulating layer (12) and the first lower insulating layer (13). [15] Semiconductor device according to any one of claims 1 to 14, wherein the semiconductor substrate comprises a wide bandgap semiconductor. [16] Semiconductor device according to any one of claims 1 to 3, wherein the semiconductor device is a metal-oxide-semiconductor field-effect transistor (MOSFET) which has a drain layer (37) located in the semiconductor substrate on the side of the back surface.

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