DISPLAY DEVICE

Abstract

A display device is provided, comprising a substrate, a display area, and a non-display area; a pixel driver circuit in the display area on the substrate; an insulating layer on the pixel driver circuit; a bank arranged in several subpixels, including a first subpixel and a second subpixel, on the insulating layer; a first electrode arranged on the bank and comprising a central area, an edge area, and a reflective area between the central area and the edge area; and a light emission device electrically connected to the first electrode and overlapping the bank. The width of a reflective area of ​​the first electrode in the first subpixel differs from the width of a reflective area of ​​the first electrode in the second subpixel.

Description

[0001] This application claims the benefit and priority of Korean patent application No. 10-2024-0118536, filed on September 2, 2024. BACKGROUND 1. Technical field

[0002] The present disclosure relates to a display device. 2. Description of the related technology

[0003] A display device is applied to various electronic devices such as televisions, mobile phones, laptops and tablets.

[0004] The display devices include an organic light emission display (OLED), which emits light independently, and a liquid crystal display (LCD), which requires a separate light source.

[0005] Recently, a display device using a light-emitting diode (LED) has attracted attention as a next-generation display. The LED is made of an inorganic material, not an organic one. Consequently, compared to liquid crystal displays or organic light-emitting displays, the LED display exhibits a higher illumination speed and excellent luminous efficiency, displaying a high-luminance image.

[0006] In the case of a display device with a light emission device, a process is required to transfer multiple light emission devices onto a substrate. However, an error can occur during the transfer process, where the light emission device cannot be transferred into the correct position for various reasons.

[0007] The description of related technology should not be considered prior art merely because it is mentioned or associated with this section. The description of related technology comprises information describing one or more aspects of the technology in question, and the description in this section does not limit the scope of protection of the invention. SUMMARY

[0008] The present disclosure was made in light of the above problems, and it is an objective of the present disclosure to provide a display device that can reduce errors that may occur during a transfer process of light emission devices. One or more of these problems are solved by the features of the independent claims.

[0009] According to one aspect of the present disclosure, a display device comprises a substrate, a display area and a non-display area, a pixel drive circuit in the display area on the substrate, an insulating layer on the pixel drive circuit, a bank arranged in several subpixels, including a first subpixel and a second subpixel, on the insulating layer, a first electrode arranged on the bank and comprising a central area, an edge area and a reflection area between the central area and the edge area, and a light emission device arranged on the first electrode and electrically connected to the first electrode and overlapping the bank: The width of the reflection area of ​​the first electrode in the first subpixel may differ from the width of the reflection area of ​​the first electrode in the second subpixel.

[0010] The width of the central area of ​​the first electrode in the first subpixel can be equal to the width of the central area of ​​the first electrode in the second subpixel.

[0011] The width of the reflection area of ​​the first electrode in the first subpixel can be larger than the width of the reflection area of ​​the first electrode in the second subpixel.

[0012] The width of the edge region of the first electrode in the first subpixel can be smaller than the width of the edge region of the first electrode in the second subpixel.

[0013] The first electrode can comprise multiple conductive layers, including a first conductive layer and a second conductive layer that is distinct from the first. The upper surface of the central region and the edge region of the first electrode can comprise the same first conductive layer. The upper surface of the reflection region of the first electrode can comprise the second conductive layer.

[0014] The first conductive layer can be made from a transparent conductive oxide.

[0015] The second conductive layer can be located below the first conductive layer and / or can be made of a reflective material.

[0016] The first electrode and the light emission device can be electrically connected by a solder pattern. The central area of ​​the first electrode can overlap with the solder pattern. The reflection area and the edge area of ​​the first electrode do not need to overlap with the solder pattern.

[0017] The reflection area of ​​the first electrode can surround the central area of ​​the first electrode and / or the edge area of ​​the first electrode can surround the reflection area of ​​the first electrode.

[0018] The display device may further include a signal line arranged on the insulating layer and / or electrically connecting the first electrode to the pixel control circuit. The edge region of the first electrode may extend to and be connected to the signal line.

[0019] The display device may further include a passivation layer on the first electrode. The passivation layer may cover the reflection area and the edge area of ​​the first electrode.

[0020] The display device may further comprise a second electrode which is provided on the light emission device and is electrically connected to the light emission device.

[0021] The display device may further comprise a first optical layer provided below the second electrode and / or covering a side surface of the light emission device and a side surface of the bank.

[0022] The display device may further comprise a second optical layer in contact with a side surface of the first optical layer.

[0023] The display device may further comprise a black matrix on the second electrode. The display device may further comprise a third optical layer between the second electrode and the black matrix.

[0024] Each subpixel can have a light-emitting device or light-emitting element. The light-emitting device or light-emitting element can be a light-emitting diode made of an inorganic material.

[0025] The pixel control circuits can be circuits for controlling the light emission devices.

[0026] According to one aspect of the present disclosure, a display device further comprises a display area with a first display area, a second display area, and a third display area between the first and second display areas, multiple light-emitting devices arranged in multiple subpixels with a matrix structure in the display area, and multiple first electrodes electrically connected to the multiple light-emitting devices in the multiple subpixels, each electrode comprising a central area, an edge area, and a reflection area between the central area and the edge area. The widths of the reflection areas of the multiple first electrodes may differ from one another in the multiple subpixels in the third display area.

[0027] The widths of the reflection areas of the multiple first electrodes in the multiple subpixels in the first display area and in the second display area can be the same.

[0028] The multiple first electrodes in the multiple subpixels in the third display area can include the multiple first electrodes with the reflection areas with widths of all sizes from the reflection area with the smallest width to the reflection area with the largest width among several widths applied to the entire display area.

[0029] The width of the reflection area of ​​the multiple first electrodes in the multiple subpixels in the third display area can gradually increase or decrease as the row or column of the matrix structure increases.

[0030] The width of the reflection area of ​​the multiple first electrodes in the multiple subpixels in the third display area can gradually increase or decrease as the column in an odd row increases, and / or can gradually decrease or increase as the column in an even row increases.

[0031] The width of the reflection area of ​​the multiple first electrodes in the multiple subpixels in the third display area can gradually increase or decrease as the column increases in two adjacent rows, and / or can gradually decrease or increase as the column increases in other two adjacent rows.

[0032] The width of the reflection area of ​​the multiple first electrodes in the multiple subpixels in the third display area can gradually increase or decrease as the number of rows in an odd column increases, and / or can gradually decrease or increase as the number of rows in an even column increases.

[0033] The width of the reflection area of ​​the multiple first electrodes in the multiple subpixels in the third display area can gradually increase or decrease as the number of rows in two adjacent columns increases, and / or can gradually decrease or increase as the number of rows in other two adjacent columns increases.

[0034] According to one aspect of the present disclosure, a display device further comprises a display area with a first display area, a second display area on a right-hand side of the first display area, a third display area between the first display area and the second display area, a fourth display area on a left-hand side of the first display area, a fifth display area below the fourth display area; and a sixth display area between the fourth display area and the fifth display area, several light-emitting devices in several subpixels with a matrix structure in the display area, and several first electrodes electrically connected to the several light-emitting devices in the several subpixels, comprising a central area, an edge area, and a reflection area between the central area and the edge area.The width of the reflection area of ​​the multiple first electrodes in the multiple subpixels in the third display area can gradually increase or decrease as a column of the matrix structure increases, and / or the width of the reflection area of ​​the multiple first electrodes in the multiple subpixels in the sixth display area can gradually increase or decrease as a row of the matrix structure increases. The widths of the reflection areas of the multiple first electrodes in the multiple subpixels in the first display area, the second display area, the fourth display area, and the fifth display area can be the same.

[0035] Additional features, advantages, and aspects of the present disclosure are partly set forth in the following description and partly become apparent from the present disclosure or can be learned by carrying out the invention concepts provided herein. Other features, advantages, and aspects of the present disclosure can be realized and achieved through or derived from the descriptions provided in the present disclosure and the claims thereto and the drawings. It is intended that all such features, advantages, and aspects are contained within this description, are within the scope of protection of the present disclosure, and are protected by the following claims. Nothing in this section should be construed as limiting these claims. Further aspects and advantages are discussed below in connection with embodiments of the present disclosure.

[0036] It should be self-evident that both the preceding description and the following description of the present revelation are examples and are intended to provide a further explanation of the revelation, as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings, which are included to provide a further understanding of the present revelation, are integrated into and form a part of this present revelation, represent aspects and embodiments of the present revelation, and, together with the description, serve to explain principles and examples of the revelation. Fig. Figure 1 is a perspective view of a display device according to an embodiment of the present disclosure in an expanded arrangement. Fig. Figure 2 is a top view of a display device according to an embodiment of the present disclosure. Fig. Figure 3 is an enlarged view of a display device according to an embodiment of the present disclosure. Fig. Figure 4 is a diagram representing a circuit structure according to an embodiment of the present disclosure. Fig. Figure 5 is a top view of a display device according to an embodiment of the present disclosure. Fig. Figure 6 is a top view of a display device according to an embodiment of the present disclosure. Fig. Figure 7 is a top view of a display device according to an embodiment of the present disclosure. Fig. Figure 8 is a cross-sectional view of a display device according to an embodiment of the present disclosure. Fig. Figure 9 is a cross-sectional view of a display device according to an embodiment of the present disclosure. Fig. 10A is a top view showing a transition area of ​​a display device according to an embodiment of the present disclosure. Fig. 10B is a top view showing a transition area of ​​a display device according to another embodiment of the present disclosure. Fig. 11A and Fig. Figures 11B are a cross-sectional view and a top view of a subpixel according to an embodiment of the present disclosure. Fig. 12A and Fig. Figures 12B are a cross-sectional view and a top view of a subpixel according to another embodiment of the present disclosure. Fig. 13A and Fig. Figure 13B shows a cross-sectional view and a top view of a subpixel according to another embodiment of the present disclosure. Fig. 14A and Fig. Figures 14B are a cross-sectional view and a top view of a subpixel according to another embodiment of the present disclosure. Fig. 15 represents several subpixels located in an X-region of Fig. 10A according to an embodiment of the present disclosure, for example in a region near a first boundary line between a first transfer region and a second transfer region. Fig. 16 represents several subpixels located in an X-region of Fig. 10A according to another embodiment of the present disclosure, for example in a region near a first boundary line between a first transfer region and a second transfer region. Fig. 17 represents several subpixels located in a Y-region of Fig. 10A according to another embodiment of the present disclosure, for example in a region near a second boundary line between a first transfer region and a third transfer region. Fig. 18 represents several subpixels located in a Y-region of Fig. 10A according to another embodiment of the present disclosure, for example in a region near a second boundary line between a first transfer region and a third transfer region. Fig. 19 represents several subpixels located in a Z-region of Fig. 10A according to another embodiment of the present disclosure, for example in a nearby region in which a first boundary line between a first transfer region and a second transfer region and a second boundary line between a first transfer region and a third transfer region intersect. Fig. 20 represents several subpixels located in a Z-region of Fig. 10A according to another embodiment of the present disclosure, for example, are arranged in a nearby region in which a first boundary line between a first transfer region and a second transfer region and a second boundary line between a first transfer region and a third transfer region intersect. Fig. Diagrams 21 to 24 are diagrams depicting devices to which a display device according to embodiments of the disclosure is applied.

[0038] Unless otherwise specified, all drawing reference symbols used in the drawings and detailed descriptions should be understood as referring to the same elements, features, and structures. The relative size and representation of these elements may be exaggerated for the sake of clarity, illustration, and practicality. Detailed description

[0039] Reference will now be made in detail to embodiments of the present disclosure, examples of which may be shown in the accompanying drawings. The progression of described processing steps and / or operations is an example; however, the sequence of steps and / or operations is not limited to that set forth here and may be modified as is known in the field, with the exception of steps and / or operations that necessarily take place in a specific order. The names of the respective elements used in the following explanations may only be chosen for the convenience of writing the patent description and may therefore differ from those used in actual products.

[0040] The advantages and features of the present disclosure and its implementation methods are illustrated by the following embodiments, which are described with reference to the accompanying drawings. However, the present disclosure can be embodied in various forms and should not be considered limited to the embodiments presented here. Rather, these embodiments are intended to ensure that this disclosure is thorough and complete and fully conveys the scope of protection of the present disclosure to the person skilled in the field. Furthermore, the present disclosure is defined only by the scope of protection of the claims.

[0041] A shape, size, ratio, angle, and number disclosed in the drawings to describe embodiments of the present disclosure are merely examples, and consequently, the present disclosure is not limited to the details shown. The same reference numerals refer to the same elements throughout the patent description. If, in the following description, a detailed description of the relevant known function or configuration is determined to make the important point of the present disclosure unnecessarily unclear, the detailed description is omitted. In cases where "comprise," "have," and "include," as described in the present disclosure, are used, another part may be added if "only" is not used. Terms in a singular form may include plural forms unless otherwise indicated.An element can be, for example, one or more elements. An element can comprise multiple elements. The word "exemplary" is used to indicate serving as an example or explanation. Embodiments are exemplary embodiments. Aspects are exemplary aspects. In one or more implementations, "embodiments," "examples," "aspects," and the like should not be considered as preferred or advantageous over other implementations. An embodiment, an example, an exemplary embodiment, an aspect, or the like may refer to one or more embodiments, one or more examples, one or more exemplary embodiments, one or more aspects, or the like, unless otherwise specified. Furthermore, the term "may" encompasses all meanings of the term "can."

[0042] When interpreting the components, this is interpreted as encompassing the entire fault area if no separate explicit description of the fault area exists.

[0043] When describing a positional relationship, for example, when the positional sequence is described as "on top," "above," "below," and "next to," one or more parts may be positioned between two other parts unless "only" or "directly" is used. Terms such as "below," "lower," "above," "upper," and the like can be used here to describe a relationship between elements, as illustrated in the drawings. It is understood that these terms are spatially relative and based on the orientation shown in the drawings.

[0044] A description of a temporal relationship may include a case where the temporal ranking relationship is described as "after", "following", or "before", etc., and is not continuous unless "immediately" or "directly" is used.

[0045] Although terms like "first," "second," and the like are used to describe different components, these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, a first component mentioned below may be a second component in a technical idea of ​​the present disclosure.

[0046] It is self-evident that, although the terms "first," "second," "A," "B," "(a)," and "(b)," etc., may be used here to describe different elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. A first element, for example, could be called a second element, and likewise a second element could be called a first element, without departing from the scope of protection of the present disclosure.

[0047] If a component is specified as being "connected", "coupled", "linked", or "attached" to another component, that component may be directly connected, coupled, linked, or attached to that other component, but it should be understood that other components may be inserted between any component, which may be indirectly connected, coupled, linked, or attached without any specific description.

[0048] It should be self-evident that if a component or layer is specified as being "in contact" or "overlapping" with another component or layer, that component or layer may be in direct contact or overlapping with another component or layer, but other components may be inserted between any component that may be in indirect contact or overlapping without a specific explicit description.

[0049] The term "at least one" should be understood to encompass all combinations of one or more of the related listed items. For example, the meaning of "at least one of a first element, a second element, and a third element" includes combinations of all three listed elements, combinations of any two of the three elements, and each individual element—the first element, the second element, or the third element.

[0050] “First direction”, “second direction”, “third direction”, “X-axis direction”, “Y-axis direction” and “Z-axis direction” should not only be interpreted as mutually perpendicular geometric relationships, but may mean that the configuration of the present disclosure has a wider direction within a range in which the configuration of the present disclosure can function functionally.

[0051] Features of each of the different embodiments of the present patent description can be partially or completely coupled or combined with each other, technically different cooperation and control are possible, and each of the embodiments can be implemented independently with reference to each other or can be implemented in a related relationship with each other.

[0052] An embodiment of the present disclosure is described in detail below with reference to the accompanying drawings.

[0053] Fig. Figure 1 is a perspective view representing a display device according to an embodiment of the present disclosure.

[0054] With reference to Fig. 1. A display device 1000 according to an embodiment of the present disclosure may comprise a display field 100, a polarization layer 280, an adhesive layer 290, a cover element 120, a support substrate 190, a flexible printed circuit board 170 and a printed circuit board 160.

[0055] Display field 100 can implement information, a video and / or an image that is provided to a user.

[0056] The polarization layer 280 can be arranged on the display field 100. The polarization layer 280 can prevent or reduce the amount of light generated by an external light source entering the display field 100 and affecting a light-emitting element or the like.

[0057] The adhesive layer 290 can attach the cover element 120 to the display field 100. The adhesive layer 290 can be arranged between the polarization layer 280 and the cover element 120 to attach the cover element 120 to the polarization layer 280. The adhesive layer 290 can comprise an optically clear adhesive (OCA), an optically clear resin (OCR), a pressure-sensitive adhesive (PSA), or the like, but embodiments of the present disclosure are not limited thereto.

[0058] The cover element 120 can be arranged on the polarization layer 280. The cover element 120 can be arranged on the adhesive layer 290. The cover element 120 can be an element for protecting the display field 100. The cover element 120 can be made of a transparent material.

[0059] The support substrate 190 can be arranged between the display panel 100 and the printed circuit board 160. The support substrate 190 can increase the rigidity of the display panel 100. The support substrate 190 can be a backplate, but embodiments of the present disclosure are not limited to this.

[0060] The flexible circuit board 170 and the printed circuit board 160 can be arranged on a bottom side of the display field 100. The flexible circuit board 170 and the printed circuit board 160 can be arranged on at least one edge of the display field 100, but embodiments of the present disclosure are not limited thereto. One side of the flexible circuit board 170 can be attached to the display field 100 and the other side of the flexible circuit board 170 can be attached to the printed circuit board 160, but embodiments of the present disclosure are not limited thereto. The flexible circuit board 170 can be a flexible film, but embodiments of the present disclosure are not limited thereto.

[0061] The printed circuit board 160 can include at least one hole 180, but embodiments of the present disclosure are not limited thereto. An internal component that detects ambient light or temperature, which can be supplied to multiple sensors, can be arranged in an area corresponding to the at least one hole 180. The internal component can, for example, include an ambient light sensor (ALS) or a temperature sensor, but embodiments of the present disclosure are not limited thereto. The hole 180 can, for example, be a through-hole, etc., but embodiments of the present disclosure are not limited thereto.

[0062] Fig. Figure 2 is a top view of a display device according to an embodiment of the present disclosure. And Fig. Figure 3 is an enlarged view of a display device according to an embodiment of the present disclosure.

[0063] With reference to Fig. 2 and Fig. 3. The display device 1000 can include the display panel 100, the flexible circuit board 170 and the printed circuit board 160.

[0064] The display field 100 can comprise a substrate 110. The substrate 110 can be an element that supports other components of the display device 1000. The substrate 110 can be made of an insulating material. For example, the substrate 110 can be made of glass or resin. The substrate 110 can also be made of a flexible material. For example, the substrate 110 can be made of a flexible plastic material such as polyimide (PI). However, embodiments of the present disclosure are not limited thereto.

[0065] The display field 100 can, for example, comprise a display area AA and a non-display area NA. The substrate 110 can, for example, comprise the display area AA and the non-display area NA. The display area AA and the non-display area NA are not limited to the substrate 110, but can be described in the entire display device 1000.

[0066] The display area AA can be an area in which an image is displayed. The display area AA can comprise multiple pixels PX. Each of the multiple pixels PX can comprise multiple subpixels. Multiple light-emitting elements can be arranged in each of the multiple subpixels. Multiple light-emitting elements can be configured to be different according to a type of display device 1000. For example, if the display device 1000 is an inorganic light-emitting display device, the light-emitting element can be a light-emitting diode (LED), a micro-light-emitting diode (micro-LED), or a miniature light-emitting diode (MLED), but embodiments of the present disclosure are not limited thereto.

[0067] The display area AA can be configured in various shapes according to the design of the display device 1000. For example, the display area AA can be configured in a rectangular shape with four rounded corners, but configurations of the present disclosure are not limited to these. As another example, the display area AA can be configured in a rectangle with four corners or in a circular shape, but configurations of the present disclosure are not limited to these.

[0068] With reference to Fig. 3. Multiple pixel drive circuits (PDs) can be arranged in the display area (AA). These multiple pixel drive circuits (PDs) can be circuits for driving light-emitting elements (LEDs) of multiple subpixels. Each PD can include multiple transistors with drive transistors and storage capacitors. Furthermore, each PD can control a light emission operation of the LEDs by supplying a control signal, a power source, and a drive current to the LEDs of the multiple subpixels. For example, a PD can include a power line and a signal line for switching the LED on and off and / or controlling the LED's emission time.The multiple pixel drive circuits PD can, for example, be drive drivers fabricated using a manufacturing process for a metal oxide silicon field-effect transistor (MOSFET) on a semiconductor substrate, but embodiments of the present disclosure are not limited thereto. The drive driver comprises the multiple pixel drive circuits PD and can drive the multiple subpixels.

[0069] The non-display area NA can be an area in which no image is displayed. Various wiring, circuits, and the like for controlling the multiple pixels PX of the display area AA can be arranged in the non-display area NA. For example, various wiring and control circuits can be mounted in the non-display area NA. A contact point part PAD, connected to an integrated circuit, a printed circuit, and the like, can also be arranged in the non-display area NA, but embodiments of the present disclosure are not limited thereto.

[0070] The control circuit can be, for example, a data control circuit and / or a gate control circuit, but embodiments of the present disclosure are not limited thereto. Wiring to which a control signal for controlling the control circuits is supplied can be arranged in the non-display area NA. The control signal can, for example, comprise various timing signals, including a clock signal, an input data enable signal, and synchronization signals, but embodiments of the present disclosure are not limited thereto. The control signal can be received by the contact point part PAD. Link lines LL for transmitting a signal can, for example, be arranged in the non-display area NA. A control component, such as the flexible printed circuit board 170 and the printed circuit board 160, can be connected to the contact point part PAD.

[0071] According to the present disclosure, the non-display area NA can comprise a first non-display area NA1, a bending area BA, and a second non-display area NA2. The first non-display area NA1 can, for example, be an area surrounding at least a portion of the display area AA. The bending area BA can be an area extending from at least one of several sides of the first non-display area NA1 and can be a bendable area. The second non-display area NA2 is an area extending from the bending area BA, and the contact point portion PAD can be located there. The bending area BA can, for example, be curved, and a remaining area of ​​the substrate 110 apart from the bending area BA can be flat. In this case, if the bending area BA is curved, the second non-display area NA2 can be located on a rear surface of the display area AA.However, embodiments of the present disclosure are not limited thereto.

[0072] Several interconnection lines LL can be arranged in the non-display area NA. These interconnection lines LL can be wires for transmitting various signals from one or more flexible printed circuit boards (or flexible films) 170 and the printed circuit board 160 to the display area AA. The interconnection lines LL can extend from several contact electrodes PE of the second non-display area NA2 towards the bending area BA and the first non-display area NA1 and can be electrically connected to several drive lines VL of the display area AA. The multiple pixel drive circuits PD can be driven by receiving signals from one or more flexible printed circuit boards (or flexible films) 170 and the printed circuit board 160 via the drive line VL in the display area AA and the interconnection line LL in the non-display area NA.

[0073] The multiple control lines VL can, for example, be wiring for transmitting a signal output from the flexible circuit board (or flexible film) 170 and the printed circuit board 160 to the multiple pixel drive circuits PD via the multiple linkage lines LL. The multiple control lines VL can be located in the display area AA and be electrically connected to each of the multiple pixel drive circuits PD. The multiple control lines VL can extend from the display area AA towards the non-display area NA and can be electrically connected to the multiple linkage lines LL. Consequently, the signal output from the flexible circuit board (or flexible film) 170 and the printed circuit board 160 can be transmitted to each of the multiple pixel drive circuits PD via the multiple linkage lines LL and the multiple control lines VL.

[0074] When the bending region BA is bent, sections of the multiple linking lines LL may also be bent. Stress is concentrated on a section of the bent linking line LL, and consequently, a crack may occur in the linking line LL. Therefore, the multiple linking lines LL may be formed from a conductive material with excellent ductility to reduce cracking when the bending region BA is bent. For example, the multiple linking lines LL may be formed from a conductive material with excellent ductility, such as gold (Au), silver (Ag), aluminum (Al), and the like, but embodiments of the present disclosure are not limited thereto. The multiple linking lines LL may also be formed from one of the various conductive materials used in the display region AA.The multiple interconnection conductors LL can be made, for example, of molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), an alloy of silver (Ag) and magnesium (Mg), or the like, but embodiments of the present disclosure are not limited thereto. The multiple interconnection conductors LL can be a multilayer structure with different conductive materials. The multiple interconnection conductors LL can, for example, be a triple-layer structure with titanium (Ti), aluminum (Al), and titanium (Ti), but embodiments of the present disclosure are not limited thereto.

[0075] Multiple linking lines LL can be configured in various shapes to reduce stress. At least one segment of the multiple linking lines LL, located on the bending area BA, can extend in the same direction as the direction of the bending area BA or in a direction different from the direction of the bending area BA to reduce stress. For example, if the bending area BA extends in one direction from the first non-indication area NA1 to the second non-indication area NA2, at least one segment of the linking line LL, located on the bending area BA, can extend in a direction inclined to that one direction. As another example, at least one segment of the multiple linking lines LL can comprise patterns with different shapes.At least one section of the multiple interconnecting lines LL, arranged on the bending region BA, may, for example, have a shape in which a conductive pattern with at least one of a diamond shape, a rhombus shape, a trapezoidal shape, a triangular waveform, a sawtooth waveform, a sinusoidal shape, a circular shape, and an omega shape is repeatedly arranged, but embodiments of the present disclosure are not limited thereto. Therefore, to minimize the stress concentrated on the multiple interconnecting lines LL and the corresponding cracking, the shape of the multiple interconnecting lines LL may be formed in various shapes, including the shape described above, but embodiments of the present disclosure are not limited thereto.

[0076] According to the present disclosure, the width of the second non-display area NA2, in which the multiple contact electrodes PE are arranged, can be wider than the width of the bending area BA, in which only the multiple linking wires LL are arranged. Similarly, the width of the display area AA, in which the multiple subpixels are arranged, can be wider than the width of the bending area BA, in which only the multiple linking wires LL are arranged. Although the width of the bending area BA is shown to be narrower than the width of other areas of the substrate 110, one form of the substrate 110 with the bending area BA is exemplary, and embodiments of the present disclosure are not limited to it.

[0077] A contact point part PAD with multiple contact point electrodes PE can be arranged in the second non-display area NA2. A driver component with one or more of the flexible printed circuit boards (or flexible films) 170 and the printed circuit board 160 can be attached to or bonded to the contact point part PAD. The multiple contact point electrodes PE of the contact point part PAD are electrically connected to one or more flexible printed circuit boards (or flexible films) 170, and various signals (or power) received by the printed circuit board 160 and the flexible printed circuit board (or flexible film) 170 can be transmitted to the multiple pixel driver circuits PD of the display area AA.

[0078] The flexible printed circuit board (or flexible film) 170 can be a film in which various components are arranged on a flexible base film. For example, a driver IC, such as a gate driver IC or a data driver IC, can be arranged on the flexible printed circuit board (or flexible film), but embodiments of the present disclosure are not limited thereto. The driver IC can be a component that processes data and a drive signal for displaying an image. The driver IC can be arranged by a chip-on-glass (COG) or chip-on-film (COF) or tape carrier package (TCP) method, depending on the method by which it is mounted, but embodiments of the present disclosure are not limited thereto.The flexible printed circuit board (or flexible film) 170 can be attached to or bonded to the multiple contact electrodes PE by means of a conductive adhesive layer, but embodiments of the present disclosure are not limited thereto.

[0079] The printed circuit board 160 can be a component that is electrically connected to one or more flexible circuit boards (or flexible films) 170 and supplies signals to the driver IC. The printed circuit board 160 can be located on one side of the flexible circuit board (or flexible film) 170 and can be electrically connected to the flexible circuit board (or flexible film). Various components for supplying various signals to the driver IC can be arranged on the printed circuit board 160. Various components, such as a timing control unit, a power supply unit, a memory, a processor, etc., can be arranged on the printed circuit board 160, for example. The printed circuit board 160 can, for example, include an integrated power management circuit (PMIC), but embodiments of the present disclosure are not limited to this.

[0080] Fig. Figure 4 is a diagram representing a circuit structure according to an embodiment of the present disclosure.

[0081] Fig. Figure 4 shows that a light-emitting device (LED) is connected to a microdriver (µDriver), but this is not limited to the number of connected devices. For example, eight LEDs can be connected to one microdriver (µDriver). Alternatively, 16, 32, or 64 LEDs can be connected to one microdriver (µDriver) simultaneously. The LED can be a micro-LED.

[0082] A microdriver (µDriver) can control a drive transistor T DR and a light-emitting transistor T EM These include, but embodiments of the present disclosure are not limited to them.

[0083] For example, a high-potential power voltage VDD can be applied to a first electrode of the drive transistor T. DR to be applied, a first electrode of the light emission transistor T EM can be connected to a second electrode of the control transistor T DR be connected and a sampling signal SC can be applied to a gate electrode of the drive transistor T DR The sampling signal SC, which is applied to the gate electrode of the drive transistor T, is then applied. DR A DC power source and a fixed reference voltage Vref can be applied to any frame, but embodiments of the present disclosure are not limited thereto.

[0084] The second electrode of the control transistor T DR can be connected to a first electrode of the light emission transistor T EM The light emission device ED can be connected to a second electrode of the light emission transistor T. EMbe connected and a light emission signal EM can be sent to a gate electrode of the light emission transistor T EM The light emission signal EM, which is applied to the gate electrode of the light emission transistor T, EM The applied signal can be a pulse width modulation signal that changes in each frame, but embodiments of the present disclosure are not limited to this.

[0085] A first electrode of the light emission device ED can be connected to the second electrode of the light emission transistor T. EM The first electrode of the light emission device ED may be connected to ground, and a second electrode of the light emission device ED may be connected to ground. The first electrode of the light emission device ED may, for example, be an anode electrode and the second electrode of the light emission device ED may be a cathode electrode, but embodiments of the present disclosure are not limited thereto.

[0086] Each of the control transistor TDR and the light emission transistor T EM It can be an n-type transistor or a p-type transistor.

[0087] The control transistor T DR can be switched on by the sampling signal SC, which is applied by a timing control unit T-CON in the microdriver (µDriver), and the light emission transistor T EM The light emission signal EM can be switched on. Consequently, a control current is supplied to the light emission device ED via the control transistor T. DR and the light emission transistor T EM by applying the high-potential power voltage VDD, which is connected to the first electrode of the drive transistor T DR is applied, and consequently the light emission device ED can emit light.

[0088] Fig. Figures 5 to 7 are top views of a display device according to an embodiment of the present disclosure. Fig. 5, for example, is an enlarged top view of a display area with several pixels. Fig. Image 6, for example, is an enlarged top view of a display area with one pixel. Fig. Figure 7, for example, is a magnified top view of a display area with several pixels. Although Fig. 5 and Fig. 7. Several signal lines TL, several communication lines NL, several first electrodes CE1, several banks BNK and several light emission devices ED are embodiments of the present disclosure, and these are not the only embodiments. Fig. Figure 7 is an enlarged top view showing the multiple second electrodes CE2 additionally in Fig. 5 are arranged, for convenience an area that overlaps with the second electrodes CE2 is indicated by a dashed line.

[0089] With reference to Fig. 5 to 7, several pixels PX with several subpixels can be arranged in the display area AA. Each of the several subpixels includes a light-emitting device ED and can emit light independently. The several subpixels can be configured in several rows and several columns and can be arranged in a matrix form, but embodiments of the present disclosure are not limited thereto.

[0090] The multiple subpixels can comprise a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3. For example, any one of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 can be a red subpixel, another can be a green subpixel, and another can be a blue subpixel. The types of multiple subpixels are examples, and embodiments of the present disclosure are not limited thereto.

[0091] Each of the multiple pixels PX can comprise one or more first subpixels SP1, one or more second subpixels SP2, and one or more third subpixels SP3. For example, a pixel PX can comprise a pair of first subpixels SP1, a pair of second subpixels SP2, and a pair of third subpixels SP3. The pair of first subpixels SP1 can comprise a 1-1 subpixel SP1a and a 1-2 subpixel SP1b. The pair of second subpixels SP2 can comprise a 2-1 subpixel SP2a and a 2-2 subpixel SP2b. The pair of third subpixels SP3 can comprise a 3-1 subpixel SP3a and a 3-2 subpixel SP3b. For example, a pixel PX may comprise the 1-1th subpixel SP1a, the 1-2th subpixel SP2a, the 2-1th subpixel SP2a, the 2-2th subpixel SP2b, the 3-1th subpixel SP3a and the 3-2th subpixel SP3b, but embodiments of the present disclosure are not limited thereto.

[0092] The multiple subpixels that form a pixel PX can be arranged in various ways. For example, in a pixel PX, the pair of first subpixels SP1 can be arranged in the same column, the pair of second subpixels SP2 can be arranged in the same column, and the pair of third subpixels SP3 can be arranged in the same column. The first subpixel SP1, the second subpixel SP2, and the third subpixel SP3 can be arranged in the same row. The number and arrangement of multiple subpixels that form a pixel PX are examples, and embodiments of the present disclosure are not limited thereto.

[0093] The multiple signal lines TL can be arranged in a region between the multiple subpixels. The multiple signal lines TL can extend in a column direction between the multiple subpixels. The multiple signal lines TL can be lines that carry the anode voltage from the pixel drive circuit PD (in Fig. 3) to the multiple subpixels. The multiple signal lines TL can be used, for example, with the multiple pixel control circuits PD (in Fig. 3 shown) and the first electrode CE1 of the several subpixels are electrically connected. The anode voltage, which comes from the pixel drive circuit PD (in Fig. The output (as shown in Figure 3) can be transmitted to the first electrode CE1 of the multiple subpixels via the multiple signal lines TL. The first electrode CE1 can, for example, be an electrode connected to the anode 134 of the light emission device ED (in Figure 3). Fig. 9) is electrically connected. Consequently, the anode voltage can be supplied from the signal line TL to the anode 134 of the light emission device ED (in Fig. 9) are transferred through the first electrode CE1.

[0094] Instead of forming several transistors and storage capacitors in each of the several subpixels, a structure of the display device 1000 can therefore be implemented using a pixel drive circuit PD (in Fig. 3 shown) can be simplified by combining the multiple pixel circuits into a single pixel control circuit PD (in Fig. 3) are integrated. Since a circuit arranged in each of the several subpixels is integrated into a pixel drive circuit PD (in Fig. 3 shown) is integrated, and control with high efficiency and low power is also possible.

[0095] The multiple signal lines TL can include a first signal line TL1, a second signal line TL2, a third signal line TL3, a fourth signal line TL4, a fifth signal line TL5, and a sixth signal line TL6. Each of the first signal line TL1 and the second signal line TL2 can be electrically connected to each of the pair of first subpixels SP1. The third signal line TL3 and the fourth signal line TL4 can be electrically connected to each of the pair of second subpixels SP2. Each of the fifth signal line TL5 and the sixth signal line TL6 can be electrically connected to each of the pair of third subpixels SP3.

[0096] The first signal line TL1 can be located on one side of the pair of first subpixels SP1, and the second signal line TL2 can be located on the other side of the pair of first subpixels SP1. The first signal line TL1 can be electrically connected to one of the pair of first subpixels SP1, for example, the first electrode CE1 of the 1-1th subpixel SP1a. The second signal line TL2 can be electrically connected to the remaining first subpixel SP1 of the pair of first subpixels SP1, for example, the first electrode CE1 of the 1-2nd subpixel SP1b.

[0097] The third signal line TL3 can be located on one side of the pair of second subpixels SP2, and the fourth signal line TL4 can be located on the other side of the pair of second subpixels SP2. The third signal line TL3 can, for example, be located adjacent to the second signal line TL2. The third signal line TL3 can be electrically connected to one of the pair of second subpixels SP2, for example, the first electrode CE1 of the 2-1 subpixel SP2a. The fourth signal line TL4 can be electrically connected to the remaining second subpixel SP2 of the pair of second subpixels SP2, for example, the first electrode CE1 of the 2-2 subpixel SP2b.

[0098] The fifth signal line TL5 can be located on one side of the pair of third subpixels SP3, and the sixth signal line TL6 can be located on the other side of the pair of third subpixels SP3. For example, the fifth signal line TL5 can be located adjacent to the fourth signal line TL4. The sixth signal line TL6 can be located adjacent to the first signal line TL1, which is connected to the adjacent pixel PX. The fifth signal line TL5 can be electrically connected to one of the pair of third subpixels SP3, for example, the first electrode CE1 of the 3-1 subpixel SP3a. The sixth signal line TL6 can be electrically connected to the remaining third subpixel SP3 of the pair of third subpixels SP3, for example, the first electrode CE1 of the 3-2 subpixel SP3b.

[0099] The multiple signal lines TL can be formed from a conductive material. For example, the multiple signal lines TL can be formed from conductive materials such as titanium (Ti), aluminum (Al), copper (Cu), molybdenum (Mo), nickel (Ni), chromium (Cr), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), etc., but embodiments of the present disclosure are not limited thereto. As another example, the multiple signal lines TL can be formed from a multilayer structure of a conductive material. For example, the multiple signal lines TL can be formed from a multilayer structure in which titanium (Ti), aluminum (Al), titanium (Ti), and indium tin oxide (ITO) are stacked, but embodiments of the present disclosure are not limited thereto.

[0100] The multiple communication lines NL can be arranged in a region between the multiple pixels PX. The multiple communication lines NL can be arranged to extend in a series direction in a region between the multiple pixels PX. The multiple communication lines NL can be arranged in a region between the multiple second electrodes CE2 and need not overlap with the multiple second electrodes CE2. The multiple communication lines NL can, for example, be wiring used for short-range communication such as near-field communication (NFC). The multiple communication lines NL can function as antennas. The multiple communication lines NL can, for example, be multiple interconnect lines, etc., but embodiments of the present disclosure are not limited thereto.

[0101] According to the present disclosure, banks BNK can be arranged in each of the multiple subpixels. The multiple banks BNK can be structures in which the multiple light-emitting devices ED are arranged. The multiple banks BNK can guide positions of the multiple light-emitting devices ED in a transfer process. The multiple light-emitting devices ED can be transferred to the multiple banks BNK in the transfer process. The multiple banks BNK can be bank patterns or a bank structure, but embodiments of the present disclosure are not limited thereto.

[0102] The BNK banks of the first subpixel SP1, the BNK banks of the second subpixel SP2, and the BNK banks of the third subpixel SP3 can be arranged to be spaced apart from each other. Alternatively, the BNK banks of the first subpixel SP1, the BNK banks of the second subpixel SP2, and the BNK banks of the third subpixel SP3 can be configured to be separate. Consequently, the BNK banks of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3, to which different types of light-emitting devices (EDs) are transferred, can be easily identified.

[0103] The bank of light emission spectral density (BNK) of the 1-1 subpixel SP1a and the bank of light emission spectral density (BNK) of the 1-2 subpixel SP1b can be connected or spaced apart. For example, the bank of light emission spectral density (BNK) of the 1-1 subpixel SP1a and the bank of light emission spectral density (BNK) of the 1-2 subpixel SP1b, in which the same light emission device (ED) is arranged, can be connected, separated, or spaced apart according to design requirements such as transfer process requirements. The bank of light emission spectral density (BNK) of the 2-1 subpixel SP2a and the bank of light emission spectral density (BNK) of the 2-2 subpixel SP2b can be connected or spaced apart. The bank of light emission spectral density (BNK) of the 3-1 subpixel SP3a and the bank of light emission spectral density (BNK) of the 3-2 subpixel SP3b can be connected or spaced apart.Consequently, the bank BNK of the pair of first subpixels SP1, the bank BNK of the pair of second subpixels SP2 and the bank BNK of the pair of third subpixels SP3 can be configured differently, and embodiments of the present disclosure are not limited thereto.

[0104] The multiple BNK banks can, for example, be formed from an organic insulating material. The multiple BNK banks can be formed from a single layer or a multilayer of an organic insulating material. The multiple BNK banks can, for example, be formed from a photoresist, a polyimide (PI), an acrylic-based material, or the like, but embodiments of the present disclosure are not limited thereto.

[0105] The first electrode CE1 can be located in any of the multiple subpixels. The first electrode CE1 can be located on bank BNK. The first electrode CE1 can be electrically connected to one of the multiple signal lines TL. At least one segment of the first electrode CE1 can extend to an outside of bank BNK, such that it is electrically connected to the signal line TL that is closest to the first electrode CE1. For example, a segment of the first electrode CE1 of the 1-1th subpixel SP1a can extend to one side region of the 1-1th subpixel SP1a, such that it is electrically connected to the first signal line TL1, and a segment of the first electrode CE1 of the 1-2nd subpixel SP1b can extend to the other side region of the 1-2nd subpixel SP1b, such that it is electrically connected to the second signal line TL2.A section of the first electrode CE1 of the 2-1 subpixel SP2a can extend to one side region of the 2-1 subpixel SP2a, such that it is electrically connected to the third signal line TL3, and a section of the first electrode CE1 of the 2-2 subpixel SP2b can extend to the other side region of the 2-2 subpixel SP2b, such that it is electrically connected to the fourth signal line TL4. A section of the first electrode CE1 of the 3-1 subpixel SP3a can extend to one side region of the 3-1 subpixel SP3a, such that it is electrically connected to the fifth signal line TL5, and a section of the first electrode CE1 of the 3-2 subpixel SP3b can extend to the other side region of the 3-2 subpixel SP3b, such that it is electrically connected to the sixth signal line TL6.

[0106] The first electrode CE1 is connected to the anode electrode 134 (in Fig. (shown in 14) the light emission device ED is electrically connected. The anode voltage from the pixel drive circuit PD (in Fig. (as shown in Figure 3) can be transmitted to the light emission device ED via the signal line TL and the first electrode CE1. Different voltages can be applied to the first electrode CE1 from each of the multiple subpixels according to an image that is displayed. For example, different voltages can be applied to the first electrode CE1 from each of the multiple subpixels. Consequently, the first electrode CE1 can be a pixel electrode, and embodiments of the present disclosure are not limited thereto.

[0107] The first electrode CE1 can be formed from a conductive material. For example, the first electrode CE1 can be formed integrally with the multiple signal lines TLs. The first electrode CE1 can, for example, be formed from the same conductive material as the multiple signal lines TLs, but embodiments of the present disclosure are not limited thereto. The first electrode CE1 can, for example, be formed from the conductive material such as titanium (Ti), aluminum (Al), copper (Cu), molybdenum (Mo), nickel (Ni), chromium (Cr), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), and the like, but embodiments of the present disclosure are not limited thereto. As another example, the first electrode CE1 can be formed from a multilayer structure of the conductive material.The multiple first electrodes CE1 can, for example, be formed from the multilayer structure in which titanium (Ti), aluminum (Al), titanium (Ti) and indium tin oxide (ITO) are stacked, but embodiments of the present disclosure are not limited thereto.

[0108] The light-emitting device ED can be arranged in any of several subpixels. The multiple light-emitting devices ED can be any light-emitting diode (LED) or micro-LED, but embodiments of the present disclosure are not limited thereto. The multiple light-emitting devices ED can be arranged on the bank BNK and the first electrode CE1. The multiple light-emitting devices ED can be arranged on the first electrode CE1 and can be electrically connected to the first electrode CE1. Consequently, the light-emitting device ED can emit light by receiving the anode voltage from the pixel drive circuit PD through the signal line TL and the first electrode CE1.

[0109] The multiple light-emitting devices ED can comprise a first light-emitting device 130, a second light-emitting device 140, and a third light-emitting device 150. The first light-emitting device 130 can be arranged in the first subpixel SP1. The second light-emitting device 140 can be arranged in the second subpixel SP2. The third light-emitting device 150 can be arranged in the third subpixel SP3. For example, one of the first light-emitting device 130, the second light-emitting device 140, and the third light-emitting device 150 can be a red light-emitting device, another can be a green light-emitting device, and another can be a blue light-emitting device, but embodiments of the present disclosure are not limited thereto.Consequently, light of various colors, including white, can be implemented by combining the red, green, and blue light emitted by the multiple light-emitting devices ED. The types of multiple light-emitting devices ED are examples and embodiments of the present disclosure and are not limited thereto.

[0110] The first light-emitting device 130 can comprise a 1-1th light-emitting device 130a located in the 1-1th subpixel SP1a, and a 1-2th light-emitting device 130b located in the 1-2th subpixel SP1b. The second light-emitting device 140 can comprise a 2-1th light-emitting device 140a located in the 2-1th subpixel SP2a, and a 2-2th light-emitting device 140b located in the 2-2th subpixel SP2b. The third light emission device 150 can comprise a 3-1-th light emission device 150a located in the 3-1-th subpixel SP3a and a 3-2-th light emission device 150b located in the 3-2-th subpixel SP3b.

[0111] The second electrode CE2 can be located in any of the multiple subpixels. The second electrode CE2 can be located on the light emission device ED. The second electrode CE2 can be connected to the pixel control circuit PD (in Fig. 3 shown) are electrically connected by several contact electrodes CCE.

[0112] The second electrode CE2 can, for example, be connected to the cathode electrode 135 (in Fig. (14 shown) the light emission device ED be electrically connected to supply the cathode voltage from the pixel drive circuit PD (in Fig. 3) to transmit to the light emission device ED. The same cathode voltage can be applied to the second electrode CE2 of each of the multiple subpixels. The same voltage can, for example, be applied to the second electrode CE2 of each of the multiple subpixels and the cathode electrode 135 (in Fig. (9 shown) the light emission device ED is applied. Consequently, the second electrode CE2 can be a common electrode, but embodiments of the present disclosure are not limited to this.

[0113] At least some of the multiple subpixels can share the second electrode CE2. Some of the second electrodes CE2 of each of the multiple subpixels can be formed as a single unit, so that they are electrically connected. If the same voltage is applied to the second electrode CE2, the second electrode CE2 can be shared and used by some of the subpixels. For example, the second electrodes CE2 of some of the pixels PX that are arranged in the same row in the horizontal direction can be formed as a single unit and connected to each other. A second electrode CE2 can be arranged, for example, in the multiple pixels PX. A second electrode CE2 can be arranged in each of n subpixels.

[0114] For example, some of the second electrodes CE2 of each of the multiple subpixels may be spaced apart or separated from one another. The second electrode CE2 connected to the pixels PX of the nth row and the second electrode CE2 connected to the pixels PX of the n+1th row may, for example, be spaced apart from one another. The multiple second electrodes CE2 may, for example, be spaced apart from one another, with the multiple communication lines NL, extending in a row direction, inserted between them. Consequently, the number of multiple subpixels may be greater than the number of multiple second electrodes CE2. As another example, all of the second electrodes CE2 of the multiple subpixels may be connected in one piece, so that only one second electrode CE2 needs to be arranged on the substrate 110, and embodiments of the present disclosure are not limited thereto.

[0115] The multiple second electrodes CE2 can be formed from a transparent conductive material, but embodiments of the present disclosure are not limited thereto. The multiple second electrodes CE2 can be formed from the transparent conductive material such that light emitted by the light-emitting device ED is directed to an upper section of the second electrode CE2. The second electrode CE2 can, for example, be formed from the transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), or the like, but embodiments of the present disclosure are not limited thereto.

[0116] Several contact electrodes CCE can be arranged on the substrate 110. These multiple contact electrodes CCE can be spaced apart from, for example, the multiple banks BNK and the multiple signal lines TL. Each of the multiple second electrodes CE2 can overlap with at least one contact electrode CCE. For example, a second electrode CE2 can overlap with the multiple contact electrodes CCE.

[0117] The multiple contact electrodes CCE can, for example, be electrically connected to the multiple second electrodes CE2. The multiple contact electrodes CCE can be arranged between the substrate 110 and the multiple second electrodes CE2 to supply the cathode voltage from the pixel drive circuit PD (in Fig. 3 shown) to transfer to the second electrode CE2.

[0118] For example, if a micro-LED is used as the light-emitting device (LED), multiple micro-LEDs can be formed on a wafer and transferred to substrate 110 to fabricate the display field 100. Various defects can occur during the transfer process of the multiple micro-sized LEDs from the wafer to substrate 110. A non-transfer defect, where the LED fails to transfer, can occur in some subpixels, and a defect, where the LED is transferred from a correct position due to an alignment error, can also occur in some subpixels. In these cases, the transfer process may proceed normally, but the transferred LED itself may also be defective.Consequently, the multiple identical light-emitting devices (LEDs) can be converted to a subpixel, taking into account the defect during the conversion process. After the illumination test of the multiple LEDs is performed, only one LED, which is ultimately determined to be normal, can be used.

[0119] The 1-1 light emission device 130a and the 1-2 light emission device 130b can, for example, be combined into a single pixel PX, and it is possible to investigate whether a defect exists in the 1-1 light emission device 130a and the 1-2 light emission device 130b. If both the 1-1 light emission device 130a and the 1-2 light emission device 130b are determined to be normal, only the 1-1 light emission device 130b can be used, and the 1-2 light emission device 130b cannot be used. As another example, if only the 1-2th light emission device 130b of the 1-1th light emission device 130a and the 1-2th light emission device 130b is determined to be normal, the 1-1th light emission device 130a cannot be used and only the 1-2th light emission device 130b can be used.Even if the multiple identical light emission devices ED are converted into one pixel PX, ultimately only one light emission device ED can be used.

[0120] Consequently, either of the pair of light-emitting devices ED can be a primary light-emitting device ED, and the other light-emitting device ED can be a redundant light-emitting device ED. The redundant light-emitting device ED can be an additional light-emitting device ED that is converted to prepare for a failure in the primary light-emitting device ED. If the primary light-emitting device ED fails, the redundant light-emitting device ED can be used instead of the primary light-emitting device ED. Consequently, the primary light-emitting device ED and the redundant light-emitting device ED are converted to a single pixel PX, thereby minimizing the degradation in display quality due to defects in the primary light-emitting device ED and the redundant light-emitting device ED.

[0121] The 1-1 light emission device 130a, the 2-1 light emission device 140a and the 3-1 light emission device 150a, which are converted to a pixel PX, can, for example, be used as the main light emission device ED, and the 1-2 light emission device 130b, the 2-2 light emission device 140b and the 3-2 light emission device 150b can be used as the redundant light emission device ED.

[0122] Fig. Figure 8 is a cross-sectional view of a display device according to an embodiment of the present disclosure. And Fig. Figure 9 is a cross-sectional view of a display device according to an embodiment of the present disclosure. Fig. Figure 8, for example, is a cross-sectional view of the display area AA, the first non-display area NA, the bending area BA, and the second non-display area NA2. Fig. Figure 9 is a cross-sectional view of a section of the display area AA.

[0123] With reference to Fig. 8 A first buffer layer 111a and a second buffer layer 111b can be arranged in the remaining area of ​​the substrate 110 apart from the bending area BA.

[0124] The first buffer layer 111a and the second buffer layer 111b can be arranged in the display region AA, in the first non-display region NA1, and in the second non-display region NA2. The first buffer layer 111a and the second buffer layer 111b can reduce the penetration of moisture or contaminants through the substrate 110. The first buffer layer 111a and the second buffer layer 111b can be formed from an inorganic insulating material. For example, the first buffer layer 111a and the second buffer layer 111b can be formed from a single layer or a multiple layer made of silicon dioxide (SiOx) or silicon nitride (SiNx), but embodiments of the present disclosure are not limited thereto.

[0125] Sections of the first buffer layer 111a and the second buffer layer 111b on the bending area BA may, for example, be removed. An upper surface of the substrate 110, located in the bending area BA, may be exposed through the first buffer layer 111a and the second buffer layer 111b. The first buffer layer 111a and the second buffer layer 111b, which are made of the inorganic insulating material, may be removed from the bending area BA, thereby minimizing cracks in the first buffer layer 111a and the second buffer layer 111b that may occur during bending.

[0126] Several alignment wedges MK can be arranged between the first buffer layer 111a and the second buffer layer 111b. These multiple alignment wedges MK can identify the position of the pixel driver circuit PD during the manufacturing process of the display panel 100. For example, the multiple alignment wedges MK can align the position of the pixel driver circuit PD as it is transferred to an adhesive layer 112. Alternatively, the multiple alignment wedges MK can be omitted.

[0127] An adhesive layer 112 can be arranged on the second buffer layer 111b. The adhesive layer 112 can be located in the display area AA, in the first non-display area NA1, in the flex area BA, and in the second non-display area NA2. Alternatively, a section of the adhesive layer 112 can be located away from the non-display area NA, including the flex area BA. The adhesive layer 112 can, for example, be formed from any adhesive polymer, an epoxy resin, a UV-curable resin, a polyimide-based resin, an acrylic-based material, a urethane-based material, or a polydimethylsiloxane (PDMS), but embodiments of the present disclosure are not limited thereto.

[0128] In the display area AA, the pixel control circuit PD can be arranged on the adhesive layer 112. If the pixel control circuit PD is implemented as a control driver, the control driver can be mounted on the adhesive layer 112 by a transfer process, but embodiments of the present disclosure are not limited to this.

[0129] A first protective layer 113a and a second protective layer 113b can be arranged on the adhesive layer 112 and the pixel control circuit PD. The first protective layer 113a and the second protective layer 113b can surround a side surface of the pixel control circuit PD, but embodiments of the present disclosure are not limited thereto. The second protective layer 113b can, for example, cover at least a portion of a top surface of the pixel control circuit PD. At least one of the first protective layer 113a and the second protective layer 113b arranged on the bending area BA can, for example, be omitted. The first protective layer 113a is, for example, arranged entirely in the display area AA and in the non-display area NA, and the second protective layer 113b is arranged partially in the display area AA, in the first non-display area NA1, and in the second non-display area NA2, and may not be arranged in the bending area BA.For example, a section of the second protective layer 113b in the bending area BA may be removed. However, embodiments of the present disclosure are not limited to this.

[0130] The first protective layer 113a and the second protective layer 113b can be formed from an organic insulating material, but embodiments of the present disclosure are not limited thereto. The first protective layer 113a and the second protective layer 113b can, for example, be formed from a photoresist, polyimide (PI), a photoacrylic-based material, or the like, but embodiments of the present disclosure are not limited thereto. The first protective layer 113a and the second protective layer 113b can, for example, be a coating layer or an insulating layer, but embodiments of the present disclosure are not limited thereto.

[0131] According to the present disclosure, several first connecting lines 121 can be arranged on the second protective layer 113b in the display area AA. The several first connecting lines 121 can be wiring for electrically connecting the pixel control circuit PD to other elements. The pixel control circuit PD can, for example, be electrically connected to the several signal lines TL, the several contact electrodes CCE, and the like by means of the several first connecting lines 121. The several first connecting lines 121 can, for example, comprise several 1-1th connecting lines 121a, several 1-2th connecting lines 121b, several 1-3th connecting lines 121c, and several 1-4th connecting lines 121d, but embodiments of the present disclosure are not limited thereto.

[0132] The multiple 1-1 interconnects 121a can, for example, be arranged on the second protective layer 113b. The multiple 1-1 interconnects 121a can be electrically connected to the pixel control circuit PD. The multiple 1-1 interconnects 121a can transmit voltages output from the pixel control circuit PD to the first electrode CE1 or to the second electrode CE2.

[0133] A third protective layer 114 can, for example, be arranged on top of the second protective layer 113b. The third protective layer 114 can be arranged over the entire display area AA and the non-display area NA. In the bending area BA, the third protective layer 114 can be arranged on or cover a side surface of the second protective layer 113b and a top surface of the first protective layer 113a. The third protective layer 114 can be formed from an organic insulating material. The third protective layer 114 can, for example, be formed from a photoresist, polyimide (PI), a photoacrylic-based material, or the like, but embodiments of the present disclosure are not limited thereto. The first protective layer 113a, the second protective layer 113b, and the third protective layer 114 can, for example, be formed from the same material, but embodiments of the present disclosure are not limited thereto.

[0134] The multiple 1-2 connecting lines 121b can be arranged on the third protective layer 114. The multiple 1-2 connecting lines 121b can be connected to the pixel control circuit PD via the 1-1 connecting lines 121a or can be directly connected to the pixel control circuit PD. For example, one section of the 1-2 connecting line 121b can be directly connected to the pixel control circuit PD through a contact hole in the third protective layer 114. The other section of the 1-2 connecting line 121b can be electrically connected to the 1-1 connecting line 121a through a contact hole in the third protective layer 114. However, embodiments of the present disclosure are not limited to this.The voltage output from the pixel control circuit PD can be transmitted, for example, to the first electrode CE1 or to the second electrode CE2 via connecting lines that are different from the several 1-2th connecting lines 121b.

[0135] A first insulating layer 115a can be arranged on the multiple 1-2 connecting lines 121b. The first insulating layer 115a can be arranged throughout the entire display area AA and the non-display area NA, but embodiments of the present disclosure are not limited thereto. The first insulating layer 115a can be formed from an organic insulating material, but embodiments of the present disclosure are not limited thereto. The first insulating layer 115a can, for example, be formed from a photoresist, polyimide (PI), a photoacrylic-based material, or the like, but embodiments of the present disclosure are not limited thereto.

[0136] The multiple 1-3 connecting lines 121c can be arranged on the first insulating layer 115a. The multiple 1-3 connecting lines 121c can be electrically connected to the multiple 1-2 connecting lines 121b. The 1-3 connecting lines 121c can, for example, be electrically connected to the 1-2 connecting lines 121b through a contact hole in the first insulating layer 115a.

[0137] A second insulating layer 115b can be arranged on the multiple 1-3 connecting lines 121c. The second insulating layer 115b can be arranged in the remaining area except for the bending region BA, but embodiments of the present disclosure are not limited to this. The second insulating layer 115b can be arranged in the display region AA, in the first non-display region NA1, and in the second non-display region NA2, but embodiments of the present disclosure are not limited to this. At least one section of the second insulating layer 115b that is arranged in the bending region BA can, for example, be removed. The second insulating layer 115b can be formed from an organic insulating material, but embodiments of the present disclosure are not limited to this.The second insulating layer 115b can, for example, be formed from a photoresist, polyimide (PI), a photoacrylic-based material or the like, but embodiments of the present disclosure are not limited thereto.

[0138] The multiple 1-4 connecting lines 121d can be arranged on the second insulating layer 115b. The multiple 1-4 connecting lines 121d can be electrically connected to the multiple 1-3 connecting lines 121c. The 1-4 connecting lines 121d can, for example, be electrically connected to the 1-3 connecting lines 121c through a contact hole in the second insulating layer 115b.

[0139] The 1-4th connecting line 121d can be connected to the contact electrode CCE through a contact hole in the third insulating layer 115c. Consequently, the contact electrode CCE and the pixel control circuit PD can be electrically connected to each other through the first connecting line 121.

[0140] Although not shown, the 1-4th connecting line 121d can be directly connected to the signal line TL through a contact hole located in the third insulating layer 115c, or it can be electrically connected to the signal line TL through other additional lines or electrodes. Consequently, the signal line TL and the pixel drive circuit PD can be electrically connected through the first connecting line 121.

[0141] According to the present disclosure, several second interconnection lines 122 can be arranged on the second protective layer 113b in the non-display area NA. The several second interconnection lines 122 can be wiring for transmitting a signal originating from the flexible printed circuit board (or flexible film) 170 (in Fig. 2 shown) and a printed circuit board 160 (in Fig. 2 shown) is received, for the pixel control circuit PD of the display area AA.

[0142] The multiple second connecting lines 122 can, for example, be electrically connected to the multiple contact point electrodes PE to transmit signals from flexible printed circuit boards (or flexible films) 170 (in Fig. 2 shown) and printed circuit board 160 (in Fig. 2 shown) to receive.

[0143] The several second connecting lines 122 can, for example, extend from the contact point part PAD (in Fig. (2 shown) extend towards the display area AA to transmit signals to the wiring of the display area AA. In this case, the multiple second connecting lines 122 can be used as linking lines LL (in Fig. (as shown in Figure 3) function. The multiple second connecting lines 122 can include a 2-1 connecting line 122a, a 2-2 connecting line 122b, a 2-3 connecting line 122c, and a 2-4 connecting line 122d.

[0144] The multiple 2-in-1 interconnects 122a can be arranged on the second protective layer 113b. The multiple 2-in-1 interconnects 122a can extend from the second non-indicating area NA2 to the bending area BA and to the first non-indicating area NA1. The multiple 2-in-1 interconnects 122a can carry signals originating from the flexible printed circuit board (or flexible film 170) (in Fig. 2 shown) and the printed circuit board 160 (in Fig. (shown in Figure 2) are received and transmitted to the pixel control circuit PD of the display area AA. Consequently, the multiple 2-1 connecting lines 122a can be electrically connected to the contact point electrode PE or the pixel control circuit PD.

[0145] Although not shown, the 2-1-th connecting line 122a, for example, can extend to the display area AA, so that it is directly connected to the pixel control circuit PD in the display area AA, or it can be electrically connected to the pixel control circuit PD via another additional line or electrodes. Furthermore, the 2-1-th connecting line 122a can be electrically connected to the contact electrode PE in the second non-display area NA2 via the 2-2-th connecting line 122b, the 2-3-th connecting line 122c, and the 2-4-th connecting line 122d. Consequently, the pixel control circuit PD and the contact electrode PE can be electrically connected to each other via the second connecting line 122.

[0146] The multiple 2-2 interconnects 122b can be arranged on the third protective layer 114. The multiple 2-2 interconnects 122b can be arranged in the second non-display area NA2. The 2-2 interconnects 122b can be electrically connected to the 2-1 interconnects 122a through a contact hole in the third protective layer 114. Therefore, signals from the flexible printed circuit board (or flexible film) 170 (in Fig. 2 shown) and the printed circuit board 160 (in Fig. 2 shown) to the 2-1 connecting lines 122a are transmitted via the 2-2 connecting lines 122b.

[0147] The 2-3 connection line 122c can be arranged on the first insulating layer 115a. The 2-3 connection line 122c can be arranged in the second non-display area NA2. The 2-3 connection line 122c can be electrically connected to the 2-2 connection line 122b through a contact hole in the first insulating layer 115a. Consequently, signals from the flexible printed circuit board (or flexible film) 170 (in Fig. 2 shown) and the printed circuit board 160 (in Fig. 2 shown) to the 2-1st connecting line 122a through the 2-3rd connecting line 122c and the 2-2nd connecting line 122b.

[0148] The 2-4th connecting wire 122d can be arranged on the second insulating layer 115b. The 2-4th connecting wire 122d can be arranged in the second non-indicating area NA2. The 2-4th connecting wire 122d can be electrically connected to the 2-3rd connecting wire 122c through a contact hole in the second insulating layer 115b. The 2-4th connecting wire 122d can be electrically connected to the contact point electrode PE through a contact hole in the third insulating layer 115c.

[0149] Consequently, signals from the flexible printed circuit board (or flexible film) can be transmitted 170 (in Fig. 2 shown) and the printed circuit board 160 (in Fig. 2 shown) to the 2-1st connecting line 122a through the 2-4th connecting line 122d, the 2-3rd connecting line 122c and the 2-2 connecting line 122b.

[0150] The multiple first connecting lines 121 and the multiple second connecting lines 122 can be formed from a conductive material with excellent ductility or from various conductive materials used in the display area AA. The second connecting line 122, which is partially located in the bending area BA, can, for example, be formed from a conductive material with excellent ductility, such as gold (Au), silver (Ag), or aluminum (Al), but embodiments of the present disclosure are not limited thereto. As another example, the multiple first connecting lines 121 and multiple second connecting lines 122 can be formed from molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), an alloy of silver (Ag) and magnesium (Mg), or an alloy thereof, but embodiments of the present disclosure are not limited thereto.

[0151] A third insulating layer 115c can be arranged on the multiple first connecting lines 121 and the multiple second connecting lines 122. The third insulating layer 115c can be arranged in the remaining area except for the bending region BA, but embodiments of the present disclosure are not limited to this. The third insulating layer 115c can be arranged in the display region AA, in the first non-display region NA1, and in the second non-display region NA2. At least a portion of the third insulating layer 115c in the bending region BA can be omitted. The third insulating layer 115c can be formed from an organic insulating material, but embodiments of the present disclosure are not limited to this.The third insulating layer 115c can, for example, be formed from a photoresist, polyimide (PI), a photoacrylic-based material or the like, but embodiments of the present disclosure are not limited thereto.

[0152] Multiple banks of BNK can be arranged on the third insulation layer 115c in the display area AA. The multiple banks of BNK can overlap with any of the multiple subpixels. The multiple banks of BNK cannot be arranged in the first non-display area NA1, in the second non-display area NA2, or in the bending area BA. One or more light-emitting devices ED of the same type can be arranged on an upper section of each of the multiple banks of BNK.

[0153] In the display area AA, several signal lines TLs can be arranged on the third insulation layer 115c. These multiple signal lines TLs can be located between the multiple banks BNK. For example, the multiple signal lines TLs can be located adjacent to any of the multiple banks BNK. Each of the multiple signal lines TLs can be electrically connected to the first connecting line 121, for example, the 1st-4th connecting line 121d.

[0154] Several contact electrodes CCE can be arranged on the third insulating layer 115c in the display area AA. These multiple contact electrodes CCE can supply the cathode voltage from the pixel control circuit PD to the second electrode CE2. Each of the multiple contact electrodes CCE can be electrically connected to the first connecting line 121, for example, the 1st-4th connecting line 121d.

[0155] A first electrode CE1 can be arranged on the bank BNK. For example, the first electrode CE1 can extend from the adjacent signal line TL to an upper section of the bank BNK. The first electrode CE1 can be arranged on an upper surface of the bank BNK and a side surface of the bank BNK. For example, the first electrode CE1 can extend from the signal line TL on an upper surface of the third insulating layer 115c to the side surface of the bank BNK and to the upper surface of the bank BNK. The first electrode CE1 can be formed integrally with the signal line TL.

[0156] With reference to Fig. 9. The first electrode CE1 may comprise several conductive layers. For example, the first electrode CE1 may comprise a first conductive layer CE1a, a second conductive layer CE1b, a third conductive layer CE1c, and a fourth conductive layer CE1d, but embodiments of the present disclosure are not limited thereto.

[0157] The first conductive layer CE1a can be arranged on the bank BNK. The second conductive layer CE1b can be arranged on the first conductive layer CE1a. The third conductive layer CE1c can be arranged on the second conductive layer CE1b, and the fourth conductive layer CE1d can be arranged on the third conductive layer CE1c. The first conductive layer CE1a, the second conductive layer CE1b, the third conductive layer CE1c, and the fourth conductive layer CE1d can, for example, be formed from titanium (Ti), molybdenum (Mo), aluminum (Al), or titanium (Ti) and indium tin oxide (ITO), but embodiments of the present disclosure are not limited thereto.

[0158] According to the present disclosure, some of the multiple conductive layers contained in the first electrode CE1, which has high reflection efficiency, can be made from an alignment wedge and / or a reflector for aligning the light emission device ED. The second conductive layer CE1b among the multiple conductive layers of the first electrode CE1 can, for example, comprise a reflective material. The second conductive layer CE1b can, for example, comprise aluminum (Al), but embodiments of the present disclosure are not limited thereto. Consequently, the second conductive layer CE1b can be used as a reflection plate. Due to the high reflection efficiency of the second conductive layer CE1b, identification in a manufacturing process, and consequently of an arrangement position or a transfer position of the light emission device ED with respect to the second conductive layer CE1b, can also be easily carried out.

[0159] To use the second conductive layer CE1b as a reflective plate, the third conductive layer CE1c and the fourth conductive layer CE1d, which cover the second conductive layer CE1b, can be partially removed or etched. For example, sections of the third and fourth conductive layers CE1c and CE1d, which are arranged on the BNK bed, can be removed or etched to expose a top surface of the second conductive layer CE1b. A central section and an edge section of the third and fourth conductive layers CE1c and CE1d, on which a solder pattern SDP is arranged, can, for example, remain, and the remaining sections, apart from the central section, of the third and fourth conductive layers CE1c and CE1d can be removed.For example, the central and edge sections of each of the third conductive layer CE1c, which is made of titanium (Ti), and the fourth conductive layer CE1d, which is made of indium tin oxide (ITO), cannot be etched. Consequently, corrosion of another conductive layer of the first electrode CE1 by a TMAH (tetramethylammonium hydroxide) solution used in a masking process of the first electrode CE1 can be prevented.

[0160] According to the present disclosure, the first conductive layer CE1a and the third conductive layer CE1c may comprise titanium (Ti) or molybdenum (Mo). The second conductive layer CE1b may comprise aluminum (Al). The fourth conductive layer CE1d may comprise a transparent conductive oxide layer such as indium tin oxide (ITO) or indium zinc oxide (IZO), which exhibits high adhesion to the solder pattern SDP and provides corrosion and acid resistance. However, embodiments of the present disclosure are not limited thereto.

[0161] The first conductive layer CEla, the second conductive layer CE1b, the third conductive layer CE1c and the fourth conductive layer CE1d can be deposited sequentially and then structured by a photolithography process and an etching process, but embodiments of the present disclosure are not limited thereto.

[0162] As in Fig. 8 and Fig. As shown in Figure 9, according to the present disclosure, the signal line TL, the contact electrode CCE, and the contact point electrode PE, which are arranged on the same layer as the first electrode CE1, can be formed from several layers of conductive materials, but embodiments of the present disclosure are not limited thereto. For example, the signal line TL, the contact electrode CCE, and the contact point electrode PE can be formed from several layers in which indium tin oxide (ITO), titanium (Ti), aluminum (Al), and titanium (Ti) are stacked, but embodiments of the present disclosure are not limited thereto.

[0163] According to the present disclosure, a solder pattern SDP can be arranged on the first electrode CE1 in each of the multiple subpixels. The solder pattern SDP can bond the light emission device ED to the first electrode CE1. The first electrode CE1 and the light emission device ED can be electrically connected to each other by eutectic bonding using the solder pattern SDP, but embodiments of the present disclosure are not limited to this. For example, if the solder pattern SDP is formed from indium (In) and the anode electrode 134 of the light emission device ED is formed from gold (Au), the solder pattern SDP and the anode electrode 134 can be bonded to each other by applying heat and pressure during the transfer process of the light emission device ED. The light emission device ED can be bonded to the solder pattern SDP and the first electrode CE1 by eutectic bonding without a separate adhesive element.The solder pattern SDP can, for example, be formed from indium (In), tin (Sn), or alloys thereof, but embodiments of the present disclosure are not limited thereto. The solder pattern SDP can, for example, be a bond contact point, a contact block, or the like, but embodiments of the present disclosure are not limited thereto.

[0164] According to the present disclosure, a passivation layer 116 can be arranged on the multiple signal lines TL, the multiple first electrodes CE1, the multiple contact electrodes CCE, and the third insulating layer 115c. The passivation layer 116 can, for example, be arranged in the display area AA, in the first non-display area NA1, and in the second non-display area NA2. A section of the passivation layer 116 located in the bending area BA can be omitted. A section of the passivation layer 116 covering the multiple contact electrodes PE can be omitted in the second non-display area NA2. A section of the passivation layer 116 covering the multiple contact electrodes CCE can be omitted in the display area AA. The passivation layer 116 covering the solder pattern SDP can be omitted in the display area AA.

[0165] Since the passivation layer 116 covers the remaining areas while exposing a portion of the multiple contact electrodes PE, a portion of the multiple contact electrodes CCE, and a portion of the solder pattern SDP, the ingress of moisture or contaminants flowing into the light-emitting device ED can be reduced. The passivation layer 116 can, for example, be formed from a single layer or multiple layers, including silicon oxide (SiOx) or silicon nitride (SiNx), but embodiments of the present disclosure are not limited thereto. The passivation layer 116 can, for example, be a protective layer or an insulating layer, but embodiments of the present disclosure are not limited thereto. The passivation layer 116 can, for example, include a hole exposing the solder pattern SDP and a hole exposing the contact electrode CCE.

[0166] In each of the multiple subpixels, the light emission device ED can be arranged on the solder pattern SDP. The first light emission device 130 can be arranged in the first subpixel SP1. The second light emission device 140 can be arranged in the second subpixel SP2. The third light emission device 150 can be arranged in the third subpixel SP3.

[0167] The light emission device ED can be formed on silicon wafers by metal-organic vapor deposition (MOCVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), molecular beam growth (MBE), hybrid vapor deposition (HVPE) or sputtering, but embodiments of the present disclosure are not limited thereto.

[0168] With reference to Fig. 9 The first light-emitting device 130 may comprise an anode 134, a first semiconductor layer 131, an active layer 132, a second semiconductor layer 133, a cathode 135, and an encapsulation layer 136, but embodiments of the present disclosure are not limited thereto. The encapsulation layer 136, for example, may not be included in the first light-emitting device 130.

[0169] The first semiconductor layer 131 can be arranged on the solder pattern SDP. The second semiconductor layer 133 can be arranged on the first semiconductor layer 131.

[0170] One of the first semiconductor layer 131 and one of the second semiconductor layer 133 can, for example, comprise a composite semiconductor such as a Group III-V or a Group II-VI and can be doped with impurities (or dopant materials). One of the first semiconductor layer 131 and one of the second semiconductor layer 133 can, for example, be a semiconductor layer doped with n-type impurities, and the other can be a semiconductor layer doped with p-type impurities, but embodiments of the present disclosure are not limited thereto. At least one of the first semiconductor layer 131 and one of the second semiconductor layer 133 can be a layer in which an n-type or p-type impurity is incorporated into a material such as, for example,The impurity may be gallium nitride (GaN), gallium phosphide (GaP), gallium arsenic phosphide (GaAsP), aluminum gallium indium phosphide (AlGaInP), indium aluminum phosphide (InAlP), aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlInGaN), aluminum gallium arsenic (AlGaAs), or a material such as gallium arsenic (GaAs), but embodiments of the present disclosure are not limited thereto. The n-type impurity may be, for example, silicon (Si), germanium (Ge), selenium (Se), carbon (C), tellurium (Te), tin (Sn), or the like, but embodiments of the present disclosure are not limited thereto. The p-type defect can be, for example, magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), beryllium (Be) or the like, but embodiments of the present disclosure are not limited thereto.

[0171] Each of the first semiconductor layer 131 and the second semiconductor layer 133 can, for example, be a nitride semiconductor with the defect of n-type and a nitride semiconductor with the defect of p-type, respectively, but embodiments of the present disclosure are not limited thereto. The first semiconductor layer 131 can, for example, be a nitride semiconductor with the defect of p-type and the second semiconductor layer 133 can be a nitride semiconductor with the defect of n-type, but embodiments of the present disclosure are not limited thereto.

[0172] The active layer 132 can be arranged between the first semiconductor layer 131 and the second semiconductor layer 133. The active layer 132 can emit light by receiving holes and electrons from the first semiconductor layer 131 and the second semiconductor layer 133. The active layer 132 can, for example, be formed from a single-potential well structure, a multi-potential well structure, a single-quantum potential well structure, a multi-quantum potential well (MQW) structure, a quantum dot structure, or a quantum line structure, but embodiments of the present disclosure are not limited thereto. The active layer 132 can, for example, be formed from indium gallium nitride (InGaN) or gallium nitride (GaN), but embodiments of the present disclosure are not limited thereto.

[0173] As another example, the active layer 132 can comprise a multi-quantum potential well (MQW) structure with a potential well layer and a barrier layer having a band gap higher than that of the potential well layer. The active layer 132 can, for example, comprise InGaN as the potential well layer and an AlGaN layer as the barrier layer, but embodiments of the present disclosure are not limited thereto.

[0174] The anode 134 can be arranged between the first semiconductor layer 131 and the solder pattern SDP. The anode 134 can, for example, electrically connect the first semiconductor layer 131 to the first electrode CE1. The anode voltage output from the pixel drive circuit PD can be applied to the first semiconductor layer 131 via the signal line TL, the first electrode CE1, and the anode 134. The anode 134 can, for example, be made of a conductive material capable of eutectic bonding with the solder pattern SDP, but embodiments of the present disclosure are not limited thereto. The anode 134 can, for example, be made of gold (Au), tin (Sn), tungsten (W), silicon (Si), silver (Ag), titanium (Ti), iridium (Ir), chromium (Cr), indium (In), zinc (Zn), lead (Pb), nickel (Ni), platinum (Pt), copper (Cu) or alloys thereof, but embodiments of the present disclosure are not limited thereto.

[0175] The cathode 135 can be arranged on the second semiconductor layer 133. The cathode 135 can, for example, electrically connect the second semiconductor layer 133 to the second electrode CE2. The cathode voltage output from the pixel drive circuit PD can be applied to the second semiconductor layer 133 through the contact electrode CCE, the second electrode CE2, and the cathode 135. The cathode 135 can be made of a transparent conductive material to allow light emitted from the light emission device ED to be directed to an upper section of the light emission device ED, but embodiments of the present disclosure are not limited to this. The cathode 135 can, for example, be made of a material such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), or the like, but embodiments of the present disclosure are not limited to this.

[0176] The encapsulation layer 136 can be arranged on at least a section of each of the first semiconductor layer 131, the active layer 132, the second semiconductor layer 133, the anode 134, and the cathode 135. For example, the encapsulation layer 136 can surround at least a section of each of the first semiconductor layer 131, the active layer 132, the second semiconductor layer 133, the anode 134, and the cathode 135.

[0177] The encapsulation layer 136 can, for example, protect the first semiconductor layer 131, the active layer 132, and the second semiconductor layer 133. The encapsulation layer 136 can, for example, be arranged on a side surface of the first semiconductor layer 131, a side surface of the active layer 132, and a side surface of the second semiconductor layer 133.

[0178] The encapsulation layer 136 can, for example, be arranged on at least one section of the anode 134 and the cathode 135, for instance, on the edge section (or a side) of the anode 134 and the edge section (or a side) of the cathode 135. At least one section of the anode 134 can be exposed by the encapsulation layer 136, and the anode 134 can connect to the solder pattern SDP. At least one section of the cathode 135 can, for example, be exposed by the encapsulation layer 136, and the cathode 135 can connect to the second electrode CE2. The encapsulation layer 136 can, for example, be formed from an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx), but embodiments of the present disclosure are not limited thereto.

[0179] As another example, the encapsulation layer 136 can have a structure in which a reflective material is distributed within a resin layer, but embodiments of the present disclosure are not limited to this. The encapsulation layer 136 can, for example, be manufactured as a reflector with various structures, but embodiments of the present disclosure are not limited to this. Light emitted by the active layer 132 can be reflected upwards by the encapsulation layer 136, thus improving the light extraction efficiency. The encapsulation layer 136 can, for example, be a reflective layer, but embodiments of the present disclosure are not limited to this.

[0180] According to the present disclosure, the light emission device ED has been described as a vertical structure, but embodiments of the present disclosure are not limited thereto. The light emission device ED may, for example, have a lateral structure or a flip-chip structure.

[0181] Although the first light-emitting device 130 with reference to Fig. As described in Figure 9, the second light-emitting device 140 and the third light-emitting device 150 can have essentially the same structure as the first light-emitting device 130. For example, the second light-emitting device 140 and the third light-emitting device 150 can have essentially the same configuration as the first semiconductor layer 131, the active layer 132, the second semiconductor layer 133, the anode 134, the cathode 135, and the encapsulation layer 136.

[0182] How Fig. 8 and Fig. As shown in Figure 9, a first optical layer 117a, surrounding the multiple light-emitting devices ED, can be arranged in the display area AA. The first optical layer 117a can, for example, cover the side surfaces of the multiple light-emitting devices ED and the side surfaces of the multiple banks BNK in the multiple subpixels. The first optical layer 117a can, for example, cover a portion of the passivation layer 116. The first optical layer 117a can, for example, cover the second electrode CE2, a portion of the passivation layer 116, and an area between the multiple light-emitting devices ED. The first optical layer 117a can be arranged or covered between the multiple light-emitting devices ED and between the multiple banks BNK contained in a pixel PX.The first optical layer 117a can, for example, extend in the first direction X, and the multiple first optical layers 117a can be spaced apart from one another in the second direction Y in a top view. The first optical layer 117a can, for example, be arranged between the passivation layer 116 and the second electrode CE2 to surround the side surface of the light emission device ED and the side surface of the bank BNK, but embodiments of the present disclosure are not limited thereto. The first optical layer 117a can, for example, be a scattering layer, a sidewall scattering layer, or the like, but embodiments of the present disclosure are not limited thereto.

[0183] The first optical layer 117a can comprise an organic insulating material in which fine particles are dispersed, but embodiments of the present disclosure are not limited thereto. For example, the first optical layer 117a can be formed of siloxane in which fine metal particles, such as titanium dioxide (TiO2) particles, are dispersed, but embodiments of the present disclosure are not limited thereto. Light from the multiple light-emitting devices ED can be scattered by fine particles dispersed in the first optical layer 117a and emitted to an outside of the display field 100. Consequently, the first optical layer 117a can improve the extraction efficiency of light emitted by the multiple light-emitting devices ED.

[0184] The first optical layer 117a can, for example, be arranged in each of the multiple pixels PX, or it can be arranged in some pixels PX that are arranged in the same row, but embodiments of the present disclosure are not limited thereto. The first optical layer 117a can, for example, be arranged in each of the multiple pixels PX, or the multiple pixels PX can share a first optical layer 117a. As another example, each of the multiple subpixels can separately comprise a first optical layer 117a, but embodiments of the present disclosure are not limited thereto.

[0185] According to the present disclosure, the second optical layer 117b can be arranged on the passivation layer 116 in the display area AA. The second optical layer 117b can, for example, surround the first optical layer 117a. The second optical layer 117b can, for example, be in contact with a side surface of the first optical layer 117a. The second optical layer 117b can, for example, be arranged in a region between the multiple pixels PX. However, embodiments of the present disclosure are not limited thereto. The second optical layer 117b can, for example, be a diffusing layer, a window diffusing layer, or the like, but embodiments of the present disclosure are not limited thereto.

[0186] The second optical layer 117b can be formed from an organic insulating material, but embodiments of the present disclosure are not limited to this. The second optical layer 117b can be formed from the same material as the first optical layer 117a, but embodiments of the present disclosure are not limited to this. For example, the first optical layer 117a can comprise fine particles and the second optical layer 117b can not comprise fine particles. The second optical layer 117b can, for example, be formed from siloxane, but embodiments of the present disclosure are not limited to this.

[0187] The thickness of the first optical layer 117a may, for example, be less than the thickness of the second optical layer 117b, but embodiments of the present disclosure are not limited thereto. Consequently, in a top view, a region in which the first optical layer 117a is arranged may include a concave section recessed by an upper surface of the second optical layer 117b.

[0188] According to the present disclosure, the second electrode CE2 can be arranged on the first optical layer 117a and the second optical layer 117b. The second electrode CE2 can, for example, be electrically connected to the multiple contact electrodes CCE through a contact hole in the second optical layer 117b. The second electrode CE2 can, for example, be arranged on the multiple light-emitting devices ED. The second electrode CE2 can, for example, comprise a transparent conductive oxide such as indium tin oxide (ITO) or indium zinc oxide (IZO), but embodiments of the present disclosure are not limited thereto. The second electrode CE2 can, for example, be in contact with the cathode 135. The second electrode CE2 can, for example, overlap the entire first optical layer 117a and can overlap a portion of the second optical layer 117b.

[0189] The second electrode CE2 can extend continuously in the first direction of substrate 110. Consequently, the second electrode CE2 can be connected together with the multiple pixels PX that are arranged in the first direction of substrate 110. For example, the second electrode CE2 can be connected together with the multiple pixels PX.

[0190] According to the present disclosure, the second electrode CE2 can extend continuously across the first optical layer 117a, the second optical layer 117b, and the light-emitting device ED. The area in which the first optical layer 117a is arranged can include the concave section recessed from the upper surface of the second optical layer 117b. Since a first section of the second electrode CE2, which is arranged on the first optical layer 117a, is positioned along the concave section, the first section can consequently be positioned lower than a second section of the second electrode CE2, which is arranged on the second optical layer 117b.

[0191] The third optical layer 117c can be arranged on the second electrode CE2. The third optical layer 117c can overlap with the multiple light-emitting devices ED and the first optical layer 117a. The third optical layer 117c, for example, cannot overlap with the second optical layer 117b. Because the third optical layer 117c is arranged on the second electrode CE2 and the multiple light-emitting devices ED, a spot (von Mura) that may occur in some of the multiple light-emitting devices ED can be improved. For example, when the multiple light-emitting devices ED are transferred to the substrate 110 of the display field 100, a region may be formed where a gap between the multiple light-emitting devices ED is not uniform due to a process deviation, or the like.If the gap between the multiple light-emitting devices ED is not uniform, the light emission area from each of the multiple light-emitting devices ED may be unevenly distributed, and consequently, a spot (or mura) may be perceived by a user. Since the third optical layer 117c is designed to uniformly scatter light at an upper section of the multiple light-emitting devices ED, it is therefore possible to reduce the visibility of light emitted by some of the light-emitting devices ED as spots (or mura). Because the light emitted by the multiple light-emitting devices ED is uniformly scattered by the third optical layer 117c and extracted to the outside of the display field 100, the luminance uniformity of the display device can be improved.

[0192] The third optical layer 117c can be formed from an inorganic insulating material in which fine particles are dispersed, but embodiments of the present disclosure are not limited to this. The third optical layer 117c can, for example, be formed from siloxane in which fine metal particles, such as titanium dioxide (TiO2) particles, are dispersed, but embodiments of the present disclosure are not limited to this. The third optical layer 117c can, for example, be formed from the same material as the first optical layer 117a, but embodiments of the present disclosure are not limited to this. The third optical layer 117c can, for example, be a scattering layer, an upper scattering layer, or the like, but embodiments of the present disclosure are not limited to this.

[0193] According to the present disclosure, light from the multiple light-emitting devices ED can be scattered by fine particles distributed in the third optical layer 117c and emitted to the outside of the display field 100. The third optical layer 117c can uniformly mix the light emitted by the multiple light-emitting devices ED to further improve the luminance uniformity of the display device. Furthermore, the light extraction efficiency of the display device can be improved by the light scattered by the multiple fine particles, and consequently, the display device can be driven with lower power.

[0194] In the display area AA, a black matrix BM can be arranged on the second electrode CE2, the first optical layer 117a, the second optical layer 117b, and the third optical layer 117c. The black matrix BM can, for example, fill a contact hole in the second optical layer 117b. Because the black matrix BM can cover the display area AA, color mixing of light from the multiple subpixels and reflection of external light can be reduced. Since the black matrix BM is located within a contact hole where the second electrode CE2 and the contact electrode CCE are connected, light leakage between the multiple adjacent subpixels can be prevented.

[0195] The black matrix BM can, for example, be made of an opaque material, but embodiments of the present disclosure are not limited thereto. The black matrix BM can, for example, be an organic insulating material to which a black pigment or a black dye is added, but embodiments of the present disclosure are not limited thereto.

[0196] With reference to Fig. 8. A cover layer 118 can be arranged on the black matrix BM in the display area AA. The cover layer 118 can protect an element beneath it; for example, the cover layer 118 can be made of an organic insulating material, but embodiments of the present disclosure are not limited to this. The cover layer 118 can, for example, be made of a photoresist, polyimide (PI), a photoacrylic-based material, or the like, but embodiments of the present disclosure are not limited to this. The cover layer 118 can, for example, be a coating layer, an insulating layer, or the like, but embodiments of the present disclosure are not limited to this.

[0197] A polarizing layer 280 can be arranged on the cover layer 118 over a first adhesive layer 291. A cover element 120 can be arranged on the polarizing layer 280 over a second adhesive layer 295. The first adhesive layer 291 and the second adhesive layer 295 can, for example, comprise an optically clear adhesive (OCA), an optically clear resin (OCR), a pressure-sensitive adhesive (PSA), or the like, but embodiments of the present disclosure are not limited thereto.

[0198] According to the present disclosure, the multiple contact electrodes PE can be arranged on the third insulating layer 115c in the second non-indicating region NA2. A section of the multiple contact electrodes PE can, for example, be exposed by the passivation layer 116. The multiple contact electrodes PE can, for example, be electrically connected to the 2-4th connecting line 122d through a contact hole in the third insulating layer 115c.

[0199] An adhesive film ACF can be arranged on the multiple contact electrodes PE. The adhesive film ACF can be an adhesive layer in which conductive spheres are distributed within an insulating material, but embodiments of the present disclosure are not limited to this. When heat or pressure is applied to the adhesive film ACF, the conductive sphere can exhibit conductive properties in a region where heat or pressure is applied. An adhesive film ACF can be arranged between the multiple contact electrodes PE and the flexible printed circuit board (or flexible film) 170, so that a flexible printed circuit board (or flexible film) 170 can be attached to or bonded to the multiple contact electrodes PE. The adhesive film ACF can, for example, be an anisotropic conductive film (ACF), but embodiments of the present disclosure are not limited to this.

[0200] The flexible printed circuit board (or flexible film) 170 can be arranged on the adhesive film ACF. The flexible printed circuit board (or flexible film) 170 can be electrically connected to the multiple contact electrodes PE through the adhesive film ACF. Therefore, signals output from the flexible printed circuit board (or flexible film) 170 and the printed circuit board 160 can be transmitted to the pixel control circuit PD of the display area AA through the multiple contact electrodes PE, the 2-4th connection line 122d, the 2-3rd connection line 122c, the 2-1st connection line 122b, and the 2-1st connection line 122a.

[0201] Fig. Figure 10A is a top view showing a transition area of ​​a display device according to an embodiment of the present disclosure. Fig. 10B is a top view showing a transition area of ​​a display device according to another embodiment of the present disclosure.

[0202] With reference to Fig. 10A and Fig. 10B, several light emission devices can be transferred to a display area AA of a display device by several transfer processes.

[0203] As in Fig. As shown in Figure 10A, for example, the multiple light-emitting devices can be transferred to the display area AA by performing a transfer process six times on the first to sixth transfer regions using a transfer stamp capable of transferring the multiple light-emitting devices. In this case, the first to sixth transfer regions can be subdivided by a first boundary line D1 in a vertical direction and a second boundary line D2 and a third boundary line D3 in a horizontal direction, and the multiple subpixels can be arranged in each of the first to sixth transfer regions.

[0204] As in Fig. As shown in Figure 10, alternatively, the multiple light-emitting devices can be transferred to the display area AA by performing a transfer process nine times on the first to ninth transfer regions using a transfer stamp capable of transferring the multiple light-emitting devices. In this case, the first to ninth transfer regions can be subdivided by a first boundary line D1 and a second boundary line D2 in the vertical direction, a third boundary line D3 and a fourth boundary line D4 in the horizontal direction, and the multiple subpixels can be arranged in each of the first to sixth transfer regions.

[0205] When carrying out the transfer process according to Fig. 10A and Fig. 10B A transfer error or transfer deviation may occur between each transfer process using a transfer stamp.

[0206] For example, no transfer error occurred during the transfer process to the first transfer region, but the transfer error can occur during the transfer process to the second transfer region. Alternatively, although no transfer error occurred in either the transfer process to the first transfer region or the transfer process to the second transfer region, a discrepancy can occur between the light emission characteristics of the multiple light emission devices transferred to the multiple subpixels in the first transfer region and the light emission characteristics of the multiple light emission devices transferred to the multiple subpixels in the second transfer region.

[0207] If there is a difference in the presence or absence of the transition error, or a difference in the characteristics of the light emission devices, between the multiple transition regions, a difference in light emission intensity can occur between these regions. In this case, a spot may appear near the boundary lines D1, D2, D3, and D4 between the multiple transition regions, thus degrading the display quality.

[0208] Below is a description of a display device that is able to reduce the problem of spots occurring near the boundary line between the multiple transfer regions.

[0209] Fig. 11A and Fig. Figures 11B are a cross-sectional view and a top view of a subpixel according to an embodiment of the present disclosure. Fig. 12A and Fig. Figures 12B are a cross-sectional view and a top view of a subpixel according to another embodiment of the present disclosure. Fig. 13A and Fig. Figures 13B are a cross-sectional view and a top view of a subpixel according to another embodiment of the present disclosure. Fig. 14A and Fig. Figures 14B are a cross-sectional view and a top view of a subpixel according to another embodiment of the present disclosure.

[0210] Fig. 11A, Fig. 12A, Fig. 13A and Fig. 14A each only represents bank BNK and the first electrode CE1 in Fig. 9, which is described above. And Fig. 11B is a view that represents a state in which a signal line TL is connected according to an example with the first electrode CE1 according to Fig. It is connected to 11A. And Fig. 12B is a view that represents a state in which a signal line TL is connected according to an example with the first electrode CE1 according to Fig. It is connected to 12A. And Fig. 13B is a view that represents a state in which a signal line TL is connected according to an example with the first electrode CE1 according to Fig. It is connected to 13A. And Fig. 14B is a view that represents a state in which a signal line TL is connected according to an example with the first electrode CE1 according to Fig. It is connected to 14A.

[0211] As can be seen from each drawing, each subpixel comprises a bank BNK and a first electrode CE1 arranged on the bank BNK. The first electrode CE1 can include a first conductive layer CEla, a second conductive layer CE1b, a third conductive layer CE1c, and a fourth conductive layer CE1d.

[0212] In this case, the first electrode CE1, which is arranged in each subpixel, can include a central area CA, reflection areas RA1, RA2, RA3 and RA4 and edge areas EA1, EA2, EA3 and EA4.

[0213] The central area CA is an area in which the soldering pattern SDP described above is applied. Fig. 9 is arranged so that it is connected to the soldering pattern SDP of Fig. 9 is in contact. The central area CA of the first electrode CE1 is connected to the light emission device ED by the soldering pattern SDP of Fig. 9 electrically connected. In the central area CA, an upper surface of the first electrode CE1 can be formed from the fourth conductive layer CE1d. The fourth conductive layer CE1d has a transparent conductive oxide layer with good adhesion to the solder pattern SDP. Fig. 9 and corrosion resistance and acid resistance can, for example, form the upper surface of the first electrode CE1 in the central area CA.

[0214] In this case, the width of the central area CA can be determined in all subpixels according to various embodiments of Fig. 11A, Fig. 12A, Fig. 13A and Fig. 14A will be the same.

[0215] As in Fig. 11B, Fig. 12B, Fig. 13B and Fig. As shown in Figure 14B, the central area CA can have a rectangular structure, for example a square structure, but is not limited to this.

[0216] The reflection areas RA1, RA2, RA3, and RA4 are areas located between the central area CA and the edge areas EA1, EA2, EA3, and EA4. The reflection areas RA1, RA2, RA3, and RA4 do not need to be connected to the SDP soldering pattern. Fig. 9 are in contact. In the reflection regions RA1, RA2, RA3, and RA4, the upper surface of the first electrode CE1 can be formed from the second conductive layer CE1b. Since the third and fourth conductive layers CE1c and CE1d, which form the first electrode CE1, are located away from the reflection regions RA1, RA2, RA3, and RA4, the second conductive layer CE1b, positioned beneath the third and fourth conductive layers CE1c and CE1d, can be exposed on the upper surfaces of the reflection regions RA1, RA2, RA3, and RA4. The second conductive layer CE1b, which has good reflection efficiency and can function as a reflector, can, for example, form an upper surface of the first electrode CE1 in the reflection regions RA1, RA2, RA3, and RA4.

[0217] In this case, the widths of the reflection areas RA1, RA2, RA3, and RA4 can be configured to differ from each other within the subpixel according to various embodiments. The width of the first reflection area RA1 of the subpixel according to one embodiment of Fig. 11A and Fig. 11B, for example, is the relatively smallest and the width of the second reflection area RA2 of the subpixel according to another embodiment of Fig. 12A and Fig. 12B is larger than the width of the first reflection area RA1 and the width of the third reflection area RA3 of the subpixel according to another embodiment of Fig. 13A and Fig. 13B can be larger than the width of the second reflection area RA2 and the width of the fourth reflection area RA4 of the subpixel according to another embodiment of Fig. 14A and Fig. 14B can be larger than the width of the third reflection area RA3.

[0218] Therefore, according to another embodiment of Fig. 12a and Fig. 12b exhibit a better reflection efficiency than the subpixels according to the embodiment of Fig. 11a and Fig. 11b, the subpixels according to another embodiment of Fig. 13a and Fig. 13b can exhibit a better reflection efficiency than the subpixels according to another embodiment of Fig. 12a and Fig. 12b and the subpixels according to another embodiment of Fig. 14a and Fig. 14b can exhibit a better reflection efficiency than the subpixels according to the other embodiments of Fig. 13a and Fig. 13b.

[0219] As in Fig. 11B, Fig. 12B, Fig. 13B and Fig. As shown in Figure 14B, the reflection areas RA1, RA2, RA3 and RA4 can have a rectangular frame structure, for example a square frame structure, while surrounding the central area CA, but are not limited to it.

[0220] With reference to Fig. 9, as described above, the reflection areas RA1, RA2, RA3 and RA4 can be covered by the passivation layer 116.

[0221] Edge regions EA1, EA2, EA3, and EA4 are located outside the reflection regions RA1, RA2, RA3, and RA4. Edge regions EA1, EA2, EA3, and EA4 do not need to be connected to the SDP soldering pattern. Fig. 9 are in contact. In the edge regions EA1, EA2, EA3, and EA4, an upper surface of the first electrode CE1 can be formed from the fourth conductive layer CE1d. The fourth conductive layer CE1d, with a transparent conductive oxide layer offering corrosion and acid resistance, can, for example, form the upper surface of the first electrode CE1 in the edge regions EA1, EA2, EA3, and EA4. In the edge regions EA1, EA2, EA3, and EA4, the upper surface of the first electrode CE1 can be formed from the same material layer as the upper top surface of the first electrode CE1 in the central region CA, for example, the same fourth conductive layer CE1d.

[0222] In this case, the widths of the edge regions EA1, EA2, EA3, and EA4 can be configured to differ from each other in subpixels of different embodiments. The widths of the edge regions EA1, EA2, EA3, and EA4 in the subpixels of different embodiments can be opposite to the widths of the reflection regions RA1, RA2, RA3, and RA4 in the subpixels of different embodiments. The width of the first edge region EA1 of the subpixel according to the embodiment of Fig. 11A and Fig. 11B, for example, is the relatively largest and the width of the second edge region EA2 of the subpixel according to the other embodiment of Fig. 12A and Fig. 12B is smaller than the width of the first edge region EA1 and the width of the third edge region EA3 of the subpixel according to another embodiment of Fig. 13A and Fig. 13B is smaller than the width of the second edge region EA2 and the width of the fourth edge region EA4 of the subpixel according to another embodiment of Fig. 14A and Fig. 14B can be smaller than the width of the third edge region EA3.

[0223] As in Fig. 11B, Fig. 12B, Fig. 13B and Fig. As shown in Figure 14B, the edge regions EA1, EA2, EA3 and EA4 can comprise a rectangular frame structure surrounding the reflection regions RA1, RA2, RA3 and RA4, but are not limited to it.

[0224] The edge regions EA1, EA2, EA3, and EA4 of the first electrode CE1 can extend through one end of the bank BNK, thus connecting to the signal line TL. The signal line TL can be formed integrally with the edge regions EA1, EA2, EA3, and EA4 of the first electrode CE1. Consequently, the signal line TL can include, but is not limited to, the first conductive layer CE1a, the second conductive layer CE1b, the third conductive layer CE1c, and the fourth conductive layer CE1d.

[0225] With reference to Fig. 9, as described above, the edge areas EA1, EA2, EA3 and EA4 can be covered by the passivation layer 116.

[0226] Fig. 15 represents several subpixels located in an X-region of Fig. 10A according to an embodiment of the present disclosure, for example in a region near a first boundary line D1 between a first transfer region and a second transfer region.

[0227] As from Fig. As can be seen in Figure 15, for example, based on the first boundary line D1 between the first transfer region and the second transfer region, a first display area AA1 is arranged on a left side and a second display area AA2 is arranged on a right side.

[0228] Furthermore, a third display area AA3 is arranged between the first display area AA1 and the second display area AA2. A portion of the third display area AA3, for example a left portion, can be arranged on the left side of the first boundary line D1, and the remaining portion of the third display area AA3, for example a right portion, can be arranged on the right side of the first boundary line D1.

[0229] Consequently, the multiple light-emitting devices of the multiple subpixels to the first display area AA1 and a sub-area of ​​the third display area AA3, corresponding to the first transition region, can be transferred by a first transition process. Furthermore, the multiple light-emitting devices of the multiple subpixels to the second display area AA2 and to the remaining areas of the third display area AA3, corresponding to the second transition region, can be transferred by a second transition process.

[0230] For practical purposes, subpixels with a 4×8 matrix structure are shown in the first to fourth rows R1 to R4 and the first to eighth rows C1 to C8. In this case, the first display area AA1 has subpixels with a 4×2 matrix structure in the first to fourth rows R1 to R4 and the first to second rows C1 to C2, the second display area AA2 has subpixels with a 4×2 matrix structure in the first to fourth rows R1 to R4 and the seventh to eighth rows C7 to C8, and the third display area AA3 has subpixels with a 4×4 matrix structure in the first to fourth rows R1 to R4 and the third to sixth rows C3 to C6. The matrix structure of the subpixels forming the third display area AA3 can be modified in various ways. For example, the number of columns C3 to C6 forming the third display area AA3 can be changed.

[0231] A first electrode CE1 with a reflection area of ​​the same width can be located in any of the multiple subpixels in the first display area AA1. A first electrode CE1 with a reflection area of ​​an intermediate width among several widths applied to the entire display area can, for example, be located in the multiple subpixels in the first display area AA1. For instance, if the reflection area with multiple widths applied to the entire display area is made up of the first through fourth reflection areas RA1, RA2, RA3, and RA4 described above, the first electrode CE1_RA3 with the third reflection area can be located in the multiple subpixels in the first display area AA1. In some cases, the first electrode CE1_RA2 with the second reflection area can be located in the multiple subpixels in the first display area AA1.As shown, the first electrode CE1_RA3 with the third reflection area can, for example, be arranged in all of the several subpixels with the 4×2 matrix structure of the first to fourth rows R1 to R4 and the first to second columns C1 to C2 in the first display area AA1.

[0232] Similarly, a first electrode CE1 with a reflection area of ​​the same width can be arranged in the multiple subpixels within the second display area AA2. Like the first display area AA1, the first electrode CE1 with the reflection area of ​​an intermediate width among the multiple widths applied to the entire display area can, for example, be arranged in multiple subpixels within the second display area AA2. For instance, if the reflection area with multiple widths applied to the entire display area is made up of the first through fourth reflection areas RA1, RA2, RA3, and RA4 described above, the first electrode CE1_RA3 with the third reflection area can be arranged in the multiple subpixels within the second display area AA2, as shown.In some cases, the first electrode CE1_RA2 can be arranged with the second reflection area in the multiple subpixels in the second display area AA2. As shown, for example, the first electrode CE1_RA3 can be arranged with a third reflection area in all of the multiple subpixels with the 4×2 matrix structure of the first to fourth rows R1 to R4 and the seventh to eighth columns C7 to C8.

[0233] A first electrode CE1 with reflection areas of varying widths can be arranged in the multiple subpixels of the third display area AA3. Among the multiple widths applied to the entire display area, for example, the first electrode CE1 with a reflection area of ​​all widths can be arranged in the multiple subpixels of the third display area AA3. Specifically, the first electrodes CE1 with the smallest reflection area up to the first electrode CE1 with the largest reflection area can be arranged in the multiple subpixels of the third display area AA3.For example, if the multi-width reflection area applied to the entire display area is constructed from the first through fourth reflection areas RA1, RA2, RA3, and RA4 described above, as shown, then the first electrode CE1_RA1 with the first reflection area, the first electrode CE1_RA2 with the second reflection area, the first electrode CE1_RA3 with the third reflection area, and the first electrode CE1_RA4 with the fourth reflection area can be located in the multiple subpixels within the third display area AA3. Although not shown, a first electrode with a fifth reflection area larger than the fourth reflection area RA4, a first electrode with a sixth reflection area larger than the fifth reflection area, and so on, can additionally be included within the third display area AA3.

[0234] In odd-numbered rows R1 and R3, the first electrode can be positioned such that the width of the reflection area gradually increases across the subpixels from the third column C3 to the sixth column C6, and in even-numbered rows R2 and R4, the first electrode can be positioned such that the width of the reflection area gradually decreases across the subpixels from the third column C3 to the sixth column C6. For example, in odd-numbered rows R1 and R3, the first electrode CE1_RA1 (with the first reflection area), the first electrode CE1_RA2 (with the second reflection area), the first electrode CE1_RA3 (with the third reflection area), and the first electrode CE1_RA4 (with the fourth reflection area) are sequentially arranged across the subpixels from the third column C3 to the sixth column C6.And in a straight row R2 and R4, the first electrode CE1_RA4 with the fourth reflection area, the first electrode CE1_RA3 with the third reflection area, the first electrode CE1_RA2 with the second reflection area and the first electrode CE1_RA1 with the first reflection area can be arranged sequentially in the several subpixels from the third column C3 to the sixth column C6.

[0235] In some cases, in the odd rows R1 and R3, the first electrode can be arranged such that the width of the reflection area in the several subpixels gradually decreases from the third row C3 to the sixth row C6, and in the even rows R2 and R4, the first electrode can be arranged such that the width of the reflection area in the several subpixels gradually increases from the third row C3 to the sixth row C6.

[0236] Meanwhile, a primary light emission device ED is arranged in the odd rows R1 and R3, and a redundant light emission device ED is arranged in the even rows R2 and R4, so that a subpixel can be formed by a combination of the two rows. In this case, in the odd rows R1 and R3, where the primary light emission device ED is located, the width of the reflection area gradually increases or decreases as the columns C3 to C6 increase, and conversely, in the even rows R2 and R4, where the redundant light emission device ED is located, the first electrode can be arranged such that the width of the reflection area gradually decreases or increases as the columns C3 to C6 increase.

[0237] As described above, according to a configuration of the present disclosure in the third display area AA3 with the first boundary line D1 between the first transition region and the second transition region, the first electrode can be arranged such that the width of the reflection area gradually increases in odd or even rows, and the first electrode can be arranged such that the width of the reflection area gradually decreases in even or odd rows.Consequently, the reflectivity of the first electrode is distributed differently in the several subpixels in the third display area AA3; even if there is a difference in the presence or absence of the transition error or a difference in the characteristics of light emission devices between the first transition region and the second transition region, a problem of spots appearing near the first boundary line D1 between the first transition region and the second transition region can be solved or reduced.

[0238] Fig. 16 represents several subpixels located in an X-region of Fig. 10A according to another embodiment of the present disclosure, for example in a region near a first boundary line D1 between a first transfer region and a second transfer region.

[0239] According to Fig. 15, which is described above, in the third display area AA3 with the first boundary line D1 between the first transition region and the second transition region, the first electrode is arranged such that the width of the reflection area in odd rows gradually increases as the columns C3 to C6 increase, and the width of the reflection area in even rows gradually decreases as the columns C3 to C6 increase, or the first electrode is arranged such that the width of the reflection area in odd rows gradually decreases as the columns C3 to C6 increase, and the width of the reflection area in even rows gradually increases as the columns C3 to C6 increase.

[0240] On the other hand, according to Fig. 16 in the third display area AA3 with the first boundary line D1 between the first transition region and the second transition region, the first electrode may be arranged such that the width of the reflection area in two adjacent rows, for example in the first row R1 and the second row R2, gradually increases as the columns C3 to C6 increase, and the first electrode may be arranged such that the width of the reflection area in two adjacent rows, for example in the third row R3 and the fourth row R4, gradually decreases as the columns C3 to C6 increase.Alternatively, in the third display area AA3 with the first boundary line D1 between the first transition region and the second transition region, the first electrode can be arranged such that the width of the reflection area in two adjacent rows, for example in the first row R1 and the second row R2, gradually decreases as the columns C3 to C6 increase, and the first electrode can be arranged such that the width of the reflection area in the other two adjacent rows, for example in the third row R3 and the fourth row R4, gradually increases as the columns C3 to C6 increase.

[0241] The main light emission device ED is arranged in odd rows R1 and R3 and the redundant light emission device ED is arranged in even rows R2 and R4, so that a subpixel can be formed by a combination of the two rows.

[0242] In this case, the first electrode can be arranged such that the width of the reflection area in two adjacent rows R1 and R2, in which the main light emission device ED and the redundancy light emission device ED are arranged, gradually increases or decreases as the columns C3 to C6 increase, and the first electrode can be arranged such that the width of the reflection area in the other two adjacent rows R3 and R4, in which the main light emission device ED and the redundancy light emission device ED are arranged, gradually decreases or increases as the columns C3 to C6 increase.

[0243] As described above, according to another configuration of the present disclosure, in the third display area AA3 with the first boundary line D1 between the first transition region and the second transition region, the first electrode can be arranged such that the width of the reflection area in two adjacent rows gradually increases or decreases as the slit increases, and a first electrode can be arranged such that the width of the reflection area in the other two adjacent rows gradually decreases or increases as the slit increases.Consequently, the reflectivity of the first electrode is distributed differently in the several subpixels in the third display area AA3. Even if the difference in the presence or absence of the transition error or the difference in characteristics of light emission devices occurs between the first transition region and the second transition region, the problem of spots appearing near the first boundary line D1 between the first transition region and the second transition region can be solved or reduced.

[0244] Fig. 17 represents several subpixels located in a Y-region of Fig. 10A according to another embodiment of the present disclosure, for example in a region near a second boundary line D2 between a first transfer region and a third transfer region.

[0245] As from Fig. As can be seen in Figure 17, for example, a fourth display area AA4 is arranged on a top side based on the second boundary line D2 between the first transfer region and the third transfer region, and a fifth display area AA5 is arranged on the bottom side.

[0246] Furthermore, a sixth display area AA6 is arranged between the fourth display area AA4 and the fifth display area AA5. A portion of the sixth display area AA6, for example an upper portion, can be arranged above the second boundary line D2, and the remaining portion of the sixth display area AA6, for example a lower portion, can be arranged below the second boundary line D2.

[0247] Consequently, the multiple light-emitting devices of the multiple subpixels to the fourth display area AA4 and a sub-area of ​​the sixth display area AA6, corresponding to the first transition region, can be transferred by a first transition process. Furthermore, the multiple light-emitting devices of the multiple subpixels to the fifth display area AA5 and to the remaining areas of the sixth display area AA6, corresponding to the third transition region, can be transferred by a third transition process.

[0248] For practical purposes, subpixels with an 8×4 matrix structure in the first to eighth rows R1 to R8 and the first to fourth columns C1 to C4 are shown. In this case, the fourth display area AA4 has subpixels with a 2×4 matrix structure in the first to second rows R1 to R2 and the first to fourth columns C1 to C4, the fifth display area AA5 has subpixels with a 2×4 matrix structure in the seventh to eighth rows R7 to R8 and the first to fourth columns C1 to C4, and the sixth display area AA6 has subpixels with a 4×4 matrix structure in the third to sixth rows R3 to R6 and the first to fourth columns C1 to C4. In this case, the matrix structure of the subpixels that make up the sixth display area AA6 can be modified in various ways. For example, the number of rows R3 to R6 that make up the sixth display area AA6 can be changed.

[0249] A first electrode CE1 with a reflection area of ​​the same width can be located in any of the multiple subpixels in the fourth display area AA4. A first electrode CE1 with a reflection area of ​​an intermediate width among several widths applied to the entire display area can, for example, be located in the multiple subpixels in the fourth display area AA4. If the reflection area with multiple widths applied to the entire display area is made up of the first through fourth reflection areas RA1, RA2, RA3, and RA4 as described above, the first electrode CE1_RA3 with the third reflection area can, for example, be located in the multiple subpixels in the fourth display area AA4. In some cases, the first electrode CE1_RA2 with the second reflection area can be located in the multiple subpixels in the fourth display area AA4.As shown, the first electrode CE1_RA3 with the third reflection area can, for example, be arranged in all of the several subpixels with the 2×4 matrix structure of the first to second rows R1 to R2 and the first to fourth columns C1 to C4 in the fourth display area AA4.

[0250] Similarly, a first electrode CE1 with a reflection area of ​​the same width can be arranged in the multiple subpixels within the fifth display area AA5. Like the fourth display area AA4, for example, the first electrode CE1 with the reflection area having an intermediate width among the multiple widths applied to the entire display area can be arranged in multiple subpixels within the fifth display area AA5. If the reflection area with the multiple widths applied to the entire display area is made up of the first through fourth reflection areas RA1, RA2, RA3, and RA4 described above, then, for example, the first electrode CE1_RA3 with the third reflection area can be arranged in the multiple subpixels within the fifth display area AA5, as shown.In some cases, the first electrode CE1_RA2 with the second reflection area can be located in the multiple subpixels in the fifth display area AA5. As shown, the first electrode CE1_RA3 with a third reflection area can, for example, be located in all of the multiple subpixels with the 2×4 matrix structure of the seventh to eighth rows R7 to R8 and the first to fourth columns C1 to C4.

[0251] A first electrode CE1 with reflection areas of varying widths can be arranged in the multiple subpixels of the sixth display area AA6. Among the multiple widths applied to the entire display area, for example, the first electrode CE1 with a reflection area of ​​all widths can be arranged in the multiple subpixels of the sixth display area AA6. Specifically, the first electrodes CE1 with a reflection area of ​​the smallest width up to the first electrode CE1 with the reflection area of ​​the largest width can be arranged in the multiple subpixels of the sixth display area AA6.For example, if the multi-width reflection area applied to the entire display area is constructed from the first through fourth reflection areas RA1, RA2, RA3, and RA4 described above, as shown, then the first electrode CE1_RA1 with the first reflection area, the first electrode CE1_RA2 with the second reflection area, the first electrode CE1_RA3 with the third reflection area, and the first electrode CE1_RA4 with the fourth reflection area can be located in the multiple subpixels within the sixth display area AA6. Although not shown, a first electrode with a fifth reflection area larger than the fourth reflection area RA4, a first electrode with a sixth reflection area larger than the fifth reflection area, and so on, can additionally be included in the sixth display area AA6.

[0252] In odd-numbered columns C1 and C3, the first electrode can be positioned such that the width of the reflection area gradually decreases across the subpixels from the third row R3 to the sixth row R6, and in even-numbered columns C2 and C4, the first electrode can be positioned such that the width of the reflection area gradually increases across the subpixels from the third row R3 to the sixth row R6. For example, in odd-numbered columns C1 and C3, the first electrode CE1_RA4 with the fourth reflection area, the first electrode CE1_RA3 with the third reflection area, the first electrode CE1_RA2 with the second reflection area, and the first electrode CE1_RA1 with the first reflection area are sequentially arranged across several subpixels from the third row R3 to the sixth row R6.And in an even column C2 and C4, the first electrode CE1_RA1 with the first reflection area, the first electrode CE1_RA2 with the second reflection area, the first electrode CE1_RA3 with the third reflection area and the first electrode CE1_RA4 with the fourth reflection area can be arranged sequentially in the several subpixels from the third row R3 to the sixth row R6.

[0253] In some cases, in the odd columns C1 and C3, a first electrode can be arranged such that the width of the reflection area in the several subpixels gradually increases from the third row R3 to the sixth row R6, and in the even columns C2 and C4, the first electrode can be arranged such that the width of the reflection area in the several subpixels gradually decreases from the third row R3 to the sixth row R6.

[0254] As described above, according to a configuration of the present patent description, in the sixth display area AA6 with the second boundary line D2 between the first transition region and the third transition region in the odd or even column, the first electrode can be arranged such that the width of the reflection area gradually increases as the rows R3 to R6 increase, and in the even or odd columns, the width of the reflection area can be arranged such that the width of the reflection area gradually decreases as the rows R3 to R6 increase.Consequently, the reflectivity of the first electrode is distributed differently in several subpixels in the sixth display area AA6; even if there is a difference in the presence or absence of a transition error or a difference in characteristics of light emission devices between the first transition region and the third transition region, a problem of spot occurrence near the second boundary line D2 between the first transition region and the third transition region can be solved or reduced.

[0255] Fig. 18 represents several subpixels located in a Y-region of Fig. 10A according to another embodiment of the present disclosure, for example in a region near a second boundary line between a first transfer region and a third transfer region.

[0256] According to Fig. 17, which is described above, in the sixth display area AA6 with the second boundary line D2 between the first transition region and the third transition region, the first electrode is arranged such that the width of the reflection area in odd columns gradually increases as the number of rows increases, or the first electrode is arranged such that the width of the reflection area in even columns gradually decreases as the number of rows increases, or the first electrode is arranged such that the width of the reflection area in odd columns gradually decreases as the number of rows increases, and the width of the reflection area in even columns gradually increases as the number of rows increases.

[0257] According to Fig. 18 On the other hand, in the sixth display area AA6 with the second boundary line D2 between the first transition region and the third transition region, the first electrode can be arranged such that the width of the reflection area in two adjacent columns, for example in the first column C1 and the second column C2, gradually decreases as the rows R3 to R6 increase, and the first electrode can be arranged such that the width of the reflection area in two adjacent columns, for example in the third column C3 and the fourth column C4, gradually increases as the rows R3 to R6 increase.Alternatively, in the sixth display area AA6 with the second boundary line D2 between the first transition region and the third transition region, the first electrode can be arranged such that the width of the reflection area in two adjacent columns, for example in the first column C1 and the second column C2, gradually increases as the rows R3 to R6 increase, and the first electrode can be arranged such that the width of the reflection area in the other two adjacent columns, for example in the third column C3 and the fourth column C4, gradually decreases as the rows R3 to R6 increase.

[0258] As described above, according to another configuration of the present disclosure, in the sixth display area AA6 with the second boundary line D2 between the first transition region and the third transition region, the first electrode can be arranged such that the width of the reflection area in two adjacent columns gradually increases or decreases as the series increases, and the first electrode can be arranged such that the width of the reflection area in the other two adjacent columns gradually decreases or increases as the series increases.Consequently, the reflectivity of the first electrode is distributed differently in several subpixels in the sixth display area AA6; even if the difference in the presence or absence of a transition error or the difference in the characteristics of light emission devices occurs between the first transition region and the third transition region, a problem of spot occurrence near the second boundary line D2 between the first transition region and the third transition region can be solved or reduced.

[0259] Fig. 19 represents several subpixels located in a Z-region of Fig. 10A according to another embodiment of the present disclosure, for example in a nearby region in which a first boundary line D1 between a first transfer region and a second transfer region and a second boundary line D2 between a first transfer region and a third transfer region are arranged.

[0260] As from Fig. As can be seen in Figure 19, for example, based on the first boundary line D1 between the first and second transfer regions and between the third and fourth transfer regions, a seventh display area AA7 is arranged on the left and an eighth display area AA8 is arranged on the right. In this case, a portion of the seventh display area AA7, for example an upper portion, can be located in the first transfer region and the remaining portion of the seventh display area AA7, for example a lower portion, can be located in the third transfer region. A portion of the eighth display area AA8, for example an upper portion, can be located in the second transfer region and the remaining portion of the eighth display area AA8, for example a lower portion, can be located in the fourth transfer region.

[0261] Furthermore, a ninth display area AA9 is arranged between the seventh display area AA7 and the eighth display area AA8. A portion of the ninth display area AA9, for example, a left portion, may be located on the left side of the first boundary line D1, and the remaining portion of the ninth display area AA9, for example, a right portion, may be located on the right side of the first boundary line D1. In this case, an upper left portion of the ninth display area AA9 is located in the first transition region, an upper right portion of the ninth display area AA9 is located in the second transition region, a lower left portion of the ninth display area AA9 may be located in the third transition region, and the lower right portion of the ninth display area AA9 may be located in the fourth transition region.

[0262] Consequently, the multiple light-emitting devices of the multiple subpixels to the upper region of the seventh display area AA7 and to the upper left region of the ninth display area AA9, corresponding to the first transition region, are transferred by the first transition process. Furthermore, the multiple light-emitting devices of the multiple subpixels to the upper region of the eighth display area AA8 and to the upper right region of the ninth display area AA9, corresponding to the second transition region, are transferred by the second transition process. Additionally, the multiple light-emitting devices of the multiple subpixels to the lower region of the seventh display area AA7 and to the lower left region of the ninth display area AA9, corresponding to the third transition region, are transferred by the third transition process.Furthermore, the multiple light emission devices of the multiple subpixels to the lower area of ​​the eighth display area AA8 and to the lower right area of ​​the ninth display area AA9, which correspond to the fourth transfer region, are transferred by the fourth transfer process.

[0263] For practical purposes, subpixels with an 8×8 matrix structure in the first to eighth rows R1 to R8 and the first to eighth columns C1 to C8 are shown. In this case, the seventh display area AA7 can have subpixels with an 8×2 matrix structure in the first to eighth rows R1 to R8 and the first to second columns C1 to C2, the eighth display area AA8 can have subpixels with an 8×2 matrix structure in the first to eighth rows R1 to R8 and the seventh to eighth columns C7 to C8, and the ninth display area AA9 can have subpixels with an 8×4 matrix structure in the first to eighth rows R1 to R8 and the third to sixth columns C3 to C6. In this case, the matrix structure of a subpixel forming the ninth display area AA9 can be modified in various ways. For example, the number of columns C3 to C6 forming the ninth display area AA9 can be modified in various ways.

[0264] A first electrode CE1 with a reflection area of ​​the same width can be located in any of the multiple subpixels in the seventh display area AA7. A first electrode CE1 with a reflection area of ​​an intermediate width among several widths applied to the entire display area can, for example, be located in the multiple subpixels in the seventh display area AA7. If the reflection area with multiple widths applied to the entire display area is made up of the first through fourth reflection areas RA1, RA2, RA3, and RA4 as described above, the first electrode CE1_RA3 with the third reflection area can, for example, be located in the multiple subpixels in the seventh display area AA7. In some cases, the first electrode CE1_RA2 with the second reflection area can be located in the multiple subpixels in the seventh display area AA7.As shown, the first electrode CE1_RA3 with the third reflection area can, for example, be arranged in all of the several subpixels with the 8×2 matrix structure of the first to eighth rows R1 to R8 and the first to second columns C1 to C2 in the seventh display area AA7.

[0265] Similarly, a first electrode CE1 with a reflection area of ​​the same width can be arranged in the multiple subpixels within the eighth display area AA8. Like the seventh display area AA7, for example, the first electrode CE1 with the reflection area having an intermediate width among the multiple widths applied to the entire display area can be arranged in multiple subpixels within the eighth display area AA8. For example, if the reflection area with multiple widths applied to the entire display area is made up of the first through fourth reflection areas RA1, RA2, RA3, and RA4 described above, the first electrode CE1_RA3 with the third reflection area can be arranged in the multiple subpixels within the eighth display area AA8, as shown. In some cases, the first electrode CE1_RA2 with the second reflection area can be arranged in the multiple subpixels within the eighth display area AA8.As shown, the first electrode CE1_RA3 with a third reflection area can, for example, be arranged in all of the several subpixels with the 8×2 matrix structure of the first to eighth rows R1 to R8 and the seventh to eighth columns C7 to C8.

[0266] A first electrode CE1 with reflection areas of varying widths can be arranged in the multiple subpixels of the ninth display area AA9. Among the multiple widths applied to the entire display area, for example, the first electrode CE1 with a reflection area of ​​all widths can be arranged in the multiple subpixels of the ninth display area AA9. Specifically, the first electrodes CE1 with a reflection area of ​​the smallest width up to the first electrode CE1 with the reflection area of ​​the largest width can be arranged in the multiple subpixels of the ninth display area AA9.If the reflection area with multiple widths applied to the entire display area is constructed from the first through fourth reflection areas RA1, RA2, RA3, and RA4 described above, as shown, then, for example, the first electrode CE1_RA1 with the first reflection area, the first electrode CE1_RA2 with the second reflection area, the first electrode CE1_RA3 with the third reflection area, and the first electrode CE1_RA4 with the fourth reflection area can be located in the multiple subpixels in the ninth display area AA9. Although not shown, a first electrode with a fifth reflection area larger than the fourth reflection area RA4, a first electrode with a sixth reflection area larger than the fifth reflection area, and so on, can additionally be contained in the ninth display area AA9.

[0267] In odd-numbered rows R1, R3, R5, and R7, the first electrode can be positioned such that the width of the reflection area gradually increases across several subpixels from the third column C3 to the sixth column C6. Conversely, in even-numbered rows R2, R4, R6, and R8, the first electrode can be positioned such that the width of the reflection area gradually decreases across several subpixels from the third column C3 to the sixth column C6. For example, in odd-numbered rows R1, R3, R5, and R7, the first electrode CE1_RA1 (with the first reflection area), the first electrode CE1_RA2 (with the second reflection area), the first electrode CE1_RA3 (with the third reflection area), and the first electrode CE1_RA4 (with the fourth reflection area) are sequentially arranged across several subpixels from the third column C3 to the sixth column C6.And in a straight row R2, R4, R6 and R8, the first electrode CE1_RA4 with the fourth reflection area can be arranged sequentially in several subpixels from the third column C3 to the sixth column C6, the first electrode CE1_RA3 with the third reflection area, the first electrode CE1_RA2 with the second reflection area and the first electrode CE1_RA1 with the first reflection area can be arranged sequentially in several subpixels.

[0268] In some cases, in odd rows R1, R3, R5 and R7, a first electrode can be arranged such that the width of the reflection area in the several subpixels gradually decreases from the third column C3 to the sixth column C6, and in even rows R2, R4, R6 and R8, the first electrode can be arranged such that the width of the reflection area in the several subpixels gradually increases from the third column C3 to the sixth column C6.

[0269] Meanwhile, the primary light emission device ED is arranged in odd-numbered rows R1, R3, R5, and R7, and the secondary light emission device ED is arranged in even-numbered rows R2, R4, R6, and R8, such that a subpixel can be formed by a combination of the two rows. In this case, in odd-numbered rows R1, R3, R5, and R7, where the primary light emission device ED is located, a first electrode can be positioned such that the width of the reflection region gradually increases or decreases as the slits C3 to C6 increase, and conversely, in even-numbered rows R2, R4, R6, and R8, where the secondary light emission device ED is located, the width of the reflection region gradually decreases or increases as the slits C3 to C6 increase.

[0270] As described above, according to another configuration of the present disclosure, in the ninth display area AA9 with an area where the first boundary line D1 and the second boundary line D2 intersect, a first electrode can be arranged such that the width of the reflection area in odd or even rows gradually increases as the slit increases, and a first electrode can be arranged such that the width of the reflection area in even or odd rows gradually decreases as the slit increases.Consequently, the reflectivity of the first electrode is distributed differently in several subpixels in the ninth display area AA9; even if a difference in the presence or absence of a transition error or a difference in characteristics of light-emitting elements occurs between the first to fourth transition areas, a problem of spot occurrence near the first boundary line D1 and the second boundary line D2 can be solved or reduced.

[0271] Fig. 20 represents several subpixels located in a Z-region of Fig. 10A according to another embodiment of the present disclosure, for example in a nearby region in which a first boundary line between a first transfer region and a second transfer region and a second boundary line between a first transfer region and a third transfer region are arranged.

[0272] As from Fig. As can be seen in Figure 20, for example, based on the second boundary line D2 between the first and third transfer regions and between the second and fourth transfer regions, a seventh display area AA7 is arranged on a top side and an eighth display area AA8 is arranged on a bottom side. In this case, a portion of the seventh display area AA7, for example a left area, can be located in the first transfer region and the remaining portion of the seventh display area AA7, for example a right area, can be located in the second transfer region. A portion of the eighth display area AA8, for example a left area, can be located in the third transfer region and the remaining portion of the eighth display area AA8, for example a right area, can be located in the fourth transfer region.

[0273] Furthermore, a ninth display area AA9 is arranged between the seventh display area AA7 and the eighth display area AA8. A portion of the ninth display area AA9, for example, an upper portion, may be located above the second boundary line D2, and the remaining portion of the ninth display area AA9, for example, a lower portion, may be located below the second boundary line D2. In this case, an upper left portion of the ninth display area AA9 is located in the first transition region, an upper right portion of the ninth display area AA9 is located in the second transition region, a lower left portion of the ninth display area AA9 may be located in the third transition region, and a lower right portion of the ninth display area AA9 may be located in the fourth transition region.

[0274] Consequently, the multiple light-emitting devices of the multiple subpixels to the left region of the seventh display area AA7 and to the upper left region of the ninth display area AA9, corresponding to the first transition region, are transferred by the first transition process. Furthermore, the multiple light-emitting devices of the multiple subpixels to the right region of the seventh display area AA7 and to the upper right region of the ninth display area AA9, corresponding to the second transition region, are transferred by the second transition process. Additionally, the multiple light-emitting devices of the multiple subpixels to the left region of the eighth display area AA8 and to the lower left region of the ninth display area AA9, corresponding to the third transition region, are transferred by the third transition process.Furthermore, the multiple light emission devices of the multiple subpixels to the right area of ​​the eighth display area AA8 and to the lower right area of ​​the ninth display area AA9, which correspond to the fourth transfer region, are transferred by the fourth transfer process.

[0275] For practical purposes, subpixels with an 8×8 matrix structure are shown in the first to eighth rows R1 to R8 and the first to eighth columns C1 to C8. In this case, the seventh display area AA7 has subpixels with a 2×8 matrix structure in the first to second rows R1 to R2 and the first to eighth columns C1 to C8, and the eighth display area AA8 has subpixels with a 2×8 matrix structure in the seventh to eighth rows R7 to R8 and the first to eighth columns C1 to C8, and the ninth display area AA9 has subpixels with a 4×8 matrix structure in the third to sixth rows R3 to R6 and the first to eighth columns C1 to C8. In this case, the matrix structure of the subpixels that make up the ninth display area AA9 can be modified in various ways. For example, the number of rows R3 to R6 that make up the ninth display area AA9 can be changed.

[0276] A first electrode CE1 with a reflection area of ​​the same width can be located in any of the multiple subpixels in the seventh display area AA7. A first electrode CE1 with a reflection area of ​​an intermediate width among several widths applied to the entire display area can, for example, be located in any of the multiple subpixels in the seventh display area AA7. A first electrode CE1_RA3 with the third reflection area, or a first electrode CE1_RA2 with the second reflection area, can, for example, be located in any of the multiple subpixels in the seventh display area AA7. As shown, for example, a first electrode CE1_RA3 with the third reflection area can be located in any of the multiple subpixels with the 2×8 matrix structure of the first to second rows R1 to R2 and the first to eighth columns C1 to C8 in the seventh display area AA7.

[0277] Similarly, a first electrode CE1 with a reflection area of ​​the same width can be arranged in the multiple subpixels within the eighth display area AA8. Like the seventh display area AA7, for example, the first electrode CE1 with the reflection area having an intermediate width among the multiple widths applied to the entire display area can be arranged in multiple subpixels within the eighth display area AA8. The first electrode CE1_RA3 with the third reflection area, or the first electrode CE1_RA2 with the second reflection area, can, for example, be arranged in the multiple subpixels within the eighth display area AA8. As shown, for example, the first electrode CE1_RA3 with a third reflection area can be arranged in all of the multiple subpixels with the 2×8 matrix structure in the seventh to eighth rows R7 to R8 and the first to eighth columns C1 to C8 within the eighth display area AA8.

[0278] A first electrode CE1 with reflection areas of varying widths can be arranged in the multiple subpixels of the ninth display area AA9. Among the multiple widths applied to the entire display area, for example, the first electrode CE1 with a reflection area of ​​all widths can be arranged in the multiple subpixels of the ninth display area AA9. In particular, the first electrode CE1 with a reflection area of ​​the smallest width can be arranged in the multiple subpixels of the ninth display area AA9, up to the first electrode CE1 with the reflection area of ​​the largest width.The first electrode CE1_RA1 with the first reflection area, the first electrode CE1_RA2 with the second reflection area, the first electrode CE1_RA3 with the third reflection area and the first electrode CE1_RA4 with the fourth reflection area can, for example, be arranged in the several subpixels in the ninth display area AA9.

[0279] In odd-numbered columns C1, C3, C5, and C7, the first electrode can be positioned such that the width of the reflection area gradually decreases across several subpixels from the third row R3 to the sixth row R6. Conversely, in even-numbered columns C2, C4, C6, and C8, a first electrode can be positioned such that the width of the reflection area gradually increases across several subpixels from the third row R3 to the sixth row R6. For example, in odd-numbered columns C1, C3, C5, and C7, the first electrode CE1_RA4 (fourth reflection area), the first electrode CE1_RA3 (third reflection area), the first electrode CE1_RA2 (second reflection area), and the first electrode CE1_RA1 (first reflection area) are sequentially arranged across several subpixels from the third row R3 to the sixth row R6.And in an even column C2, C4, C6 and C8, the first electrode CE1_RA1 with the first reflection area, the first electrode CE1_RA2 with the second reflection area, the first electrode CE1_RA3 with the third reflection area and the first electrode CE1_RA4 with the fourth reflection area can be arranged sequentially in several subpixels from the third row R3 to the sixth row R6.

[0280] In some cases, in the odd columns C1, C3, C5 and C7, the first electrode can be arranged such that the width of the reflection area in the several subpixels gradually increases from the third row R3 to the sixth row R6, and in the even columns C2, C4, C6 and C8, the first electrode can be arranged such that the width of the reflection area in the several subpixels gradually decreases from the third row R3 to the sixth row R6.

[0281] As described above, according to another configuration of the present disclosure, in the ninth display area AA9 with an area in which the first boundary line D1 and the second boundary line D2 intersect, the first electrode can be arranged such that the width of the reflection area in the odd or even columns gradually increases as the rows increase, and a first electrode can be arranged such that the width of the reflection area in the even or odd columns gradually decreases as the rows increase.Consequently, the reflectivity of the first electrode is distributed differently in several subpixels in the ninth display area AA9; even if a difference in the presence or absence of a transition error or a difference in characteristics of light emission devices occurs between the first to fourth transition areas, a problem of spot occurrence near the first boundary line D1 and the second boundary line D2 can be solved or reduced.

[0282] Fig. Figures 21 to 24 are diagrams depicting devices to which a display device according to embodiments of the present disclosure is applied.

[0283] With reference to Fig. 21 to 24, the display device according to embodiments of the present disclosure can be contained in various devices or electronic devices. Various electronic devices can, for example, be a portable device 1100, as described in Fig. 21 shown, a mobile device 1200, as in Fig. 22 shown, a 1300 laptop, as in Fig. 23 shown, and a monitor or television set 1400, as in Fig. 24, but embodiments of the present disclosure are not limited thereto.

[0284] Each of the portable device 1100, the mobile device 1200, the laptop 1300 and the monitor or television 1400 may comprise a housing unit 1005, 1010, 1015 and 1020 and a display panel 100 and a display device 1000 according to the embodiments described above in the present disclosure.

[0285] The display device according to one embodiment of the present disclosure comprises, for example, a mobile device, a video phone, a smart watch, a watch phone, a portable device, a foldable device, a rollable device, a flexible device, a curved device, a sliding device, a variable device, an electronic notebook, an electronic book, a portable multimedia player (PMP), a PDA (personal digital assistant), an MP3 player, a mobile medical device, a desktop PC, a laptop PC, a netbook computer, a workstation computer, a navigation device, a vehicle display, a theater display, a television set, a background image device, a signage device, a gaming device, a laptop, a gaming device, a monitor, a camera, a camcorder, or a household appliance.

[0286] It is evident to a person skilled in the art that the present disclosure described above is not limited by the embodiments described above and the accompanying drawings, and that various substitutions, modifications, and variations can be made in the present disclosure without departing from the intent or scope of protection of the disclosures. Consequently, the scope of protection of the present disclosure is defined by the accompanying claims, and it is intended that all variations or modifications derived from the meaning, scope, and equivalent concept of the claims fall within the scope of protection of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] KR 10-2024-0118536

[0001]

Claims

[1] Display device comprising: a substrate (110); a display area (AA) and a non-display area (NA); a pixel control circuit (PD) in the display area (AA); an insulating layer (114, 115a, 115b, 115c) on the pixel control circuit (PD); a bank (BNK) that is arranged in several subpixels, including a first subpixel (SP1) and a second subpixel (SP2), on the insulation layer; a first electrode (CE1) arranged on the bench (BNK) comprising a central region (CA), an edge region (EA), and a reflection region (RA) between the central region and the edge region; and a light emission device (ED) which is arranged on the first electrode (CE1) and is electrically connected to the first electrode (CE1), where the width of the reflection area (RA1) of the first electrode (CE1) in the first subpixel (SP1) differs from the width of the reflection area (RA2) of the first electrode (CE1) in the second subpixel (SP2). [2] Display device according to claim 1, wherein a width of the central area (CA) of the first electrode (CE1) in the first subpixel (SP1) is equal to a width of the central area (CA) of the first electrode (CE1) in the second subpixel (SP2), and / or where the width of the reflection area (RA1) of the first electrode in the first subpixel is greater than the width of the reflection area (RA2) of the first electrode in the second subpixel, and / or where the width of the edge region (EA1) of the first electrode in the first subpixel (SP1) is smaller than the width of the edge region (EA2) of the first electrode in the second subpixel (SP2). [3] Display device according to claim 1 or 2, wherein the first electrode (CE2) has several conductive layers comprising a first conductive layer (CE1d) and a second conductive layer (CE1b) different from the first conductive layer, wherein an upper surface of the central region (CA) and the edge region (EA) of the first electrode (CE1) comprises the same first conductive layer (CE1d) and wherein an upper surface of the reflection area (RA) of the first electrode (CE1) comprises the second conductive layer (CE1b). [4] Display device according to claim 3, wherein the first conductive layer (CE1d) is made of a transparent conductive oxide and the second conductive layer (CE1b) is arranged below the first conductive layer and is made of a reflective material. [5] Display device according to one of the preceding claims, wherein the first electrode (CE1) and the light emission device (ED) are electrically connected to each other by a solder pattern (SDP), and wherein the central area (CA) of the first electrode (CE1) overlaps with the solder pattern (SDP), and / or wherein the reflection area (RA) and the edge area (EA) of the first electrode (CE1) do not overlap with the solder pattern (SDP). [6] Display device according to one of the preceding claims, wherein the reflection area (RA) of the first electrode surrounds the central area (CA) of the first electrode and the edge area (EA) of the first electrode surrounds the reflection area (RA) of the first electrode. [7] Display device according to one of the preceding claims, further comprising a signal line (TL) arranged on the insulating layer (114, 115a, 115b, 115c) and electrically connecting the first electrode (CE1) to the pixel control circuit (PD), wherein the edge region of the first electrode (CE1) extends to the signal line (TL) and is connected to the signal line (TL). [8] Display device according to one of the preceding claims, further comprising a passivation layer (116) on the first electrode (CE1), wherein the passivation layer (116) covers the reflection area (RA) and the edge area (EA) of the first electrode (CE1). [9] Display device according to any of the preceding claims, further comprising: a second electrode (CE2) provided on the light emission device (ED) and electrically connected to the light emission device (ED); a first optical layer (117a) which is provided between the second electrode (CE2) and the substrate (110) and covers a side surface of the light emission device (ED) and a side surface of the bank (BNK). [10] Display device according to claim 9, further comprising: a second optical layer (117b) in contact with a side surface of the first optical layer (117a); a black matrix (BM) on the second electrode (CE2); and a third optical layer (117c) between the second electrode (CE2) and the black matrix (BM). [11] Display device comprising: a display area (AA) with a first display area (AA1), a second display area (AA2) and a third display area (AA3) between the first display area and the second display area; multiple light emission devices (EDs) arranged in multiple subpixels (SPs) in a matrix structure in the display area (AA); and multiple first electrodes (CE1) electrically connected to the multiple light emission devices (ED) in the multiple subpixels (SP), each first electrode (CE1) comprising a central region (CA), an edge region (EA) and a reflection region (RA) between the central region and the edge region, where the widths of the reflection areas (RA) of the multiple first electrodes (CE1) in the multiple subpixels (SP) in the third display area (AA3) are different from each other. [12] Display device according to claim 11, wherein the widths of the reflection areas (RA) of the multiple first electrodes (CE1) in the multiple subpixels in the first display area (AA1) and in the second display area (AA2) are equal to each other. [13] Display device according to claim 11 or 12, wherein in the third display area (AA3) the multiple first electrodes (CE1) have reflection areas (RA) with widths of all sizes and / or comprise first electrodes (CE1) with a reflection area (RA) with a smallest width and first electrodes (CE1) with a reflection area (RA) with a largest width among multiple widths of reflection areas (RA) applied to the entire display area (AA). [14] Display device according to claim 11, 12 or 13, wherein the width of the reflection area (RA) of the multiple first electrodes in the multiple subpixels in the third display area (AA3) gradually increases or decreases as the row or column of the matrix structure increases. [15] Display device according to claim 14, wherein the width of the reflection area (RA) of the multiple first electrodes in the multiple subpixels in the third display area (AA3) gradually increases or decreases in an odd row as the slit increases, and gradually decreases or increases in an even row as the slit increases; or wherein the width of the reflection area (RA) of the multiple first electrodes in the multiple subpixels in the third display area (AA3) gradually increases or decreases in two adjacent rows as the column increases, and gradually decreases or increases in other two adjacent rows as the column increases; or wherein the width of the reflection area (RA) of the multiple first electrodes in the multiple subpixels in the third display area (AA3) gradually increases or decreases in an odd column as the rows increase, and gradually decreases or increases in an even column as the rows increase, or wherein the width of the reflection area (RA) of the multiple first electrodes in the multiple subpixels in the third display area (AA3) gradually increases or decreases in two adjacent columns as the rows increase, and gradually decreases or increases in other two adjacent columns as the rows increase. [16] Display device comprising: a display area (AA) with a first display area (AA1), a second display area (AA2) on one side of the first display area (AA1), a third display area (AA3) between the first display area (AA1) and the second display area (AA2), a fourth display area (AA4) on one side of the first display area (AA1) opposite the second display area (AA2), a fifth display area (AA5) on one side of the fourth display area and a sixth display area (AA6) between the fourth display area and the fifth display area; multiple light emission devices (EDs) in multiple subpixels (SP) with a matrix structure in the display area (AA); and several first electrodes (CE1) electrically connected to the multiple light emission devices (ED) in the multiple subpixels (SP) and comprising a central area (CA), an edge area (EA) and a reflection area (RA) between the central area (CA) and the edge area (EA), wherein a width of the reflection area (RA) of the multiple first electrodes (CE1) in the multiple subpixels (SP) in the third display area (AA3) gradually increases or decreases as a column of the matrix structure increases, and wherein a width of the reflection area (RA) of the multiple first electrodes (CE1) in the multiple subpixels in the sixth display area (AA6) gradually increases or decreases as a row of the matrix structure increases. [17] Display device according to claim 16, wherein the widths of reflection areas (RA) of the multiple first electrodes (CE1) in the multiple subpixels in the first display area (AA1), in the second display area (AA2), in the fourth display area (AA5) and in the fifth display area (AA6) are equal.

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