Semiconductor device and method for manufacturing the same

Abstract

A semiconductor substrate comprises a p-type substrate region, a buried n-type layer on the p-type substrate region, and a p-type semiconductor layer on top of the buried n-type layer. A DTI region is formed in a trench that penetrates the p-type semiconductor layer and the buried n-type layer, reaching the p-type substrate region. A plurality of corrugations forms on one side face of the trench. The size of each plurality of first corrugations formed on the side face of the trench in the p-type semiconductor layer is larger than the size of each plurality of second corrugations formed on the side face of the trench in the buried n-type layer.

Description

CROSS-REFERENCE TO RELATED REGISTRATIONS

[0001] The disclosure of Japanese patent application No. 2024-163928, filed on September 20, 2024, including the description, drawings and abstract, is incorporated herein by reference in its entirety. BACKGROUND

[0002] The present invention relates to a semiconductor device and a method for manufacturing the same and can be suitably used for a semiconductor device containing a DTI area and a method for manufacturing the same.

[0003] The techniques listed below will be revealed.

[0004] [Patent Document 1] Japanese Disclosure Document No. 2011-66067

[0005] Patent document 1 discloses a semiconductor device with a DTI structure. SUMMARY

[0006] It is also desirable to improve the performance of a semiconductor device with a DTI area.

[0007] Further problems and novel features will become apparent from the description of this application and the attached drawings.

[0008] According to one embodiment, a semiconductor device comprises a semiconductor substrate and an element isolation region. The semiconductor substrate comprises a substrate region of a first conductivity type, a first semiconductor layer of a second conductivity type formed on the substrate region, and a second semiconductor layer of the first conductivity type formed on the first semiconductor layer. The element isolation region is formed in a trench that penetrates the second semiconductor layer and the first semiconductor layer and reaches the substrate region. Each size of the plurality of first corrugations ("scallops") formed on a side face of the trench in the second semiconductor layer is larger than each size of the plurality of second corrugations formed on a side face of the trench in the first semiconductor layer.

[0009] According to one embodiment, the performance of the semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a cross-sectional view of a main section of a semiconductor device of one embodiment. Fig. Figure 2 is a cross-sectional view of a main section during a manufacturing step of the semiconductor device of the embodiment. Fig. Figure 3 is a cross-sectional view of a main section during a manufacturing step of the semiconductor device according to Fig. 2. Fig. Figure 4 is a cross-sectional view of a main section during a manufacturing step of the semiconductor device according to Fig. 3. Fig. Figure 5 is a cross-sectional view of a main section during a manufacturing step of the semiconductor device according to Fig. 4. Fig. Figure 6 is a cross-sectional view of a main section during a manufacturing step of the semiconductor device according to Fig. 5. Fig. Figure 7 is a cross-sectional view of a main section during a manufacturing step of the semiconductor device according to Fig. 6. Fig. Figure 8 is a cross-sectional view of a main section during a manufacturing step of the semiconductor device according to Fig. 7. Fig. Figure 9 is a cross-sectional view of a main section during a manufacturing step of the semiconductor device according to Fig. 8. Fig. Figure 10 is a cross-sectional view of a main section during a manufacturing step of the semiconductor device according to Fig. 9. Fig. Figure 11 is a cross-sectional view of a main section during a manufacturing step of the semiconductor device according to Fig. 10. Fig. Figure 12 is a cross-sectional view of a main section during a manufacturing step of the semiconductor device according to Fig. 11. Fig. Figure 13 is a process flow diagram showing part of the manufacturing step of the semiconductor device of the embodiment. Fig. Figure 14 is an explanatory diagram of a trench formation step. Fig. Figure 15 is an explanatory diagram of the trench formation step. Fig. Figure 16 is an explanatory diagram of the trench formation step. Fig. Figure 17 is an explanatory diagram of the trench formation step. Fig. Figure 18 is an explanatory diagram of the trench formation step. Fig. Figure 19 is an explanatory diagram of the trench formation step. Fig. Figure 20 is an explanatory diagram of the trench formation step. Fig. Figure 21 is an explanatory diagram of the trench formation step. Fig. Figure 22 is an explanatory diagram of the trench formation step. Fig. Figure 23 is an explanatory diagram of the trench formation step. Fig. Figure 24 is a partially enlarged cross-sectional view of a part of Fig. 7. Fig. Figure 25 is a partially enlarged cross-sectional view of a part of Fig. 1. Fig. Figure 26 is a cross-sectional view of a main section during a manufacturing step of a semiconductor device of an investigated example. Fig. Figure 27 is a cross-sectional view of a main section during a manufacturing step of the semiconductor device of the example under investigation. Fig. Figure 28 is a cross-sectional view of a main section during a manufacturing step of the semiconductor device of the example under investigation. Fig. 27. Fig. Figure 29 is a partially enlarged cross-sectional view of a part of Fig. 8. Fig. Figure 30 is a partially enlarged cross-sectional view of a part of Fig. 1. Fig. Figure 31 is a graph showing the correlation between the size of the ripples and the leakage current. Fig. Figure 32 is a graph showing the correlation between the size of the ripples and the sidewall resistance of the DTI area. Fig. Figure 33 is a top view showing a test pattern for measuring the sidewall resistance of the DTI area. DETAILED DESCRIPTION

[0010] In the following embodiments, for the sake of simplicity, the description may, if necessary, be divided into a multitude of sections or embodiments, but unless expressly stated otherwise, they are not unrelated to one another, and one is related to another as part or all of a modified example, detail, supplementary explanation, etc. Also, in the following embodiments, where reference is made to the number of elements, etc. (including counts, numerical values, quantities, ranges, etc.), unless expressly stated otherwise, and which is in principle clearly limited to a specific number, it is not limited to that specific number and may be more or less than that specific number. Furthermore, in the following embodiments, the constituent elements (including element steps, etc.)) not necessarily essential unless expressly stated otherwise and which is clearly considered essential in principle. Similarly, in the following embodiments, when reference is made to the shapes, positional relationships, etc. of components, unless expressly stated otherwise and which is clearly not considered essential in principle, it is assumed that they include those which are substantially approximate or similar to the shapes, etc. The same applies to the preceding numerical values ​​and ranges.

[0011] The embodiments are described in detail below with reference to the drawings. In all drawings illustrating the embodiments, elements with the same functions are designated with the same reference numerals, and repetitive descriptions of these elements are omitted. Similarly, descriptions of identical or similar parts are generally not repeated in the following embodiments, unless specifically necessary.

[0012] In the drawings used in the embodiments, hatching can be omitted even in the case of cross-sectional views to make the drawings easier to read. Hatching can also be used in the case of top views to make the drawing easier to read.

[0013] The term "top view" refers to a view from a plane that is essentially parallel to the main surface or back surface of a semiconductor substrate 1. The terms "bottom surface" and "top surface" have the same meaning. DESIGN STRUCTURE OF THE SEMICONDUCTOR DEVICE

[0014] The semiconductor device of the embodiment is described with reference to Fig. 1 described.

[0015] As in Fig. As shown in Figure 1, the semiconductor device of the embodiment comprises a semiconductor substrate 1, a Zener diode 2, an STI area 3, a DTI area 5, an insulating film IL, a plurality of plugs (contact plugs) PG and a plurality of wiring M1.

[0016] As in Fig. As shown in Figure 1, the semiconductor substrate 1 comprises a p-type substrate region SB, a buried n-type layer BL formed on the p-type substrate region SB, and a p-type semiconductor layer EP formed on the buried n-type layer BL.

[0017] The p-type substrate region SB consists of single-crystal p-type silicon doped with p-type impurities such as boron (B). The thickness of the p-type substrate region SB is nearly uniform. The buried n-type layer BL is an n-type semiconductor layer. The buried n-type layer BL consists of single-crystal n-type silicon formed on the p-type substrate region SB. The thickness of the buried n-type layer BL is nearly uniform. The p-type semiconductor layer EP consists of single-crystal p-type silicon formed on the buried n-type layer BL. The buried n-type layer BL and the p-type substrate region SB are in contact with each other. The p-type semiconductor layer EP and the buried n-type layer BL are in contact with each other.

[0018] The p-type substrate region SB can have a laminated structure consisting of a p-type substrate body, which is made up of a single-crystal p-type silicon substrate, and a p-type semiconductor layer formed on the p-type substrate body. In this case, the p-type impurity concentration of the p-type semiconductor layer on the p-type substrate body is lower than the p-type impurity concentration of the p-type substrate body, and the p-type impurity concentration of the p-type semiconductor layer EP on the buried n-type layer BL is lower than the p-type impurity concentration of the p-type substrate body.

[0019] The main surface of semiconductor substrate 1 is equivalent to the main surface of the p-type semiconductor layer EP. Furthermore, the back surface of semiconductor substrate 1 is equivalent to the back surface of the p-type substrate region SB. The main surface and back surface of semiconductor substrate 1 are located on opposite sides of each other.

[0020] The STI region 3 (Shallow Trench Isolation) consists of an insulating film buried in a trench formed in the semiconductor substrate 1. The DTI region 5 (Deep Trench Isolation) consists of an insulating film buried in a trench 4 formed in the insulating film IL on the semiconductor substrate 1 and within the semiconductor substrate 1 itself. The bottom surface of the DTI region 5 is in contact with the bottom surface of trench 4, and the side surface of the DTI region 5 is in contact with the side surface of trench 4. Therefore, the depth of the bottom surface of the DTI region 5 is the same as the depth of the bottom surface of trench 4. Both the STI region 3 and the DTI region 5 can be considered isolation regions.

[0021] The bottom surface of STI region 3 is shallower than the bottom surface of the p-type semiconductor layer EP. The bottom surface of DTI region 5 is deeper than the bottom surface of STI region 3. Trench 4 and DTI region 5 within trench 4 penetrate the insulating film IL, STI region 3, the p-type semiconductor layer EP, and the buried n-type layer BL, reaching the p-type substrate region SB. The bottom surface of trench 4 is deeper than the bottom surface of the buried n-type layer BL, and therefore the bottom surface of DTI region 5 is also deeper than the bottom surface of the buried n-type layer BL. Trench 4 and DTI region 5 within trench 4 do not penetrate the p-type substrate region SB. Part of the p-type substrate area SB exists below the bottom surface of trench 4. The DTI area 5 functions as an element isolation area.

[0022] In the case of Fig. In the following cases, the trench 4 and the DTI region 5 penetrate the insulating film IL. Part of the DTI region 5 is located within the insulating film IL, and another part of the DTI region 5 is located within the semiconductor substrate 1. The trench 4 can also be formed within the semiconductor substrate 1 without penetrating the insulating film IL. In this case, the DTI region 5 is embedded within the trench 4 in the semiconductor substrate 1, and the elevation of the upper surface of the DTI region 5 is almost the same as the elevation of the main surface of the semiconductor substrate 1.

[0023] The Zener diode 2 comprises a p-type trough region PW, a p-type semiconductor region AD, an n-type semiconductor region CD, and a p-type semiconductor region PR. In a top view, the Zener diode 2 is surrounded by the DTI region 5.

[0024] The p-type trough region PW, the p-type semiconductor region AD, the n-type semiconductor region CD, and the p-type semiconductor region PR are formed in the p-type semiconductor layer EP. Specifically, the p-type trough region PW is formed in the upper part of the p-type semiconductor layer EP, and the p-type semiconductor regions AD, CD, and PR are formed in the p-type trough region PW.

[0025] The n-type semiconductor region CD is in contact with the main surface of the semiconductor substrate 1 and extends to a predetermined depth from the main surface of the semiconductor substrate 1. The n-type semiconductor region CD functions as the n-type cathode region of the Zener diode 2.

[0026] The p-type semiconductor region AD is located beneath the n-type semiconductor region CD. The base area of ​​the p-type semiconductor region AD is shallower than the base area of ​​the p-type trough region PW. A portion of the p-type trough region PW extends beneath the base area of ​​the p-type semiconductor region AD. The p-type impurity concentration in the p-type semiconductor region AD is higher than the p-type impurity concentration in the p-type trough region PW. A portion of the p-type semiconductor layer EP (p-type semiconductor region) extends beneath the base area of ​​the p-type trough region PW. The p-type impurity concentration in the p-type trough region PW is higher than the p-type impurity concentration in the p-type semiconductor layer EP beneath the p-type trough region PW.

[0027] In a direction from the main surface to the back surface of the semiconductor substrate 1, the n-type semiconductor region CD and the p-type semiconductor region AD are in contact with each other, and a PN junction is formed between the n-type semiconductor region CD and the p-type semiconductor region AD.

[0028] A planar dimension (planar area) of the p-type semiconductor region AD is smaller than a planar dimension (planar area) of the n-type semiconductor region CD.

[0029] The central part of the base surface of the n-type semiconductor region CD is in contact with the p-type semiconductor region AD, and the outer peripheral part of the base surface of the n-type semiconductor region CD is in contact with the p-type trough region PW. Therefore, a PN junction is also formed between the n-type semiconductor region CD and the p-type trough region PW. The side and base surfaces of the p-type semiconductor region AD are covered by the p-type trough region PW.

[0030] The p-type semiconductor region, comprising the p-type semiconductor region AD and the p-type trough region PW, functions as the p-type anode region of Zener diode 2. The PN junction formed at the interface between the n-type cathode region and the p-type anode region is configured by the PN junction between the n-type semiconductor region CD and the p-type semiconductor region AD, and by the PN junction between the n-type semiconductor region CD and the p-type trough region PW. In a top view, the PN junction between the n-type semiconductor region CD and the p-type semiconductor region AD is surrounded by the PN junction between the n-type semiconductor region CD and the p-type trough region PW.

[0031] Since the p-type impurity concentration of the p-type semiconductor region AD is higher than the p-type impurity concentration of the p-type trough region PW, the breakdown of Zener diode 2 occurs at the PN junction between the n-type semiconductor region CD and the p-type semiconductor region AD. Therefore, the breakdown voltage of Zener diode 2 is determined by the PN junction between the n-type semiconductor region CD and the p-type semiconductor region AD.

[0032] The p-type semiconductor region PR is in contact with the main surface of the semiconductor substrate 1 and extends to a predetermined depth from the main surface of the semiconductor substrate 1. The depth of the base surface of the p-type semiconductor region PR is shallower than the depth of the base surface of the p-type trough region PW. A portion of the p-type trough region PW exists below the base surface of the p-type semiconductor region PR. The p-type impurity concentration in the p-type semiconductor region PR is higher than the p-type impurity concentration in the p-type trough region PW.

[0033] In a top view, the p-type semiconductor region PR does not overlap the n-type semiconductor region CD. For example, in a top view, the p-type semiconductor region PR surrounds the n-type semiconductor region CD. In a top view, the STI region 3 is located between the n-type semiconductor region CD and the p-type semiconductor region PR.

[0034] A back electrode (not shown) can be formed on the back surface of the semiconductor substrate 1. A ground potential can, for example, be supplied from the back electrode to the substrate region SB.

[0035] Next, the structure above the semiconductor substrate 1 will be described.

[0036] The insulating film IL is formed on the main surface of the semiconductor substrate 1. The insulating film IL is formed, for example, from a laminated film of a silicon nitride film and a silicon oxide film. A plurality of contact holes are formed in the insulating film IL, and a plurality of conductive connectors PG are formed in the plurality of contact holes. The plurality of connectors PG includes a connector PGA and a connector PGC. The connector PGA is located on the p-type semiconductor area PR and is electrically connected to the p-type semiconductor area PR. The connector PGC is located on the n-type semiconductor area CD and is electrically connected to the n-type semiconductor area CD.

[0037] A metal silicide layer (not shown) can also be formed on the n-type semiconductor region CD and the p-type semiconductor region PR. In this case, connector PGC is electrically connected to the n-type semiconductor region CD via the metal silicide layer on the n-type semiconductor region CD. Connector PGA is electrically connected to the p-type semiconductor region PR via the metal silicide layer on the p-type semiconductor region PR.

[0038] A multitude of wires M1 are formed on the insulating film IL. These wires comprise an anode wiring M1A and a cathode wiring M1C. The cathode wiring M1C is electrically connected to the n-type semiconductor area CD via connector PGC. A cathode potential is supplied from the cathode wiring M1C, via connector PGC, to the n-type cathode area of ​​Zener diode 2. The anode wiring M1A is electrically connected to the p-type semiconductor area PR via connector PGA and is further connected, via the p-type semiconductor area PR, to the p-type trough area PW. An anode potential is supplied from the anode wiring M1A, via connector PGA, to the p-type anode area of ​​Zener diode 2. The cathode wiring M1C and the anode wiring M1A are not connected to each other and are isolated from one another.

[0039] The representation and description of the structure formed above the insulating film IL and the multitude of wiring M1 have been omitted.

[0040] The n-type and p-type cathode regions of Zener diode 2 are formed in the p-type semiconductor layer EP, which is surrounded by the DTI region 5 and the buried n-type layer BL. Therefore, Zener diode 2, formed in the semiconductor substrate 1, can be electrically isolated from other semiconductor elements formed in the semiconductor substrate 1.

[0041] By forming the Zener diode 2 in the p-type semiconductor substrate EP, surrounded by the DTI region 5 and the buried n-type layer BL, a parasitic NPN transistor and a parasitic PNP transistor can be formed in the semiconductor substrate SB. The parasitic NPN transistor has an n-type emitter region formed from the n-type semiconductor region CD, a p-type base region formed from the p-type semiconductor region AD, the p-type semiconductor region PR, and the p-type trough region PW, and an n-type collector region formed from the buried n-type layer BL.The parasitic PNP transistor has a p-type emitter region formed from the p-type substrate region SB, an n-type base region formed from the n-type buried layer BL, and a p-type collector region formed from the p-type semiconductor region AD, the p-type semiconductor region PR, and the p-type trough region PW. A parasitic thyristor can be formed from the parasitic NPN transistor and the parasitic PNP transistor.

[0042] The case in which the Zener diode 2 is formed as a semiconductor element in the p-type semiconductor layer EP, surrounded by the DTI region 5 and the buried n-type layer BL, has been described. There may also be cases in which semiconductor elements other than the Zener diode 2 are formed in the p-type semiconductor layer EP, surrounded by the DTI region 5 and the buried n-type layer BL. MANUFACTURING STEP OF A SEMICONDUCTOR DEVICE

[0043] As in Fig. As shown in Figure 2, the semiconductor substrate 1 is fabricated with the p-type substrate region SB, the n-type buried layer BL on the p-type substrate region SB, and the p-type semiconductor layer EP on the buried n-type layer BL. The thickness of the p-type semiconductor layer EP is, for example, 3 micrometers or more and 6 micrometers or less. The thickness of the buried n-type layer BL is, for example, 4 micrometers or more and 7 micrometers or less.

[0044] For example, the buried n-type layer BL can be formed by ion implantation in the surface layer region of a p-type silicon substrate, and then the p-type semiconductor layer EP can be formed on the buried n-type layer BL using an epitaxial growth process. In this case, the p-type silicon substrate beneath the buried n-type layer BL corresponds to the p-type substrate region SB. An epitaxial wafer can also be used instead of the p-type silicon substrate mentioned above. The epitaxial wafer has a p-type silicon substrate body and a p-type semiconductor layer formed on the p-type silicon substrate body.

[0045] Next, as in Fig. Figure 3 shows the STI area 3 formed using the STI method.

[0046] After forming a trench on the main surface of the semiconductor substrate 1, an insulating film, consisting of a silicon oxide film or the like, is formed on the main surface of the semiconductor substrate 1 to fill the trench. The insulating film located outside the trench is then removed using a process such as CMP (chemical-mechanical polishing). This allows the formation of the STI region 3, which is formed from the insulating film buried in the trench.

[0047] Next, as in Fig. Figure 4 shows the p-type trough region PW, the p-type semiconductor region AD, the n-type semiconductor region CD, and the p-type semiconductor region PR being formed in the p-type semiconductor layer EP using ion implantation or the like. The formation order of the p-type trough region PW, the p-type semiconductor region AD, the n-type semiconductor region CD, and the p-type semiconductor region PR can be selected as needed.

[0048] Next, as in Fig. Figure 5 shows the formation of the insulating film IL on the main surface of the semiconductor substrate 1 using a process such as CVD (chemical vapor deposition). After the formation of the insulating film IL, the upper surface of the insulating film IL can be polished and flattened using a process such as CMP.

[0049] Next, as in Fig. Figure 5 shows a photoresist pattern RP1 formed on the insulating film IL using photolithography technology.

[0050] Next, as in Fig. Figure 6 shows that the trench 4 is formed by etching the insulating film IL and the STI area 3 using the photoresist pattern RP1 as an etching mask. This etching step is referred to as the etching step of Fig. 6 is designated.

[0051] In the etching step of Fig. In step 6, the trench 4 is formed to penetrate the insulating film IL and the STI region 3, and the semiconductor substrate 1 (p-type semiconductor layer EP) acts as an etch stopper. Therefore, the etching step comprises Fig. 6. One step of etching the insulating film IL and one step of etching the STI region 3. The step of etching the STI region 3 is performed under conditions where the etch rate of the semiconductor substrate 1 (p-type semiconductor layer EP) is lower than the etch rate of the STI region 3. As a result, in the etching step of Fig. 6. The semiconductor substrate 1 (p-type EP semiconductor layer) is barely etched. At the end of the etching step of Fig. 6. The side surfaces of the trench 4 are configured by the insulating film IL and the STI area 3, the bottom surface of the trench 4 is configured by the semiconductor substrate 1 (p-type semiconductor layer EP), and the depth of the bottom surface of the trench 4 is almost the same as the depth of the surface of the semiconductor substrate 1 (p-type semiconductor layer EP) under the STI area 3. The side surfaces of the trench 4 are aligned with the side surfaces of an opening OP1 of the photoresist pattern RP1.

[0052] Next, as in Fig. Figure 7 shows that, using the photoresist pattern RP1 as an etching mask, the semiconductor substrate 1 (p-type semiconductor layer EP, n-type buried layer BL, and p-type substrate region SB), exposed by trench 4, is etched to deepen trench 4. This etching step is referred to as the etching step of Fig. 7 is designated.

[0053] By performing the etching step of Fig. In step 7, the trench 4 penetrates the p-type semiconductor layer EP and the buried n-type layer BL to reach the p-type substrate region SB. At the end of the etching step of Fig. Trench 4 penetrates the insulating film IL, the STI region 3, the p-type semiconductor layer EP, and the buried n-type layer BL to reach the p-type substrate region SB, and the bottom surface of trench 4 is deeper than the bottom surface of the buried n-type layer BL. However, trench 4 does not penetrate the p-type substrate region SB. The bottom surface of trench 4 is located at the midpoint of the thickness of the p-type substrate region SB. For example, the depth from the bottom surface of the buried n-type layer BL to the bottom surface of trench 4 is approximately 6 micrometers or more and approximately 9 micrometers or less.

[0054] The etching step of Fig. 7 will be described in more detail later.

[0055] Next, as in Fig. Figure 8 shows an ion implantation of p-type impurities onto the semiconductor substrate 1, which is exposed by the trench 4. This ion implantation is schematically referred to as ion implantation IM in Figure 8. Fig. 8 shown.

[0056] In ion implantation (IM), an oblique ion implantation of p-type impurities is performed. In oblique ion implantation, the direction of incidence of the impurity ions is inclined with respect to the normal direction of the main surface of the semiconductor substrate. A region PL, in which p-type impurities are implanted into the semiconductor substrate 1 by ion implantation IM, is defined in Fig. Figure 9 shows that p-type impurities are implanted into the semiconductor substrate 1 by ion implantation (IM) from the bottom and side surfaces of the trench 4. Therefore, the region PL is formed along the bottom and side surfaces of the trench 4 in the semiconductor substrate 1.

[0057] Next, as in Fig. Figure 9 shows the photoresist pattern RP7 removed. It should be noted that the representation of the area PL is shown. Fig. 9 to Fig. 12 is omitted.

[0058] Next, as in Fig. 10 shows the DTI area 5 formed in trench 4.

[0059] After the formation of trench 4, an insulating film, consisting of a silicon oxide film or the like, is formed on the insulating film IL to fill the trench 4. The insulating film located outside the trench 4 is then removed using a CMP process or the like. This allows the formation of the DTI region 5, which consists of the insulating film buried in the trench 4. A cavity can be formed in the DTI region 5. Although the case in which the insulating film located outside the trench 4 is removed using a CMP process or the like has been described, this step can be omitted. In this case, the insulating film, which is integral with the DTI region 5, remains on the insulating film IL.

[0060] Next, as in Fig. Figure 11 shows that a plurality of contact holes penetrating the insulating film IL are formed by etching the insulating film IL using a photoresist pattern (not shown) formed on the insulating film IL as an etching mask. Subsequently, a plurality of conductive connectors PG are formed in each of the plurality of contact holes.

[0061] For example, a barrier conductor film is formed on the bottom surface of the contact hole, on the side surface of the contact hole, and on the top surface of the insulating film IL. Next, a main conductor film, made of tungsten or the like, is formed on top of the barrier conductor film to fill the contact hole.

[0062] Afterwards, the main conductor film and the barrier conductor film, which are located outside the contact hole, are removed by a CMP process or similar method. This enables the formation of the multitude of PG connectors.

[0063] Next, as in Fig. Figure 12 shows the formation of multiple wires M1 on the insulating film IL. For example, a conductive film is formed on the insulating film IL. Subsequently, by structuring the conductive film using photolithography and etching techniques, multiple wires M1 can be formed from the conductive film. Although aluminum wiring is preferred for the multiple wires M1, wiring using other metallic materials, such as tungsten wiring, can also be used. Additionally, copper wiring formed using damascene technology can also be used as the multiple wires M1.

[0064] The multitude of wiring configurations M1 includes the anode wiring M1A and the cathode wiring M1C.

[0065] The representation and description of the step of forming an insulating film and wiring on the multitude of wirings M1 have been omitted. DITCHING STEP

[0066] Trench formation step 4 is described further. Fig. Figure 13 shows a specific flow of the etching step of Fig. 7.

[0067] Fig. Figure 14 is a cross-sectional view showing the state after the etching step of Fig. 6 is completed and before the etching step of Fig. 7 is carried out. In Fig. 14 is a laminated structure formed from the STI area 3, the insulating film IL on the STI area 3, and the photoresist pattern RP1 on the insulating film IL, shown schematically as a mask layer MK. An opening OP2 of the in Fig. The mask layer MK shown in section 14 is from the opening OP1 of the photoresist pattern RP1 and the one in Fig. Trench 4, as shown in section 6, was formed. The side surfaces of opening OP2 of the in Fig. The 14 mask layers MK shown are formed by the side surfaces of the in Fig. The trench 4 shown in Figure 6 and the side faces of the opening OP1 of the photoresist pattern RP1 are configured. The opening OP2 of the mask layer MK penetrates the mask layer MK. The semiconductor substrate 1 exposed by the opening OP2 of the mask layer MK corresponds to the semiconductor substrate 1 exposed by the trench 4.

[0068] After the etching step of Fig. 6, as in Fig. As shown in Figure 15, using the mask layer MK as an etching mask, the semiconductor substrate 1 exposed by the opening OP2 of the mask layer MK (and thus the semiconductor substrate 1 exposed by the trench 4) is isotropically etched (step S1 of Fig. 13).

[0069] In the isotropic etching step of step S1, isotropic dry etching is preferably used. Isotropic dry etching can be carried out, for example, using fluorine radicals. SF6 gas can preferably be used as the etching gas in step S1. The isotropic etching step of step S1 is carried out under conditions where the etch rate of the semiconductor substrate 1 is greater than the etch rate of the mask layer MK.

[0070] In the isotropic etching step of step S1, etching occurs not only along the depth direction but also along the sides. The depth direction is orthogonal to the main face of the semiconductor substrate 1 and extends from the main face to the back face of the semiconductor substrate 1. The isotropic etching step of step S1 creates a removal region 4a in the semiconductor substrate 1. The removal region 4a is, for example, a conchoidal or shell-shaped corrugation. The removal region 4a configures part of the trench 4. The bottom area of ​​the removal region 4a corresponds to the bottom area of ​​the trench 4. In plan view, the planar dimension (planar area) of the removal region 4a is larger than the planar dimension of the opening OP2 of the mask layer MK.

[0071] Next, as in Fig. 16 shown, a protective film DP formed (step S2 of Fig. 13).

[0072] In the protective film formation step of step S2, the protective film DP is formed on the top surface of the mask layer MK, on ​​the side surface of the opening OP2 of the mask layer MK, and on the surface of the semiconductor substrate 1 exposed by the trench 4. Therefore, the protective film DP is formed on the side and bottom surfaces of the trench 4. In the protective film formation step of step S2, the protective film DP can be formed, for example, using fluorocarbon radicals. For example, the protective film DP can be formed (deposited) using C4F8 gas.

[0073] Next, as in Fig. 17 shows, using the mask layer MK as an etching mask, the protective film DP is anisotropically etched (step S3 of Fig. 13).

[0074] In the anisotropic etching step of step S3, anisotropic dry etching is used. This anisotropic dry etching can be performed, for example, using fluorine-based ions. Preferably, SF6 gas can be used as the etching gas in the anisotropic etching step of step S3.

[0075] In the anisotropic etching step of step S3, the portion of the protective film DP on the lower surface of trench 4, which overlaps the opening OP2 of the mask layer MK in plan view, is removed, creating an opening OP3 in the protective film DP. The semiconductor substrate 1 is exposed through the opening OP3 of the protective film DP. The opening OP3 of the protective film DP is formed on the lower surface of trench 4. In plan view, the planar dimension (planar area) of the removal region of the protective film DP is approximately equal to or slightly smaller than the planar dimension of the opening OP2 of the mask layer MK. Therefore, in plan view, the planar dimension of the opening OP3 of the protective film DP is smaller than the planar dimension of the removal region 4a.

[0076] Next, as in Fig. Figure 18 shows that, using the mask layer MK and the protective film DP as an etching mask, the semiconductor substrate 1, exposed by the opening OP3 of the protective film DP, is isotropically etched (step S4 in Fig. 13).

[0077] In the isotropic etching step of step S4, isotropic dry etching is preferably used. Isotropic dry etching can be carried out, for example, using fluorine radicals. SF6 gas can preferably be used as the etching gas in the isotropic etching step of step S4. The isotropic etching step of step S4 is carried out under conditions where the etch rate of the semiconductor substrate 1 is greater than the etch rate of the protective film DP.

[0078] In the isotropic etching step of step S4, since the semiconductor substrate 1, which is exposed through the opening OP3 of the protective film DP, is etched isotropically, not only does etching occur along the depth direction, but also lateral etching in the semiconductor substrate 1. The isotropic etching step of step S4 leads to the formation of a distance region 4b in the semiconductor substrate 1. Distance region 4b is located below distance region 4a. Distance region 4b is, for example, a conch-shaped or shell-shaped corrugation.

[0079] The removal area 4b configures a part of trench 4. The floor area of ​​removal area 4b corresponds to the floor area of ​​trench 4. In plan view, the planar dimension of removal area 4b is larger than the planar dimension of opening OP3 of the protective film DP and also larger than the planar dimension of opening OP2 of the mask layer MK.

[0080] Next, as in Fig. 19 shown, the protective film DP removed (step S5 in Fig. 13).

[0081] Then the protective film formation step of step S2, the anisotropic etching step of step S3, the isotropic etching step of step S4 and the protective film removal step of step S5 are repeated as a cycle for a multitude of cycles.

[0082] That is, as in Fig. As shown in step 20, the protective film DP is formed (step S2 in Fig. 13). The protective film DP is formed on the side and bottom surfaces of trench 4.

[0083] Next, as in Fig. 21 shows, using the mask layer MK as an etching mask, the protective film DP is anisotropically etched (step S3 in Fig. 13) The anisotropic etching step of step S3 forms the opening OP3 in the protective film DP and exposes the semiconductor substrate 1 through the opening OP3 of the protective film DP. The opening OP3 of the protective film DP is formed on the lower surface of the trench 4.

[0084] Next, as in Fig. Figure 22 shows that, using the mask layer MK and the protective film DP as an etching mask, the semiconductor substrate 1, exposed by the opening OP3 of the protective film DP, is isotropically etched (step S4 in Fig. 13) The isotropic etching step of step S4 leads to the formation of a removal region 4c in the semiconductor substrate 1. The removal region 4c is located below the removal region 4b. The removal region 4c is, for example, a conch-shaped or shell-shaped corrugation. The removal region 4c configures part of the trench 4, and the bottom area of ​​the removal region 4c corresponds to the bottom area of ​​the trench 4.

[0085] Next, as in Fig. 23 shown, the protective film DP removed (step S5 in Fig. 13).

[0086] Each time steps S2, S3, S4, and S5 are repeated, the depth of trench 4 gradually increases. Steps S2, S3, S4, and S5 are repeated until trench 4 penetrates the p-type semiconductor layer EP and the buried n-type layer BL to reach the p-type substrate region SB. DITCH 4 AND DTI AREA 5

[0087] Fig. 24 and Fig. Figure 25 shows the X, Y, and Z directions. The X, Y, and Z directions are orthogonal to each other. The X and Y directions are approximately parallel to the main surface of the semiconductor substrate, and the Z direction is approximately orthogonal to the main surface of the semiconductor substrate. Therefore, the Z direction is parallel to the depth direction. Fig. 24 and

[0088] Fig. Figure 25 shows a cross-section parallel to the X and Z directions and orthogonal to the Y direction. The one in Fig. Trench 4, shown in Figure 24, extends in the Y direction. The X direction is the latitude direction of the trench. Fig. 24 shown trench 4.

[0089] In the semiconductor substrate 1, the trench 4 is formed by connecting a multitude of distance regions of the semiconductor substrate 1, such as the distance regions 4a, 4b and 4c mentioned above, in the Z-direction. Therefore, as in Fig. 24 and Fig. Figure 25 shows a plurality of corrugations 6 formed on the side surface of the trench 4 in the semiconductor substrate 1. The plurality of corrugations 6 are connected in the Z direction.

[0090] The corrugation 6, for example, has a shell-shaped or bowl-shaped curved surface form or an inverted conical shape, and a projection (convex section) 7 exists at the boundary between the plurality of corrugations 6. The projection 7 is a section where the side surface of the trench 4 projects locally inward. Each projection 7 extends in a direction approximately orthogonal (horizontal direction) to the Z-direction along the side surface of the trench 4. The in Fig. 24 and Fig. The 25 projections 7 shown project in the X direction and extend in the Y direction along the side surface of the trench 4. Since the plurality of corrugations 6 is connected in the Z direction, the plurality of projections 7, which extend in the Y direction along the side surface of the trench 4, are arranged periodically in the Z direction.

[0091] The reason why the multitude of corrugations 6 are formed is that the etching of the semiconductor substrate 1 during the formation of the trench 4 is mainly carried out by the isotropic etching step of step S4. A corrugation 6 is formed by the removal region of the semiconductor substrate 1, which is generated in an isotropic etching step of step S4. For example, as in Fig. As shown in Figure 23, a ripple 6a is formed through the side surface of the distance region 4a, a ripple 6b is formed below the ripple 6a through the side surface of the distance region 4b, and a ripple 6c is formed below the ripple 6b through the side surface of the distance region 4c. A projection 7a is formed at the boundary between the ripple 6a and the ripple 6b, and a projection 7b is formed at the boundary between the ripple 6b and the ripple 6c. The number of ripples 6, corresponding to the number of cycles of the repetition steps S2, S3, S4, and S5, is stacked in the Z-direction.

[0092] Fig. 23, Fig. 24 and Fig. Figure 25 shows the size L1 of the corrugation 6. The size L1 of the corrugation 6 corresponds to the distance between the tip of the projection 7 and the bottom of the corrugation 6 in the lateral (X-direction) of the trench 4. The bottom of each corrugation 6 corresponds to the part furthest from the center of the trench 4 in the lateral (X-direction) of the trench 4. Therefore, the size L1 of the corrugation 6 indicates the size of the unevenness (step) on the side surface of the trench 4 caused by the corrugation 6. A larger size L1 of the corrugation 6 indicates a larger unevenness (step) caused by the corrugation 6. The size L1 of the corrugation 6 can be controlled by factors such as the amount of etch in the isotropic etching step of step S4. The larger the etch quantity of the semiconductor substrate 1 in the isotropic etching step of step S4 (etch quantity in the Z direction), the larger the size L1 of the corrugation 6.

[0093] Trench 4 penetrates the p-type semiconductor layer EP and the buried n-type layer BL to reach the p-type substrate region SB. Therefore, the side face of trench 4 comprises the side face of trench 4 formed in the p-type semiconductor layer EP, the side face of trench 4 formed in the buried n-type layer BL, and the side face of trench 4 formed in the p-type substrate region SB. The side face of trench 4 formed in the p-type semiconductor layer EP is continuous with the side face of trench 4 formed in the buried n-type layer BL, and the side face of trench 4 formed in the buried n-type layer BL is continuous with the side face of trench 4 formed in the p-type substrate region SB.

[0094] Here, the corrugation 6 formed on the side face of trench 4 in the p-type semiconductor layer EP is designated as corrugation 6d, the corrugation 6 formed on the side face of trench 4 in the buried n-type layer BL is designated as corrugation 6e, and the corrugation 6 formed on the side face of trench 4 in the p-type substrate region SB is designated as corrugation 6f. The size L1 of corrugation 6d is designated as size L1d, the size L1 of corrugation 6e is designated as size Lle, and the size L1 of corrugation 6f is designated as size L1f.The protrusion 7 formed on the side face of the trench 4 in the p-type semiconductor layer EP is designated as a protrusion 7d, the protrusion 7 formed on the side face of the trench 4 in the buried n-type layer BL is designated as a protrusion 7e, and the protrusion 7 formed on the side face of the trench 4 in the p-type substrate region SB is designated as a protrusion 7f.

[0095] Preferably, the size L1d of the corrugation 6d is larger than the size L1e of the corrugation 6e. Preferably, the size L1f of the corrugation 6f is larger than the size L1e of the corrugation 6e. The reason for this will be explained in detail later.

[0096] The corrugation 6d is formed by isotropic etching of the p-type semiconductor layer EP in the isotropic etching step of step S4. The corrugation 6e is formed by isotropic etching of the buried n-type layer BL in the isotropic etching step of step S4. The corrugation 6f is formed by isotropic etching of the p-type substrate region SB in the isotropic etching step of step S4. BACKGROUND OF THE INVESTIGATION

[0097] The example under investigation, which is considered by the inventor of the present invention, is described with reference to Fig. 26 to Fig. 28 described.

[0098] Fig. Figure 26 shows a state in which a trench 104 for a DTI region is formed in the semiconductor substrate 1. The trench 104 is formed by anisotropic etching of the p-type semiconductor layer EP, the buried n-type layer BL, and the p-type substrate region SB. Therefore, the corrugation 6 mentioned above is not formed on the side surface of the trench 104.

[0099] In the trench 104 formation step, if the buried BL layer is etched with n-type semiconductors, there is a risk that etch residues containing n-type impurities may adhere to the side face of trench 104 in the p-type semiconductor layer EP. As a result of these etch residues containing n-type impurities, there is a risk that an n-type semiconductor region NR may form in the p-type semiconductor layer EP along the side face of trench 104, as shown in Fig. 27 shown.

[0100] If the n-type semiconductor region NR is formed in the p-type semiconductor layer EP along the side face of trench 104, it can adversely affect the operation of semiconductor devices (such as the Zener diode 2 mentioned above) formed in the p-type semiconductor layer EP. This is because the n-type semiconductor region NR can configure part of a parasitic transistor and may promote its operation. Therefore, it is desirable to prevent the formation of an unnecessary n-type semiconductor region NR in the p-type semiconductor layer EP in order to improve the performance of the semiconductor device.

[0101] Thus, after forming the trench, 104, as in Fig. Figure 28 shows the implantation of p-type impurities into the semiconductor substrate 1, which is exposed by trench 104. This ion implantation is schematically referred to as ion implantation IM101 in Figure 28. Fig. 28 shown.

[0102] The IM101 ion implantation process is an oblique ion implantation of p-type impurities. A region PL100, in which p-type impurities are implanted into the semiconductor substrate 1 by the IM101 ion implantation process, is shown in Fig. 28. The region PL100 is formed along the bottom and side surfaces of trench 104 in the semiconductor substrate 1. The region PL100 comprises a region PL101 located in the p-type semiconductor layer EP, a region PL102 located in the buried n-type layer BL, and a region PL103 located in the p-type substrate region SB.

[0103] It is desirable that the amount of p-type impurities implanted into the PL101 region by the IM101 ion implantation process be large. This is because if the amount of p-type impurities implanted into the PL101 region by the IM101 ion implantation process is small, the n-type semiconductor region NR may remain in the p-type semiconductor layer EP even after the IM101 ion implantation process. It is necessary for the conductivity type of the PL101 region to be p-type, and for this purpose, it is necessary to implant p-type impurities into the PL101 region at a higher concentration than the impurity concentration in the n-type semiconductor region NR by the IM101 ion implantation process.

[0104] On the other hand, it is desirable that the amount of p-type impurities implanted into region PL102 by ion implantation IM101 be small. This is because if the amount of p-type impurities implanted into region PL102 by ion implantation IM101 is large, there is a possibility that the conductivity type of region PL102 could become p-type. If the conductivity type of region PL102 becomes p-type, the substrate region SB and the semiconductor layer EP could become p-type through region PL102. It is necessary to prevent the substrate region SB and the semiconductor layer EP from becoming p-type through region PL102.Therefore, it is necessary to prevent the conductivity type of area PL102 from becoming p-type, and for this purpose it is desirable that the amount of p-type impurities implanted into area PL102 by ion implantation IM101 be small.

[0105] Therefore, it is desirable that the amount of p-type impurities implanted into the PL101 area by ion implantation IM101 be large, and that the amount of p-type impurities implanted into the PL102 area by ion implantation IM101 be small. However, even when the conditions of ion implantation IM101 are adjusted, it is difficult to achieve both an increase in the amount of p-type impurities implanted into the PL101 area and a decrease in the amount of p-type impurities implanted into the PL102 area. MAIN FEATURES AND EFFECTS

[0106] The semiconductor device of the embodiment has the trench 4, which penetrates the p-type semiconductor layer EP and the buried n-type layer BL and reaches the p-type substrate region SB, and the DTI region 5, which is formed in the trench 4.

[0107] One of the main features is that the plurality of corrugations 6 is formed on the side face of the trench 4, and the plurality of corrugations 6 includes the plurality of corrugations 6d, which is formed on the side face of the trench 4 in the p-type semiconductor layer EP, and the plurality of corrugations 6e, which is formed on the side face of the trench 4 in the buried n-type layer BL. The size L1d of each of the plurality of corrugations 6d is larger than the size L1e of each of the plurality of corrugations 6e.

[0108] Fig. Figure 29 is a partially enlarged cross-sectional view of a part of Fig. 8. Fig. Figure 30 is a partially enlarged cross-sectional view of a part of Fig. 1, but the area PL, into which p-type impurities are implanted by ion implantation IM, is also in Fig. 30 shown.

[0109] The reason for performing ion implantation IM, which is in Fig. The reason shown in Figure 29 is the same as the reason for performing the ion implantation IM101 described above. That is, when the buried n-type BL layer is etched in the trench 4 formation step, etch residues containing n-type impurities are generated and adhere to the side face of trench 4 in the p-type semiconductor layer EP, thus creating a possibility for an n-type semiconductor region to form in the p-type semiconductor layer EP along the side face of trench 4. After trench 4 is formed, as shown in Figure 29, the n-type BL layer is etched into the p-type semiconductor layer EP. Fig. 8 and Fig. Figure 29 shows that p-type ion implantation (IM) is performed, and p-type impurities are implanted into the semiconductor substrate 1 exposed by the trench 4. During IM ion implantation, it is necessary to implant p-type impurities into the side face of the trench 4. Therefore, it is desirable to use an oblique ion implantation of p-type impurities instead of IM ion implantation.

[0110] The region PL, into which p-type impurities are implanted by ion implantation IM, is formed along the bottom and side surfaces of trench 4 in the semiconductor substrate 1. As shown in Fig. 29 and Fig. As shown in Figure 30, the region PL comprises a region PL1 located in the p-type semiconductor layer EP, a region PL2 located in the buried n-type layer BL, and a region PL3 located in the p-type substrate region SB.

[0111] By increasing the size L1d of each of the multiple corrugations 6d formed on the side face of the trench 4 in the p-type semiconductor layer EP, the amount of p-type impurities implanted into the PL1 region by ion implantation IM can be increased. The reason is as follows.

[0112] Increasing the size L1d of the corrugation 6d increases the protrusion size of protrusion 7d, and consequently, the effective area (area) of the side face of trench 4 in the p-type semiconductor layer EP can be increased. A large protrusion size of protrusion 7d increases the amount of p-type impurities implanted into the p-type semiconductor layer EP from the surface of protrusion 7d. Similarly, a large effective area (area) of the side face of trench 4 in the p-type semiconductor layer EP also increases the amount of p-type impurities implanted into the p-type semiconductor layer EP from the side face of trench 4. As a result, the amount of p-type impurities implanted into the PL1 region by ion implantation IM can be increased.

[0113] If the size L1d of the 6d corrugation is large, the probability increases that p-type impurities reflected by the 6d corrugation will be implanted into the p-type semiconductor layer EP. As a result, the amount of p-type impurities implanted into the PL1 region by ion implantation IM can be increased.

[0114] By reducing the size L1e of each of the multiple undulations 6e formed on the side surface of trench 4 in the buried n-type layer BL, the amount of p-type contaminants implanted into area PL2 by ion implantation IM can be reduced. The reason is as follows.

[0115] By reducing the size L1e of the corrugation 6e, the unevenness (steps) of the side surface of trench 4 in the buried n-type layer BL is reduced, and the flatness of the side surface of trench 4 in the buried n-type layer BL is improved. Therefore, by reducing the size L1e of the corrugation 6e, the influence of the projection 7e is reduced, and the increase in the effective area (surface area) of the side surface of trench 4 due to the corrugation 6e can be suppressed. As a result, the amount of p-type contaminants implanted into the PL2 area by ion implantation IM can be reduced.

[0116] Increasing the size L1 of corrugation 6 increases the amount of p-type impurities implanted into area PL by ion implantation IM, while decreasing the size L1 of corrugation 6 decreases the amount of p-type impurities implanted into area PL by ion implantation IM. Therefore, the size L1d of corrugation 6d is made larger than the size L1e of corrugation 6e. This allows the amount of p-type impurities implanted into area PL1 by ion implantation IM to be greater than the amount of p-type impurities implanted into area PL2 by ion implantation IM.As a result, it is possible to achieve both an increase in the amount of p-type impurities implanted into the PL1 region by ion implantation (IM) and a decrease in the amount of p-type impurities implanted into the PL2 region by ion implantation (IM). This can improve the performance of the semiconductor device.

[0117] This means that by increasing the amount of p-type impurities implanted into region PL1 via ion implantation (IM), the conductivity of region PL1 can be reliably made p-type, thus preventing the presence of unnecessary n-type semiconductor regions, such as the aforementioned n-type semiconductor region NR, within the p-type semiconductor layer EP. This prevents the operation of parasitic transistors due to unnecessary n-type semiconductor regions, such as the aforementioned n-type semiconductor region NR. Furthermore, by decreasing the amount of p-type impurities implanted into region PL2 via ion implantation (IM), it becomes easier to maintain the conductivity of region PL2 as n-type, thus precisely preventing the p-type substrate region SB and the p-type semiconductor layer EP from becoming conductive through region PL2.

[0118] Therefore, in the fabricated semiconductor device, region PL1 is a p-type semiconductor region and region PL2 is an n-type semiconductor region. Region PL1 is formed along the side face of trench 4 in the p-type semiconductor layer EP and is in contact with the DTI region 5. Region PL2 is formed along the side face of trench 4 in the buried n-type layer BL and is in contact with the DTI region 5. The p-type impurity concentration of region PL1 is preferably higher than the p-type impurity concentration of the p-type semiconductor layer EP.

[0119] The size L1 of corrugation 6 can be controlled by factors such as the etch quantity in the isotropic etching step of step S4. The etch quantity of the p-type semiconductor layer EP in step S4 (etch quantity in the Z direction) is made larger than the etch quantity of the buried n-type layer BL in step S4 if the buried n-type layer BL is etched isotropically. This allows the size L1d of corrugation 6d to be made larger than the size L1e of corrugation 6e. The etch quantity in step S4 can be controlled by factors such as the etching time in step S4. Increasing the etching time in step S4 increases the etch quantity in step S4.

[0120] The plurality of corrugations 6 formed on the side surface of the trench 4 further comprises the plurality of corrugations 6f formed on the side surface of the trench 4 in the p-type substrate region SB. Preferably, the size L1f of each plurality of corrugations 6f is larger than the size L1e of each plurality of corrugations 6e. The reason is as follows.

[0121] It is undesirable for the n-type semiconductor region NR to form within the p-type semiconductor layer EP along the side face of trench 4. This is because the n-type semiconductor region formed within the p-type semiconductor layer EP can configure part of a parasitic transistor. In comparison, the adverse effect of forming an n-type semiconductor region within the p-type substrate region SB along the side face of trench 4 is smaller.

[0122] On the other hand, reducing the size L1 of the corrugation 6 increases the time required for the etching step in Fig. 7 is required, while increasing the size L1 of the corrugation 6 reduces the time required for the etching step in Fig. 7 is required. This is because the smaller the size L1 of the corrugation 6, the more cycles of steps S2, S3, S4 and S5 are required.

[0123] Therefore, the size L1f of the corrugation 6f is made larger than the size L1e of the corrugation 6e. This allows the time required to form trench 4 in the p-type substrate region SB after penetrating the buried n-type layer BL to be suppressed. As a result, the time required for the etching step in Fig. The time required for step 7 can be reduced. Consequently, the manufacturing time of the semiconductor device can be decreased. Additionally, the throughput of the semiconductor device can be improved.

[0124] Therefore, it is preferable to increase the size L1d of corrugation 6d, decrease the size L1e of corrugation 6e, and increase the size L1f of corrugation 6f. For this reason, the size L1d of corrugation 6d is made larger than the size L1e of corrugation 6e, and the size L1f of corrugation 6f is made larger than the size L1d of corrugation 6d that is larger than the size L1e of corrugation 6e. This allows for an increase in the amount of p-type impurities implanted into region PL1 by ion implantation IM, a decrease in the amount of p-type impurities implanted into region PL2 by ion implantation IM, and a reduction in the time required for the etching step in Fig. 7 is required.

[0125] The etch quantity of the p-type substrate region SB in step S4, when the p-type substrate region SB is isotropically etched, is made larger than the etch quantity of the buried n-type layer BL in step S4, when the buried n-type layer BL is isotropically etched. This allows the size L1f of the corrugation 6f to be made larger than the size L1e of the corrugation 6e.

[0126] If the width of the trench 4 is large, it is easy to implant p-type impurities from the side face of the trench 4 into the p-type semiconductor layer EP by performing oblique ion implantation after trench 4 formation. However, if the width of the trench 4 is 1 micrometer or less, it is difficult to implant p-type impurities from the side face of the trench 4 into the p-type semiconductor layer EP by performing oblique ion implantation after trench 4 formation. By forming the plurality of corrugations 6 on the side face of the trench 4, as described above, even when the width of the trench 4 is 1 micrometer or less, the amount of p-type impurities implanted from the side face of the trench 4 into the p-type semiconductor layer EP can be increased.Therefore, the present embodiment is very effective when applied to cases where the width of the trench is 4 1 micrometer or less.

[0127] Fig. Figure 31 is a graph showing the correlation between the size L1e of the corrugation 6e and the leakage current between the p-type substrate region SB and the p-type semiconductor layer EP. The horizontal axis of the graph in Fig. 31 corresponds to the size L1e of the undulation 6e. The vertical axis of the graph in Fig. 31 corresponds to the leakage current between the p-type substrate region SB and the p-type semiconductor layer EP.

[0128] From the graph in Fig. It is evident from paragraph 31 that if the corrugation size L1e 6e is 20 nm or less, the leakage current between the p-type substrate region SB and the p-type semiconductor layer EP can be sufficiently suppressed. Therefore, it is preferred that the corrugation size L1e 6e be 20 nm or less.

[0129] The size L1e of the corrugation 6e can be controlled by the etch amount of the buried layer BL of the n-type if the buried layer BL of the n-type is etched isotropically in step S4. For example, by setting the etch amount of the buried layer BL of the n-type in step S4 (etch amount in the Z direction) to 60 nm or less, the size L1e of the corrugation 6e can be made 20 nm or less.

[0130] Fig. Figure 32 is a graph showing the correlation between the size of the corrugation and the sidewall resistance of the DTI area. The horizontal axis of the graph in Fig. 32 corresponds to the size of the ripple. The vertical axis of the graph in Fig. 32 corresponds to the sidewall resistance of the DTI area. Fig. Figure 33 is a top view showing a test pattern for measuring the sidewall resistance of the DTI area.

[0131] The in Fig. The 33 test pattern shown comprises the n-type region NW1 and the n-type region NW2 formed in the p-type semiconductor layer EP1 of a test semiconductor substrate, a connector PG1 located on the n-type region NW1, a connector PG2 located on the n-type region NW2, and a test DTI region 5a in contact with both the n-type region NW1 and the n-type region NW2. The plurality of corrugations is formed on the side surface of the trench in which the DTI region 5a is embedded. The sidewall resistance of the DTI region 5a is measured by the electrical resistance between connector PG1 and connector PG2.

[0132] If the n-type semiconductor region NR forms in the p-type semiconductor layer EP1 along the sidewall of the DTI region 5a, the n-type regions NW1 and NW2 conduct through the n-type semiconductor region NR, resulting in a lower sidewall resistance of the DTI region 5a. Conversely, if the n-type semiconductor region NR does not form in the p-type semiconductor layer EP1 along the sidewall of the DTI region 5a, no conductive path is formed along the sidewall of the DTI region 5a, resulting in a higher sidewall resistance of the DTI region 5a.

[0133] Therefore, the magnitude of the sidewall resistance of DTI region 5a can be used to assess whether the n-type semiconductor region NR is formed along the sidewall of DTI region 5a. In other words, if the sidewall resistance of DTI region 5a is large, it can be determined that the n-type semiconductor region NR is not formed along the sidewall of DTI region 5a. The absence of the n-type semiconductor region NR along the sidewall of DTI region 5a means that the n-type impurities in the n-type semiconductor region NR can be compensated for by the p-type impurities that are implanted after trenching (corresponding to the ion implantation IM mentioned above).

[0134] From the graph in Fig. Figure 32 shows that when the corrugation size is less than 20 nm, the sidewall resistance of the DTI region decreases. From the graph in Fig.Figure 32 shows that if the corrugation size is greater than 150 nm, the sidewall resistance of the DTI region decreases. If the corrugation size is 20 nm or greater and 150 nm or less, the sidewall resistance of the DTI region is high. If the corrugation size is greater than 150 nm, the protrusion 7 slightly shields the implantation of p-type impurities into the p-type semiconductor layer EP1 from the corrugation, which should lead to a decrease in the sidewall resistance of the DTI region.

[0135] Therefore, it is preferred that the size L1d of the 6d corrugation be 20 nm or more and 150 nm or less. By setting the size L1d of the 6d corrugation in the range of 20 nm or more and 150 nm or less, the amount of p-type impurities implanted into the PL1 region by ion implantation IM can be increased, thereby preventing the presence of unnecessary n-type semiconductor regions, such as the n-type semiconductor region NR along the DTI region in the p-type semiconductor layer EP.

[0136] The size L1d of the 6d corrugation can be controlled by the etch amount of the p-type semiconductor layer if the p-type semiconductor layer is isotropically etched in step S4. For example, by setting the etch amount of the p-type semiconductor layer in step S4 (etch amount in the Z direction) to 60 nm or more and 450 nm or less, the size L1d of the 6d corrugation can be set to 20 nm or more and 150 nm or less.

[0137] The invention made by the present inventor has been described in detail above on the basis of the embodiment, but the present invention is not limited to the embodiment described above, and it is needless to say that various modifications can be made without deviating from its core.

[0138] In the embodiment described above, the Zener diode 2 is formed as a semiconductor element in the p-type semiconductor layer EP, which is surrounded by the DTI region 5 and the buried n-type layer BL. When the Zener diode 2 is formed in the p-type semiconductor layer EP and the n-type semiconductor region NR is formed in the p-type semiconductor layer EP along the side face of the trench 4, the n-type semiconductor region NR configures part of a parasitic transistor and serves to promote the operation of the parasitic transistor.

[0139] In this embodiment, an n-channel LDMOSFET (Laterally Diffused Metal Oxide Semiconductor Field Effect Transistor) can also be formed as a semiconductor element in the p-type semiconductor layer EP, which is surrounded by the DTI region 5 and the buried n-type layer BL. Even if an n-channel LDMOSFET is formed in the p-type semiconductor substrate EP, surrounded by the DTI region 5 and the buried n-type layer BL, a parasitic n-channel NPN transistor and a parasitic PNP transistor are formed in the semiconductor substrate SB, potentially forming a parasitic thyristor. If an n-channel LDMOSFET is formed in the p-type semiconductor layer EP and the n-type semiconductor region NR is formed in the p-type semiconductor layer EP along the side face of trench 4, the n-type semiconductor region NR configures part of a parasitic transistor and serves to promote the operation of the parasitic transistor.It should be noted that the term LDMOSFET encompasses not only MOSFETs that use an oxide film as the gate insulating film, but also MOSFETs that use insulating films other than oxide films as the gate insulating film. Furthermore, an n-channel LDMOSFET is referred to as an n-type LDMOSFET, and a p-channel LDMOSFET is referred to as a p-type LDMOSFET.

[0140] Therefore, the described embodiment is very effective when applied to cases in which a Zener diode or an n-channel LDMOSFET (n-type LDMOSFET) is formed as a semiconductor element in the p-type semiconductor layer EP, which is surrounded by the DTI region 5 and the buried n-type layer BL. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] JP 2024-163928

[0001] JP 2011-66067

[0004]

Claims

[1] Semiconductor device comprising: a semiconductor substrate, comprising: a substrate region of a first conductivity type; a first semiconductor layer of a second conductivity type, opposite to the first conductivity type, formed on the substrate area; and a second semiconductor layer of the first conductivity type, formed on top of the first semiconductor layer; a trench that penetrates the second semiconductor layer and the first semiconductor layer and reaches the substrate region; and an element isolation area formed in the trench, where a multitude of undulations are formed on one side surface of the ditch, including the multitude of undulations: a multitude of first corrugations formed on a side face of the trench in the second semiconductor layer; and a multitude of second corrugations formed on a side surface of the trench in the first semiconductor layer, and where each size of the plurality of first waves is larger than each size of the plurality of second waves. [2] Semiconductor device according to claim 1, where a bottom surface of the trench is deeper than a bottom surface of the first semiconductor layer, wherein the multitude of undulations includes a multitude of third undulations formed on a side surface of the trench in the substrate area, and where each size of the plurality of third waves is larger than each size of the plurality of second waves. [3] Semiconductor device according to claim 1, further comprising: a semiconductor element formed in the second semiconductor layer, wherein the semiconductor element is surrounded by the element insulation region in top view. [4] Semiconductor device according to claim 3, wherein the semiconductor element is a Zener diode or an LDMOSFET of the second conductivity type. [5] Semiconductor device according to claim 4, the Zener diode includes: a trough region of the first conductivity type, which is formed in the second semiconductor layer; and a cathode region of the second conductivity type, which is formed in the trough area. [6] Semiconductor device according to claim 1, further comprising: a first semiconductor region of the first conductivity type, which is formed in the second semiconductor layer along the side surface of the trench, where the impurity concentration of the first conductivity type in the first semiconductor region is greater than the impurity concentration of the first conductivity type in the first semiconductor layer. [7] Semiconductor device according to claim 1, wherein each size of the plurality of first ripples is 20 nm or more and 150 nm or less. [8] Semiconductor device according to claim 7, wherein each size of the plurality of second waves is 20 nm or less. [9] Method for manufacturing a semiconductor device, the method comprising: (a) Manufacturing a semiconductor substrate, comprising: a substrate region of a first conductivity type; a first semiconductor layer of a second conductivity type, opposite to the first conductivity type, formed on the substrate area; and a second semiconductor layer of the first conductivity type, formed on top of the first semiconductor layer; (b) Forming a trench that penetrates the second semiconductor layer and the first semiconductor layer and reaches the substrate area; (c) following (b), performing ion implantation of impurities of the first conductivity type into the semiconductor substrate exposed by the trench; and (d) following (c), forming an element isolation area in the trench, wherein in (b) the trench is designed such that a plurality of undulations are formed on one side surface of the trench, including the multitude of undulations: a multitude of first corrugations formed on a side face of the trench in the second semiconductor layer; and a multitude of second corrugations formed on a side surface of the trench in the first semiconductor layer, and where each size of the plurality of first waves is larger than each size of the plurality of second waves. [10] Method according to claim 9, where the ion implantation in (c) is an oblique ion implantation. [11] Method according to claim 9, where a bottom surface of the trench is deeper than a bottom surface of the first semiconductor layer, wherein the multitude of undulations includes a multitude of third undulations formed on a side surface of the trench in the substrate area, and where each size of the plurality of third waves is larger than each size of the plurality of second waves. [12] Method according to claim 9, where (b) comprises a plurality of cycles, and each of the many cycles includes: (b1) Forming a protective film on the semiconductor substrate; (b2) after (b1), forming an opening in the protective film by anisotropic etching of the protective film; (b3) according to (b2), isotropic etching of the semiconductor substrate exposed by the opening in the protective film; and (b4) after (b3), removal of the protective film. [13] Method according to claim 12, where the etch quantity of the second semiconductor layer, if the second semiconductor layer is etched isotropically in (b3), is greater than the etch quantity of the first semiconductor layer, if the first semiconductor layer is etched isotropically in (b3). [14] Method according to claim 13, where a bottom surface of the trench is deeper than a bottom surface of the first semiconductor layer, wherein the multitude of undulations includes a multitude of third undulations formed on a side surface of the trench in the substrate area, and where each size of the plurality of third waves is larger than each size of the plurality of second waves. [15] Method according to claim 9, where (b) comprises a plurality of cycles, each of the many cycles includes: (b1) Forming a protective film on the semiconductor substrate; (b2) after (b1), forming an opening in the protective film by anisotropic etching of the protective film; (b3) according to (b2), isotropic etching of the semiconductor substrate exposed by the opening in the protective film; and (b4) after (b3), removal of the protective film, where the etch quantity of the second semiconductor layer, if the second semiconductor layer is etched isotropically in (b3), is greater than the etch quantity of the first semiconductor layer, if the first semiconductor layer is etched isotropically in (b3), and where the etch quantity of the substrate region, if the substrate region is etched isotropically in (b3), is greater than the etch quantity of the first semiconductor layer, if the first semiconductor layer is etched isotropically in (b3). [16] The method of claim 9, comprising: (e) Forming a semiconductor element in the second semiconductor layer, wherein the semiconductor element is surrounded by the element insulation region in top view. [17] Method according to claim 16, wherein the semiconductor element is a Zener diode or a second conductivity type LDMOSFET. [18] Method according to claim 17, the Zener diode includes: a trough region of the first conductivity type, which is formed in the second semiconductor layer; and a cathode region of the second conductivity type, which is formed in the trough area. [19] Method according to claim 9, wherein each size of the plurality of first corrugations is 20 nm or more and 150 nm or less. [20] Method according to claim 19, wherein each size of the plurality of second corrugations is 20 nm or less.

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