Co-packed optical systems incorporating optical engines, and methods for manufacturing them

Abstract

Optical engines and methods for manufacturing optical engines. In embodiments, the optical engine comprises a silicon substrate and a photonic component mounted on the silicon substrate. The photonic component has an edge coupler and a coupling interface configured to connect to one or more external optical components. The edge coupler has a photonic component edge at the coupling interface. The silicon substrate has a substrate coupling edge at the coupling interface. The photonic component edge extends beyond the substrate coupling edge at the coupling interface.

Description

BACKGROUND

[0001] Silicon photonics technology can be useful for high-speed data transmission and optical communication systems. One component in some of these optical communication systems is the edge coupler, which facilitates the efficient transmission of optical signals between silicon photonic devices within the optical communication system and external optical elements. These external elements typically include, for example, a fiber array unit (FAU) or a micro-optical lens, which can be used to guide and focus the optical signals into and out of the silicon photonic chip. Integrating an effective edge coupler can help minimize coupling losses and ensure high-performance operation of the entire optical communication system. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figures 1A - 1G illustrate an exemplary co-packed optical system comprising an optical engine of one embodiment. Fig. Figures 2A and 2B are vertical cross-sectional views of a configuration of an alternative embodiment for the optical engine. Fig. Figures 3A - 3E illustrate various intermediate structures that can be formed and used in an embodiment process for manufacturing an optical engine that may include an edge coupler. Fig. Figures 4A - 4E illustrate various intermediate structures that can be formed and used in an embodiment process for manufacturing an optical engine having an edge coupler with a silicon nitride (SiN) spot size converter. Fig. Figures 5A-5D illustrate various intermediate structures that can be formed and used in another embodiment process to manufacture an optical engine that includes an edge coupler. Fig. Figures 6A - 6D illustrate various intermediate structures that can be formed and used in another embodiment process to manufacture an optical engine that includes an edge coupler. Fig. Figures 7A - 7D illustrate elements of an optical engine of one embodiment after removal of a silicon edge. Fig. Figures 8A and 8B illustrate various intermediate structures that can be formed and used in an embodiment process for aligning an edge coupler with an exemplary optical component. Fig. Figure 9 illustrates a flowchart of an embodiment process for manufacturing an optical engine. DETAILED DESCRIPTION

[0003] The following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first structural element over or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements, such that the first and second structural elements might not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition serves the purpose of simplification and clarity and does not itself imply any relationship between the different embodiments and / or configurations discussed.

[0004] Furthermore, spatially relative terms such as "underlying," "below," "under," "superior," "above," and the like may be used herein to facilitate description of the relationship of one element or structural element to another element(s) or structural element(s), as illustrated in the figures. These spatially relative terms are intended to encompass various orientations of the component in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. Unless expressly stated otherwise, each element bearing the same reference numeral is assumed to have the same material composition and thickness within the same range of thicknesses.Various embodiments are described in detail with reference to the accompanying drawings. Where possible, the same reference numbers are used across the drawings to refer to the same or similar parts. References to specific examples and implementations are for illustrative purposes only and are not intended to limit the scope of the claims.

[0005] The fabrication of edge couplers in silicon photonics can present several technical challenges. These challenges include achieving precise alignment between the silicon waveguide and the external optical elements, as well as maintaining low insertion loss and high coupling efficiency over a wide wavelength range. Various methods have been proposed to address these problems, including conical waveguides, lattice couplers, and butt coupling techniques. However, each approach has its own set of challenges in terms of fabrication complexity, alignment tolerance, and overall coupling performance.

[0006] The proximity of the edge coupler to external optical components, such as a fiber array assembly (FAU) or a micro-optical lens system, is a factor that influences the efficiency and performance of silicon photonics systems. Positioning the edge coupler close to these components can be beneficial for minimizing optical feed loss and maximizing coupling efficiency. This close positioning results in a reduced distance, which helps ensure that the optical signal is transmitted with minimal deviation and attenuation, thus preserving signal integrity. However, achieving such proximity and tight positioning can present technical challenges, particularly regarding precise alignment and mechanical stability.

[0007] In optical engines designed for co-packed optics, a residual silicon edge may remain after the photonic integrated circuit (PIC) chip has been singulated. This residual silicon edge limits the minimum achievable distance between the edge coupler and the fiber array assembly (FAU) or micro-optical lens system. The presence of this silicon edge can adversely affect alignment precision and coupling efficiency, as it prevents the edge coupler from being positioned at optimal proximity to the external optical components.

[0008] In some embodiments, a device incorporates an edge coupler fabricated on a silicon substrate, designed to improve coupling efficiency with external optical components such as a fiber array assembly (FAU) or a micro-optical lens system. The edge coupler can be integrated into the silicon substrate by photolithography and etching processes. To achieve closer proximity to the external optical components, specific sections of the silicon substrate can be selectively removed. This removal process involves precise etching techniques that create a recess in the substrate around the edge coupler. In some embodiments, the recess can provide a space for subsequent singulation, which must be performed while maintaining a safe distance from the edge coupler.

[0009] After selective etching, the substrate can be separated to allow the edge coupler to extend beyond the physical boundary of the remaining substrate. This extension enables the edge coupler to be positioned closer to the external optical components, thereby reducing the optical path length and potential signal loss. The reduced distance between the edge coupler and the external components facilitates improved alignment and coupling efficiency, as the optical signal can be transmitted with less deviation and attenuation.

[0010] The substrate removal and singulation process can be controlled to maintain the structural integrity and alignment precision of the edge coupler. By allowing the edge coupler to protrude, the design eliminates the constraints imposed by the remaining silicon edge, which typically limits the minimum distance between the edge coupler and external optical components. This approach can improve the overall performance of the optical coupling system, making it more suitable for high-density, high-performance silicon photonics applications.

[0011] Now, the focus will shift to... Fig. Reference is made to 1A - 1F, which illustrate an exemplary co-packed optical system 102, which includes an exemplary optical engine 104.

[0012] Fig. Figure 1A is a schematic block diagram of the co-packed optical system 102. The co-packed optical system 102 comprises a printed circuit board 106 (for example, a circuit board) and an application-specific integrated circuit (ASIC) 108 (which may also be referred to as a first die 108) mounted on the printed circuit board 106. Optical engines, comprising the exemplary optical engine 104, may be arranged around the perimeter of the printed circuit board 106 or in any other suitable arrangement on the printed circuit board 106. The optical engine 104 may be configured to communicate with the ASIC 108 via electrical connections in the printed circuit board 10.

[0013] In general, co-packed optics is a technology where optical transceivers, typically used for high-speed data transmission in network applications, can be tightly integrated with at least one interchangeable ASIC on a single package or module. The printed circuit board 106 serves as the foundation for integrating various components of the co-packed optical system 102. The printed circuit board 106 provides electrical connections between the interchangeable ASIC 108, the optical engine 104, and, in some embodiments, other circuits.

[0014] The Wechsel-ASIC 108 is an integrated circuit designed to handle tasks such as switching and forwarding data packets in a network. In some embodiments, the Wechsel-ASIC 108 processes incoming and outgoing data traffic, manages data flow, and may include structural elements such as buffer and forwarding tables and network interface controls.

[0015] In some embodiments, the optical engine 104 is an optical transceiver module integrated into the co-packed optical system 102. The optical engine 104 may, for example, include components such as lasers, photodiodes, modulators, and associated circuitry for transmitting and receiving optical signals.

[0016] In some embodiments, the use of co-packed optics reduces latency by minimizing the physical distance between the optical components and the interchangeable ASIC 108, thereby improving overall network performance. By tightly integrating optics and electronics, co-packed optics can also improve power efficiency compared to a related configuration where optical transceivers are separate. This integration of optics and electronics can, in some embodiments, optimize power consumption in data centers and high-performance computing environments. Furthermore, co-packed optics enables higher connection density and increased data throughput, addressing the proliferating bandwidth requirements of modern networks.

[0017] Fig. Figure 1B is a cross-sectional view of the exemplary optical engine 104. In this example, the optical engine 104 has an electronic IC 110 and a photonic component 112 mounted on a silicon substrate 114. The silicon substrate 114 can be mounted on the printed circuit board 106.

[0018] In some embodiments, the electronic IC 110 in the optical engine 104 can be configured to process electronic signals, including data modulation, signal amplification, and error correction. The electronic IC 110 can include drivers for modulating laser diodes, transimpedance amplifiers (TIAs) for amplifying signals received from photodetectors, and various control circuits for managing power and data flow. The electronic IC 110 can be manufactured using, for example, complementary metal-oxide-semiconductor (CMOS) technology, which enables high integration density and low power consumption.

[0019] In some embodiments, the photonic component 112 includes components such as lasers, modulators, waveguides, photodetectors, and dot size converters. These components are configured to convert electronic signals into optical signals for transmission and to convert received optical signals back into electronic signals. Lasers and modulators generate the optical signals, waveguides transmit the signals through the photonic circuit, photodetectors convert incoming optical signals into electrical signals, and dot size converters adjust the mode field diameter for efficient coupling with optical fibers or other photonic components.

[0020] Both the electronic IC 110 and the photonic component 112 can be mounted on a silicon substrate 114, which provides a stable platform for integrating electronic and photonic devices. The silicon substrate 114 can be a silicon-on-insulator wafer (SOI wafer) to electrically and optically isolate the active devices from a bulk silicon substrate. The silicon substrate 114 can be shaped and positioned for precise alignment and thermal management of the integrated components.

[0021] The optical engine 104 can be optically coupled to one or more optical components 116, which facilitates the transmission of optical signals between the optical engine 104 and external components. The optical components 11 can include elements such as fiber optic cables, optical connectors, micro-optical lenses, and photonic integrated circuits (PICs). The optical coupling mechanism can be configured for efficient alignment and signal transmission, minimizing insertion loss and signal degradation.

[0022] For example, fiber optic cables can be directly connected to the optical engine 104 using precisely aligned connectors or splicing techniques, enabling high-speed data transmission over long distances. Micro-optical lenses can be used to focus and align the light beams between the optical engine 104 and other photonic devices, improving coupling efficiency and signal integrity. Photonic integrated circuits (PICs) can be integrated with the optical engine 104 to perform complex signal processing tasks such as wavelength multiplexing, switching, and filtering.

[0023] Optical coupling can be achieved using various techniques, such as butt coupling, lens coupling, or grating couplers, depending on the specific requirements of the application. Butt coupling involves directly aligning the optical fiber or component with the photonic component edge of the optical engine 104, providing a straightforward and efficient coupling method. Lens coupling utilizes micro-optical lenses to focus the light from the optical engine 104 into the optical fiber or component, reducing coupling losses. Grating couplers employ refractive structures to couple light between the optical engine 104 and optical fibers, enabling more flexible alignment and integration.

[0024] Fig. Figure 1C is a diagram illustrating an exemplary edge coupler 118 for the photonic component 112. The edge coupler 118 has a casing 118a, a spot size converter 118b, and a buried oxide layer 118c. The edge coupler 118 transmits and receives light 120 to and from optical components such as an optical fiber 122 and a lens 124. The edge coupler 118 can be mounted on a silicon substrate 140 inside the photonic component 112.

[0025] The casing 118a can surround the core of the edge coupler 118 and can be configured to maintain the confinement of transmitted and received light within the core by having a lower refractive index than the core. This difference in refractive index can be selected such that light is guided along the core by total internal reflection, minimizing signal loss and maintaining the integrity of the transmitted optical signal. The casing 118a also provides mechanical protection for the core, improving the durability and reliability of the edge coupler 118.

[0026] The point size converter 118a is a structure within the edge coupler 118, configured, for example, to stepwise adjust the mode field diameter of the optical signal. Stepwise adjustment of the mode field diameter of the optical signal can be useful for efficient coupling between the photonic component 112 and external optical fibers or other photonic devices exhibiting different mode field diameters. By matching the mode size of the emitted or received light, the point size converter 118b, in some embodiments, minimizes coupling losses and maximizes signal transmission efficiency.

[0027] The buried oxide layer 118c, also known as the BOX layer, is part of the silicon-on-insulator (SOI) structure and can be configured to provide electrical and optical isolation between the photonic devices and the underlying silicon substrate 114. In some embodiments, this electrical and optical isolation helps to reduce substrate-induced losses and crosstalk between adjacent photonic components, thus improving the overall performance of the optical engine 104. In some embodiments, the buried oxide layer 118c also assists in thermal management, dissipating heat generated by the photonic components and maintaining stable operating conditions.

[0028] In some embodiments, manufacturing the photonic component 112 includes singulating the photonic component 112 along a singulation plane 126, such that a silicon edge 128 remains in the silicon substrate 140 after singulation. Singulating the optical engine 104 may include performing facet etching. In various embodiments, to prevent damage to the dot size converter 118b, it is recommended to maintain the singulation plane 126 at a certain distance from the edge coupler 118 during the singulation process. The silicon edge 128 may be a result of maintaining this distance during the singulation process.

[0029] However, the silicon edge 128 can prevent close positioning of the edge coupler 118 with external optical components. To reduce the lateral dimension of the silicon edge 128 and enable closer positioning of the edge coupler 118 with external optical components, a further process for etching and singulating the silicon substrate 140 can be carried out, while preventing damage to the spot size converter 118b.

[0030] Fig. Figure 1D is a diagram illustrating the exemplary edge coupler 118 after etching and singulation to remove the silicon edge 128. The etching creates a depression 130 in the silicon substrate 140, and the subsequent singulation along a singulation plane 132 closer to the photonic component 112 removes a section of the silicon substrate 140.

[0031] Fig. 1E and Fig. Figure 1F shows vertical cross-sectional views illustrating a coupling interface 134 of the edge coupler 118 facing one or more external optical components. The edge coupler 118 has a photonic component edge 136 (i.e., a first edge 136) at the coupling interface 134. The silicon substrate 140 has a substrate coupling edge 138 at the coupling interface 134.

[0032] As in Fig. As shown in Figure 1E, the substrate coupling edge 138 (i.e., a second edge 138) projects beyond the photonic component edge 136 at the coupling interface 134 as a result of the singulation process of the photonic component 112. This extension restricts the distance between the photonic component edge 136 and an external optical component.

[0033] Fig. Figure 1F shows the edge coupler 118 after etching the silicon substrate 140 to create a recess in the silicon substrate 140 beneath the photonic component edge 136 and to singulate the silicon substrate 140 by removing a section of the silicon substrate 140, so that the photonic component edge 136 extends beyond the substrate coupling edge 138 at the coupling interface 134. As a result, the silicon substrate 140 no longer restricts the distance between the photonic component edge 136 and an external optical component.

[0034] In some embodiments, the silicon substrate 140 has an L-shape in a vertical cross-sectional view. The coupling interface 134 extends along a coupling plane 142. The substrate coupling edge 138 has a depression section 138a, which is spaced from the coupling plane 142 by a first predetermined non-zero distance 144, and an end section 138b, which is spaced from the coupling plane 142 by a second predetermined non-zero distance 146. The first and second predetermined non-zero distances 144 and 146 are different; for example, the depression section 138a may be farther from the coupling plane 142 than the end section 138b, such that the first predetermined non-zero distance 144 is greater than the second predetermined non-zero distance 146.

[0035] Fig. Figure 1G is a transparent top view showing point size converters 118b above the silicon substrate 140 at the coupling interface 134. Each point size converter 118b extends along a direction from a position above the silicon substrate 140 to a position beyond the substrate edge 138. The width of each point size converter 118b in a second horizontal direction hd2 decreases stepwise as the point size converters 118b extend in a first horizontal direction hd1.

[0036] Fig. 2A is a cross-sectional view of an alternative configuration for optical engine 104. As in the example of Fig. As shown in Figure 2A, the optical engine 104 has the electronic IC 110 mounted on the photonic component 112. The photonic component 112 is mounted on the silicon substrate 114, and the silicon substrate 114 is mounted on the printed circuit board 106.

[0037] The in Fig. The embodiment shown in Figure 1B offers a simpler packing process, but due to the connection through the silicon substrate 114, it can result in a higher resistance between the electronic integrated component 110 and the photonic component 112. Alternatively, the embodiment shown in Figure 1B offers a simpler packing process. Fig. 2A shows a lower resistance between the electronic IC 110 and the photonic component 112, albeit with a more complex packing process.

[0038] For example, the packing process for the in Fig. The embodiment shown in Figure 1B is simplified due to the separation of the electronics and photonics components on the same substrate. In some cases, the components can be tested individually before integration to reduce potential assembly complexity.

[0039] In contrast, the one in Fig. The exemplary configuration shown in Figure 2A represents a stacked approach that reduces the electrical resistance between the electronic IC 110 and the photonic component 112, as the direct interface between these components reduces the distance that electrical signals travel. This lower resistance can result in improved performance characteristics, such as reduced power consumption and improved signal integrity.

[0040] The packing process for the in Fig. The exemplary configuration shown in Figure 2A may be more complex due to the need for precise alignment and bonding of the stacked components. In some embodiments, the direct interface between the electronic IC 110 and the photonic component 112 may incorporate packing techniques such as flip-chip bonding or through-silicon vias (TSVs) to ensure reliable electrical connections and thermal management.

[0041] In the Fig. In the embodiment shown in Figure 1B, the electrical IC 110 and the photonic component 112 are each mounted on the silicon substrate 114, for example, using solder balls. The solder balls facilitate the electrical connections between the respective components and the substrate 114. Once these connections are established, the silicon substrate 114, with the electronics and photonic components attached, is mounted on the printed circuit board 106 using additional solder balls. The assembly process can include precise placement and reflow soldering to ensure robust connections.

[0042] For the in Fig. In the embodiment shown in Figure 2A, the electronic IC 110 is mounted directly onto the photonic component 112. This vertical stacking can be achieved, for example, using hybrid bonding, a technique in which both electrical and mechanical connections can be achieved simultaneously by combining direct metal-to-metal connections with dielectric bonding between two surfaces. For example, hybrid bonding can include planarization and surface preparation of both surfaces, direct bonding of dielectric materials, and metal-to-metal connections formed on metal bonding pads under heat and pressure without the need for additional solder.

[0043] The photonic component 112, now with the electronic IC 110 mounted on its top surface, is then attached to the silicon substrate 114 using solder balls. The silicon substrate 114 is then mounted onto the printed circuit board 106 using the same solder ball technique. The packing process for this configuration may involve precise alignment and control during the reflow soldering process to ensure reliable and effective connections given the complexity of the stacked arrangement.

[0044] Both configurations, as in Fig. 1B and Fig. The embodiment shown in 2A can be useful in certain situations. Fig. 1B offers a simpler assembly process but may encounter certain performance limitations due to higher resistance. In contrast, the embodiment in Fig. While 2A offers better electrical performance at lower resistance, it can involve a more delicate and potentially more expensive packaging process. The choice between these configurations may depend on specific application requirements, including considerations of performance, manufacturing capacity, and cost constraints.

[0045] Fig. Figure 2B is a detailed view showing the electronic IC 110 and the photonic component 112 according to some embodiments. The photonic component 112 may have a waveguide 148 optically coupled to the edge coupler 118 and a dielectric layer 150 over the waveguide 148. The photonic component 112 may have silicon vias (TSVs) 152 extending through the substrate 140 to establish electrical connections between the electronic integrated component 110 and an external component, for example, the substrate 114 or the printed circuit board 106.

[0046] For example, the photonic component 112 can have metal interconnect structures 154 within one or more dielectric layers 156. The interconnect structures 154 can be connected to conductive pads 158, which in turn are connected to conductive terminals 160. Each of the conductive terminals 160 can provide an electrical connection for a ground or power supply voltage and an external component 114. Each of the conductive terminals 160 can, for example, be a solder ball having a solder region and an intermetallic connection region (IMC region) 162 at the interface between the solder and the conductive pads 158.

[0047] The electronic IC 110 can have a substrate 164 and transistors 166 on the substrate 164. The electronic IC 110 can have metal interconnect structures 168 in one or more dielectric layers 170. The interconnect structures 168 can connect the transistors 116 to the TSVs 152 in embodiments in which the electronic IC 110 can be bonded to the photonic component 112.

[0048] Fig. Figures 3A and 3E illustrate an exemplary process for manufacturing an optical engine 104 that incorporates the edge coupler 118. Fig. Figures 3A - 3E show cross-sectional views of the optical engine at different stages of the process.

[0049] Fig. Figure 3A shows the silicon substrate 140 and the edge coupler 118 mounted on the silicon substrate 140. The edge coupler 118 has a casing 118a, the silicon point size converter 118b, and the buried oxide layer 118c.

[0050] Fig. Figure 3B shows the edge coupler 118 after facet etching. Facet etching can be useful, for example, to create a clean and smooth optical interface, which can help minimize coupling losses associated with connecting to external optical components, such as optical fibers.

[0051] In some embodiments, facet etching includes masking, etching, and cleaning. A photolithographic mask is applied to protect specific areas of the edge coupler 118 during the etching process. The mask precisely defines the regions where material removal is desired, ensuring that etching occurs only at the facet.

[0052] The etching process itself can be performed using dry etching techniques such as reactive ion etching (RIE) or inductively coupled plasma (ICP) etching. These dry etching techniques enable highly anisotropic etching, which can achieve vertical sidewalls and a smooth surface finish. The choice of etching gases and process parameters is based on achieving the desired etch profile and surface quality.

[0053] After etching, the remaining mask material and all etching byproducts are removed through a cleaning process. This cleaning process can be useful, for example, to ensure that the facet is free of contaminants that could otherwise impair optical performance.

[0054] As an alternative to the method described, the facet etching process can incorporate various etching techniques or materials. For example, wet etching can be used for some applications, although it generally offers less control over the etch profile compared to dry etching. Additionally, laser-assisted etching or focused ion beam milling (FIB milling, focused ion beam etching) can be used to create facets in specific scenarios where precision and surface quality are essential.

[0055] Fig. Figure 3C shows the edge coupler 118 and the silicon substrate 140 after performing an undercut using sulfur hexafluoride (SF6), creating a depression 130 in the form of a semicircular notch in the silicon substrate 140 at the coupling interface 134 to one or more external optical components.

[0056] In the example that is in Fig. As shown in Figure 3C, sulfur hexafluoride (SF6) is chosen as the etching gas due to its high selectivity for silicon, which allows precise control of the etch depth and profile. In general, any isotropic etchant, such as SF6, tetramethylammonium hydroxide (TMAH), or potassium hydroxide (KOH), can be used for undercutting and creating the depression 130. TMAH etches at specific angles based on the orientation of the Si crystal but has a lower etch rate, resulting in a longer process time. On the other hand, SF6 has a faster etch rate but cannot allow for profile control based on the crystal lattice.

[0057] In some examples, the undercutting process begins with the application of a protective mask to define an area for undercut etching. This mask ensures that only the desired regions of the silicon substrate 140 are exposed to the etching gas, thus preserving the integrity of the remaining structure.

[0058] The etching process is then carried out in a controlled environment where SF6 gas is introduced into a plasma etching chamber. The SF6 molecules dissociate in the plasma, forming reactive fluorine species that chemically react with the exposed silicon to etch away the silicon and form the circular well 130.

[0059] The etching parameters, such as gas flow rate, chamber pressure, and RF power, can be selected to achieve the desired depression profile. Once the etching process is complete, the protective mask can be removed, and the newly formed circular depression 130 can be cleaned to remove any remaining etching byproducts or contaminants.

[0060] Fig. Figures 3D and 3E illustrate the removal of a section 140a of the silicon substrate 140 using stealth singulation. Fig. 3D shows the formation of a groove along a singulation plane 308 using a laser. Fig. Figure 3E shows splitting of the silicon substrate 140 along the groove to remove section 140a of the silicon substrate 140.

[0061] Stealth singulation uses a focused laser beam to create subsurface modifications in the silicon substrate 140. The laser, operating at a specific wavelength that penetrates the silicon, induces localized changes in the material without affecting the surface. The laser beam can be precisely controlled to follow the intended singulation plane 308, creating a continuous subsurface groove. This groove exhibits a series of microcracks, or modified zones, within the silicon lattice, which serve as starting points for subsequent cleavage.

[0062] In Fig. In step 3E, the silicon substrate 140 can be cleaved along the pre-scored groove to remove section 140a. The cleavage process utilizes the subsurface modifications introduced by the laser scribing. Mechanical force can be applied to the substrate, typically using a tool or by applying pressure, causing the substrate to fracture cleanly along the groove. This stealth singulation method enables precise and controlled separation, minimizing mechanical stress and potential damage to the remaining structure. The resulting edge can be smooth and well-defined.

[0063] Stealth singulation can offer several advantages over related mechanical singulation methods in certain cases. Stealth singulation can reduce the generation of particles and residues because laser-induced modifications occur below the surface, and the actual cleavage produces minimal mechanical disruption. Such purity can be beneficial in maintaining the integrity of sensitive photonic components and reducing the need for extensive post-singulation cleaning processes.

[0064] Alternative singulation techniques include mechanical sawing and plasma singulation. Mechanical sawing uses a diamond-tipped blade to physically cut through the substrate, which can introduce mechanical stress and residue, but is largely used for its simplicity and effectiveness. Plasma singulation, on the other hand, uses reactive plasma to etch through the substrate along defined lines, ensuring a stress-free and clean singulation process, but requiring more complex equipment and process control.

[0065] Fig. Figures 4A-4E illustrate an exemplary process for fabricating an optical engine 104 with an edge coupler 118 and a silicon nitride dot size converter 118b' (SiN dot size converter 118b'). Silicon and silicon nitride dot size converters are both used in photonic ICs to manage the transition of optical modes between components such as fibers and waveguides. Each material offers different advantages and disadvantages based on its physical properties and integration capacity.

[0066] Silicon point-size converters exploit the high refractive index of silicon, which enables tight optical confinement and efficient mode conversion. Silicon's high refractive index allows silicon waveguides to achieve smaller mode-field diameters, which can be advantageous for compact photonic circuits. Silicon point-size converters can efficiently couple light from small silicon waveguides to larger optical fibers by gradually expanding the mode size. The high index contrast between silicon and its cladding materials, such as silicon dioxide (SiO2), allows for precise control of the optical mode shape and size. Additionally, silicon is compatible with common complementary metal-oxide-semiconductor (CMOS) fabrication processes, enabling large-area integration and mass production of photonic devices.

[0067] Silicon point size converters can also have disadvantages. While their high refractive index contrast is advantageous for tight confinement, it can lead to increased sensitivity to manufacturing defects such as sidewall roughness and dimensional variations. This increased sensitivity can result in higher optical losses and reduced performance consistency between devices. Silicon can also be more susceptible to nonlinear optical effects such as two-photon absorption and free-carrier absorption, which can limit the performance of high-power photonic applications.

[0068] Alternatively, 118b' point size converters made of silicon nitride (SiN) offer various advantages and disadvantages due to their material properties. SiN has a lower refractive index than silicon, resulting in less restricted optical modes. This lower index contrast can be beneficial for low-loss transitions between waveguides and optical fibers, as mode overlap with the fiber can be better optimized. Compared to silicon, SiN is less susceptible to manufacturing defects, leading to more robust and consistent device performance. The lower refractive index can also reduce nonlinear optical effects, making SiN suitable for high-power applications.

[0069] However, the use of SiN 118b point size converters can present challenges in some embodiments. The lower refractive index can result in larger mode field diameters, which may require more space for the waveguides and converters, potentially increasing the overall area of ​​the photonic circuit. This larger mode size can also limit the integration density of SiN-based devices. Furthermore, SiN is not as widely integrated into standard CMOS processes as silicon, which can complicate fabrication and increase production costs.

[0070] Fig. Figure 4A shows the edge coupler 118 with the SiN point size converter 118b'. Fig. Figure 4B shows the edge coupler 118 after facet etching. Fig. Figure 4C shows the silicon substrate 140 after undercutting to create the depression 130. Fig. Figures 4D and 4E show the stealth singulation process to remove section 140a of silicon substrate 140.

[0071] Fig. Figures 5A - 5D illustrate another exemplary process for manufacturing an optical engine 104 with an edge coupler 118. Fig. Figures 5A - 5D show vertical cross-sectional views of the optical engine 104 at different stages of the process.

[0072] Fig. Figure 5A shows the silicon substrate 114 and the edge coupler 118 mounted on the silicon substrate 140. The edge coupler 118 has the cladding 118a, the point size converter 118b and the buried oxide layer 118c. Fig. Figure 5B shows the edge coupler 118 after performing facet etching.

[0073] Fig. Figure 5C shows the edge coupler 118 after back-grinding on the silicon substrate 140. The thickness 504 of the silicon substrate 140 after back-grinding is less than the thickness 502 of the silicon substrate 140 before back-grinding, as shown in Fig. 5B shown.

[0074] Back-side grinding is a mechanical process used to reduce the thickness of the silicon substrate 140 by removing material from the back or underside of the wafer. This process can involve securing the silicon wafer to a support, typically with an adhesive, and then grinding the exposed back side using a rotating grinding wheel. The grinding process can be controlled to achieve the desired final thickness with high precision. Controlling the grinding parameters helps prevent damage such as microcracks or deformations that could compromise the structural integrity and performance of the silicon substrate 140 and the integrated components.

[0075] A thinner silicon backsheet may be desirable, for example, in embodiments where heating elements are located within the photonic component. A thinner silicon backsheet can be useful in preventing heat dissipation that could potentially impair the efficiency of the heating elements.

[0076] Alternatively, performing back-side loops may be undesirable in embodiments where improved heat dissipation is beneficial. For example, in embodiments involving the placement of an on-chip laser on the silicon substrate 140, improved heat dissipation may be useful to increase the stability of the laser chip.

[0077] Fig. Figure 5D shows the edge coupler 118 after performing an undercut and singulation to create a circular depression 130 in the silicon substrate 140. For example, performing an undercut can include undercutting using SF6 or TMAH, and singulation can include stealth singulation or laser singulation.

[0078] Fig. Figures 6A - 6D illustrate another exemplary process for manufacturing an optical engine 104 with an edge coupler 118. Fig. Figures 6A - 6D show vertical cross-sectional views of the optical engine at different stages of the process.

[0079] Fig. Figure 6A shows the silicon substrate 140 and the edge coupler 118 mounted on the silicon substrate 140. The edge coupler 118 has the casing 118a, the point size converter 118b and a buried oxide layer 118c. Fig. Figure 6B shows the edge coupler 118 after performing a facet etching process. Fig. Figure 6C shows the edge coupler 118 and silicon substrate 140 after performing an undercut using sulfur hexafluoride (SF6), creating a depression 130 shaped as a semicircular notch in the silicon substrate 140.

[0080] Fig. Figure 6D shows the optical engine 104 after it has been inverted and prepared to singulate the silicon substrate 140 using a laser. The laser can be, for example, an ultraviolet pulsed laser (UV pulsed laser). In some embodiments, the laser can be an excimer laser or a UV Nd:YAG laser.

[0081] Excimer lasers with deep ultraviolet wavelengths (around 248 nm) are widely used due to their short pulse duration and high peak power. These properties minimize heat-affected zones and enable clean material removal.

[0082] During the singulation process, the inverted optical engine 104 can be mounted on a high-precision table, and the laser beam is then focused along a singulation plane 602 onto the silicon substrate 140 using, for example, mirrors and lenses, following a programmed structure to define the final shape. Each laser pulse removes a small amount of material from the silicon substrate 140, effectively singulating the silicon substrate 140 along the desired singulation plane 602.

[0083] After completion of the singulation process, compressed air or another suitable method can be used to remove residues and separated parts. By controlling the laser parameters such as pulse energy and scan speed, the singulation process can ensure clean cuts with minimal damage to the remaining material, especially the edge coupler 118.

[0084] Fig. Figures 7A - 7D illustrate features of the optical engine 104 after removal of a silicon edge. Fig. Figures 7A - 7D show vertical cross-sectional views of optical engine 104.

[0085] Fig. Figure 7A shows the edge coupler 118 with the SiN dot size converter 118b'. The silicon substrate 140 was singulated along a first singulation plane 702, and the edge coupler 118 was singulated along a second singulation plane 704, creating a gap 706 between the first plane 702 and the second plane 704. The gap 706 is ≥ 0, so the silicon substrate 140 does not restrict the distance between the edge coupler 118 and an external optical component.

[0086] The first singulation level 702 can generally be configured to follow any angle 708 with respect to the base of the silicon substrate 140. Furthermore, the silicon substrate 140 can have any suitable thickness 710. By controlling the angle 708, the thickness 710, and the depth and shape of the depression 130, the shape of the remaining silicon substrate 140 can be controlled to form various suitable structures.

[0087] Fig. Figure 7B shows the edge coupler 118 after TMAH undercutting has defined a triangular recess 730 in the silicon substrate 140. The parameters of the TMAH undercutting can be controlled to create various other suitable shapes for the recess 730.

[0088] For example, a higher concentration of TMAH generally leads to a faster etch rate, resulting in a wider and deeper triangular depression 730. Conversely, a lower concentration leads to slower etching and a shallower, narrower triangular depression 730. The temperature of the TMAH solution can also be varied or selected to achieve a desired shape of the depression 730. Higher temperatures generally accelerate the etch rate, similar to using a higher concentration. However, excessively high temperatures can lead to undesirable effects such as increased etching of the sidewalls.

[0089] Longer exposure times allow for deeper etching, creating a more pronounced triangular shape for the depression 730. Conversely, shorter exposure times result in a shallower etch. In some cases, a masking material (not shown) can be applied to specific areas of the silicon substrate 140 prior to TMAH exposure. This mask protects desired regions from the etching process, thus enabling more complex depression shapes that go beyond simple geometries. The pattern and thickness of the mask influence the final profile of the etched depression 730.

[0090] Fig. Figures 7C-7D show the edge coupler 118 with the silicon dot size converter 118b. The same gap 706 is produced by etching and singulation, and the same shapes can be produced in the silicon substrate 140.

[0091] Fig. Figures 8A-8B illustrate an exemplary process for aligning an edge coupler 118 with an exemplary optical component 802. In this example, the optical component 802 is a microlens. In general, the alignment process can be used with any suitable optical component or system of optical components.

[0092] Fig. Figure 8A is a vertical cross-sectional view of the silicon substrate 140 and edge coupler 118. A silicon edge 804 is present in the silicon substrate 140. In cases where the alignment is performed while the silicon edge 804 is present, the distance 806 between the edge coupler 118 and the microlens 802 may be limited by the silicon edge 804, since the silicon substrate 140 contacts the microlens 802 when the edge coupler 118 is brought close to the microlens 802.

[0093] Fig. Figure 8B is a cross-sectional view of the silicon substrate 140 and edge coupler 118 after the silicon edge 804 has been removed by etching and singulation. Now the edge coupler 118 can be aligned with the microlens 802 at a closer distance 806, so that the distance 806 between the edge coupler 118 and the microlens 802 is not limited by the silicon edge 804.

[0094] The edge coupler 118, as in Fig. As shown in Figure 8B, the microlens 802 can be positioned closer (i.e., at a smaller distance 806), which in some cases may be useful for creating better optical coupling. For example, in some embodiments, the distance 806 between the edge coupler 118 and the microlens 802 is less than 10 µm.

[0095] The following discussion now refers to a series of procedures and procedural steps. Although the procedural steps are discussed in a particular order or depicted in a flowchart as being carried out in a specific sequence, no order is required unless explicitly stated or necessary because one step depends on another step being fully completed before the step can be carried out.

[0096] Embodiments are now discussed in conjunction with Fig. 9 described, which illustrates a flowchart of an exemplary method 900 for manufacturing an optical engine 104 according to some embodiments of the present disclosure.

[0097] In one embodiment of method 900, step 902 comprises mounting a photonic component 112 onto a silicon substrate 114 to form the optical engine 104. The photonic component 112 may have an edge coupler 118 and a coupling interface 134 configured to connect to one or more external optical components 802. The edge coupler 118 may have a photonic component edge 136 at the coupling interface 134. The silicon substrate 140 has a substrate coupling edge 138 at the coupling interface 134. In some embodiments, the edge coupler 118 may include a spot size converter 118b, 118b', a buried oxide layer 118c, and encapsulation 118a.

[0098] The substrate coupling edge 138 projects beyond the photonic component edge 136 at the coupling interface 134. For example, in some embodiments, manufacturing the optical engine 104 includes performing facet etching such that the substrate coupling edge 138 projects beyond the photonic component edge 136 at the coupling interface 134.

[0099] In one embodiment, step 904 comprises mounting an electronic IC 110. In some embodiments, step 900 comprises mounting an electronic IC 110 on the silicon substrate 114 next to the photonic component 112. In some embodiments, step 900 comprises mounting an electronic IC 110 on the top surface of the photonic component 112.

[0100] In one embodiment, step 906 comprises etching the silicon substrate 140 to create a recess 130 in the silicon substrate 140 below the photonic component rim 136. In some embodiments, etching the silicon substrate 140 to create the recess 130 in the silicon substrate 140 below the photonic component rim 136 comprises undercutting the silicon substrate 140 using sulfur hexafluoride (SF6). Undercutting the silicon substrate 140 using sulfur hexafluoride (SF6) can result in a semicircular notch 130 formed in the silicon substrate 140 below the photonic component rim 136. In some embodiments, etching the silicon substrate 140 to create the recess 130 in the silicon substrate 140 under the photonic component edge 136 includes undercutting the silicon substrate 140 using tetramethylammonium hydroxide (TMAH).

[0101] In one embodiment, step 908 comprises singulating the silicon substrate 140 to remove a section 140a of the silicon substrate 140, such that the photonic component edge 136 extends beyond the silicon substrate coupling edge 138 at the coupling interface 134. In some embodiments, singulating the silicon substrate 140 to remove the section 140a of the silicon substrate 140 comprises: forming at least one groove on the silicon substrate 140 using a laser; and splitting the silicon substrate 140 along the groove to remove the section of the silicon substrate 140. In some embodiments, singulating the silicon substrate 140 to remove the section of the silicon substrate 140 comprises performing laser singulation.

[0102] In one embodiment, step 910 comprises aligning the edge coupler 118 with an external optical component (e.g., lens 802). The distance 806 between the edge coupler 118 and the external optical component is not restricted by the protruding silicon substrate 804.

[0103] The various embodiments disclosed herein can provide various advantages and improvements. For example, different embodiments can remove a protruding silicon edge 804 of an optical engine 104 by etching and singulation. As a result, the optical engine 104 can be positioned closer to an optical component, since the protruding silicon edge 804 can no longer be in contact with the optical component.

[0104] With reference to the various figures, a method 900 for manufacturing a semiconductor package can be provided, wherein the method may comprise the following operations: mounting a photonic component 112 on a silicon substrate P14 to form an optical engine 104, wherein: the photonic component 112 may have an edge coupler 118 and a coupling interface 134 configured to be connected to one or more external optical components 802; the edge coupler 118 may have a first edge 136 at the coupling interface 134; a silicon substrate 140 may have a second edge 138 at the coupling interface; the method may further comprise the operations for removing a section of the silicon substrate 140 such that the first edge 136 extends beyond the second edge 138 at the coupling interface 134.

[0105] In one embodiment, the method may include performing a facet etching. In another embodiment, the method may include etching the silicon substrate 140 to create a recess 130 in the silicon substrate 140 below the first edge 136. In another embodiment, etching the silicon substrate 140 may include undercutting the silicon substrate 140 using sulfur hexafluoride. In another embodiment, undercutting the silicon substrate 140 using sulfur hexafluoride forms a semicircular notch 130 in the silicon substrate 140 below the first edge 136. In another embodiment, etching the silicon substrate 140 to create the recess 130 in the silicon substrate 140 below the first edge 136 may include undercutting the silicon substrate 140 using tetramethylammonium hydroxide.In one embodiment, the method may include singulating the silicon substrate 140 to remove the section of the silicon substrate 140 by: forming at least one groove on the silicon substrate 140 using a laser; and splitting the silicon substrate 140 along the groove to remove the section of the silicon substrate 140. In one embodiment, singulating the silicon substrate 140 to remove the section of the silicon substrate includes performing laser singulation. In one embodiment, the method may also include mounting an electronic IC 110 on the silicon substrate 140 adjacent to the photonic component 112. In one embodiment, the method may also include mounting an electronic IC 110 on the top surface of the photonic component 112. In one embodiment, the edge coupler 118 can comprise a spot size converter (SSC) 118b, a buried oxide layer 118c and sheathing 118a.

[0106] According to another aspect of the present disclosure, a semiconductor package 104 may be provided. The semiconductor package 104 may comprise: a silicon substrate 140; and a photonic component 112 mounted on the silicon substrate 140, wherein: the photonic component 112 has an edge coupler 118 and a coupling interface 134 configured to be connected to one or more external optical components 102; the edge coupler 118 may have a photonic component edge 136 at the coupling interface 134; the silicon substrate 114 may have a substrate coupling edge 138 at the coupling interface 134; the photonic component edge 136 projects beyond the substrate coupling edge 138 at the coupling interface 134; and a shape of the silicon substrate 114 has a semicircular notch below the photonic component edge 136.The semiconductor package 104 can have a conductive terminal 160 that provides an electrical connection for a ground or power supply voltage between the semiconductor package 104 and an external component 114, and the conductive terminal 160 can have a solder region and an intermetallic interconnect (IMC) region 162.

[0107] In one embodiment, the coupling interface extends along a coupling plane 142. The substrate coupling edge 138 has a recessed section 138a, which is spaced from the coupling plane 142 by a first predetermined non-zero distance 144, and an end section 138b, which is spaced from the coupling plane 142 by a second predetermined non-zero distance 146. The first and second predetermined non-zero distances 144 and 146 are different. In one embodiment, the edge coupler 118 can include a point size converter (SSC) 118b. In another embodiment, the edge coupler 118 can further include a buried oxide layer 118c and a casing 118a. In another embodiment, the optical engine 104 can also include an electronic IC 110, which is mounted on the silicon substrate 114 next to the photonic component 112.In one embodiment, the optical engine 104 can also include an electronic IC 110 mounted on the top side of the photonic component 112. In one embodiment, the edge coupler 118 can include a point size converter (SSC) 118b, a buried oxide layer 118c, and a casing 118a.

[0108] According to another aspect of the present disclosure, a photonic semiconductor package 104 comprises: a silicon substrate 140; and a photonic component 112 mounted on the silicon substrate 140, wherein the photonic component 112 has an edge coupler 118 and a coupling interface 134 configured to be connected to one or more external optical components 102, wherein the edge coupler 118 has a photonic component edge 136 at the coupling interface 134, and wherein the silicon substrate 140 has a substrate edge 138 at the coupling interface 134; and wherein, in a top view of the photonic semiconductor package 104, the edge coupler 118 extends along a direction from a position above the silicon substrate 140 to a position beyond the substrate edge 138, and the width of the edge coupler 118 gradually decreases along that direction.

[0109] In one embodiment, the photonic semiconductor package can include an electronic IC hybrid 110 bonded to a top surface of the photonic component 112. In another embodiment, the photonic semiconductor package can include one or more silicon vias (TSVs) 152 electrically connecting one or more transistors 166 of the electronic IC 110 to an external component 114. In another embodiment, the photonic semiconductor package 112 can include one or more interconnect structures 154 electrically connecting the TSVs 152 to one or more conductive pads 158. In another embodiment, the photonic semiconductor package 112 can include one or more conductive terminals 160 across the conductive pads 158.

[0110] The foregoing outlines features of some embodiments so that those skilled in the art will better understand the aspects of this disclosure. Those skilled in the art will appreciate that they can already use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or obtain the same advantages as the embodiments presented herein. Those skilled in the art should also recognize that such equivalent designs do not deviate from the nature and scope of this disclosure and that they can make various changes, substitutions, and modifications herein without deviating from the nature and scope of this disclosure.

Claims

[1] Method for manufacturing a semiconductor package, the method comprising: Mounting a photonic component on a silicon substrate, wherein: the photonics component has an edge coupler and a coupling interface that is configured to be connected to an external optical component; the edge coupler has a first edge at the coupling interface; and the silicon substrate has a second edge at the coupling interface; and Removing a section of the silicon substrate so that the first edge extends beyond the second edge at the coupling interface. [2] The method of claim 1, comprising performing facet etching and etching the silicon substrate to create a depression in the silicon substrate below the first edge. [3] Method according to claim 2, wherein etching the silicon substrate comprises undercutting the silicon substrate using sulfur hexafluoride. [4] Method according to claim 3, wherein undercutting the silicon substrate using sulfur hexafluoride forms a semicircular notch in the silicon substrate below the first edge. [5] Method according to claim 1, wherein etching the silicon substrate to form the depression in the silicon substrate under the first edge comprises undercutting the silicon substrate using tetramethylammonium hydroxide. [6] Method according to any one of claims 1 to 5, comprising singling the silicon substrate to remove a section of the silicon substrate by: Forming at least one groove on the silicon substrate using a laser; and Splitting the silicon substrate along the groove to remove the section of silicon substrate. [7] Method according to any one of claims 1 to 6, wherein removing the section of the silicon substrate comprises performing laser singulation. [8] Method according to any one of claims 1 to 7, comprising mounting an electronic IC on the silicon substrate next to the photonic component. [9] Method according to any one of claims 1 to 8, comprising mounting an electronic IC on the top side of the photonic component. [10] Method according to any one of claims 1 to 9, wherein the edge coupler comprises a spot size converter (SSC), a buried oxide layer and sheathing. [11] Semiconductor package comprising: a silicon substrate; and a photonic component mounted on the silicon substrate, wherein: the photonic component has an edge coupler and a coupling interface that is configured to be connected to one or more external optical components; the edge coupler has a photonic component edge at the coupling interface; the silicon substrate has a substrate coupling edge at the coupling interface; the photonic component edge extends beyond the substrate coupling edge at the coupling interface; and a form of the silicon substrate has a semicircular notch below the edge of the photonic component; and a conductive connection that provides an electrical connection for a ground or power supply voltage between the semiconductor package and an external component, wherein the conductive connection has a solder region and an intermetallic compound (IMC) region. [12] Semiconductor package according to claim 11, wherein the coupling interface extends along a coupling plane, the substrate coupling edge has a recess section spaced from the coupling plane by a first predetermined non-zero distance, and an end section spaced from the coupling plane by a second predetermined non-zero distance, and the first and second predetermined non-zero distances are different. [13] Semiconductor package according to claim 12, wherein the edge coupler comprises a spot size converter (SSC), a buried oxide layer and encapsulation. [14] Semiconductor package according to one of claims 11 to 13, comprising an electronic IC mounted on the silicon substrate next to the photonic component. [15] Semiconductor package according to any one of claims 11 to 14, comprising an electronic IC mounted on the top side of the photonic component. [16] Photonic semiconductor package comprising: a silicon substrate; and a photonic component mounted on the silicon substrate, wherein the photonic component has an edge coupler and a coupling interface which is configured to be connected to one or more external optical components, wherein the edge coupler has a photonic component edge at the coupling interface, wherein the silicon substrate has a substrate edge at the coupling interface, wherein, from a top view of the photonic semiconductor package, the edge coupler extends along a direction from a position above the silicon substrate to a position beyond the substrate edge, and where the width of the edge coupler gradually decreases along the direction. [17] Photonic semiconductor package according to claim 16, comprising an electronic IC hybrid bonded to a top surface of the photonic component. [18] Photonic semiconductor package according to claim 17, wherein the photonic component has one or more silicon through-silicon vias (TSVs) that electrically connect one or more transistors of the electronic IC to an external component. [19] Photonic semiconductor package according to claim 18, wherein the photonic component has one or more interconnect structures connecting the TSVs to one or more conductive pads. [20] Photonic semiconductor package according to claim 19, wherein the photonic component has one or more conductive terminals over the conductive pads.

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