Semiconductor module with power bridge for integrated die connection

Abstract

A semiconductor module can include a first substrate with a first substrate surface that encompasses a region, a first semiconductor die located within the region on the first substrate surface, and a second semiconductor die located within the region on the first substrate surface. The semiconductor module can further include a second substrate with a second substrate surface that extends over the region and faces the first semiconductor die, the second semiconductor die, and the region, wherein the second substrate surface has a dielectric layer formed thereon, on which a metallization layer is located, comprising structured metals configured to electrically connect the first semiconductor die and the second semiconductor die to each other and to at least one conductive element on the first substrate surface located outside the region.

Description

CROSS-REFERENCE TO RELATED REGISTRATION

[0001] This application claims the priority and benefit of (1) the preliminary US application No. 63 / 715,912 dated November 4, 2024, and (2) the preliminary US application No. 63 / 736,415 dated December 19, 2024, and the simultaneously filed non-preliminary US application xx / xxx,xxx entitled SEMICONDUCTOR PACKAGING WITH EMBEDDED DEVICE AND REDISTRIBUTION LAYER, all of which are hereby incorporated by reference in their entirety. TECHNICAL AREA

[0002] This description refers to power semiconductor devices. STATE OF THE ART

[0003] Conventional power semiconductor modules can use wire bonds to create connections between a die and the package and / or between individual dies. However, wire bonds are associated with a number of disadvantages, including increased inductance and resistance, which can negatively impact switching performance. Furthermore, wire bonds tend to be bulky, unreliable, and difficult to inspect or rework after connection.

[0004] Another widely used technique involves die embedding in power semiconductor packages. Such approaches provide electrical access to both the top and bottom of the power die, which can improve connectivity. While effective for two-sided access, these methods also introduce process complexities and difficulties in ensuring consistent electrical characteristics across multiple parallel dies. Consequently, they can reach their limits when providing synchronized switching, such as in half-bridge configurations. The inability to test and adjust resistance and inductance prior to assembly further restricts the optimization of such modules under demanding conditions.

[0005] Conventional enclosures for power devices often fail to provide the desired level of reliability. For example, differences in thermal expansion properties between a die and an enclosure (e.g., made of ceramic) can lead to cracks or other defects.

[0006] Furthermore, established methods reach their limits when it comes to manufacturing compact devices that simultaneously provide the desired thermal management. For example, heat sinks that ensure sufficient heat dissipation are often too large to provide a finished enclosure of the required size. Additionally, molding materials or organic materials used in embedded enclosures tend to be poor thermal conductors.

[0007] The aforementioned difficulties, and others, are further exacerbated by the need to produce power equipment on a large scale. Therefore, current power equipment and associated housing technologies cannot meet market demand. SUMMARY

[0008] According to a general aspect, a semiconductor module comprises a first substrate with a first substrate surface enclosing a region, a first semiconductor die located within the region on the first substrate surface, a second semiconductor die located within the region on the first substrate surface, and a second substrate with a second substrate surface spanning the region and facing the first semiconductor die, the second semiconductor die, and the region, wherein the second substrate surface has a dielectric layer formed thereon with a metallization layer formed on the dielectric layer, which includes structured metals configured to electrically connect the first semiconductor die and the second semiconductor die to each other and to at least one conductive element on the first substrate surface located outside the region.

[0009] According to another general aspect, a semiconductor module comprises a first substrate with a first substrate surface having a region, a first semiconductor die located within the region on the first substrate surface having a first height, a second semiconductor die located within the region on the first substrate surface having a second height, and a second substrate with a second substrate surface spanning the region and facing the first semiconductor die, the second semiconductor die, and the region, wherein the second substrate surface has a dielectric layer formed thereon with a metallization layer formed on the dielectric layer, which includes structured metals configured to electrically connect the first semiconductor die and the second semiconductor die.and a height-adjustment structure between the second substrate and both the first semiconductor die and the second semiconductor die, which keeps the outer surfaces of the semiconductor module parallel to each other.

[0010] According to a further general aspect, a method for fabricating a semiconductor module comprises arranging, on a first substrate having a first substrate surface enclosing a region, a first semiconductor die and a second semiconductor die, which are arranged within the region on the first substrate surface; forming a second substrate having a second substrate surface with a dielectric layer formed thereon, with a metallization layer formed on the dielectric layer that includes structured metals; and joining the second substrate to the first substrate, wherein the second substrate surface of the second substrate spans the region and faces the first semiconductor die and a second semiconductor die within the region, and wherein the structured metals are configuredto connect the first semiconductor die and the second semiconductor die to each other and to at least one conductive element on the first substrate surface, which is located outside the area.

[0011] The details of one or more implementations are set out in the accompanying drawings and the description below. Other features will become apparent from the description, the drawings, and the claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is an exploded view illustrating exemplary embodiments of a semiconductor module with a power bridge for integrated die interconnection. Fig. Figure 2 is a cross-sectional side view of an exemplary implementation of the semiconductor module of Fig. 1. Fig. Figure 3 illustrates a view of the exemplary implementation of Fig. 2, along line AA. Fig. Figure 4 illustrates a view of the exemplary implementation of Fig. 2, along line BB. Fig. 5A is a top view of a first exemplary semiconductor module, which is designed according to the embodiments of Fig. 1-4 was manufactured. Fig. 5B is a cross-sectional view of the exemplary implementation of Fig. 5A, along line 5B. Fig. Figure 6A is a top view of a second exemplary semiconductor module, which is designed according to the embodiments of Fig. 1-4 was manufactured. Fig. 6B is a cross-sectional view of the exemplary implementation of Fig. 6A, along line 6B. Fig. 7A illustrates initial exemplary processes for creating the exemplary implementation of Fig. 2-4. Fig. 7B illustrates initial exemplary processes for creating the exemplary implementation of Fig. 2-4. Fig. 7C illustrates initial exemplary processes for creating the exemplary implementation of Fig. 2-4. Fig. 7D illustrates initial exemplary processes for creating the exemplary implementation of Fig. 2-4. Fig. 7E illustrates initial exemplary processes for creating the exemplary implementation of Fig. 2-4. Fig. Section 7F illustrates initial exemplary processes for creating the exemplary implementation of Fig. 2-4. Fig. 7G illustrates initial exemplary processes for creating the exemplary implementation of Fig. 2-4. Fig. Figure 8 is a cross-sectional side view of another exemplary implementation of the semiconductor module of Fig. 1. Fig. Figure 9 is a cross-sectional side view of the exemplary implementation of Fig. Figure 8 illustrates an exemplary encapsulation. Fig. Figure 10 is a cross-sectional side view of the exemplary implementation of Fig. 8 and illustrates a first example of embedded enclosures. Fig. Figure 11 is a cross-sectional side view of the exemplary implementation of Fig. 8 and illustrates a second example of embedded enclosures. Fig. 12 is a process flow for processing at the wafer level of the power bridges of Fig. 1. Fig. Figure 13 is a flowchart illustrating exemplary manufacturing techniques for a semiconductor package that supports the power bridges of Fig. 1 includes. DETAILED DESCRIPTION

[0012] The described packaging techniques for power semiconductors enable improvements over the aforementioned and other disadvantages of conventional techniques. For example, these techniques provide improved inductance / resistance, enhanced module post-processing, synchronized die switching, pre-assembly testing and adjustment, and simplified two-sided electrical / thermal access. These techniques also enable more compact and reliable packages while providing increased reliability and improved thermal management, to name just a few advantages.

[0013] In the described techniques, semiconductor dies can be distributed and positioned in a desired manner on a region of a first substrate. A second substrate can then be positioned over the first, spanning the region of the first substrate containing the dies to be connected. The second substrate can be fabricated with a dielectric layer and a metallization layer in a pattern that enables the desired connections between the spanned dies and with other elements on the first substrate located outside the area spanned by the second substrate. The second substrate can then be positioned over the defined region and bonded to the underlying dies and to the first substrate itself.

[0014] In this way, the second substrate (i.e., the metallization layer(s) it contains) can replace wire bonds or other conventional joining techniques. Furthermore, a top surface of the second substrate can be held parallel to a surface of the first substrate, thus providing two-sided connectivity, similar to conventional embedding techniques. In other words, the outer, opposing surfaces of the first and second substrates can be kept parallel to each other.

[0015] The second substrate (and its associated wiring), also known as the power bridge, overcomes the difficulties of inconsistent electrical properties typical of known methods. For example, the structured metals on the second substrate, which electrically connects the underlying dies and to conductive elements outside the designated area, ensure uniform switching behavior, important for half-bridge configurations, while simultaneously providing a reliable interconnection network that improves the overall performance of the module under demanding conditions. The metallization layer on the dielectric of the second substrate provides a robust interconnection network, thus addressing the challenge of integrating multiple parallel devices with uniform characteristics.

[0016] The described methods also address the challenge of pre-assembly testing and adjustment, for example, by enabling individual die evaluation before integration. This allows, for instance, the adjustment of resistance and inductance before final assembly, thereby reducing the risk of performance degradation and improving reliability in high-power environments. Even if testing reveals a failure to meet desired quality assurance standards, the second substrate can be removed to allow further modifications to the installed dies, after which the second substrate can be reinstalled, providing a rework capability not available with conventional techniques.

[0017] In addition to providing two-sided electrical connectivity, the two-sided access enabled by the spanning second substrate also supports effective heat dissipation. For example, if one surface of the second substrate is held parallel to and exposed against a surface of the first substrate, a heat sink can easily be installed on it.

[0018] The second substrate can be made using silicon or variations thereof (e.g., silicon carbide (SiC)). As a result, active or passive devices can be embedded in the second substrate, thus increasing the flexibility of available module design options while further reducing the module size.

[0019] In many cases, height differences can exist between the various semiconductor chips on the first substrate. To compensate for such height differences, one or more height-adjustment structures can be used between the dies and the second substrate. For example, one or more cavities can be formed in the second substrate, allowing a first, taller die to be placed in a deeper cavity than a second, shorter die. In other examples, the height-adjustment structures can include additional interconnect layers between the dies and the second substrate, so that fewer additional layers can be placed between a first, taller die and the second substrate than between a second die and the second substrate.For example, a top surface of the second substrate can be held parallel to a surface of the first substrate to facilitate electrical and / or thermal connectivity with respect to the second substrate, as mentioned above.

[0020] Fig. Figure 1 is a split view illustrating exemplary embodiments of a semiconductor module 100 with a power bridge for integrated die interconnection. In the example of Fig. Figure 1 represents a substrate 102, a first substrate of the semiconductor module 100, which can be made of any suitable substrate material, e.g., Si, SiC, gallium nitride (GaN), ceramic, or DBM. Further example substrate materials are provided below or would be obvious. In some implementations, a lower surface 101 of the first substrate 102 can be exposed for electrical and / or thermal connectivity, as mentioned above and described in more detail below.

[0021] A second substrate 104 is positioned over an area 106 of the first substrate 102. The second substrate 104 has a size and associated perimeter / dimensions that extend over the area 106, and / or it can be said that it has or possesses a base area in relation to the first substrate 102, which is defined by the area 106. Although the second substrate 104 (and thus the area 106) is shown in the cross-sectional view of Fig. When shown in two dimensions, it can have any shape, such as a square or a rectangle.

[0022] The second substrate 104 can be formed from or include a semiconductor substrate. That is, the second substrate 104 can be formed from any material suitable for forming semiconductor devices, including, for example, Si, SiC, or GaN. As described herein, forming the second substrate using such a semiconductor material provides a number of advantages, including, for example, the use of fabrication techniques commonly employed with such materials, as well as the ability to form one or more semiconductor devices in and / or on such materials.

[0023] A first semiconductor die 108 and a second semiconductor die 110 are positioned on the first substrate 102 and arranged within the region 106. Additional elements may also be arranged on the first substrate 102. For illustration, an element 112 and an element 114 are shown, with element 112 partially located within the region 106 and element 114 completely outside the region 106. The semiconductor dies 108 and 110 can, for example, represent any suitable power semiconductor device, such as an insulated-gate bipolar transistor (IGBT) or a metal-oxide-semiconductor field-effect transistor (MOSFET). The elements 112 and 114 can represent any passive or active elements that may be enclosed within the semiconductor module 100, including any conductive elements (including metallization layers) that may be arranged on the first substrate 102.

[0024] As already mentioned and in Fig. As shown in Figure 1, the semiconductor dies 108, 110 (or additional dies) can have different heights. A height-adjustment structure 116 can be included to accommodate such height differences. For example, as shown in the examples of Fig. Figures 2-7G show that the height-adjustment structure 116, for example, has cavities formed in the material of the second substrate 104. In other examples, such as the examples of Fig. As shown in Figures 8-11, the height-adapted structure can include 116 layers, which are selectively added for each of the semiconductor dies 108, 110. For example, 104 platings or other conductive layers can be added to the second substrate. In the example of Fig. More such layers can be added to semiconductor die 108 than to semiconductor die 110 because semiconductor die 110 has a greater relative height. Using these or other suitable height-adjustment structures, the second substrate 104 can be held with its top surface parallel to the top surface of the first substrate 102. In other words, the outer, opposite surfaces of the first substrate 102 and the second substrate 104 can be kept parallel to each other.

[0025] To provide an interconnection of the semiconductor dies 108, 110 with another and with one or more of the elements 112, 114, a dielectric layer 118 and associated metallization layer 120 can be arranged on the second substrate 104. As shown in Fig. 3 and Fig. As illustrated in greater detail in Figure 7A-7G, any desired metallization pattern 120 can thus be deposited onto the second substrate 104, thereby enabling corresponding connections between, for example, the semiconductor dies 108, 110 and the conductive element 112.

[0026] For example, such structuring can be carried out with respect to the second substrate 104, and then the second substrate 104 can be aligned with the area 106 and deposited over it, simultaneously connecting the semiconductor dies 108, 110 and the conductive element 112. For example, a direct connection 122 (e.g., soldering or sintering) can be formed between the metallization layer 120 and the conductive element 112, so that the second substrate 104 is physically connected to the first substrate 102. Furthermore, if desired or necessary, the second substrate 104 can be removed from the first substrate 102 and subsequently reconnected.

[0027] Using these and related techniques, the semiconductor module 100 can be provided with the aforementioned adjustment and post-processing features. For example, the metallization layer 120 can be formed and / or trimmed as desired so that relative inductances and / or resistances can be obtained and the semiconductor dies 108, 110 (and other dies within the range 106) can be operated in the desired synchronization with each other. If the desired results are not achieved, the second substrate 104 can be removed. Then all exposed elements can be post-processed and the second substrate 104 can be reattached. These processes can be continued until the semiconductor module 100 is ready for use.

[0028] Furthermore, numerous additions and / or modifications can be made to the second substrate 104. For example, if the second substrate 104 is made of or includes Si, additional elements, illustrated as elements 124 and 126, can be incorporated into, with, or on the second substrate using standard procedures.

[0029] For example, either element 124 or element 126, or both, can represent any passive or active circuit element that can be used in the context of the semiconductor module 100. For example, element 124 or element 126 can represent a temperature sensor. By placing a temperature sensor on the second substrate 104 instead of on an exposed surface of the first substrate 102, the overall size of the device can be reduced and precise temperature measurement can be provided. In other examples, as mentioned above, element 126 can include a heat sink or other thermal management solution.

[0030] Furthermore, a silicon through-hole (TSV) 125 can be formed through the second substrate 104. For example, the TSV 125 can be used to connect elements 124 and 126, or it can be used to connect element 126 to elements on a surface of the first substrate 102, such as the semiconductor die 110. One or both elements 124 and 126 can represent a conductive element or layer used for interconnection purposes.

[0031] In some embodiments, a stacked arrangement can also be created by adding a third (or more) substrate as a second power bridge for the second substrate 104 / first power bridge. In such embodiments, the TSV 125 can provide a connection between the power bridges and / or between the third substrate / second power bridge and the first substrate 102.

[0032] Although in the simplified example of Fig. Not illustrated in Figure 1, the semiconductor module 100 can be encapsulated with any suitable encapsulating material. For example, any suitable epoxy can be used, as in the example of Fig. 5, Fig. 6 and Fig. Figure 9 shows that in other examples, an embedded packaging can be made from a suitable material, such as an organic material. For example, flame retardant 4 (FR-4), a glass fiber reinforced epoxy laminate, can be used. Advantageously, virtually all of these embodiments can be realized with the possibility of an electrical and / or thermal connection to the first substrate 102 and / or the second substrate 104.

[0033] Fig. Figure 2 is a cross-sectional side view of an exemplary implementation of the semiconductor module from Fig. 1. That means, Fig. Figure 2 illustrates an exemplary assembled version of the unfolded side view of the semiconductor module 100. Fig. 1. For example, the embodiment of Fig. 2 represent a section of an inverter module or other power module.

[0034] In the example of Fig. 2 represents a substrate 202, a first substrate, as an example of the first substrate 102 of Fig. 1. As in Fig. 1 In some implementations, a lower surface of the first substrate 202 can be exposed for electrical and / or thermal connectivity using a connecting element 201. For example, the connecting element 201 can represent or enclose a metal layer, as when the first substrate 202 is DBM. In other examples, a back-side metal layer can be soldered or sintered as the connecting element 201. In still other examples, an epoxy compound can be used.

[0035] A second substrate 204 is positioned above an area 206 of the first substrate 202 and defines, as described above, a span or a base area with respect to the first substrate 202. A first semiconductor die 208 and a second semiconductor die 210, both IGBTs in the example of Fig. 2 can be represented, are positioned on the first substrate 202 and arranged within the area 206.

[0036] In the example of Fig. Figure 2 illustrates a conductive element 212a and a conductive element 212b as metallization or connecting elements. As already mentioned with reference to element 112 of Fig. As described in section 1, one or both of the conductive elements 212a, 212b can extend outside the area 206, e.g. in the plane of the cross-section of Fig. 2 and / or in a direction perpendicular to this plane, as in Fig. 4 shown in detail, whereby the connection(s) between dies 208, 210 and other elements of the semiconductor module of Fig. 2 is made easier and possible.

[0037] One element 214a is illustrated as a negative temperature coefficient / thermistor, also called NTC sensor 214a, while the second element 214b is illustrated generally as a passive circuit element. As already mentioned with reference to Fig. As described in Figure 1, elements 214a and 214b generally represent all elements that can be arranged on the first substrate 202 and completely outside the area 206. An advantage is that such elements can be provided more flexibly in the described embodiments than in conventional methods. For example, the NTC sensor 214a can be placed very close to dies 208 and 210, i.e., closer than in conventional techniques. As already mentioned, the NTC sensor 214a or other elements can also be arranged on the second substrate 204.

[0038] As previously mentioned, the semiconductor dies 208 and 210 are in Fig. Two different heights. As an example of the implementation of the height adjustment structure 116 of Fig. Figure 1 illustrates a cavity 216a and a cavity 216b containing dies 208 and 210, respectively, which have depths to ensure that a heat sink 226 and an underlying surface of the second substrate 204 are held on the same plane or parallel to one or more surfaces of the first substrate 202, such as its top or bottom, and / or parallel to the connecting element 201, such as a back-side metal layer. In particular, die 208 is taller than die 210. Fig. 2, such that the cavity 216a is slightly deeper than the cavity 216b within the second substrate 204. The width and / or length of each cavity 216a, 216b can be designed to fit or accommodate the corresponding dimensions of the respective dies 208, 210.

[0039] To provide interconnection between the semiconductor dies 208, 210 and with one or more elements 212a, 212b, a dielectric layer 218, a metallization layer 219, a metallization layer 220, and a dielectric layer 221 can be arranged on the second substrate 204. In particular, a section 220a of the metallization layer 220 can be directly connected to the conductive element 212a, for example, by soldering or sintering. Similarly, a section 220b of the metallization layer 220 can have a direct connection 222b, for example, by soldering or sintering to a conductive element 212b, which may extend outside the area 206.

[0040] More generally, in Fig. Figure 2 shows that a dielectric layer 203 is formed on the first substrate 202, which has a metallization layer 212 that includes conductive elements 212a, 212b. Connections 222 (e.g., solder, sinter), including the described connections 222a, 222b, which connect the second substrate 204 to the first substrate 202, are formed by the dielectric layer 205 in order to also attach the dies 208, 210 to the first substrate as well as the NTC sensor 214a and the passive element 214b to the first substrate 202.

[0041] As with reference to Fig. As described in Figure 1, the direct connection of the second substrate 204 to the first substrate 202 provides a reliable connection in addition to the connection via dies 208, 210. At the same time, such an approach allows the removal of the second substrate 204, if necessary, to rework any aspect ratio of the second substrate 204 and / or dies 208, 210 or other elements in area 206.

[0042] For example, the second substrate 204 can be removed using a "hot-pull" process, in which heat is used to soften a solder or other adhesive so that the second substrate 204 can be lifted off the first substrate 202. Then, machining processes for metals (e.g., copper) or other cleaning / forming processes can be used to modify exposed metal / copper surfaces and ensure they are smooth and ready for reattachment.

[0043] The inclined or angled walls of the cavities 216a, 216b enable and facilitate the deposition of the dielectric layer 218, the metallization layer 219 and the metallization layer 220. The inclined or angled walls of the cavities 216a, 216b thus facilitate the types of structured connecting elements described herein for connecting the dies 208, 210 to each other and to other conductive elements, which may be located partially or completely outside the area 206.

[0044] In Fig. 2 The metallization layer 212 of the first substrate 202 can contain any standard intermediate connections and associated elements, including one or more dielectrics and conductors (e.g., contact pads or metal layers), as well as attachment points for mounting a terminal frame or other housing elements, as shown below in Fig. 5B and Fig. 6B is shown. After assembly, the module is of Fig. 2 thus ready for the attachment of the mounting frame, the attachment of the heat sink, encapsulation or other processing, as described below with reference to Fig. 5A-6B are described and illustrated in more detail.

[0045] The example of Fig. Figure 2 thus illustrates the use of the second substrate 204 and associated features as a power bridge for a semiconductor module, such as a power semiconductor module, which replaces wire bonds, tape bonds, clips, and other conventional interconnection techniques for connections between multiple dies and / or between one or more dies and a package. Such a power bridge enables improved assembly efficiency and avoids resistance losses from electrical superposition of currents flowing into a wire bond. The power bridge thus provides connections with improved inductance, resistance, tunability, and reworkability. The resulting modules can be more compact (in length, width, and height) and provide more functionality per area than conventional modules. Furthermore, the resulting modules are more reliable than conventional modules, e.g.,They are less susceptible to damage from different thermal expansion rates of components within the module than conventional modules.

[0046] Specifically, the described power bridge enables, for example, the adjustment of electrical properties within and between power dies on a module, e.g., for simultaneous switching, which is important in many applications (e.g., for accelerating an electric vehicle). For this purpose, power dies can be tested before being installed in a module, and then the metal interconnects (e.g., conductor widths) of the power bridge(s) can be trimmed or otherwise modified to adjust their resistance / inductance before package assembly. Package assembly can include attaching (e.g., soldering or sintering) the second substrate 204 to the first substrate 104, thereby creating all the interconnects of the second substrate simultaneously.Following the tests performed after such assembly, the second substrate 204 can be removed if necessary, and updates can be made either on the second substrate 204, on the first substrate 202, and / or on any of the elements on either substrate. This makes it possible to achieve adjustments both between individual dies of a single power bridge and between multiple power bridges / power bridge modules.

[0047] The described techniques enable two-sided access (i.e., to opposite surfaces of the substrates 202, 204) without the process complexity of conventional package-die embedding. Therefore, for example, heat sinks or other thermal management structures can be provided on both surfaces to facilitate heat dissipation, such as heat sink attachments, thermally conductive materials (TIMs), backside silicon fins, or direct contact with a thermally conductive potting compound. Electrical connectivity can also be provided via one or both surfaces, enabling, for example, the connection of both sides of a power die to a single surface of a power package.

[0048] Fig. Figure 3 illustrates a view of the exemplary implementation of Fig. 2, along line AA. Fig. Figure 3 thus illustrates a view of the second substrate 204, showing an outer edge or perimeter corresponding to the area 206 of Fig. 2 corresponds to or defines this, as also in Fig. 4 shown below. Fig. Figure 3 also illustrates a gate connection 308a and a source connection 308b of the first semiconductor die 208 as an embodiment, although the first semiconductor die 208 can represent any type of semiconductor die.

[0049] Fig. Figure 4 illustrates a view of the exemplary implementation of Fig. 2, along line BB. As already mentioned in relation to the Fig. 2 and Fig. As noted in paragraph 3, the area 206 is defined by and corresponds to a surface of the first substrate 202 that is spanned or covered by the second substrate 204.

[0050] Fig. Figure 4 further illustrates that various structured metals can be configured to electrically connect the first semiconductor die 208 and the second semiconductor die 210 to each other and to various conductive elements on a surface of the first substrate 202, which lies outside the area 206. For example, Figure 4 illustrates that... Fig. Figure 4 shows a gate pad 408a and a source pad 408b for semiconductor die 208, as well as a drain pad 410 for semiconductor die 410. Either the gate pad 408a or the source pad 408b can be connected via a trace 415 to the pad(s) 414b for one or more passive elements. As further illustrated, the gate pad 408a, the pad 414b, an NTC pad 414a, and a connection 222a can be connected to various corresponding contact pads 418 for external connections. Likewise, the connection 222b can be connected via a trace 417 to a contact pad 416, while the drain pad 410 is illustrated as being connected via a trace 419 to a contact pad 414.

[0051] Fig. Figure 5A is a top view of a first exemplary semiconductor module 500, which is constructed according to the embodiments of Fig. 1-4 was produced. In Fig. 5A The connecting leads 500a include a variety of measuring, gate, and shunt connections, while the connecting leads 500b include ground, output phase, and input power (battery) connecting leads. The individual connecting leads 528, 530, and the encapsulation molding material 532 are, with respect to Fig. 5B is illustrated and described in greater detail.

[0052] In particular, Fig. 5B a cross-sectional view of the exemplary implementation of Fig. 5A, along line 5B. As already mentioned, illustrates Fig. 5B the connecting line 528 and the connecting line 530 from Fig. 5A and a cross-sectional view of the mold material 532.

[0053] Fig. 5B further illustrates similar or analogous components, which generally follow the example of Fig. 2 correspond, except as indicated below. In the example of Fig. 5B represents a substrate 502, a first substrate, as an example of the first substrate 102 of Fig. 1 or the first substrate 202 of Fig. 2. A lower surface of the first substrate 502 for electrical and / or thermal connectivity can be exposed using a connecting element 501.

[0054] A second substrate 504 is positioned above a region 506 of the first substrate 502 and defines, as described above, a span or a base area with respect to the first substrate 502. A first semiconductor die 508 and a second semiconductor die 510, both of which are MOSFETs in the example of Fig. The components shown in 5B are positioned on the first substrate 502 and arranged within the area 506.

[0055] In the example of Fig. 5B are a conductive element 512a and a conductive element 512b illustrated as metallization or connecting elements. As described above, one or both of the conductive elements 512a, 512b can extend outside the area 506, e.g., within a plane of the cross-section and / or in a direction perpendicular to the plane of the cross-section, thereby facilitating the connection(s) between the dies 508, 510 and other elements of the semiconductor module. Fig. 5B facilitates and enables. For example, as shown, the conductive element 512b extends to be connected to the connecting lead 530 by means of the metallization 512c.

[0056] The 514 element is represented as a negative temperature coefficient / thermistor, also referred to as NTC sensor 514. The NTC sensor 514 from Fig. 5B is connected to connection line 528 via connection line 515.

[0057] As in Fig. 2 have the semiconductor dies 508, 510 in Fig. 5B different heights. As an example of the implementation of the height adjustment structure 116 of Fig. Figure 1 illustrates a cavity 516a and a cavity 516b containing dies 508 and 510, respectively, and having associated depths to ensure that an underlying surface of the second substrate 504 is kept at the same level as, or parallel to, one or more surfaces of the first substrate 502, such as its top or bottom, and / or parallel to the back layer 501. In particular, die 508 is taller than die 510. Fig. 2, so that the cavity 516a is slightly deeper than the cavity 516b within the second substrate 504. As in Fig. 2. The width and / or length of each cavity 516a, 516b can be designed to fit or accommodate the corresponding dimensions of the respective dies 508, 510.

[0058] To provide interconnection between the semiconductor dies 508, 510 and with one or more elements 512a, 512b, a dielectric layer 518, a metallization layer 519, a metallization layer 520, and a dielectric layer 521 can be arranged on the second substrate 504. In particular, a section of the metallization layer 520 can be directly connected 522a, for example, by soldering or sintering to the conductive element 512a. Likewise, a section of the metallization layer 520 extending outside the area 506 within the first substrate 502 can be soldered or sintered to establish a connection with the connecting lead 530.

[0059] In Fig. 5 indicates, similar to in Fig. 2. The first substrate 502 has a dielectric layer 503 formed on it, which has a metallization layer 512 that includes the previously discussed conductive elements 512a, 512b, 512c. Connections 522 (e.g., solder, sinter), including the described connections 522a, 522b, which connect the second substrate 504 to the first substrate 502, are formed by the dielectric layer 505 in order to also attach the dies 508, 510 to the first substrate 502 and to attach the NTC sensor 514 to the first substrate 502.

[0060] As with reference to Fig. 1 and Fig. As described in Figure 2, the direct connection of the second substrate 504 to the first substrate 502 provides a reliable connection in addition to the connection via dies 508, 510. At the same time, such an approach allows the removal of the second substrate 504, if necessary, to rework any aspect ratio of the second substrate 504 and / or the dies 508, 510 or other elements in the area 506.

[0061] Once all tests and associated rework are completed, the molding material 532 can be used to encapsulate the semiconductor module 500. Fig. 5B, in contrast to, for example, from Fig. 6B below, the molding material extends around the second substrate 504 and completely encloses it, i.e., does not expose any part of the second substrate 504 outside the semiconductor module 500.

[0062] Fig. Figure 6A is a top view of a second exemplary semiconductor module 600, which is constructed according to the embodiments of Fig. 1-4 was produced. In Fig. 6A includes the 600a connecting leads, which provide a variety of measuring, gate and shunt connections, while the 600b connecting leads provide ground, output phase and input power (battery) connecting leads. Fig. Figure 6A further illustrates the heat sinks 626.

[0063] Fig. 6B is a cross-sectional view of the exemplary implementation of Fig. 6A, along line 6B. Fig. Figure 6B illustrates a connection cable 628 and a connection cable 630 from Fig. 6A as well as a cross-sectional view of the mold material 632 and one of the heat sinks 626.

[0064] Fig. 6B further illustrates similar or analogous components, which generally follow the example of Fig. 2 and Fig. 5B, except that the mold material 632 is thinned to expose a surface of the second substrate 604, thereby allowing the attachment of the heat sink 626. In detail, a first substrate 602 has a bottom surface that is exposed for electrical and / or thermal connectivity using a connecting element 601.

[0065] The second substrate 604 is positioned above a region 606 of the first substrate 602 and defines, as described above, a span or a base area with respect to the first substrate 602. A first semiconductor die 608 and a second semiconductor die 610, both of which are MOSFETs in the example of Fig. The components shown in 6B are positioned on the first substrate 602 and arranged within the area 606.

[0066] To provide interconnection between the semiconductor dies 608, 610 and with one or more elements 612a, 612b, 612c, a dielectric layer 618, a metallization layer 619, a metallization layer 620, and a dielectric layer 621 can be arranged on the second substrate 604. In particular, a section of the metallization layer 620 can be directly connected to the conductive element 612a, for example, by soldering or sintering it. Likewise, a section of the metallization layer 620 extending outside the area 606 can be soldered or sintered within the first substrate 602 to connect to the connecting lead 630.

[0067] The first substrate 602 has a dielectric layer 603 formed on it, which has a metallization layer 612 enclosing the previously discussed conductive elements 612a, 612b, 612c. Connections 622 (e.g., solder, sinter), including the described connections 622a, 622b, which connect the second substrate 604 to the first substrate 602, are formed by the dielectric layer 605 to also attach the dies 608, 610 to the first substrate 602, as well as an NTC sensor 614, which is attached to the first substrate 602 by the connecting lead 628 via the connecting lead connection 615.

[0068] As in Fig. Figure 5B illustrates a cavity 616a and a cavity 616b containing dies 608, 610 and having associated depths to ensure that an underlying surface of the second substrate 604 is kept at the same level or parallel to one or more surfaces of the first substrate 602.

[0069] Once all tests and associated rework are completed, the molding material 632 can be used to encapsulate the semiconductor module 600. Fig. 6B the molding material extends around the second substrate 604, but does not completely enclose it, leaving an upper section of the second substrate 604 exposed for the attachment of the heat sink 626 to it.

[0070] Fig. Sections 7A-7G illustrate exemplary processes for creating the exemplary implementation of Fig. 2-4. More precisely, illustrate Fig. 7A-7G exemplary processes for the production of the second substrate 204 of Fig. 2 and Fig. 3 illustrated power bridge, which with the first substrate 202 of Fig. 2 and Fig. 4 can be used.

[0071] In Fig. 7A is a silicon substrate 704a covered with a dielectric layer 700. For example, the dielectric layer 703 can enclose an oxide and / or nitride insulating material deposited using any conventional technique. For example, a chemical vapor deposition (CVD) diamond can be used. The insulators used can be electrically insulating and simultaneously highly thermally conductive, such as Si3N4 or CVD diamond.

[0072] In Fig. 7B The substrate 704a can be structured using photolithography and etching to form cavities 716a, 716b, thus providing the substrate 704b with the cavities 716a, 716b. The etching can be carried out, for example, using reactive ion etching (RIE) or using the chemical etching method.

[0073] In Fig. 7C has additional dielectric material added to form dielectric layer 718, which is related to dielectric layers 118, 218, 518, 618 of Fig. 1, Fig. 2, Fig. 5B or 6B corresponds to this. In Fig. 7D adds a metallization layer 719 in any pattern, corresponding to the metallization layers 219, 519 and 619 of Fig. 1, Fig. 2, Fig. 5B or 6B. For example, copper, aluminum, or other metals or combinations thereof can be added using structured photolithography and an underlying adhesive layer. The metallization layer 719 can be added, for example, using laminating, sputtering, printing, plating, or vapor deposition technologies. Tantalum (Ta), titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), or chromium (Cr) can be used for adhesion.

[0074] In Fig. In 7E, the dielectric layer 721 is added and structured using lithography. The dielectric layer 721 can be laminated, spray-coated, screen-coated, or rotationally coated, for example. Fig. 7F can have a solderable / sinterable metal layer 720 added, for example, by photolithography and using processes such as plating, sputtering, or evaporation. The solderable metal layer 720 can, for example, include nickel / gold, nickel / gold / tin, nickel / gold / tin, copper / nickel / gold, nickel / copper, nickel / copper / tin, or nickel / vanadium / silver.

[0075] In Fig. 7G will be the substrate 704b from Fig. 7F thinned to form substrate 704. Thinning can be achieved, for example, by grinding or etching on a glass substrate using bonding / debonding or by a tape-grind-detape process. As shown in Fig. Not shown, but already discussed above, 7G can be used to provide a back-side metal (e.g. for a heat sink) on the thinned substrate 704 by deposition, or any desired elements or materials can be added.

[0076] The processes of Fig. 7A-7G processes can be performed at the power bridge level or at the wafer level. This means, for example, that the processes of Fig. 7A-7G processes are performed on a wafer containing multiple future power bridges, which are then allocated and singulated for assembly to achieve economies of scale and other efficiencies. For example, thinning of all power bridges on the wafer can be performed prior to singulation, and inspection processes can be performed more efficiently when carried out at the wafer level.

[0077] Fig. Figure 8 is a cross-sectional side view of another exemplary implementation of the semiconductor module of Fig. 1. Fig. Figure 8 illustrates an elevation adjustment structure 816 as an example of the elevation adjustment structure 116 of Fig. 1, which includes mounting structures for compensating for height differences of underlying components without requiring one or more cavities to be etched into a substrate 804, e.g., cavities 216a, 216b of Fig. 2 or the cavities 516a, 516b of Fig. 5B is not required.

[0078] In detail, a first substrate 802 has a bottom surface exposed for electrical and / or thermal connectivity using a connecting element 801. A second substrate 804 is positioned over a region 806 of the first substrate 802 and, as described above, defines a span or base area with respect to the first substrate 802. A first semiconductor die 808 and a second semiconductor die 810, e.g., IGBTs, are positioned on the first substrate 802 and arranged within the region 806.

[0079] To provide interconnection between the semiconductor dies 808, 810 and with one or more conductive elements 812a, 812b, 812c, a dielectric layer 818, a metallization layer 819, a metallization layer 820, and a dielectric layer 821 can be arranged on the second substrate 804. A section of the metallization layer 820 can be connected to height-adjustment structures 816a, 816b, 816c, 816d and thereby to direct connections 822a, 822b and to the dies 808, 810, as shown. For example, the height-adjustment structure 816d of Fig. 8, for example, can be connected to the connection 822a and thus to the conductive element 812a, e.g., by soldering or sintering. Likewise, a section of the metallization layer 820 can be soldered or sintered to the height-adjustment structure 816c and thus to the connection 822b to the conductive element 812b, which may extend beyond the area 806. The conductive element 812c can be used for attaching connecting leads, as shown in Fig. 9 shown below.

[0080] The first substrate 802 has a dielectric layer 803 formed on it, which includes the metallization layer 812 enclosing the previously discussed conductive elements 812a, 812b, 812c. Connections 822 (e.g., solder, sinter), including the described connections 822a, 822b, which connect the second substrate 804 to the first substrate 802, are formed by the dielectric layer 805, through which the dies 808, 810, as well as an NTC sensor 814a and a passive element 814b, are also attached to the first substrate 802.

[0081] As stated above, in Fig. Figure 8 illustrates a cavity 816a and a cavity 616b, positioned on dies 808 and 810, respectively, and having associated thicknesses to ensure that an underlying surface of the second substrate 804 is kept at the same level or parallel to one or more surfaces of the first substrate 802. Additional height-adjustment structures 816c and 816d are positioned at the junctions 822b and 822a, respectively, to ensure the planarity of the second substrate 804 and a reliable connection between the second substrate 804 and dies 808 and 810 and the first substrate 802.

[0082] Parts or the entire height-adjustment structure 816 can also be positioned below the semiconductor dies 808 and 810. For example, conductive elements 816e and 816f can be positioned below the semiconductor dies 808 and 810.

[0083] Consequently, the embodiment of Fig. 8 the costs and time associated with the formation of cavities, while retaining many or all of the advantages described above. The embodiment according to Fig. In particular, 8 enables the use of the structured second substrate 804 for the electrical connection of several dies, e.g. the dies 808 and 810 within a module, while replacing wire bonds, tape bonds and / or clips.

[0084] In addition to the height adjustment structure(s) 816 of Fig. 8. The topography of such a multichip module can be modified, for example, by varying the die thicknesses, varying the die placement and the power bridge placement thicknesses, and / or by plating or adding conductive layers to the planar power bridge. Fig. 8 must be taken into account.

[0085] In addition to attaching heat sinks, such as a heat sink 826, additional functionality can be provided by adding additional dies or other circuit elements, including another module or enclosure, on an exposed top surface of the second substrate 804 or within a surface of the second substrate 804 facing the first substrate 802, as described in reference to Fig. 1 described, will be provided.

[0086] The approach of Fig. 8 thus increases the overall efficiency during assembly and the electrical performance of the module compared to existing approaches. Fig. 8. The conductor track widths can be modified to achieve equivalent inductance across multiple dies in a module, while avoiding resistance losses due to the electrical superposition of current flowing into a wire bond. As with previous embodiments, the second substrate 804 can be attached simultaneously to speed up assembly (compared to using multiple different attachment processes for wire bonds and clips).

[0087] Fig. Figure 9 is a cross-sectional side view of the exemplary implementation of Fig. Figure 8 illustrates an exemplary encapsulation. A separate top view of the exemplary implementation of Fig. 9 is not provided, but would be similar to the example of Fig. 6A.

[0088] In Fig. 9 can, once all related follow-up work in the context of Fig. 8 are tested, the molding material 922 is used to encapsulate the semiconductor module. In Fig. 9 the molding material 922 extends around the second substrate 804, but does not completely enclose it and exposes an upper section of the second substrate 804 for the attachment of the heat sink 826 to it.

[0089] Fig. Figure 10 is a cross-sectional side view of the exemplary implementation of Fig. 8 and illustrates a first example of embedded enclosures. In Fig. 10 is the semiconductor module of Fig. 8 and Fig. 9 embedded in a housing that encloses the encapsulating material 1001 and 1003, which can enclose, for example, any plastic, epoxy, ceramic, and / or organic materials such as the FR-4 mentioned above. The conductor tracks 1002 and 1004 can represent any power and / or signal conductor tracks. The connecting lines 1028 and 1030 can be, similar to the connecting lines 928 and 930 of Fig. 9, for the external connection of the embedded housing of Fig. 10 can be used. As can be seen from the description above, it is straightforward to connect the conductor tracks 1002 and 1004, since the described approach of the power bridge housing allows for two-sided connectivity.

[0090] Fig. Figure 11 is a cross-sectional side view of the exemplary implementation of Fig. 8 and illustrates a second example of embedded housings. In Fig. 11 is the semiconductor module of Fig. 8 to 10 embedded in a housing that encloses the encapsulating material 1103, which can enclose, for example, any plastic, epoxy, ceramic, and / or organic materials such as the FR-4 mentioned above. A first substrate 1101 is illustrated as a ceramic substrate that encloses or embeds conductor tracks 1102, which can represent power or signal lines, while the conductor track 1104 is illustrated as connected to a top surface of the second substrate 804. The connecting lines 1128, 1130 can be similar to the connecting lines 928 / 930 of Fig. 9 and connecting lines 1028 / 1030 from Fig. 10, for the external connection of the embedded housing of Fig. 11 can be used.

[0091] In Fig. 10 and Fig. 11. A power bridge, such as the second substrate 804, and the associated structuring can be integrated into an embedded housing using various techniques. For example, the first substrate 802 and the second substrate 804 can be assembled and then embedded in an organic substrate, such as material 1003 from Fig. 10, be embedded, or an embedded organic substrate can be used as the first / bottom substrate onto which the power bridge is applied and subsequently encapsulated to form an embedded housing, as in Fig. 11.

[0092] The embedded housings of Fig. 10 and Fig. Thus, 11 provide improved functionality for a given footprint compared to existing non-embedding enclosure technologies. At the same time, these approaches add significant functionality compared to existing embedded enclosure solutions.

[0093] Fig. 12 is a process flow for processing at the wafer level of the power bridges of Fig. 1. In Fig. 12. A wafer 1202 includes several reticule fields or panels 1204, each of which becomes or provides a first substrate, such as the first substrate 102, 202, 502, 602 or 802.

[0094] Thus, as shown, the panel 1204 serves as a substrate on which various elements can be formed, including a first die 1206, a second die 1208, an NTC sensor 1210, and further elements 1212 and 1214. For example, the dies 1206, 1208, and the sensor 1210 can be glued to the underlying panel 1204 using various methods, e.g., pick-and-place with reflow.

[0095] Performance bridges, which e.g. use the processes of Fig. 7A-7G can be formed, examined and characterized (1216), so that subsequently a housing 1218 with three matched power bridges 1220, 1222 and 1224 including a separate control element 1226 can be formed. The various processing steps of Fig. 12 can be performed either before the rolling / singling of wafer 1202 or after the rolling / singling.

[0096] As shown and described, the housing 1218 can thus have power bridges 1220, 1222, 1224, which are individually and as a group matched. Furthermore, all the above advantages, including, for example, one or more devices and / or heat sinks in or on one or more of the power bridges 1220, 1222, 1224, can be realized in the example of Fig. 12 may be present. The end packaging 1218 can also provide two-sided electrical and / or thermal connectivity.

[0097] Fig. Figure 13 is a flowchart illustrating exemplary manufacturing techniques for a semiconductor package that supports the power bridges of Fig. 1 includes. In the example of Fig. 13 One or more power bridges are formed, including, for example, height-adjustment structures and structured metallizations (1302). For example, the process of Fig. 7A-7G can be used. The height adjustment structures can include cavities and / or planarization structures and / or variations in die thickness, power bridge thickness, die attachment or power bridge attachment thickness, and / or the addition of conductive layers to the power bridge. The structured metallization can be produced by sputtering, electroplating, printing, or other available techniques.

[0098] The power bridge(s) can also be formed with devices integrated within or on it. Such components can range from simple parts like capacitors or inductors to more complex components like MOSFETs or other active devices, temperature sensors, drivers, or other components, or various combinations thereof. These devices can be manufactured internally during the fabrication of the power bridge and / or attached after the power bridge has been fabricated. Such approaches add functionality to the resulting module while minimizing its footprint.

[0099] Power bridges can be mounted on a silicon wafer, for example, and do not need to be mounted on a rectangular / square module. Such a wafer can be singulated before or after testing the individual modules. In some embodiments, power bridges can be fabricated from cost-effective 300 mm silicon without expensive epitaxial layers (unless the silicon substrate of the power bridge has, for example, active devices that require an epitaxial layer).

[0100] Wafer-based processing enables photolithography, electroplating, vapor deposition or sputtering of metal layers, etching, oxidation, silicon etching (wet and dry), laser singulation, saw singulation, and other standard wafer processes and infrastructure. Metallization can be modified or adjusted for each module as needed. A full wafer can be encapsulated with backfill material, epoxy casting compounds, transfer-molded mold materials, or metal enclosures. Wafer processing tools and infrastructure can be used to form the connection element before and / or after mounting the devices to the substrate. Full-thickness wafers or wafers on the support substrate can be used.

[0101] A substrate to which the power bridge(s) are to be attached, including the associated circuit elements and the structured metallization (1304), is formed. For example, devices can be formed on one or more panels of a wafer, as described with reference to Fig. 12 described and illustrated. The structured metallizations of the power bridge and the substrate can correspond to each other, as in Fig. 3 and Fig. 4 shown. Sections of the height adaptation structure (such as conductive plating / layers) can initially be formed on the substrate.

[0102] The tests / adjustments can be performed on the power bridge(s) and the substrate(s) (1306). Such tests may vary depending on the features of the power bridge(s) or substrate(s) included, but generally include tests of connectivity, physical structure, and functionality.

[0103] Subsequently, one or more power bridges can be connected to the substrate (1308). For example, several power bridges can be attached to an underlying substrate, as shown in Fig. Figure 12 shows that, for example, pick-and-place or other tools can be used. The current bridges can be soldered or sintered onto the underlying substrate.

[0104] Tests of the combined power bridge / substrate modules can then be performed, and if necessary, one or more of the power bridges can be disassembled to rework either the power bridge or the substrate elements, followed by reassembly (1310). In this way, collective tuning across multiple power bridges can be provided in an efficient and practical manner.

[0105] Subsequently, encapsulation or embedding can take place (1312). For example, a molding material can be used for encapsulation, or an organic material can be used for embedding. The top and / or bottom of the resulting encapsulated / embedded module may be exposed for electrical and / or thermal connections.

[0106] If desired, additional devices or heat sinks can be provided on the top and / or bottom of the module (1314). Consequently, the module can be formed with a compact footprint and size, and in a reliable manner that provides a high degree of confidence in the functionality of the final product.

[0107] Singulation can be performed at any suitable and desired stage. For example, singulation of the wafer 1202 can take place before or after the placement of one or more power bridges onto individual panels 1204.

[0108] In various embodiments, a die can be mounted on a power bridge, which is then mounted on a wafer / substrate. This allows testing of the power bridge assemblies to be performed before the power bridge wafer is diced. Conversely, as previously described, the die can be mounted on the wafer / substrate and the power bridge added subsequently.

[0109] The described techniques can be used to replace wire bonds and other conventional interconnection techniques in any context and are well-suited for power applications due to, for example, improvements in electrical and thermal performance, as described herein. The described techniques can be implemented using standard semiconductor processing methods such as lithography and can also employ soldering, polymer jetting, or sieving through a metal mask.

[0110] In some implementations, soldering may be or include a process of joining two surfaces (e.g., metal surfaces) using a molten filler metal (e.g., metal alloy, tin (Sn), lead (Pb), silver (Ag), copper (Cu)) that may be referred to as a solder.

[0111] In some implementations, sintering can be a process of fusing particles into a solid mass by using, for example, a combination of pressure and / or heat, or it can include this process without melting the materials. In some implementations, sintering can involve fusing a material (e.g., a powdered material) into a solid or porous mass by heating, and usually also compressing the material without liquefaction. In some implementations, the materials usable for sintering can include metals such as silver (Ag), copper (Cu), and / or metal alloys. In some implementations, sintered compounds can exhibit desirable electrical and / or thermal conductivity, durability, and a relatively high melting point.

[0112] In some implementations, one or more of the components described herein can be coupled using materials such as a solder, a sintered material (e.g., silver, copper material) and / or other metal-to-metal bonding materials.

[0113] In some implementations, coupling of components can be carried out, for example, using a soldering process, a sintering process (e.g., a silver sintering process, a copper sintering process) and / or other metal-to-metal joining processes.

[0114] In some implementations, the directly bonded metal substrate (DBC substrate) (e.g., directly bonded copper (DBC)) can enclose an insulating layer positioned between a first metal layer and a second metal layer. The insulating layer can be, for example, a ceramic layer. In some implementations, the insulating layer can be, for example, a ceramic material such as aluminum oxide (Al₂O₃) or aluminum nitride (AlN).

[0115] In some implementations, a DBM substrate can be formed by bonding one or more of the metal layers (e.g., first metal layer, second metal layer) to the insulating layer. In some implementations, one or more of the metal layers can be bonded to the insulating layer, for example, using a high-temperature process.

[0116] In some implementations, the first and / or second metal layer of the DBM substrate can be or function as a heat sink. In some implementations, the first and / or second metal layer can be coupled to a heat sink. In some implementations, at least a portion of one or more of the first or second metal layers can be exposed by a molding material.

[0117] In some implementations, the first and / or second metal layer of the DBM substrate may be or include a structured metal layer that incorporates one or more electrically conductive traces. In some implementations, the first and / or second metal layer may be or include a structured layer configured to form one or more electrical circuits, one or more conductive vias (both reactive and / or through-holes), and / or so forth.

[0118] In some implementations, a DBM substrate may be or include a directly bonded copper substrate (DBC substrate) (e.g., a DBM with copper metal layers). In some implementations, such as DBC substrate implementations, the first metal layer and / or the second metal layer is a copper layer.

[0119] In some implementations, one or more semiconductor dies (e.g., one or more semiconductor components) may be or include a power semiconductor die. In some implementations, one or more semiconductor dies may be (e.g., be a section of) one or more metal-oxide-semiconductor field-effect transistors (MOSFETs), an insulated two-pole gate transistor (IGBT), an integrated circuit (IC), an inverter, a power conversion circuit, a bridge circuit, a fast recovery diode (FRD), a diode, and / or so on. In some implementations, one or more semiconductor chips may be (e.g., be a part of) a component for an electric vehicle (EV).

[0120] More than one semiconductor die can be included in the implementations described herein. In some implementations, different semiconductor dies (where more than one semiconductor die is included) can be fabricated using different semiconductor substrates (e.g., a silicon carbide substrate (SiC substrate), a silicon substrate (Si substrate), a gallium nitride substrate (GaN substrate), etc.). In other words, the different semiconductor dies can be fabricated on different semiconductor wafers or materials, for example. This can be referred to as a hybrid die configuration. For example, a first semiconductor die can be formed using a SiC substrate, and a second semiconductor die (separate from the first semiconductor die) can be formed using a silicon substrate.As another example, an IGBT can be manufactured using a SiC substrate, while a controller can be manufactured using a silicon substrate.

[0121] In example implementations, a first semiconductor die can be connected to a second semiconductor die, for instance, by an electrical connection (e.g., a wire bond, an electrical clip connection) extending directly from the first die to the second die, or by a conductor formed in the first conductive layer (e.g., a metal layer) of the power electronics substrate. The first of the multiple semiconductor dies can also be connected to terminal frame posts by electrical connections such as wire bonds or clips.

[0122] In exemplary implementations, a package (e.g., a power module) can be a hybrid device package enclosing a semiconductor die or a plurality of semiconductor dies integrated on a unifying power electronics substrate (e.g., a ceramic substrate, a DBM or DBC substrate, or an AMB substrate). In some implementations, multiple semiconductor devices (e.g., fabricated on the same substrate, such as a SiC substrate) may be suitable for high-power applications.

[0123] Although referred to as a connection frame in at least some sections of this detailed description, the connection frame can encompass any type of conductive section of a package (e.g., conductive section, conductive terminal) that can provide an external connection point from the package. Accordingly, the connection frame can be referred to as the conductive section of the package.

[0124] In some implementations, one or more sections of a leadframe can be coupled to a pad (e.g., a bond pad) on at least one section of a DBM substrate.

[0125] The semiconductor device packages described herein can include a variety of signal connections. These connections can be power connections, input signal connections, output signal connections, and so on. In some implementations, the various signal connections can be enclosed within a leadframe. In some implementations, a leadframe can include any type of conductive section of a package (e.g., conductive section, conductive terminal) that can provide an external connection point from the package. Accordingly, a leadframe can be described as the conductive section of a package or assembly. In some implementations, one or more sections of a leadframe can be coupled to a pad (e.g., a bond pad) on at least one section of a DBM substrate and / or a semiconductor die.

[0126] In some implementations, a molding compound (e.g., a molding material or encapsulation material) can be or include a non-conductive layer / material. In some implementations, the molding compound is a non-conductive material, such as an epoxy resin, that can be formed (applied, etc.) using a transfer molding or compression molding process. In some implementations, the molding compound can include a separate plastic housing that is enclosed within the semiconductor device assembly.

[0127] One or more wire bonds, which may be enclosed in at least some of the implementations described herein, can be replaced by a conductive component. For example, in some implementations, one or more wire bonds can be replaced by a conductive clip. The conductive clip can be coupled to another component (e.g., a connection pad, a leadframe, a semiconductor die, and / or so on) using, for example, solder (e.g., a soldering process), a sintered connection (e.g., a sintering process), a weld, and / or so on. In some implementations, one or more wire bonds and / or clips can function as input and / or output power connectors, signal connectors, power connectors, etc.

[0128] In some implementations, one or more semiconductor chips associated with the implementations described herein may be embedded in a layer (rather than being mounted on the surface). For example, one or more semiconductor dies may be arranged in a depression (which may be a cavity or also be referred to as such) of a layer (e.g., a substrate, a printed circuit board, a conductive layer, or an insulating layer).

[0129] In some implementations, one module (e.g., a package enclosing a semiconductor device) can be enclosed within another module. The module can be referred to as a package. For example, one or more modules can be one or more submodules contained within another module. In other words, a first module can be contained as a submodule within a second module.

[0130] In some implementations, a spacer material can be an epoxy resin, a silicone adhesive, a conductive material, a non-conductive material, an organic material, a semiconductor material, a metal alloy, a metal foam, a phase-change material, etc.

[0131] In the present description, the one or more semiconductor dies that may be used can be one of a wide variety, including, as a non-limiting example, power semiconductor dies, diodes, metal-oxide field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), hybrid devices, rectifiers, random-access memory, high electron mobility transistors, image sensors, wide-bandgap semiconductor devices (WBGs), hybrid devices, or any other type of semiconductor die / device. For the semiconductor die that is packaged with the semiconductor package designs disclosed in this document, a wide variety of semiconductor substrate types may be used, including, as a non-limiting example, silicon, silicon carbide, gallium arsenide, gallium nitride, silicon on insulator, ruby, sapphire, diamond, or any other type of semiconductor material.A wide variety of semiconductor package configurations can be formed using the principles disclosed herein.

[0132] It is understood that in the foregoing description, when an element, such as a layer, region, substrate, or component, is described as being on, connected to, electrically connected, coupled, or electrically coupled to another element, it may be directly on, connected to, or coupled to the other element, or one or more intervening elements may be present. Conversely, when an element is described as being "directly on," "directly connected to," or "directly coupled to" another element or layer, no intervening elements or layers are present. Although the terms "directly on," "directly connected to," or "directly coupled to" may not be used in the detailed description, elements shown as being "directly on," "directly connected to," or "directly coupled" may be identified as such.The claims of the application may be amended, if necessary, to specify exemplary relationships that are described in the patent specification or shown in the figures.

[0133] As used in the patent specification and claims, a singular form may include a plural form unless a specific case is clearly indicated in relation to the context. Spatial terms (e.g., above, over, upper, under, below, beneath, lower, and the like) are intended to include various orientations of the device in use or operation in addition to the orientation shown in the figures. In some implementations, the relative terms "above" and "below" may each include "vertically above" and "vertically below," respectively. In some implementations, the term "adjacent" may include "laterally adjacent to" or "horizontally adjacent to."

[0134] Some implementations can be implemented using various semiconductor processing and / or packaging techniques. Some embodiments can be implemented using different types of semiconductor processing techniques in conjunction with semiconductor substrates, including, but not limited to, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), and / or the like.

[0135] The following is a list of enumerated examples. 1. A semiconductor module, comprising: a first substrate with a first substrate surface that encloses an area; a first semiconductor die that is located within the area on the first substrate surface; a second semiconductor die located within the area on the first substrate surface; and a second substrate with a second substrate surface extending over the area and facing the first semiconductor die, the second semiconductor die and the area, wherein the second substrate surface has a dielectric layer formed thereon on which a metallization layer is located, enclosing structured metals configured to electrically connect the first semiconductor die and the second semiconductor die to each other and to at least one conductive element on the first substrate surface located outside the area. 2. The semiconductor module according to Example 1, wherein the second substrate comprises at least one of silicon or gallium nitride. 3. The semiconductor module according to Example 1, wherein the first semiconductor die has a first height and the second semiconductor die has a second height which differs from the first height, and further comprising: a height-adjustment structure between the second substrate and both the first semiconductor die and the second semiconductor die, which keeps the opposing outer surfaces of the semiconductor module parallel to each other. 4. The semiconductor module according to Example 3, wherein the height-adapting structure includes a first cavity and a second cavity formed in the second substrate, each having a first depth and a second depth respectively, and wherein the first semiconductor die is located in the first cavity and the second semiconductor die is located in the second cavity. 5. The semiconductor module according to Example 4, wherein the first cavity and the second cavity have sloping walls and the dielectric layer and the metallization layer are formed on them. 6. The semiconductor module according to Example 3, wherein the height-adjusting structure includes at least one conductive layer arranged between at least one of the first semiconductor die and the second semiconductor die, and having a thickness that keeps the opposing outer surfaces of the semiconductor module parallel to each other. 7. The semiconductor module according to Example 1, wherein the second substrate has an outer surface opposite the surface of the second substrate, and further comprises a device formed on the outer surface. 8. The semiconductor module according to Example 1, wherein the second substrate has an outer surface opposite the surface of the second substrate and further comprises a heat sink formed on the outer surface. 9. The semiconductor module according to Example 1, wherein the second substrate is directly connected to the first substrate. 10. The semiconductor module according to Example 1, further comprising a sensor arranged on the second substrate. 11. A semiconductor module, comprising: a first substrate with a first substrate surface that encloses an area; a first semiconductor die that is located within the area on the first substrate surface and has a first height; a second semiconductor die that is located within the area on the first substrate surface and has a second height; a second substrate with a second substrate surface extending over the area and facing the first semiconductor die, the second semiconductor die and the area, wherein the second substrate surface has a dielectric layer formed thereon on which a metallization layer is located, enclosing structured metals configured to electrically connect the first semiconductor die and the second semiconductor die; and a height-adjustment structure between the second substrate and both the first semiconductor die and the second semiconductor die, which keeps the opposing outer surfaces of the semiconductor module parallel to each other. 12. The semiconductor module according to Example 11, wherein the second substrate is directly connected to the first substrate and the structured metals are configured to electrically connect at least one of the first semiconductor die and the second semiconductor die to at least one conductive element on the surface of the first substrate located outside the area. 13. The semiconductor module according to Example 12, wherein the height-adapting structure includes a first cavity and a second cavity formed in the second substrate, each having a first depth and a second depth respectively, and wherein the first semiconductor die is located in the first cavity and the second semiconductor die is located in the second cavity. 14. The semiconductor module according to Example 13, wherein the first cavity and the second cavity have sloping walls and the dielectric layer and the metallization layer are formed thereon. 15. The semiconductor module according to Example 11, wherein the height-adjusting structure includes at least one conductive layer arranged between at least one of the first semiconductor die and the second semiconductor die, and having a thickness that keeps the opposing outer surfaces of the semiconductor module parallel to each other. 16. The semiconductor module according to Example 11, wherein the second substrate comprises at least one of silicon or gallium nitride. 17. A method for manufacturing a semiconductor module, comprising: on a first substrate with a first substrate surface that includes a region, a first semiconductor die and a second semiconductor die arranged within the region on the first substrate surface; Forming a second substrate with a second substrate surface on which a dielectric layer is formed, wherein a metallization layer is formed on the dielectric layer, which includes structured metals; and Connecting the second substrate to the first substrate, wherein the surface of the second substrate spans the area and faces the first semiconductor die and a second semiconductor die within the area, and wherein the structured metals are configured to electrically connect the first semiconductor die and the second semiconductor die to each other and to at least one conductive element on the surface of the first substrate located outside the area. 18. The procedure according to Example 17, further comprising: Providing a height-adjustment structure between the second substrate and both the first semiconductor die and the second semiconductor die, which keeps the opposing outer surfaces of the semiconductor module parallel to each other. 19. The procedure according to Example 18, further comprising the provision of the height adjustment structure, which includes: Forming a first cavity and a second cavity in the second substrate with a first and a second depth, respectively; Arranging the first semiconductor die inside the first cavity; and arranging the second semiconductor die inside the second cavity. 20. The procedure according to Example 18, further comprising the provision of the height adjustment structure, which includes: Providing at least one conductive layer positioned between at least one of the first semiconductor die and the second semiconductor die, with a thickness that keeps the opposing outer surfaces of the semiconductor module parallel to each other.

[0136] While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes, and equivalents are now apparent to the person skilled in the art. It is therefore understood that the accompanying claims are intended to cover all such modifications and changes that fall within the scope of protection of the implementations. It is understood that they have been presented only as examples, without being limiting, and that various changes to form and details may be made. Each section of the apparatus and / or method described herein may be combined in any combination, except for mutually exclusive combinations. The implementations described herein may include various combinations and / or subcombinations of the functions, components, and / or features of the various described implementations.

[0137] While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes, and equivalents are now apparent to the person skilled in the art. It is therefore understood that the appended claims are intended to cover all such modifications and changes that fall within the scope of protection of the embodiments. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 715,912

[0001] US 63 / 736,415

[0001]

Claims

[1] Semiconductor module, comprising: a first substrate with a first substrate surface that encloses an area; a first semiconductor die that is located within the area on the first substrate surface; a second semiconductor die located within the area on the first substrate surface; and a second substrate with a second substrate surface extending over the area and facing the first semiconductor die, the second semiconductor die and the area, wherein the second substrate surface has a dielectric layer formed thereon on which a metallization layer is located, enclosing structured metals configured to electrically connect the first semiconductor die and the second semiconductor die to each other and to at least one conductive element on the first substrate surface located outside the area. [2] Semiconductor module according to claim 1, wherein the second substrate comprises at least one of silicon or gallium nitride. [3] Semiconductor module according to claim 1, wherein the first semiconductor die has a first height and the second semiconductor die has a second height which differs from the first height, and further comprising: a height-adjustment structure between the second substrate and both the first semiconductor die and the second semiconductor die, which keeps the opposing outer surfaces of the semiconductor module parallel to each other. [4] Semiconductor module according to claim 3, wherein the height-adjusting structure includes a first cavity and a second cavity formed in the second substrate and each having a first depth and a second depth respectively, and wherein the first semiconductor die is arranged in the first cavity and the second semiconductor die is arranged in the second cavity. [5] Semiconductor module according to claim 4, wherein the first cavity and the second cavity have inclined walls and the dielectric layer and the metallization layer are formed thereon. [6] Semiconductor module according to claim 3, wherein the height adjustment structure includes at least one conductive layer arranged between at least one of the first semiconductor die and the second semiconductor die and having a thickness that keeps the opposing outer surfaces of the semiconductor module parallel to each other. [7] Semiconductor module according to claim 1, wherein the second substrate has an outer surface opposite the surface of the second substrate and further comprises a device formed on the outer surface. [8] Semiconductor module according to claim 1, wherein the second substrate has an outer surface opposite the surface of the second substrate and further comprises a heat sink formed on the outer surface. [9] Semiconductor module according to claim 1, wherein the second substrate is directly connected to the first substrate. [10] Semiconductor module according to claim 1, further comprising a sensor arranged on the second substrate. [11] Semiconductor module, comprising: a first substrate with a first substrate surface that encloses an area; a first semiconductor die that is located within the area on the first substrate surface and has a first height; a second semiconductor die that is located within the area on the first substrate surface and has a second height; a second substrate with a second substrate surface extending over the area and facing the first semiconductor die, the second semiconductor die and the area, wherein the second substrate surface has a dielectric layer formed thereon on which a metallization layer is located, enclosing structured metals configured to electrically connect the first semiconductor die and the second semiconductor die; and a height-adjustment structure between the second substrate and both the first semiconductor die and the second semiconductor die, which keeps the opposing outer surfaces of the semiconductor module parallel to each other. [12] Semiconductor module according to claim 11, wherein the second substrate is directly connected to the first substrate and the structured metals are configured to electrically connect at least one of the first semiconductor die and the second semiconductor die to at least one conductive element on the surface of the first substrate located outside the area. [13] Semiconductor module according to claim 12, wherein the height-adjusting structure includes a first cavity and a second cavity formed in the second substrate and each having a first depth and a second depth respectively, and wherein the first semiconductor die is arranged in the first cavity and the second semiconductor die is arranged in the second cavity. [14] Semiconductor module according to claim 13, wherein the first cavity and the second cavity have inclined walls and the dielectric layer and the metallization layer are formed thereon. [15] Semiconductor module according to claim 11, wherein the height-adjusting structure includes at least one conductive layer arranged between at least one of the first semiconductor die and the second semiconductor die and having a thickness that keeps the opposing outer surfaces of the semiconductor module parallel to each other. [16] Semiconductor module according to claim 11, wherein the second substrate comprises at least one of silicon or gallium nitride. [17] Method for manufacturing a semiconductor module, comprising: on a first substrate with a first substrate surface that includes a region, a first semiconductor die and a second semiconductor die arranged within the region on the first substrate surface; Forming a second substrate with a second substrate surface on which a dielectric layer is formed, wherein a metallization layer is formed on the dielectric layer, which includes structured metals; and Connecting the second substrate to the first substrate, wherein the surface of the second substrate spans the area and faces the first semiconductor die and a second semiconductor die within the area, and wherein the structured metals are configured to electrically connect the first semiconductor die and the second semiconductor die to each other and to at least one conductive element on the surface of the first substrate located outside the area. [18] The method of claim 17, further comprising: Providing a height-adjustment structure between the second substrate and both the first semiconductor die and the second semiconductor die, which keeps the opposing outer surfaces of the semiconductor module parallel to each other. [19] The method of claim 18, further comprising providing the height adjustment structure, which includes: Forming a first cavity and a second cavity in the second substrate with a first and a second depth, respectively; Arranging the first semiconductor die within the first cavity; and Arranging the second semiconductor die inside the second cavity. [20] The method of claim 18, further comprising providing the height adjustment structure, which includes: Providing at least one conductive layer positioned between at least one of the first semiconductor die and the second semiconductor die, with a thickness that keeps the opposing outer surfaces of the semiconductor module parallel to each other.

Images