GLASS CORES WITH EMBEDDED POWER TRANSMITTING COMPONENTS

Abstract

Glass cores with embedded power output components are disclosed. An exemplary device includes a glass layer comprising an aperture, a dielectric material within the aperture, a first cluster of inductances extending through the dielectric material, and a second cluster of inductances extending through the dielectric material, wherein the second cluster is spaced apart from the first cluster, and the dielectric material extends continuously from around the first cluster to the second cluster.

Description

BACKGROUND Integrated circuit (IC) chips and / or semiconductor dies are routinely interconnected to larger printed circuit boards (PCBs) via a package substrate. With increasingly smaller IC chips and / or dies and increasing interconnect densities, alternatives to conventional substrate layers are being developed to provide stable transmission of high-frequency data signals between different circuit configurations and / or increased power delivery. One option under consideration is the implementation of package substrates with glass cores. Generally, glass core implementations offer several advantages over implementations with conventional epoxy cores, including higher plated through-hole (PTH) density, lower signal loss, and less overall thickness variation. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 illustrates an exemplary integrated circuit (IC) package constructed according to the teachings disclosed herein. Fig. 2 illustrates a perspective view of an exemplary first glass core that can be used with the exemplary IC package from Fig. 1. Fig. 3 is a top view of the exemplary first glass core from Fig. 2, including a power output section. Fig. 4 is a cross-sectional side view of the exemplary first glass core from Figs. 2 and 3. Fig. 5 illustrates a perspective view of an exemplary second glass core that can be used with the exemplary IC package from Fig. 1. Figs. 6A and 6B are cross-sectional side views of the exemplary second glass core from Fig. 5, including a power output section. Fig. 7 is a top view of the exemplary second glass core from Figs. 5, 6A, and 6B.Figure 8 is a cross-sectional side view of an exemplary third glass core similar to the exemplary second glass core from Figure 5. Figure 9 is a top view of a wafer containing dies that may be contained in an IC package constructed according to the teachings disclosed herein. Figure 10 is a cross-sectional side view of an IC device that may be contained in an IC package constructed according to the teachings disclosed herein. Figure 11 is a cross-sectional side view of an IC device assembly that may contain an IC package constructed according to the teachings disclosed herein. Figure 12 is a block diagram of an exemplary electrical device that may contain an IC package constructed according to the teachings disclosed herein. Generally, the same reference numbers are used throughout the drawing(s) and the accompanying written description to refer to the same or similar parts. The figures are not necessarily to scale. Instead, the thickness of the layers or areas in the drawings may be enlarged. Although the figures show layers and areas with clear lines and boundaries, some or all of these lines and / or boundaries may be idealized. In reality, the boundaries and / or lines may be unobservable, blended, and / or irregular. DETAILED DESCRIPTION Fig. 1 illustrates an exemplary integrated circuit (IC) package 100 constructed according to the teachings disclosed herein. In the illustrated example, the IC package 100 is electrically coupled to an underlying substrate 102 via an array of contacts 104 on a package mounting surface 106 (e.g., a bottom surface, an outer surface) of the package. In some examples, the substrate 102 may be implemented on a package substrate or a printed circuit board (PCB). In the illustrated example, the contacts 104 are represented as pads or contact surfaces. However, in some examples, the IC package 100 may, in addition to or instead of the pads or contact surfaces shown, include balls, pins, and / or any other type of contact to enable electrical coupling of the IC package 100 to the substrate 102. In this example, the IC package 100 contains two dies 108, 110, (e.g. silicon dies, semiconductor dies, etc.).), sometimes also referred to as chips or chiplets, which are mounted on a package substrate 112 and enclosed by a package cover 114 (e.g., a potting compound, an integrated heat spreader (IHS)). The package substrate 112 thus represents an example of a means for holding a semiconductor die. Although the exemplary IC package 100 of Fig. 1 includes two dies 108, 110, in other examples the IC package 100 may contain only one die or more than two dies. In some examples, one of the dies 108, 110 (or a separate die) is embedded in the package substrate 112. The dies 108, 110 can provide any suitable type of functionality (e.g., data processing, memory, etc.). In some examples, one or both of the dies 108, 110 are implemented by a die enclosure that includes multiple dies arranged in a stacked formation.For example, the second die 110 can contain a stack of a dynamic random access memory (DRAM) die arranged on a memory control die to form a memory die stack. As shown in the illustrated example, each of the dies 108, 110 is electrically and mechanically coupled to the housing substrate 112 via corresponding arrays of intermediate connections 116. In Fig. 1, the intermediate connections are shown as contact bumps. The intermediate connections 116 can include solder joints, micro-contact bumps, combinations of metallic (e.g., copper) pillars and solder, etc. In other examples, the intermediate connections 116 can include directly bonded or "hybrid-bonded" metallic intermediate connections. In other examples, the intermediate connections 116 can be any other type of electrical connection (e.g., balls, pins, pads, pillars, wire bonding, etc.) in addition to or instead of the contact bumps shown. The electrical connections between the dies 108, 110 and the housing substrate 112 (e.g., the intermediate connections 116) are sometimes also referred to as first-level intermediate connections.In contrast, the electrical connections between the IC package 100 and the substrate 102 (e.g., the contacts 104) are sometimes referred to as second-level interconnects. In some examples, one or both of the dies 108, 110 may be stacked on top of one or more other dies and / or an interposer. In such examples, the dies 108, 110 are coupled to the underlying die and / or interposer by a first set of first-level interconnects, and the underlying die and / or interposer may be connected to the package substrate 112 via a separate set of first-level interconnects associated with the underlying die and / or interposer. Thus, as used here, first-level interconnects refer to intermediate connections (e.g., spheres, contact bumps, pins, pads, wire bonds, etc.).) between a die and a housing substrate or a die and an underlying die and / or interposer. As shown in Fig. 1, the intermediate connections 116 of the first-level interconnects include two different types of contact mounds, corresponding to core contact mounds 118 and bridge contact mounds 120. The core contact mounds 118, as used here, are contact mounds on the dies 108, 110 through which electrical signals pass between the dies 108, 110 and components outside the IC package 100. In particular, as shown in the illustrated example, the core contact mounds 118 are physically connected and electrically coupled to contact pads 124 on a die mounting surface 126 (e.g., a top, a cover, etc.) of the package substrate 112 when the dies 108, 110 are mounted on the package substrate 112. The contact pads 124 on the die mounting surface 126 of the housing substrate 112 are electrically connected to the contacts 104 on the housing mounting surface 106 via internal intermediate connections 128 within the housing substrate 112 (e.g.the lower, outer surface) of the package substrate 112 (e.g., a surface opposite the die mounting surface 126). As a result, a continuous electrical signal path exists between the core contact mounds 118 of the dies 108, 110 and the contacts 104 mounted on the substrate 102, passing through the contact pads 124 and the internal intermediate connections 128 provided between them. As shown, the package mounting surface 106 and the die mounting surface 126 define opposite outer surfaces of the package substrate 112. Although both surfaces are outer surfaces of the package substrate, the die mounting surface 126 is sometimes referred to here as an internal or inner surface relative to the entire IC package 100. In contrast, in this example, the package mounting surface 106 is an outer surface of the IC package 100. As used here, bridge contact hills 120 are contact hills on the dies 108, 110 through which electrical signals between different dies 108, 110 pass within the IC package 100. Accordingly, as shown in the illustrated example, the bridge contact hills 120 of the first die 108 are electrically coupled to the bridge contact hills 120 of the second die 110 via an intermediate bridge 130 (e.g., a silicon-based intermediate bridge, an intermediate die, an embedded intermediate bridge (EMIB)) embedded in the package substrate 112. As shown in Fig. 1, core contact hills 118 are typically larger than bridge contact hills 120. In some examples, the intermediate bridge 130 and the associated bridge contact hills 120 are omitted. In some examples, the IC package includes 100 additional passive components, such as surface-mounted resistors, capacitors and / or inductors, which are arranged on the package mounting area 106 of the package substrate 112 and / or the die mounting area 126 of the package substrate 112. In Fig. 1, the package substrate 112 of the exemplary IC package 100 includes a glass core 132 (e.g., a glass substrate, a glass layer, etc.) between two separate build-up areas 134, 136 (hereafter also referred to as build-up layers, etc.). In some examples, the glass core 132 includes at least one of the following: aluminosilicate, borosilicate, aluminoborosilicate, silicon dioxide, and / or molten silicon dioxide. In some examples, the glass core 132 contains one or more additives, including: aluminum oxide (Al₂O₃), boron trioxide (B₂O₃), magnesium oxide (MgO), calcium oxide (CaO), stoichiometric silicon dioxide (SrO), barium oxide (BaO), tin dioxide (SnO₂), nickel alloy (Na₂O), potassium oxide (K₂O), phosphorus trioxide (P₂O₃), zirconium dioxide (ZrO₂), lithium oxide (Li₂O), titanium (Ti), and / or zinc (Zn). In some examples, the glass core 132 contains silicon and oxygen.In some embodiments, the glass core 132 comprises silicon and oxygen, as well as one or more of the following elements: aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and / or zinc. In one embodiment, the glass core 132 comprises at least 23% by weight of silicon and at least 26% by weight of oxygen. In some examples, the glass core is a glass layer comprising silicon, oxygen, and aluminum. In some embodiments, the glass core 132 comprises at least 23% by weight of silicon, at least 26% by weight of oxygen, and at least 5% by weight of aluminum. In some examples, the glass core 132 is an amorphous solid glass layer. In some examples, the glass core 132 is a glass layer that contains no organic adhesive or organic material. In some examples, the glass core 132 is a solid glass layer that has a rectangular shape when viewed from above. In some examples, the glass core 132 includes at least one glass layer as the glass substrate and no epoxy or glass fibers (e.g., no epoxy-based prepreg layer with glass fabric). In some examples, the glass core 132 is a single piece of glass extending over the entire height / thickness of the core. In other examples, the glass core 132 can be silicon, a dielectric material, and / or one or more of any other materials. In some examples, the glass core 132 has a rectangular shape that, in a plan view, is substantially congruent (e.g., within 10%) with the layers above and below the core. In some examples, the glass core 132 has a thickness ranging from about 50 micrometers (µm) to about 1.4 millimeters (mm). In some examples, the glass core 132 may be a multilayered glass substrate (e.g., a coreless substrate), with each glass layer having a thickness ranging from about 25 µm to about 50 µm. In some examples, the glass core 132 may have dimensions ranging from about 10 mm on one side to about 250 mm on one side (e.g., 10 mm × 10 mm to 250 mm × 250 mm). In some embodiments, the glass core 132 corresponds to a rectangular prism volume with sections (e.g. vias) that have been removed and filled with other materials (e.g. metal, etc.).Glass cores are advantageous over epoxy-based cores for several reasons, including the fact that glass is stiffer and therefore provides greater mechanical support or strength for the housing substrate. Thus, the glass core 132 is an exemplary means of reinforcing the housing substrate. The build-up areas 134, 136 are shown in Fig. 1 as masses / blocks, with the internal interconnections 128 extending in straight lines through the build-up areas 134, 136 (and the glass core 132). However, this has been simplified in Fig. 1 for clarity and explanation only. In fact, the interconnections are not necessarily straight. In particular, in some examples, the build-up areas 134, 136 are defined by alternating layers of dielectric material and layers of conductive material (e.g., a metal such as copper). The conductive (metal) layers serve as the basis for the internal interconnections 128, which are represented in a simplified form by straight lines, as shown in Fig. 1. In some examples, the metal layers are structured to define electrical pathways or conductor tracks that connect different metal layers through conductive (e.g.,Metal vias extending through intervening dielectric layers are electrically coupled. The use of glass as a starting core material (e.g. the glass core 132 of Fig. 1) has a mechanical advantage (e.g. reduced bending, variation of smaller thickness), an electrical advantage and a design flexibility advantage (e.g. closer through-hole spacing, finer core routing) compared to the use of conventional organic core materials (e.g. epoxy-based prepreg). For example, the glass core 132 can support multi-chip packages (e.g., embedded multi-die interposer bridge (EMIB), 2.5D / 3D heterogeneous integration, hyperchip stacking (silicon (Si) interposer), etc.), reduced first-level interposer (FLI) contact bump distances (e.g., less than 30 micrometers (µm)), reduced fine-line spacing (FLS) (e.g., 2 / 2 µm), higher-density interposers, higher input / output (I / O) density structuring, increased form factors, and decreased package thicknesses compared to conventional organic core materials.To further enable these advantages, the glass core 132 can include glass vias (TGVs) (e.g., copper-clad vias) extending through the glass core 132 to electrically couple the build area 134 to the build area 136. Although the examples described here are given with reference to the glass core 132, it is understood that the teachings of this disclosure are not limited to it. For example, the teachings of this disclosure are also applicable to organic cores. A common type of failure in known glass cores is a Seware defect. Seware defects result in the separation of a glass core along a crack that propagates from an edge of the core along its length and width between two or more of the outer surfaces (e.g., the top and bottom surfaces, the front and back surfaces, etc.) of the glass core. That is, Seware defects are characterized by a glass core being split into two separate glass plates along a line that generally extends parallel to the main plane of the glass core. One factor contributing to Seware failure is stress concentration in glass core cavities, such as those housing power-emitting components. Power-emitting components, such as inductors (e.g., coaxial metal inductor loops (CMILs)), through-hole vias (TGVs), and plated through-holes (PTHs), are often positioned in densely packed cavities in previous glass cores due to conduction and spatial constraints. The formation of densely packed cavities in previous glass cores creates a thin network between these cavities. This network, and the associated stress concentration, can lead to high stress concentrations in the thin glass walls of the cavity network due to substrate stress.In particular, the corners and / or the thin walls of the tissue of the glass cores can cause large stress concentrations, which can lead to cracks and failure of the glass core. Examples disclosed herein overcome some or all of the problems mentioned above and include glass cores with embedded power output components. One exemplary glass core disclosed herein includes a large cavity containing a dielectric filler that supports multiple power output components. Another exemplary glass core disclosed herein includes a recessed section containing embedded power output components. In some such exemplary glass cores disclosed herein, the reduced thickness of the power output section of the glass core reduces stress concentrations in the recessed section. Some exemplary glass cores disclosed herein include six coaxial metal inductance loop (CMIL) clusters staggered to allow the placement of power distribution units (PTHs) between the CMIL clusters.Some exemplary glass cores disclosed herein incorporate cavities with rounded, chamfered, and / or beveled edges to reduce stress concentrations along the edges. Compared to previous glass core designs, the examples disclosed here substantially reduce the number of failure points associated with the embedded power delivery components in glass cores. Fig. 2 illustrates a perspective view of an exemplary first glass core 200 that can be used with the exemplary IC package 100 from Fig. 1. In particular, in some examples, the first glass core 200 of Fig. 2 can be used to implement the exemplary glass core 132 of Fig. 1. In the illustrated example of Fig. 2, the first glass core 200 includes an exemplary body 202 and an exemplary cavity 204. In the illustrated example of Fig. 2, the cavity 204 is defined by an exemplary inner wall 206 and includes an exemplary edge 208 with exemplary corners 210. In the illustrated example of Fig. 2, the body 202 has an exemplary upper surface 212A and an exemplary lower surface 212B. In the illustrated example of Fig. 2, the upper surface 212A lies against the lower surface 212B (e.g.(The surfaces 212A, 212B are opposite surfaces, etc.). In the illustrated example of Fig. 2, the surfaces 212A, 212B are the outer surfaces of the body 202 (e.g., the upper surface 212A is a first outer surface, the lower surface 212B is a second outer surface, etc.). The body 202 is the structural component of the glass core 200. That is, the body 202 mechanically supports components mounted on the glass core 200 (e.g., dies 108, 110 from Fig. 1, the mounting areas 134, 136 from Fig. 1, etc.). In some examples, the body 202 is a glass layer of a substrate of a housing substrate (e.g., the IC package 100, etc.). The body 202 includes (e.g., contains, consists of, etc.) glass (e.g., one or more of the glass compositions discussed in connection with the glass core 132 of Fig. 1, etc.). In other examples, the body 202 may be made of a different material. It is understood that only a section of the body 202 is illustrated in Fig. 2 and that the body 202 may extend planarly along the surfaces 212A, 212B. In some such examples, the body 202 may include additional cavities similar to cavity 204, which may contain additional power output components.As used here, the body 202 is also referred to as a structural section of the glass core 200. The cavity 204 is a through-hole extending through the body 202. In the illustrated example of Fig. 2, the cavity 204 has a generally square cross-section (e.g., edge 208 has four sides, etc.) with rounded corners (e.g., corners 210 are rounded, etc.). In other examples, the cavity 204 may have a differently shaped cross-section (e.g., a different polygon, a circle, an oval, etc.). Furthermore, the radius of curvature of the corners 210 may be larger or smaller than that shown in the illustrated example. In the illustrated example of Fig. 2, the cavity 204 has a constant cross-sectional shape and size between the upper surface 212A and the lower surface 212B. In other examples, the cavity 204 has a variable cross-section along the thickness of the body 202. For example, the cavity 204 can be conical and / or tapered (e.g.wider at the upper surface 212A than the lower surface 212B, wider at the lower surface 212B than the upper surface 212A, etc.), hourglass-shaped (e.g., wider at opposite surfaces 212A, 212B than a midpoint between them, etc.) and / or having any other suitable cross-sectional profile between surfaces 212A, 212B. In the illustrated example of Fig. 2, the edge 208 is defined by the inner wall 206 and the upper surface 212A. In some examples, the edge 208 may be chamfered, beveled, and / or rounded. In some examples, the edge between the inner wall 206 and the lower surface 212B is also chamfered, beveled, and / or rounded. An exemplary glass core with rounded edges is described below in conjunction with Fig. 8. The cavity 204 can support (e.g., accommodate, contain, or receive, etc.) a power-emitting section of the glass core 200. An exemplary power-emitting section that may be contained within the cavity 204 is described below in conjunction with Fig. 3. In some examples, the inner wall 206 of the cavity 204 is an interface (e.g., a mechanical interface, a material interface, etc.) between the body 202 and the power-emitting section located within the cavity 204. In the illustrated example of Fig. 2, an exemplary stress concentration map 214 is superimposed on the first glass core 200. The stress concentration map 214 reflects the stress experienced by the body 202 when the glass core 200 is subjected to biaxial bending. That is, in the illustrated example of Fig. 2, the stress concentration map 214 corresponds to the stress that the glass core 200 would experience in an IC package (e.g., the IC package from Fig. 1, etc.). In the illustrated example of Fig. 2, darker areas on the stress concentration map 214 correspond to regions of the body 202 that experience a higher stress, and lighter areas on the stress concentration map 214 correspond to regions of the body 202 that experience a comparatively lower stress. In the illustrated example of Fig. 2, the corners 210 are the only section of the body 202 that is subjected to high stress concentrations.In some examples, the corners 210 can be further rounded to reduce the resulting stress concentration(s) (e.g., the radius of the corners 210 can be increased to reduce the resulting stress, etc.). Fig. 3 is a top view of the first glass core 200 of Fig. 2 including an exemplary power output section 302. In the illustrated example of Fig. 3, the power output section 302 is arranged in the cavity 204 of the body 202 of Fig. 2. In the illustrated example of Fig. 3, the power output section 302 includes an exemplary dielectric filler 304, an exemplary first CMIL cluster 306A, an exemplary second CMIL cluster 306B, an exemplary third CMIL cluster 306C, an exemplary fourth CMIL cluster 306D, an exemplary fifth CMIL cluster 306E, an exemplary sixth CMIL cluster 306F, and an exemplary PTH cluster 308. In the illustrated example of Fig. 3, the CMIL clusters 306A, 306B, and 306C are arranged in an exemplary first row 310A, and the CMIL clusters 306D, 306E, and 306F are arranged in an exemplary second row 310B.In the illustrated example of Fig. 3, the body 202 contains several TGVs 312. The exemplary dielectric filler 304 is a non-conductive material that structurally supports and surrounds the CMIL clusters 306A, 306B, 306C, 306D, 306E, 306F and the PTH cluster 308. In the example shown in Fig. 3, the dielectric filler 304 is positioned in the cavity 204 of Fig. 2. In some examples, the dielectric filler 304 is an organic epoxy (e.g., an organic resin, an organic potting compound, etc.). In other examples, the dielectric filler 304 can consist of any other suitable type of non-conductive material (e.g., a plastic, a ceramic, a build-up film, etc.). The CMIL clusters 306A, 306B, 306C, 306D, 306E, and 306F are clusters of power-dissipating intermediates that extend through the glass core 200 between the upper surface 212A and the lower surface 212B. The intermediates of the CMIL clusters 306A, 306B, 306C, 306D, 306E, and 306F improve the power dissipation through the glass core 200. In the illustrated example of Fig. 3, the intermediates of the CMIL clusters 306A, 306B, 306C, 306D, 306E, and 306F are arranged in the dielectric filler 304 of the power-dissipating section 302. This means that the CMIL clusters 306A, 306B, 306C, 306D, 306E, 306F extend through the dielectric filler 304. In the illustrated example of Fig. 3, the CMIL clusters 306A, 306B, 306C, 306D, 306E, 306F extend continuously around and between each of the CMIL clusters 306A, 306B, 306C, 306D, 306E, 306F.This means that the dielectric material 304 is deposited as a single integral component around each of the CMIL clusters 306A, 306B, 306C, 306D, 306E, 306F (e.g., the dielectric material 304 extends continuously from around the first CMIL cluster 306A to around the second CMIL cluster 306B, etc.). In the illustrated example of Fig. 3, each of the CMIL clusters 306A, 306B, 306C, 306D, 306E, 306F is spaced apart from other CMIL clusters 306A, 306B, 306C, 306D, 306E, 306F. In the illustrated example in Fig. 3, each of the CMIL clusters 306A, 306B, 306C, 306D, 306E, 306F contains eight CMILs. In other examples, some or all of the CMIL clusters 306A, 306B, 306C, 306D, 306E, 306F may contain a different number of CMILs (e.g., one CMIL, two CMILs, etc.). In the illustrated example in Fig. 3, the intermediate connections of the CMIL clusters 306A, 306B, 306C, 306D, 306E, 306F are arranged in four rows of two intermediate connections, alternately offset. In other examples, some or all of the CMIL clusters 306A, 306B, 306C, 306D, 306E, and 306F may have different arrangements. In the illustrated example in Fig. 3, the CMIL clusters 306A, 306B, 306C, 306D, 306E, and 306F are arranged in two rows (e.g., rows 310A, 310B, etc.). In other examples, the CMIL clusters 306A, 306B, 306C, 306E, and 306F are in a different arrangement (e.g., one row, three rows, five rows, etc.).In the illustrated example of Fig. 3, the second CMIL cluster 306B is offset from the first CMIL cluster 306A and the third CMIL cluster 306C, so that an exemplary offset gap 314 is formed in the power output section 302. That is, the lateral offset of the second CMIL cluster 306B from the first CMIL cluster 306A and the third CMIL cluster 306C in the first row 310A creates the offset gap 314 in the middle of the power output section 302. In the illustrated example of Fig. 3, each of the inductors of each of the CMIL clusters 306A, 306B, 306C, 306D, 306E, 306F is located closer to neighboring inductors in the same CMIL cluster than to the nearest inductor in other CMIL clusters 306A, 306B, 306C, 306D, 306E, 306F (e.g.,Each inductor in the first CMIL cluster 306A is spaced a first distance from neighboring inductors in the first CMIL cluster 306A and is spaced a second distance from the nearest inductor in each of the other CMIL clusters 306B, 306C, 306D, 306E, 306F, where the second distance is greater than the first distance, etc.). In the illustrated example of Fig. 3, the PTH cluster 308 is arranged in the offset gap 314. That is, the PTH cluster 308 is located in the center of the power-dissipating section 302 (e.g., the center of the dielectric filler 304, etc.). Like the CMIL clusters 306A, 306B, 306C, 306D, 306E, and 306F, the PTH cluster 308 improves the power dissipation through the glass core 200. In the illustrated example of Fig. 3, the PTH cluster 308 is located within the dielectric filler 304 of the power-dissipating section 302. In the illustrated example of Fig. 3, the PTH cluster 308 includes twelve intermediate connections. In other examples, the PTH cluster 308 can include any other suitable number of intermediate connections (e.g., one intermediate connection, five intermediate connections, ten intermediate connections, twenty intermediate connections, etc.). In the illustrated example of Fig.In 3, the intermediate connections of PTH cluster 308 are arranged in six alternating columns of two intermediate connections. In other examples, the intermediate connections of PTH cluster 308 can have any other suitable arrangement, such as a different number of columns (e.g., one column, two columns, ten columns, etc.) and / or a different number of PTHs within a given column (e.g., one PTH, three PTHs, five PTHs, etc.). In other examples, the offset gap 314 is missing, and the CMIL clusters 306A, 306B, 306C are aligned laterally in the first row 310A (e.g., similar to the arrangement of the CMIL clusters 306D, 306E, 306F in the second row 310B, etc.). In some such examples, the PTH cluster 308 is not present and / or is positioned at a different location in the power delivery section 302 (e.g., near edge 208 of Fig. 1).2 , lateral between the first CMIL cluster 306A and the fourth CMIL cluster 306D, lateral between the third CMIL cluster 306C and the sixth CMIL cluster 306F, etc.). In the illustrated example of Fig. 3, the power output section 302 includes the CMIL clusters 306A, 306B, 306C, 306D, 306E, 306F and the PTH cluster 308. Additionally or alternatively, the power output section 302 may include other power output components disclosed herein. For example, the power output section 302 may include one or more capacitors (e.g., deep trench capacitors (DTCs), thin-film capacitors, etc.), one or more other interconnects (e.g., a silicon-based interconnect bridge, an interconnect die, an embedded interconnect bridge (EMIB), etc.), and / or any other components that may be embedded within the glass core 200. The TGVs 312 are glass vias made of electrically conductive material (e.g., copper, silver, etc.) that extend through the body 202. The TGVs 312 allow electrical signals and / or power to be conducted through the body 202 (e.g., between surfaces 212A, 212B, etc.). In the illustrated example of Fig. 3, the TGVs 312 are arranged in an offset grid. That is, in the illustrated example of Fig. 3, the TGVs 312 are arranged in offset rows and columns. In the other examples, the TGVs 312 are arranged in one or more other patterns. In some examples, the TGVs 312 are not present. Fig. 4 is a cross-sectional side view of the exemplary first glass core 200 of Fig. 2, including the power output section 302 of Fig. 3 along line AA of Fig. 3. In the illustrated example of Fig. 4, the power output section 302 includes an exemplary upper surface 402A, an exemplary lower surface 402B, and an exemplary outer wall 404. In the illustrated example of Fig. 4, the upper surface 402A is flush with the upper surface 212A of the body 202, and the lower surface 402B is flush with the lower surface 212B of the body 202. In other examples, one or both of the surfaces 402A, 402B of the power output section 302 are recessed and / or project from the surfaces 212A, 212B of the body 202.In some examples, surfaces 402A, 402B and / or surfaces 212A, 212B are etched, polished and / or planarized so that surfaces 402A, 402B and / or surfaces 212A, 212B are flush. In the illustrated example of Fig. 4, the outer wall 404 of the power output section 302 and the dielectric filler 304 (e.g., an outer wall of the power output section 302, etc.) is adjacent to the inner wall 206 of the cavity 204 of the glass core 200 (e.g., an inner surface of the cavity 204 of the glass core 200, etc.). In the illustrated example of Fig. 4, the outer wall 404 and the inner wall 206 are straight (e.g., straight-walled, etc.). In the illustrated example of Fig. 4, the outer wall 404 is in contact with the inner wall 206 along the depth of the cavity 204 (e.g., abuts, etc.). In other examples, an adhesive and / or a bonding agent is arranged between the outer wall 404 and the inner wall 206. Fig. 5 illustrates a perspective view of an exemplary second glass core 500 that can be used with the exemplary IC package from Fig. 1. In particular, in some examples, the second glass core 500 from Fig. 2 can be used to implement the exemplary glass core 132 from Fig. 1. The second glass core 500 is similar to the first glass core 200 of Figs. 2-4, except as otherwise specified. In the illustrated example of Fig. 5, the second glass core 500 includes an exemplary body 502, an exemplary first recessed section 504, an exemplary first opening 505, an exemplary mesh 506, an exemplary first cavity 508A, an exemplary second cavity 508B, an exemplary third cavity 508C, an exemplary fourth cavity 508D, an exemplary fifth cavity 508E, and an exemplary sixth cavity 508F. In the illustrated example of Fig.In Figure 5, the body 502 includes an exemplary edge 510 with exemplary corners 512. The body 502 is the structural component of the second glass core 500. The body 502 is similar to the body 202 from Figure 2, unless otherwise stated. As used here, the body 502 is also referred to as a structural section of the second glass core 500. In the illustrated example of Fig. 5, the first recessed section 504 includes an exemplary central platform 514. In the illustrated example of Fig. 5, the body 502 has an exemplary upper surface 516A and an exemplary lower surface 516B. In the illustrated example of Fig. 5, the surfaces 516A and 516B are the outer surfaces of the body 502 (e.g., the upper surface 516A is a first outer surface, the lower surface 516B is a second outer surface, etc.). In the illustrated example of Fig. 2, the upper surface 516A faces the lower surface 516B (e.g., the surfaces 516A and 516B are opposing surfaces, etc.). In the illustrated example of Fig. 5, the first recessed section 504 includes an exemplary first inner surface 518 (e.g., a recessed or inset surface). In the illustrated example of Fig.Figure 5 is an exemplary stress concentration map 520 superimposed on the second glass core 500. The first recessed section 504 is a section of the second glass core 500 that is enclosed by the body 502 (e.g., spaced inwards from it, etc.). That is, the first recessed section 504 and the first inner surface 518 are recessed by the body 502 and the upper surface 516A through the first opening 505. In the illustrated example of Fig. 5, the first recessed section 504 includes the fabric 506 and the central platform 514. In the illustrated example of Fig. 5, the fabric 506 includes several glass walls arranged between the cavities 508A, 508B, 508C, 508D, 508E, 508F (e.g., the fabric 506 includes a first glass wall separating the first cavity 508A and the second cavity 508B; the fabric 506 includes a second glass wall separating the first cavity 508A and the fourth cavity 508D, etc.). In the illustrated example of Fig.In Figure 5, the tissue 506 and the central platform 514 are integral with the body 502. In some such examples, the first opening 505 can be formed during the initial formation of the second glass core 500 (e.g., spin coating of the second glass core 500, shaping of the second glass core 500, casting of the second glass core 500, etc.). Additionally or alternatively, the first opening 505 can be formed after the initial formation of the second glass core 500 (e.g., via routing, laser-induced etching, etc.). The first recessed section 504 and the first opening 505 are described below in conjunction with Figures 6A and 6B. In some examples, the lower surface 516B of the body 202 includes an opening similar to the first opening 505. In some examples, the first recessed section 504 is the power output section of the second glass core 500. The cavities 508A, 508B, 508C, 508D, 508E, 508F are through-holes extending through the body 502. In some examples, each of the cavities 508A, 508B, 508C, 508D, 508E, 508F can accommodate (e.g., contain, surround, etc.) one or more corresponding power output components (e.g., a CMIL cluster, etc.). In the illustrated example of Fig. 5, the cavities 508A, 508B, 508C, 508D, 508E, 508F have a generally rectangular cross-section with rounded corners (e.g., the corners of cavities 508A, 508B, 508C, 508D, 508E, 508F are rounded, etc.). In other examples, some or all of the cavities 508A, 508B, 508C, 508D, 508E, 508F may have a differently shaped cross-section (e.g., a square, another polygon, a circle, an oval, etc.). Furthermore, the radius of curvature of the corners 210 may be larger or smaller than that shown in the illustrated example. In the illustrated example of Fig.In Figure 5, each of the cavities 508A, 508B, 508C, 508D, 508E, 508F has a constant cross-sectional shape and size due to the recessed sections 504. In other examples, some or all of the cavities 508A, 508B, 508C, 508D, 508E, 508F have a variable cross-section along the thickness of the body 502. For example, some or all of the cavities 508A, 508B, 508C, 508D, 508E, 508F may be conical and / or tapered, hourglass-shaped, and / or have any other suitable cross-sectional area profile. In some examples, the first opening 505 and / or the cavities 508A, 508B, 508C, 508D, 508E, 508F are filled with a dielectric filler similar to the dielectric filler shown. In some such examples, the power output components (e.g., TGVs, PTHs, CMILs, etc.) may be arranged within the dielectric filler and the first recessed section 504. Cross-sectional views of the glass core 500, which contains a dielectric filler similar to the dielectric filler 304 shown in Fig. 4, are described below in conjunction with Fig. 6A and Fig. 6B. It is understood that a top view of the second glass core 500 is substantially similar to the top view of the glass core 200 from Fig. 2, shown in Fig. 3. Edge 510 (e.g., the straight sections of edge 510 and the corners 512, etc.) is a transition surface that extends around the first recessed section 504. In the illustrated example of Fig. 5, edge 510 is defined between the first recessed section 504 and the upper surface 516A. In the illustrated example of Fig. 5, edge 510 is rounded (e.g., chamfered, curved, etc.). That is, in the illustrated example of Fig. 5, edge 510 is a curved surface (e.g., a curved transition surface, etc.) between the first recessed section 504 and the body 502. In other examples, edge 510 may be chamfered and / or beveled. In some examples, the edge 510 is an interface (e.g. a mechanical interface, a material interface, etc.) between the body 502 and a power output section of the second glass core 500 including the first recessed section 504.Edge 510 is described in more detail below in conjunction with Fig. 6A. In the illustrated example of Fig. 5, the central platform 514 of the second glass core 500 is arranged between the cavities 508A, 508B, 508C, 508D, 508E, 508F. Similar to the CMIL clusters 306A, 306B, 306C, 306D, 306E, 306F of Fig. 3, the cavities 508A, 508B, 508C, 508D, 508E, 508F are distributed to facilitate the presence of the central platform 514 in the middle of the first recessed section 504 (e.g., the central platform 514 corresponds to the offset gap 314 of Fig. 3, etc.). This means that the second cavity 508B is offset from the first cavity 508A and the third cavity 508C (e.g., the distance between the second cavity 508B and the fifth cavity 508E is greater than the distance between the first cavity 508A and the fourth cavity 508D, and the distance between the third cavity 508C and the sixth cavity 508F, etc.). In some examples, one or more power output components (e.g., via glass vias, etc.) are used.) formed, which are positioned in the central platform 514. In the illustrated example of Fig. 5, the central platform 514 is flush with the first inner surface 518 of the first recessed section 504. In other examples, the central platform 514 is flush with the upper surface 516A. In the illustrated example of Fig. 5, the stress concentration map 520 reflects the stress experienced by the body 502 when the second glass core 500 is subjected to biaxial bending (e.g., the same load associated with the stress concentration map 214 of Fig. 2, etc.). In the illustrated example of Fig. 5, darker areas on the stress concentration map 520 correspond to regions of the body 502 experiencing greater stress, and lighter areas on the stress concentration map 520 correspond to regions of the body 502 experiencing comparatively less stress. In the illustrated example of Fig. 5, the corners 512 and the thin walls of the tissue 506 are subject to stress concentrations. In some examples, the first recessed section 504 and the softening of the edge 510 (e.g., chamfering of the edge 510, rounding of the edge 510, beveling of the edge 510, etc.) reduce) the relative part of the stress transmitted through the core (e.g. compared to previous cores without the first recessed section 504, etc.) and increase the relative part of the stress transmitted through the body 502, which reduces the probability of a failure (e.g. Seware failure, etc.) occurring at the tissue 506 or the corners 512. Figures 6A and 6B are cross-sectional side views of the exemplary second glass core 500 of Figure 5 along line BB and line CC of Figure 5, respectively. In the illustrated example of Figures 6A and 6B, the second glass core 500 includes an exemplary dielectric filler 600. The dielectric filler 600 is similar to the dielectric filler 304 of Figure 3, unless otherwise specified. In the illustrated example of Figures 6A and 6B, the second glass core 500 includes the first recessed section 504 shown in Figure 5, the first opening 505 of Figure 5, and an exemplary second opening 602 similar to the first opening 505, except that the second opening 602 is formed in the lower surface 516B. In the illustrated example of Fig. 6A and Fig. 6B, the dielectric filler 600 is arranged in the openings 505, 602 and the cavities 508A, 508B, 508C, 508D, 508E, 508F. In the illustrated example of Fig.In 6A, the dielectric filler 600 is vertically aligned with the recessed section 504. That is, the dielectric filler 600 is aligned with the recessed section 504 in a direction normal (e.g., orthogonal, etc.) to the surfaces 212A, 212B. In the illustrated example of Figs. 6A and 6B, the second glass core 500 includes the first edge 510 of Fig. 5 and an exemplary second edge 604 similar to the first edge 510, except that the second edge 604 is located between the lower surface 516B and an exemplary second inner surface 606 of the first recessed section 504. In the illustrated example of Fig. 5, the second opening 602 and the second edge 604 have the same size and shape as the first opening 505 and the first edge 510, respectively. In other examples, the second opening 602 and the second edge 604 may have different sizes and / or shapes than the first opening 505 and the first edge 510, respectively. In some examples, the first opening 505 and / or the second opening 602 are missing (e.g., the first inner surface 518 is flush with the upper surface 516A, the second inner surface 606 is flush with the lower surface 516B, etc.). In the illustrated example of Fig. 6A, the body 502 of the second glass core 500 has an exemplary first thickness 608, and the first recessed section 504 has an exemplary second thickness 610. In the illustrated example of Fig. 6A, the first thickness 608 is approximately 60% of the length of the second thickness 610. In some examples, the first thickness 608 may be between 10% and 90% of the length of the first thickness 608. In some examples, the thickness 608 is 200 micrometers (e.g., each of the openings 505, 602 has a depth of 100 micrometers, etc.). In other examples, the first thickness 608 may be any other suitable dimension. In the illustrated example of Figs. 6A and 6B, the dielectric filler 600 in the first recessed section 504 includes an exemplary upper surface 612A, an exemplary lower surface 612B, and an exemplary outer wall 614. In the illustrated example of Figs. 6A and 6B, the dielectric filler 600 extends around an upper end of the glass walls of the fabric 506 (e.g., the end of the glass walls near the first opening 505, etc.) and a lower end of the glass walls of the fabric 506 (e.g., the end of the glass walls near the second opening 602, etc.). That is, in the illustrated example of Figs. 6A and 6B, the dielectric filler 600 is arranged in the openings 505, 602, and above and between the glass walls of the fabric 506. In the illustrated example of Figs. 6A and 6B, the upper surface 612A of the dielectric filler 600 is flush with the upper surface 516A, and the lower surface 612B of the dielectric filler 600 is flush with the lower surface 516B. In some examples, the surfaces 516A, 516B and / or the surfaces 612A, 612B are etched, polished, and / or planarized so that the surfaces 516A, 516B and / or the surfaces 612A, 612B are flush. In the illustrated example of Fig. 6B, the outer wall 614 of the power output section 302 and the dielectric filler 304 abuts the edges 510, 604 of the second glass core 500. In the illustrated example of Fig. 6B, the outer wall 614 is in contact with the edges 510, 604 (e.g., abutting them, etc.). In other examples, an adhesive and / or a bonding agent may be arranged between the outer wall 614 and the edges 510, 604. In the illustrated example of Fig. 6B, the second glass core 500 contains an exemplary first CMIL cluster 616A, an exemplary second CMIL cluster 616B, and an exemplary third CMIL cluster 616C, arranged in the exemplary first cavity 508A, an exemplary second cavity 508B, and an exemplary third cavity 508C, respectively. The CMIL clusters 616A, 616B, and 616C are similar to the CMIL clusters 306A, 306B, 306C, 306D, 306E, and 306F of Fig. 3, unless otherwise specified. In the illustrated example of Fig. 6B, the CMIL clusters 616A, 616B, 616C extend through the dielectric filler 600 in the openings 505, 602 and the cavities 508A, 508B, 508C. In the illustrated example of Fig. 6B, braids of the fabric 506 are arranged between the first CMIL cluster 616A and the second CMIL cluster 616B and between the second CMIL cluster 616B and the third CMIL cluster 616C. Fig. 7 is a cross-sectional plan view of the exemplary second glass core 500 from Fig. 5, Fig. 6A, and Fig. 6B along line DD of Fig. 6B. In the illustrated example of Fig. 7, the second glass core 500 includes the first CMIL cluster 616A from Fig. 6, the second CMIL cluster 616B, the third CMIL cluster 616C, an exemplary fourth CMIL cluster 702A, an exemplary fifth CMIL cluster 702B, an exemplary sixth CMIL cluster 702C, and an exemplary TGV cluster 704. In the illustrated example of Fig. 7, the body 502 includes the multiple TGVs 312 from Fig. 3. In other examples, some or all of the multiple TGVs 312 are missing. CMIL clusters 702A, 702B, and 702C are similar to CMIL clusters 616A, 616B, and 616C of Fig. 6B, unless otherwise specified. In the illustrated example of Fig. 7, CMIL clusters 616A, 616B, 616C, 702A, 702B, and 702C have the same external and internal arrangements as CMIL clusters 306A, 306B, 306C, 306D, 306E, and 306F of Fig. 3. In other examples, some or all of the CMIL clusters 616A, 616B, 616C, 702A, 702B, 702C may have different internal arrangements, and / or the CMIL clusters 616A, 616B, 616C, 702A, 702B, 702C may have a different external arrangement. In the illustrated examples of Fig. 6B and Fig. 7, the CMIL clusters 616A, 616B, 616C, 702A, 702B, 702C extend through the dielectric filler 600. In the illustrated example of Fig. 6B and Fig. 7, the CMIL clusters 616A, 616B, 616C, 702A, 702B, 702C extend continuously around and between each of the CMIL clusters 616A, 616B, 616C, 702A, 702B, 702C and the walls of the fabric 506. That is, the dielectric material 600 is formed as a single integral component around each of the CMIL clusters 616A, 616B, 616C, 702A, 702B, 702C (e.g., the dielectric material 600 extends continuously from around the first CMIL cluster 616A to around the second CMIL cluster 616B, etc.) and the walls of the fabric 506 are deposited. In the illustrated example of Fig. 3, each of the CMIL clusters 616A, 616B, 616C, 702A, 702B, 702C is spaced apart from other CMIL clusters 616A, 616B, 616C, 702A, 702B, 702C. In the illustrated example of Fig. 7, the TGV clusters 704 are arranged in the central platform 514. The TGV cluster 704 enables and improves the power output through the second glass core 500. In the illustrated example of Fig. 7, the TGV clusters 704 are arranged in a manner similar to the arrangement of the PTH cluster 308 from Fig. 3. In other examples, the TGV cluster 704 can have any other suitable arrangement. As discussed above, it is possible to fabricate smaller PTHs with a finer spacing through a glass core than through a conventional organic epoxy-based core. Accordingly, the exemplary TGV cluster 704 of Fig. 7 is smaller than the exemplary PTH cluster 308 of Fig. 3. Fig. 8 is a cross-sectional side view of an exemplary third glass core 800 implemented according to the teachings of this disclosure. In the illustrated example of Fig. 8, the third glass core 800 includes the body 502 from Fig. 5 and the dielectric filler 600 from Fig. 6. In the illustrated example of Fig. 8, the third glass core 800 includes the surfaces 516A, 516B from Fig. 5 and edges 510, 604 from Fig. 6. The third glass core 800 is similar to the second glass core 500 from Fig. 5, except that the mesh 506 from Fig. 5 is missing. Instead, in the illustrated example of Fig. 8, the edges 510, 604 of the third glass core 800 extend between the surfaces 516A, 516B and an exemplary inner wall 802. That is, the third glass core 800 includes a through cavity 804, similar to the cavity 204 of Fig. 2. In the illustrated example of Fig.In Figure 8, the dielectric filler 600 is flush with the inner wall 802 along the depth of the cavity 804 (e.g., in contact with it, etc.). In other examples, an adhesive and / or a bonding agent may be arranged between the inner wall 802 and the dielectric filler 600. In other words, the exemplary third glass core 800 combines features of the exemplary first glass core 200 from Figures 2-4 and the exemplary second glass core 500 from Figures 5-7. The exemplary IC package 100 of Fig. 1, including the first glass core 200 from Fig. 2, the second glass core 500 from Fig. 5, and the third glass core 800 from Fig. 8, can be contained in any suitable electronic component. Figs. 9-12 illustrate various examples of devices that include, or can be contained in, the IC package 100 disclosed herein. Fig. 9 is a top view of a wafer 900 and dies 902, which may be contained in the IC package 100 of Fig. 1 (e.g., as any suitable dies 108, 110). The wafer 900 contains a semiconductor material and one or more dies 902 with a circuit arrangement. Each die 902 can be a repeating unit of a semiconductor product. After the fabrication of the semiconductor product is complete, the wafer 900 can undergo a singulation process in which the dies 902 are separated from each other to provide discrete chips. The Die 902 includes one or more transistors (e.g., some of the transistors 1840 from Fig. 18, which are discussed below), a support circuit arrangement for routing electrical signals to the transistors, passive components (e.g., conductors, resistors, capacitors, inductors and / or other circuit arrangements) and / or any other components.In some examples, the Die 902 can include and / or implement a memory device (e.g., a random-access memory (RAM) device such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuitry or electronics. Several of these devices can be combined on a single die (e.g., the Die 902, etc.). For example, a memory array can consist of several memory circuits on the same die (e.g., the Die 902), such as a programmable circuit (e.g., the Processor Circuit 2002 from Fig. 20) and / or other logic circuitry. Such memory can store information for use by the programmable circuitry.The exemplary IC package 100 revealed here can be manufactured using a die-on-wafer assembly technique in which some dies are attached to a wafer 900, which contains the other dies, and the wafer 900 is subsequently singulated. Fig. 10 is a cross-sectional side view of an IC device 1000, which may be contained in the exemplary IC package 100 (e.g., in any of the dies 108, 110). One or more of the IC devices 1000 may be contained in one or more dies 902 (Fig. 9). The IC device 1000 may be formed on a die substrate 1002 (e.g., the wafer 900 from Fig. 9) and contained in a die (e.g., the die 902 from Fig. 9). The die substrate 1002 may be a semiconductor substrate comprising semiconductor materials, including, for example, n-type or p-type material systems (or a combination of both). The die substrate 1002 can, for example, contain a crystalline substrate formed using silicon base material or a silicon-on-insulator (SOI) substructure.In some examples, the die substrate 1002 may be formed using alternative materials, which may or may not be combined with silicon, including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, III-V, or IV may also be used to form the die substrate 1002. Although only a few examples of materials from which the die substrate 1002 may be formed are described here, any material that can serve as a basis for an IC device 1000 may be used. The die substrate 1002 may be part of a single die (e.g., the die 902 from Fig. 9) or a wafer (e.g., the wafer 900 from Fig. 9). The IC device 1000 can include one or more device layers 1004 arranged on and / or above the die substrate 1002. The device layer 1004 can include features of one or more transistors 1040 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1002. The device layer 1004 can, for example, have one or more source and / or drain regions (S / D regions) 1020, a gate 1022 for controlling current flow between the S / D regions 1020, and one or more S / D contacts 1024 for carrying electrical signals to / from the S / D regions 1020. The 1040 transistors may include additional features not shown for clarity, such as device isolation areas, gate contacts, and the like. The 1040 transistors are not limited to those shown in Fig.The type and configuration shown are limited and can include a wide variety of other types and configurations, such as planar transistors, non-planar transistors, or a combination of both. Non-planar transistors can include FinFET transistors, such as dual-gate or tri-gate transistors, and wrap-around or all-around-gate transistors, such as nanoband and nanowire transistors. Each 1040 transistor can include a 1022 gate, including a gate dielectric and a gate electrode. The gate dielectric can consist of a single layer or a stack of layers. The single or multiple layers can consist of silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material. The high-k dielectric material can include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and / or zinc. Examples of high-k materials that can be used in the gate dielectric include hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide and / or lead zinc cniobate.In some examples, a tempering process can be performed on the gate dielectric to improve its quality when a high-k material is used. The gate electrode can be formed on the gate dielectric and, depending on whether the 1040 transistor is intended to be a p-type metal-oxide-semiconductor (PMOS) or an n-type metal-oxide-semiconductor (NMOS) transistor, may include at least one p-type or n-type output metal. In some implementations, the gate electrode may contain a stack of two or more metal layers, where one or more metal layers are output metal layers and at least one metal layer is a filler metal layer. Additional metal layers may be included, such as a barrier layer. For a PMOS transistor, metals that can be used for the gate electrode include, among others, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide) and / or any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning).For an NMOS transistor, metals that can be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide and / or aluminum carbide) and / or any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning). In some embodiments, when viewed as a cross-section of transistor 1040 along the source-channel-drain direction, the gate electrode may comprise a U-shaped structure comprising a lower portion that is substantially parallel to the surface of the die substrate 1002 and two sidewall portions that are substantially perpendicular to the upper surface of the die substrate 1002. In other examples, at least one of the metal layers forming the gate electrode may be a planar layer that is substantially parallel to the upper surface of the die substrate 1002 and does not include any sidewall portions that are substantially perpendicular to the upper surface of the die substrate 1002. In still other examples, the gate electrode may comprise a combination of U-shaped structures and / or planar, non-U-shaped structures.For example, the gate electrode can include one or more U-shaped metal layers formed on top of one or more planar, non-U-shaped layers. In some examples, a pair of sidewall spacers can be formed on opposite sides of the gate stack to clamp the gate stack. The sidewall spacers can be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and / or silicon oxynitride. Processes for forming sidewall spacers are well known in engineering and generally involve deposition and etching processes. In some examples, multiple pairs of spacers can be used; for example, two pairs, three pairs, or four pairs of sidewall spacers can be formed on opposite sides of the gate stack. The S / D regions 1020 can be formed within the die substrate 1002 adjacent to the gate 1022 of a corresponding transistor (or transistors) 1040. The S / D regions 1020 can be formed, for example, using an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic can be ion-implanted into the die substrate 1002 to form the S / D regions 1020. A tempering process, which activates the dopants and causes them to diffuse further into the die substrate 1002, can follow the ion implantation process. In the latter process, the die substrate 1002 can first be etched to form depressions at the locations of the S / D areas 1020.An epitaxial deposition process can then be performed to fill the wells with a material used to fabricate the S / D regions 1020. In some implementations, the S / D regions 1020 can be fabricated using a silicon alloy, such as silicon germanium or silicon carbide. In some examples, the epitaxially deposited silicon alloy can be doped in situ with dopants such as boron, arsenic, or phosphorus. In some examples, the S / D regions 1020 can be formed using one or more alternative semiconductor materials, such as germanium or a material or alloy from Group III-V. In other examples, one or more layers of metal and / or metal alloys can be used to form the S / D regions 1020. Electrical signals, such as power and / or input / output (I / O) signals, can be passed to and / or from the devices (e.g., transistors 1040) of the device layer 1004 through one or more interconnection layers arranged on the device layer 1004 (illustrated in Fig. 10 as interconnection layers 1006-1010). For example, electrically conductive features of the device layer 1004 (e.g., the gate 1022 and the S / D contacts 1024) can be electrically coupled to the interconnection structures 1028 of the interconnection layers 1006-1010. The one or more interconnection layers 1006-1010 can form a metallization stack (also referred to as an "ILD stack") 1019 of the IC device 1000. The interconnection structures 1028 can be arranged within the interconnection layers 1006-1010 to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the specific configuration of interconnection structures 1028 shown in Fig. 10. Although a specific number of interconnection layers 1006-1010 is shown in Fig. 10, examples of the present disclosure feature IC devices with more or fewer interconnection layers than shown. In some examples, the interconnection structures 1028 can include conductors 1028A and / or vias 1028B filled with an electrically conductive material, such as a metal. The conductors 1028A can be arranged to route electrical signals in a direction along a plane that is substantially parallel to a surface of the die substrate 1002 on which the device layer 1004 is formed. For example, the conductors 1028A can route electrical signals in a direction into and / or out of the side from the perspective shown in Fig. 10. The vias 1028B can be arranged to route electrical signals in a direction along a plane that is substantially perpendicular to the surface of the die substrate 1002 on which the device layer 1004 is formed.In some examples, the vias 1028B can electrically couple lines 1028A of different intermediate connection layers 1006-1010. The intermediate interconnection layers 1006 to 1010 can comprise a dielectric material 1026 arranged between the intermediate interconnection structures 1028, as shown in Fig. 10. In some examples, the dielectric material 1026 arranged between the intermediate interconnection structures 1028 in different intermediate interconnection layers 1006-1010 can have different compositions; in other examples, the composition of the dielectric material 1026 can be the same between different intermediate interconnection layers 1006-1010. A first interconnection layer 1006 (designated as metal 1 or "M1") can be formed directly on the device layer 1004. In some examples, the first interconnection layer 1006 can include conductors 1028A and / or vias 1028B, as shown. The conductors 1028A of the first interconnection layer 1006 can be coupled to contacts (e.g., the S / D contacts 1024) of the device layer 1004. A second interconnect layer 1008 (designated as Metal 2 or "M2") can be formed directly on top of the first interconnect layer 1006. In some examples, the second interconnect layer 1008 may include vias 1028B to couple the conductors 1028A of the second interconnect layer 1008 to the conductors 1028A of the first interconnect layer 1006. Although the conductors 1028A and the vias 1028B are structurally delineated by a line within each interconnect layer (e.g., within the second interconnect layer 1008) for clarity, the conductors 1028A and the vias 1028B may be structurally and / or materially connected in some examples (e.g., being filled simultaneously during a dual-damascene process). A third interconnect layer 1010 (designated as Metal 3 or “M3”) (and additional interconnect layers if required) can be formed sequentially on the second interconnect layer 1008 according to similar techniques and / or configurations described in connection with the second interconnect layer 1008 or the first interconnect layer 1006. In some examples, the interconnect layers located “further up” in the metallization stack 1019 in the IC device 1000 (i.e., farther from the device layer 1004) can be thicker. The IC device 1000 can include a solder mask material 1034 (e.g., polyimide or a similar material) and one or more conductive contacts 1036 formed on the interconnection layers 1006-1010. In Fig. 10, the conductive contacts 1036 are illustrated to take the form of bond pads. The conductive contacts 1036 can be electrically coupled to the interconnection structures 1028 and configured to carry the electrical signals from the transistor(s) 1040 to other external devices. For example, solder bonds can be formed on the one or more conductive contacts 1036 to mechanically and / or electrically couple a chip containing the IC device 1000 to another component (e.g., a printed circuit board).The IC device 1000 may have additional or alternative structures to conduct the electrical signals from the interlink layers 1006-1010; for example, the conductive contacts 1036 may include other analog features (e.g., columns) that conduct the electrical signals to external components. Fig. 11 is a cross-sectional side view of an IC device assembly 1100, which may include the IC package 100 disclosed herein. In some examples, the IC device assembly corresponds to the IC package 100. The IC device assembly 1100 includes a number of components arranged on a printed circuit board 1102 (which may, for example, be a main board). The IC device assembly 1100 includes components arranged on a first surface 1140 of the printed circuit board 1102 and on an opposite second surface 1142 of the printed circuit board 1102; generally, components may be arranged on one or both surfaces 1140 and 1142. Any of the IC packages discussed below with reference to the IC device assembly 1100 may have the shape of the exemplary IC package 100 of Fig. 1. In some examples, the printed circuit board 1102 can be a printed circuit board (PCB) containing several metal layers separated by layers of dielectric material and connected by electrically conductive vias. One or more of the metal layers can be arranged in a desired circuit pattern to carry electrical signals (optionally in conjunction with other metal layers) between components connected to the printed circuit board 1102. In some examples, the printed circuit board 1102 can be a non-PCB substrate. The IC device assembly 1100 illustrated in Fig. 11 includes a package-on-interposer structure 1136, which is coupled to the first surface 1140 of the printed circuit board 1102 by coupling components 1116. The coupling components 1116 can electrically and mechanically couple the package-on-interposer structure 1136 to the printed circuit board 1102 and can include solder balls (as shown in Fig. 11), male and female parts of a socket, an adhesive, an underfill material, and / or any other suitable electrical and / or mechanical coupling structure. The package-on-interposer structure 1136 can include an IC package 1120 coupled to an interposer 1104 by coupling components 1118. The coupling components 1118 can assume any shape suitable for the application, such as the shapes discussed above with reference to the coupling components 1116. Although a single IC package 1120 is shown in Fig. 11, multiple IC packages can be coupled to the interposer 1104; in fact, additional interposers can be coupled to the interposer 1104. The interposer 1104 can provide an intermediate substrate used to bridge the printed circuit board 1102 and the IC package 1120. The IC package 1120 can, for example, be or contain a die (the die 902 from Fig. 9), an IC device (e.g. the IC device 1000 from Fig. 10), or any other suitable component.In general, the interposer 1104 can extend a connection over a greater distance or redirect one connection to another. For example, the interposer 1104 can couple the IC package 1120 (e.g., a die) to a set of conductive BGA contacts of the coupling components 1116 for coupling to the printed circuit board 1102. In the example illustrated in Fig. 11, the IC package 1120 and the printed circuit board 1102 are attached to opposite sides of the interposer 1104; in other examples, the IC package 1120 and the printed circuit board 1102 may be attached to the same side of the interposer 1104. In some examples, three or more components may be interconnected by means of the interposer 1104. In some examples, the interposer 1104 may be formed as a PCB comprising several metal layers separated by layers of dielectric material and interconnected by electrically conductive vias. In some examples, the interposer 1104 may be formed from an epoxy resin, a glass-fiber-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some examples, the interposer 1104 may be formed from alternative rigid or flexible materials, which may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other Group III-V and Group IV materials. The interposer 1104 may include metal interconnects 1108 and through-hole vias 1110, including, but not limited to, silicon through-hole vias (TSVs) 1106.The interposer 1104 can further include embedded devices 1114, which comprise both passive and active devices. Such devices can include, among others, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD devices (ESD: electrostatic discharge), and storage devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, can also be formed on the interposer 1104. The package-on-interposer structure 1136 can take the form of any package-on-interposer structure known in the art. The IC device assembly 1100 can include an IC package 1124, which is coupled to the first surface 1140 of the printed circuit board 1102 by coupling components 1122. The coupling components 1122 can take the form of any of the examples discussed above with reference to the coupling components 1116, and the IC package 1124 can take the form of any of the examples discussed above with reference to the IC package 1120. The IC device assembly 1100 illustrated in Fig. 11 comprises a case-on-case structure 1134, which is coupled to the second surface 1142 of the printed circuit board 1102 by coupling components 1128. The case-on-case structure 1134 can include a first IC package 1126 and a second IC package 1132, which are coupled to each other by coupling components 1130 such that the first IC package 1126 is arranged between the printed circuit board 1102 and the second IC package 1132. The coupling components 1128, 1130 can take the form of any of the coupling component 1116 examples discussed above, and the IC packages 1126, 1132 can take the form of any of the IC package 1120 examples discussed above. The package-on-package structure 1134 can be configured according to any package-on-package structure known in the art. Fig. 12 is a block diagram of an exemplary electrical device 1200, which may include one or more of the exemplary IC packages 100. For example, any suitable components of the electrical device 1200 may include one or more of the device assemblies 1100, IC devices 1000, or dies 902 disclosed herein and may be arranged in the exemplary IC package 100. A number of components are illustrated in Fig. 12 as being included in the electrical device 1200; however, any one or more of these components may be omitted or duplicated as appropriate for the application. In some examples, some or all of the components included in the electrical device 1200 may be mounted on one or more mainboards. In some examples, some or all of these components may be fabricated on a single system-on-a-chip (SoC) die. In addition, in various examples, the electrical device 1200 may not include any of the components illustrated in Fig. 12, but may include an interface circuit arrangement for coupling with the one or more components. For example, the electrical device 1200 may not include a display 1206; however, it may include a display interface circuit arrangement (e.g., a connector and driver circuit arrangement) to which a display 1206 can be coupled. In another set of examples, the electrical device 1200 may not include an audio input device 1218 (e.g., microphone) or an audio output device 1208 (e.g., loudspeaker, headphones, earphones, etc.); however, it may include an audio input or output device interface circuit arrangement (e.g., a connector and driver circuit arrangement).a connector and a support circuit arrangement) to which an audio input device 1218 or an audio output device 1208 can be coupled. The electrical device 1200 can include a programmable circuit arrangement 1202 (e.g., one or more processing devices). The programmable circuit arrangement 1202 can include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or other suitable processing devices. The electrical device 1200 can include a memory 1204, which itself can include one or more memory devices, such as volatile memory (e.g., dynamic random-access memory (DRAM)), non-volatile memory (e.g.,Read-only memory (ROM), flash memory, solid-state memory, and / or a hard disk. In some examples, memory 1204 may include a memory that shares a die with programmable circuit arrangement 1202. This memory may be used as cache memory and may include embedded dynamic random-access memory (eDRAM) or magnetic spin transfer torque random-access memory (STT-MRAM). In some examples, the electrical device 1200 may include a communication chip 1212 (e.g., one or more communication chips). For example, the communication chip 1212 may be configured to manage wireless communications for the transmission of data to and from the electrical device 1200. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data through a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated devices do not contain wires, although this may well be the case in some embodiments. The 1212 communication chip can implement any number of wireless standards or protocols, including, but not limited to, IEEE standards (IEEE - Institute for Electrical and Electronic Engineers) such as WiFi (IEEE 802.11 family), IEEE 802.16 standards (e.g., the IEEE 802.16-2005 amendment), the LTE project (LTE - Long-Term Evolution) along with any modifications, updates and / or revisions (e.g., the Advanced LTE project, the UMB project (UMB - Ultra Mobile Broadband) (also known as "3GPP2"), etc.). Broadband Wireless Access (BWA) networks compliant with IEEE 802.16 are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass compliance and interoperability tests for the IEEE 802.16 standards.The 1212 communication chip can operate according to a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The 1212 communication chip can operate according to Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The 1212 communication component can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO) and derivatives thereof, as well as any other wireless protocols designated as 3G, 4G, 5G, and beyond. The 1212 communication chip can operate according to other wireless protocols in other examples.The electrical device 1200 may have an antenna 1222 to support wireless communications and / or to receive other wireless communications (such as AM or FM radio transmissions). In some examples, the 1212 communication chip can manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., Ethernet). As mentioned above, the 1212 communication chip can contain multiple communication chips. For example, a first 1212 communication chip can be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and a second 1212 communication chip can be dedicated to longer-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some examples, a first 1212 communication chip can be dedicated to wireless communications and a second 1212 communication chip can be dedicated to wired communications. The electrical device 1200 may include a battery / power circuit arrangement 1214. The battery / power circuit arrangement 1214 may include one or more energy storage devices (e.g., batteries or capacitors) and / or a circuit arrangement for coupling components of the electrical device 1200 to a power source separate from the electrical device 1200 (e.g., the AC mains supply). The electrical device 1200 can include a display 1206 (or a corresponding interface circuit arrangement, as discussed above). The display 1206 can include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display. The electrical device 1200 can include an audio output device 1208 (or a corresponding interface circuit arrangement, as discussed above). The audio output device 1208 can include any device that generates an acoustic indicator, such as a loudspeaker, headphones, or earphones. The electrical device 1200 can include an audio input device 1218 (or a corresponding interface circuit arrangement, as discussed above). The audio input device 1218 can include any device that generates a signal representing a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments with a Musical Instrument Digital Interface (MIDI) output). The electrical device 1200 can include a GPS circuit arrangement 1216. The GPS circuit arrangement 1216 can communicate with a satellite-based system and receive a location data for the electrical device 1200, as is known in the art. The electrical device 1200 can include any other output device 1210 (or a corresponding interface circuit arrangement, as discussed above). Examples of the other output device 1210 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for delivering information to other devices, or an additional storage device. The electrical device 1200 can include any other input device 1220 (or a corresponding interface circuit arrangement, as discussed above). Examples of the other input device 1220 can include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick-response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader. The electrical device 1200 can have any desired form factor, such as a handheld or mobile electrical device (e.g., a mobile phone, a smartphone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), an electrical desktop device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or an electrical wearable device. In some examples, the electrical device 1200 can be any other electronic device that processes data. The terms "including" and "comprising" (and all forms and tenses thereof) are used here as open terms. Whenever a claim uses any form of "include" and "comprise" (e.g., includes, encompasses, encompassing, containing, exhibiting, etc.) as a preamble or in a claim recitation of any kind, it should be understood that additional elements, terms, etc., may be present without falling outside the scope of protection of the claim or recitation in question. As used herein, when the expression "at least" is used as the transitional phrase in, for example, a claim preamble, it is open in the same way as the terms "comprising" and "comprising" are open.The term "and / or," when used in a form such as A, B and / or C, refers to any combination or subset of A, B, C, such as (1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) B with C, or (7) A with B and with C. As used here in the context of describing structures, components, objects, and / or things, the expression "at least one of A and B" is intended to refer to transformations that include any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used here in the context of describing structures, components, elements, objects, and / or things, the expression "at least one of A or B" is intended to refer to transformations that include any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.As used here in the context of describing the performance or execution of processes, instructions, actions, activities, etc., the phrase "at least one of A and B" is intended to refer to implementations that include any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used here in the context of describing the performance or execution of processes, instructions, actions, activities, etc., the phrase "at least one of A or B" is intended to refer to implementations that include any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein, singular references (e.g., "a," "an," "one," "first," "second," etc.) do not preclude a plural. The term "a" object, as used in this document, refers to one or more of that object. The terms "a," "one or more," and "at least one" are used interchangeably herein. Furthermore, although listed individually, a variety of means, elements, or actions may be implemented by, for example, the same entity or object. In addition, although individual features may be included in different examples or claims, they may potentially be combined, and inclusion in different examples or claims does not indicate that a combination of features is not feasible and / or advantageous. As used here, the term "above," unless otherwise specified, describes the relationship of two parts relative to the Earth. A first part is above a second part if the second part has at least one part between the Earth and the first part. Likewise, as used here, a first part is "below" a second part if the first part is closer to the Earth than the second part. As noted above, a first part may be above or below a second part, with one or more of: other parts in between, without other parts in between, with the first and second parts in contact, or without the first and second parts being in direct contact with each other. Notwithstanding the foregoing, when referring to a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, and / or an integrated circuit (IC) package containing a semiconductor die during fabrication or manufacturing, “above” does not refer relative to the ground, but instead refers to an underlying substrate on which relevant components are fabricated, assembled, mounted, supported, or otherwise provided. Therefore, as used herein and unless otherwise specified or implied from the context, a first component within a semiconductor die (e.g., a transistor or other semiconductor device) is “above” a second component within the semiconductor die if the first component is further supported by a substrate (e.g., a substrate) during fabrication / manufacturing.a semiconductor wafer) is located further away than the second component on which the two components are fabricated or otherwise provided. Unless otherwise specified or implied from the context, a first component within an IC package (e.g., a semiconductor chip) is likewise located “above” a second component within the IC package during fabrication if the first component is located farther away from a printed circuit board (PCB) on which the IC package is to be mounted or attached. It is understood that semiconductor devices are frequently used in a different orientation than their orientation during fabrication. Thus, when referring to a semiconductor device (e.g.,a transistor), a semiconductor die containing a semiconductor device, and / or an integrated circuit (IC) package containing a semiconductor die, while in one use the definition of 'over' in the preceding paragraph (i.e. the term 'over' describes the relationship of two parts relative to the ground) is expected to be determined based on the context of use. As used in this patent, the statement that any part (e.g., a layer, a film, a region, an area, or a plate) is located on another part in any way (e.g., is positioned on, is located on, or is formed on, etc.) indicates that the referenced part is either in contact with the other part or that the referenced part is located above the other part, with one or more intervening parts in between. As used herein, connection references (e.g., attached, coupled, connected, and joined) can include intermediate elements between the elements referenced by the connection reference and / or relative motion between those elements, unless otherwise specified. Therefore, connection references do not necessarily imply that two elements are directly connected and / or in a fixed relationship to each other. As used here, the statement that any part is in "contact" with another part is defined as meaning that there is no intermediate element between the two parts. Unless specifically stated otherwise, descriptors such as "first," "second," "third," etc., are used herein without implying or otherwise indicating any significance of priority, physical order, arrangement in a list, and / or sequence, but are used merely as labels and / or arbitrary names to distinguish elements for the purpose of facilitating understanding of the disclosed examples. In some examples, the descriptor "first" may be used to refer to an element in the detailed description, while the same element in a claim may be referred to by a different descriptor, such as "second" or "third." In these cases, it is understood that such descriptors are used solely to uniquely identify those elements within the context of the discussion (e.g.,within a claim) where the elements might otherwise share the same name, for example. As used here, "approximately" and "about" modify their subjects / values ​​to account for the potential presence of variations that occur in real-world applications. For example, the terms "approximately" and "about" can modify dimensions that, due to manufacturing tolerances and / or other imperfections in the real world, are not exact as understood by the average person. For example, "approximately" and "about" can indicate that such dimensions may fall within a tolerance range of + / - 10%, unless otherwise specified here. As used herein, “essentially real-time” refers to a near-instantaneous occurrence, acknowledging that real-world delays for data processing, transmission, etc., may occur. Thus, unless otherwise specified, “essentially real-time” refers to real-time + 1 second. As used herein, the term “in communication”, including variations thereof, includes direct communication and / or indirect communication via one or more intermediate components and does not require direct physical (e.g., wired) communication and / or constant communication, but instead additionally includes selective communication with periodic intervals, scheduled intervals, aperiodic intervals and / or one-off events. As used herein, “programmable circuit arrangement” is defined to include (i) one or more specialized electrical circuits (e.g., an application-specific integrated circuit (ASIC)) structured to perform one or more specific operations and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and / or (ii) one or more general-purpose semiconductor-based electrical circuits programmable with instructions to perform one or more specific functions and / or operations and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of a programmable circuit arrangement include programmable microprocessors such as central processing units (CPUs),that can execute first instructions to perform one or more operations and / or functions, field-programmable gate arrays (FPGAs) that can be programmed with second instructions to configure and / or structure the FPGAs to instantiate one or more operations and / or functions according to the first instructions, graphics processing units (GPUs) that can execute first instructions to perform one or more operations and / or functions, digital signal processors (DSPs) that can execute first instructions to perform one or more operations and / or functions, XPUs, network processing units (NPUs), one or more microcontrollers that can execute first instructions to perform one or more operations and / or functions,and / or integrated circuits such as application-specific integrated circuits (ASICs). For example, an XPU can be implemented by a heterogeneous computing system that includes several types of programmable circuit arrangements (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and / or any combination thereof), and orchestration technology (e.g., application programming interface(s) (API(s)) that can assign computational task(s) to any of the several types of programmable circuit arrangements that are suitable and available to perform the computational task(s). As used herein, an integrated circuit / circuit assembly is defined as one or more semiconductor packages containing one or more circuit elements such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more components consisting of an ASIC, an FPGA, a chip, a microchip, a programmable logic assembly, a semiconductor substrate coupling multiple circuit elements, a system-on-a-chip (SoC), etc. From the foregoing, it is understood that exemplary systems, devices, manufactured articles, and processes have been disclosed that reduce the stress experienced by glass cores during loading. Examples disclosed herein include interfaces that reduce stress concentrations in the power-dissipating regions of glass cores. Examples disclosed herein enable the packaging of power-dissipating components, such as CMILs, PTHs, and TGVs, while maintaining the structural integrity of the glass core. Examples disclosed herein reduce the Seware failure rate of glass cores, thereby increasing part yield and reducing manufacturing costs. Glass cores with embedded power output components are disclosed here. Further examples and combinations thereof are included below: Example 1 includes a device with a glass layer comprising an opening, a dielectric material inside the opening, a first cluster of inductances extending through the dielectric material, and a second cluster of inductances extending through the dielectric material, wherein the second cluster is spaced apart from the first cluster, and the dielectric material extends continuously from around the first cluster to the second cluster. Example 2 includes the setup according to a previous example, wherein the opening through the glass layer extends from a first surface of the glass layer to a second surface of the glass layer, the second surface being opposite the first surface. Example 3 includes the setup according to a previous example, wherein the opening includes an inner surface and the dielectric material includes an outer surface that abuts the inner surface. Example 4 includes the setup according to a previous example, which further includes a glass wall between the first and second clusters, wherein the dielectric material extends around an upper end and / or a lower end of the glass wall. Example 5 includes the setup according to a previous example, which further includes a transition area extending between the glass wall and the glass layer. Example 6 includes the setup according to a previous example, where the transition surface is a rounded edge. Example 7 includes the setup according to a previous example, wherein a first upper surface of the dielectric material is flush with a second upper surface of the dielectric material. Example 8 includes a device comprising a semiconductor die, a substrate supporting the semiconductor die, the substrate comprising a glass core comprising a body having an opening, a dielectric material within the opening, a first cluster of inductances extending through the dielectric material, wherein adjacent inductances in the first cluster are spaced a first distance apart, and a second cluster of inductances extending through the dielectric material, wherein a first inductance in the first cluster is at least as close to a second inductance in the second cluster as any other inductance in the first cluster is to any inductance in the second cluster, wherein the first inductance is spaced a second distance from the second inductance, the second distance being greater than the first distance.the dielectric material extends continuously between the first inductor and the second inductor. Example 9 includes the apparatus according to a previous example, wherein the first cluster of inductors and the second cluster are arranged in a row, the row further comprising a third cluster of inductors offset from the first cluster of inductors and the second cluster of inductors. Example 10 includes the device according to a previous example, which further includes several plated through-holes aligned with the third cluster, the plated through-holes extending through the dielectric material. Example 11 includes the apparatus according to a previous example, which further includes a glass fabric arranged between the first cluster of inductors and the second cluster of inductors. Example 12 includes the device according to a previous example, wherein the body includes a first outer surface and a second outer surface opposite the first outer surface, wherein the fabric is recessed by the first outer surface and the second outer surface. Example 13 includes the device according to a previous example, which further includes a curved surface extending between the first outer surface and the glass core. Example 14 includes the device according to a previous example, wherein the first outer surface is flush with a third outer surface of the glass core. Example 15 includes the device according to a previous example, wherein the opening includes an inner surface, the dielectric material includes an outer surface abutting the inner surface, and the inner surface is straight-walled. Example 16 includes a device comprising a glass core, a structural section, a power output section, and an interface between the structural section and the power output section, wherein the interface comprises at least one of (i) a material interface or (ii) a curved transition surface between a recessed section of the power output section and an outer surface of the glass core, and includes multiple coaxial metal inductance loop clusters in the power output section. Example 17 includes the setup according to a previous example, wherein the multiple coaxial metal inductance loop clusters are arranged in a first row and a second row, the first row containing a first cluster, a second cluster and a third cluster, the second cluster being offset from the first cluster and the second cluster. Example 18 includes the setup according to one of the preceding examples, wherein the outer surface is a first outer surface and a second outer surface of the power output section is flush with the first outer surface. Example 19 includes the setup according to a previous example, wherein the power output section includes a dielectric filler and the recessed section with the dielectric filler is oriented in a direction normal to the outer surface. Example 20 includes the device according to a preceding example, wherein the structural section has a first thickness and the recessed section has a second thickness that is at least 10% of the first thickness. The following claims are hereby incorporated into this detailed description by reference. Although certain exemplary systems, devices, articles, and methods have been disclosed herein, the scope of protection of this patent is not limited thereto. On the contrary, this patent covers all systems, devices, articles, and methods that are reasonably within the scope of protection of the claims of this patent.

Claims

Apparatus: a glass layer comprising an opening; a dielectric material within the opening; a first cluster of inductances extending through the dielectric material; and a second cluster of inductances extending through the dielectric material, the second cluster being spaced apart from the first cluster, the dielectric material extending continuously from around the first cluster to around the second cluster. Device according to claim 1, wherein the opening through the glass layer extends from a first surface of the glass layer to a second surface of the glass layer, the second surface being opposite the first surface. Device according to claim 2, wherein the opening includes an inner surface and the dielectric material includes an outer surface that abuts the inner surface. The device according to claim 1, further comprising a glass wall between the first and the second cluster, wherein the dielectric material extends around an upper end and / or a lower end of the glass wall. Device according to claim 4, which further includes a transition surface extending between the glass wall and the glass layer. Device according to claim 5, wherein the transition surface is a rounding. Device according to one of claims 1-6, wherein a first upper surface of the dielectric material is flush with a second upper surface of the dielectric material. Device comprising: a semiconductor die; a substrate supporting the semiconductor die, the substrate comprising: a glass core comprising: a body including an opening; a dielectric material within the opening; a first cluster of inductances extending through the dielectric material, with adjacent inductances in the first cluster being spaced a first distance apart;and a second cluster of inductances extending through the dielectric material, wherein a first inductance in the first cluster is at least as close to a second inductance in the second cluster as any other inductance in the first cluster is to any inductance in the second cluster, wherein the first inductance is spaced a second distance from the second inductance, the second distance being greater than the first distance, and wherein the dielectric material extends continuously between the first inductance and the second inductance. Device according to claim 8, wherein the first cluster of inductors and the second cluster are arranged in a row, the row further comprising a third cluster of inductors offset from the first cluster of inductors and the second cluster of inductors. Device according to claim 9, further comprising several plated through-holes aligned with the third cluster, wherein the plated through-holes extend through the dielectric material. Device according to one of claims 8-10, further comprising a glass fabric arranged between the first cluster of inductors and the second cluster of inductors. Device according to claim 11, wherein the body comprises a first outer surface and a second outer surface opposite the first outer surface, wherein the fabric is recessed by the first outer surface and the second outer surface. Device according to claim 12, further comprising a curved surface extending between the first outer surface and the glass core. Device according to claim 12, wherein the first outer surface is flush with a third outer surface of the glass core. Device according to one of claims 9-14, wherein the opening includes an inner surface, the dielectric material includes an outer surface that abuts the inner surface, and the inner surface is straight-walled. A device comprising: a glass core comprising: a structural section; a power output section; and an interface between the structural section and the power output section, wherein the interface comprises at least one of (i) a material interface or (ii) a curved transition surface between a recessed section of the power output section and an outer surface of the glass core; and multiple coaxial metal inductance loop clusters in the power output section. The apparatus according to claim 16, wherein the multiple coaxial metal inductance loop clusters are arranged in a first row and a second row, the first row comprising: a first cluster; a second cluster; and a third cluster, wherein the second cluster is offset from the first cluster and the second cluster. Device according to one of claims 16-17, wherein the outer surface is a first outer surface and a second outer surface of the power output section is flush with the first outer surface. Device according to one of claims 16-18, wherein the power output section includes a dielectric filler and the recessed section with the dielectric filler is oriented in a direction normal to the outer surface. Device according to claim 19, wherein the structural section has a first thickness and the recessed section has a second thickness which is at least 10% of the first thickness.

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