Method for manufacturing a semiconductor device

Abstract

A method for manufacturing a semiconductor device, wherein the method comprises the following steps: (a) Providing a base (1) formed by a silicon carbide semiconductor of a first conductivity type; forming a resist structure (210) as a mask, wherein the resist structure (210) is a photoresist; (b) Forming a depression structure (207) surrounding an element area based on (1) using the resist structure (210); . (d) Performing a shrinkage treatment over the resist structure (210) after step (b); and (c) Forming a protective ring (206) of a second conductivity type in a well bottom surface (15) and a well side surface (20) in the well structure (207) by dopant injection through the resist structure (210) after step (d), wherein an edge region of the depression structure (207) is covered with the protective ring (206), and wherein the depression structure (207) and the protective ring (206) are formed using the resist structure (210) as a single mask.

Description

Technical field

[0001] The present invention relates to a method for manufacturing a semiconductor device and in particular to a method for manufacturing a termination structure. State of the art

[0002] The next generation of switching element, which will achieve high voltage resistance, low loss and high heat resistance, is being considered as a semiconductor element using silicon carbide (SiC), with the application of which is expected in a power semiconductor device, such as an inverter.

[0003] However, a large number of problems need to be solved with a SiC semiconductor device. One problem is the deterioration of the dielectric strength property of the semiconductor device, which is caused by electric field concentration in a termination region of the semiconductor device (e.g., one end of a Schottky electrode in a Schottky diode or one end of a pn junction in a pn diode or a MOSFET (metal-oxide-semiconductor field-effect transistor)).

[0004] A typical example of a termination structure that attenuates an electric field generated in the termination region of the semiconductor device is a guard ring structure, a JTE structure (Junction Termination Extension), an FLR structure (Field Limiting Ring), and the like. All of these structures are dopant diffusion layers that surround a region of the element.

[0005] In general, the JTE structure is designed to reduce an electric surface field, and it features a structure in which the dopant concentration is gradually reduced from the termination region of the semiconductor device outwards. In contrast, the FLR structure is formed by a multitude of dopant diffusion layers with the same concentration.

[0006] For example, the following patent document 1 discloses a termination structure in which a protective ring and a transition termination extension are combined. In the termination structure disclosed in patent document 1, the transition termination extension is provided on an outer surface of the protective ring with a lower dopant concentration than in the protective ring.

[0007] Furthermore, patent document 1 proposes a technique for forming the guard ring and the transition termination extension under a recess structure provided on a surface of a semiconductor layer in order to increase the distance between the lower ends of the guard ring and the transition termination extension, where there is a probability of an electric field concentration occurring, and the surface of the semiconductor layer, and in this way to further weaken an electric field at the surface of the semiconductor layer.

[0008] Patent document 2 discloses a method for manufacturing a high-voltage diode.

[0009] Patent document 3 relates to a semiconductor device with a Schottky barrier.

[0010] Patent document 4 describes a semiconductor device with an active area and a region surrounding it.

[0011] Patent document 5 describes a semiconductor device with a surface barrier.

[0012] Patent document 6 teaches a novel structure of a p-doped region. State-of-the-art documents, patent documents Patent document 1: International Publication No. WO 2009 / 116444 A1 Patent document 2: German patent application no. DE 100 47 152 A1 Patent document 3: Japanese patent application JP 2006 - 173 255 A Patent document 4: US patent application US 2002 / 0 100 935 A1 Patent document 5: Japanese patent application JP S63-138 772 A Patent document 6: Japanese patent application JP 2006 - 186 134 A Brief description of the invention Problems to be solved with the invention

[0013] As described above, in the semiconductor device according to the prior art, two types of injection conditions of the guard ring / JTE structure are used to create a structure with dielectric strength.

[0014] To implement the guard ring / JTE structure under the two injection conditions, separate steps are required to create masks for injecting dopants into the corresponding positions. Furthermore, to create these masks, it is necessary to form alignment markers as references for aligning the mask positions in a preliminary step. These alignment markers are created by etching the semiconductor surface.

[0015] As mentioned above, the prior art semiconductor device requires at least three masks (for forming an alignment marker, a guard ring, and a JTE or junction termination extension), and the dopants must be injected under different conditions. This increases the number of steps and leads to problems such as increased variability, yield reductions, and rising costs.

[0016] As a method to overcome these problems, it is proposed to use only a single mask. In other words, the termination structure is first defined such that it only includes the protective ring or an FLR (field limiting ring), with a single injection step. Furthermore, a step to create an alignment mark and a step to create the injection mask are combined into a single step, so that the termination structure can be formed using a single mask.

[0017] These semiconductor devices use a single type of injection condition, and therefore a well structure is provided for the termination structure into which dopants are injected at a single concentration.

[0018] In the case of a SiC device, the injected dopants hardly diffuse but are activated. When using a single injection condition, which cannot be optimized compared to two injection conditions in the guard ring / JTE structure (in addition to the guard ring-only structure), a dopant layer with a high concentration is formed, particularly in the immediate vicinity of the well structure. Furthermore, the guard ring is formed at a relatively high dopant concentration to ensure the element's dielectric strength characteristics.

[0019] Thus, a problem arises in that the growth of a depletion layer in the dopant layer is reduced, thereby increasing the likelihood of a high electric field being generated when a high voltage is applied to a cathode.

[0020] In particular, the problem arises that dielectric breakdown occurs when a high electric field is generated in a corner or edge region of the cavity structure and this field exceeds the breakdown strength of, for example, a polyimide layer as the surface-sealing material. Furthermore, in some cases, the diffusion of the injected dopants is insufficient, and the edge region of the cavity structure is not covered by the injection layer.

[0021] The present invention is intended to solve the problems described above, and one objective of the invention is to provide a semiconductor device with which the generation of a high electric field can be suppressed and the occurrence of dielectric breakdown can be prevented, as well as a method for manufacturing the same. Means of solving the problems

[0022] The method for manufacturing a semiconductor device according to the present invention comprises the following steps: (a) Providing a base formed by a silicon carbide semiconductor of a first conductivity type, (b) Forming a depression structure surrounding an element area, based on a resist structure, and (c) Forming a dopant layer of a second conductivity type in a well bottom surface and a well side surface in the well structure by dopant injection through the resist structure after step (b), wherein a corner or edge region of the well structure is covered with the dopant layer. Effects of the invention

[0023] The method for manufacturing a semiconductor device according to the present invention comprises the following steps: (a) Providing a base formed by a silicon carbide semiconductor of a first conductivity type, (b) Forming a depression structure surrounding an element area, based on a resist structure, and (c) Forming a dopant layer of a second conductivity type in a well bottom surface and a well side surface in the well structure by dopant injection through the resist structure after step (b), wherein a corner or edge region of the well structure is covered with the dopant layer.

[0024] Consequently, even when using silicon carbide semiconductors, which hardly cause diffusion of the injected dopants, it is possible to specify a structure in which the edge region of the well structure is sufficiently covered with the dopant layer. This ensures the maintenance of stable dielectric strength in the semiconductor device.

[0025] These and other objectives, features, aspects and advantages of the present invention will become even clearer from the following detailed description of the present invention in conjunction with the accompanying drawings. Brief description of the drawings

[0026] The drawings show: Fig. 1 a sectional view to illustrate a method for manufacturing a semiconductor device according to a first embodiment of the present invention; Fig. 2 a sectional view to illustrate the method for manufacturing a semiconductor device according to the first embodiment of the present invention; Fig. 3 a sectional view to illustrate the method for manufacturing a semiconductor device according to the first embodiment of the present invention; Fig. 4 a sectional view to illustrate a structure of the semiconductor device according to the first embodiment of the present invention; Fig. 5 a sectional view to illustrate a method for manufacturing a semiconductor device according to a second embodiment of the present invention; Fig. 6 a sectional view to illustrate the method for manufacturing a semiconductor device according to the second embodiment of the present invention; Fig. 7 a sectional view to illustrate a structure of the semiconductor device according to the second embodiment of the present invention; Fig. 8 a sectional view to illustrate a method for manufacturing a semiconductor device according to a third embodiment of the present invention; Fig. 9 a sectional view to illustrate a structure of the semiconductor device in a presupposed technique according to the present invention; Fig. 10 a view illustrating the structure of a termination region of a semiconductor device according to a fourth embodiment of the present invention; Fig. 11 a view illustrating a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention; Fig. 12 a view illustrating the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention; Fig. 13 a view illustrating the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention; Fig. 14 a view illustrating the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention; Fig. 15 a view illustrating the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention; Fig. 16 a view illustrating the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention; Fig. 17 a view illustrating the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention; Fig. 18 a view illustrating the structure of a semiconductor device according to a fifth embodiment of the present invention; Fig. 19 a view illustrating a method for manufacturing a semiconductor device according to the fifth embodiment of the present invention; Fig. 20 a view illustrating the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention; Fig. 21 a view illustrating the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention; Fig. 22 a view illustrating the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention; Fig. 23 a view illustrating the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention; Fig. 24 a view illustrating the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention; Fig. 25 a view to illustrate a structure of a semiconductor device according to a sixth embodiment of the present invention; Fig. 26 a view illustrating a method for manufacturing a semiconductor device according to the sixth embodiment of the present invention; and Fig. 27 a sectional view to illustrate the structure of the semiconductor device according to the sixth embodiment of the present invention. Embodiments for carrying out the invention A. First embodiment

[0027] To save energy in a power electronics device, such as an inverter, it is necessary to reduce the loss of a semiconductor switching element, such as an insulated gate bipolar transistor (IGBT) or a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0028] The loss is determined by the on-resistance of the element. Therefore, in the present invention, silicon carbide (SiC) is used to reduce the on-resistance.

[0029] When a depression structure is used on a termination structure, a semiconductor device is formed, as described in Fig. 9 is shown.

[0030] More precisely, an n-conducting epitaxial layer 102 is formed on an n+-conducting substrate 101, and a metal layer 106 and furthermore a backside electrode 109 are formed on a backside surface of the n+-conducting substrate 101.

[0031] Furthermore, the n-conducting epitaxial layer 102 possesses a structure (a depression structure) that is formed by introducing a protective ring injection layer 103 into the n-conducting epitaxial layer 102. Additionally, a metal layer 105 is formed by covering part of the protective ring injection layer 103.

[0032] In addition, a surface electrode 107 is formed on the metal layer 105, and a polyimide 108 is formed over the metal layer 105, the protective ring injection layer 103 and the n-conducting epitaxial layer 102.

[0033] The semiconductor device has a termination structure obtained by injecting dopants of a specific concentration into the well structure. The well structure is formed by etching, creating an orientation marker (not shown).

[0034] In the case of a SiC device, the injected dopants hardly diffuse, but are activated. This results in the formation of a dopant layer with a high concentration in the immediate vicinity of the well structure. Furthermore, the protective ring is formed with a relatively high dopant concentration to ensure the dielectric strength characteristics of the element.

[0035] As a result, one problem is that the growth of a depletion layer in the dopant layer is reduced, and thus there is a probability that a high electric field will be generated when a high voltage is applied to a cathode.

[0036] In particular, a problem arises when a high electric field is generated in a corner or edge region on the bottom surface of a cavity, and this field exceeds the breakdown strength of, for example, a polyimide layer. Furthermore, in some cases, the diffusion of the injected dopants is insufficient, and the edge region of the cavity structure cannot be covered by the injection layer.

[0037] The following describes exemplary embodiments according to the present invention which can solve the problems described above. A-1. Manufacturing process

[0038] The Fig. Figures 1 to 4 show sectional views illustrating a method for fabricating a semiconductor device using SiC (a SiC Schottky diode, hereinafter also referred to as a SiC SBD). The fabrication process is described below.

[0039] First, as in Fig. Figure 1 shows an n-type epitaxial layer 2 formed on the surface of a low-resistance n-type SiC substrate (where an n+-type substrate 1 serves as the base) by a chemical vapor deposition (CVD) process. The concentration of dopants in the n-type epitaxial layer 2 is, for example, approximately 5 × 10⁻⁶. 15 cm -3 .

[0040] Next, a marker is formed on the n-conducting epitaxial layer 2 to ensure alignment in a photomechanical step (not shown). An alignment marker is formed by structuring a resist in a desired region and by etching the n-conducting epitaxial layer 2, for example, by reactive ion etching (RIE).

[0041] It should be noted that in the first embodiment, the creation of the alignment mark and the step to create the finishing structure are performed using the same mask. Since the creation of the alignment mark and the creation of the finishing structure are performed using the same mask, the number of steps can be reduced.

[0042] First, a resist structure is formed. For example, a positive resist material using a novolac resin as the base resin material or the like is used to perform a heat treatment for 60 seconds at a temperature of 110 °C.

[0043] A development process is then carried out. For one development condition, for example, a solution containing 2.8% by weight of tetramethylammonium hydroxide is used as an alkaline developing solution, with a development time of 100 seconds. After development, the film is rinsed with pure water for 60 seconds.

[0044] These steps form a resist structure 13. The resist structure 13 formed in this way has a sidewall angle (an angle formed between a side face of the resist structure 13 and a surface of the n+-conducting substrate 1 made of SiC) of approximately 82° at one end, with a chamfered shape at the end.

[0045] The resist structure 13 is used to carry out the etching process over the n-conducting epitaxial layer 2 (see Fig. 2) In the case where the etching process is carried out by reactive ion etching, the etching conditions specify, for example, the use of sulfur hexafluoride (SF6) as the etching gas, with a specified gas pressure of 1 Pa, a flow rate of approximately 50 sccm (standard cubic centimeters / minute), a radio frequency power of approximately 700 W to 900 W, and a substrate bias power of approximately 50 W to 70 W. A selectivity ratio of, for example, 0.5 is specified for the etching process.

[0046] Since the resist structure 13 assumes a beveled shape at the end (see Fig. 2) The end of the resist structure 13 can be easily etched. Thus, it is possible to increase the retreat amount at the end of the resist structure 13, and a depression structure 14 with a chamfered shape is formed in the n+-conducting substrate 1 made of SiC.

[0047] In particular, a depression side surface 20 of the depression structure 14 is inclined, and a corner or edge region 21 in the depression structure 14 (an interface between a depression bottom surface 15 and the depression side surface 20) is formed at an obtuse angle. Since the depression structure 14 is formed by creating the capping structure through the injection of a dopant layer described below, it is formed to surround an element region.

[0048] This is the in Fig. The chamfer width shown in Figure 2 is desirable to be equal to or greater than 0.2 µm, and the recess depth is desirable to be equal to or greater than 0.1 µm. Furthermore, the Fig. The edge region 21 shown in Figure 2 is preferably formed with a curvature, and furthermore, the radius of curvature of the same is preferably equal to or greater than 0.1 µm. As a method for forming the curvature, sacrificial oxidation is preferably carried out over a surface after ion implantation has been performed, as will be described below.

[0049] To reduce the electric field concentration at one end of the device, thereby ensuring a stable voltage withstand in the kilovolt class, a termination structure is next formed that encloses an element area in which a semiconductor element is to be formed (see Fig. 3) The termination structure is formed by injecting dopants through the resist structure 13, and e.g. Al ions are implanted to form a p-conducting protective ring injection layer 3.

[0050] The Al ions are implanted at room temperature with an energy of 40 keV to 800 keV, for example to achieve an implantation amount of 1 × 10 17 up to 8 × 10 17 cm -3 and to specify an implantation depth of 0.6 µm to 1.0 µm as implantation conditions. Although in Fig. Not shown in Figure 3, it should be noted that a large number of protective ring injection layers 3 can be formed surrounding the element area.

[0051] In the first embodiment, the recess side surface 20 assumes a suitable chamfer shape, as shown in Fig. 3 is shown. For this reason, for example, even when using SiC, which hardly causes diffusion of dopants, it is possible to implement a structure in which the edge region 21 of the well structure 14 is sufficiently covered with the protective ring injection layer 3.

[0052] Furthermore, by specifying the edge region 21 such that it has an obtuse angle, it is possible to prevent the electric field concentration in the edge region 21. Consequently, it is possible to maintain a stable dielectric strength in the semiconductor device.

[0053] Following this, a semiconductor device 100 with a structure such as that found in cross-section in Fig. Figure 4 shows that it is finished using the same manufacturing process as in the prior art.

[0054] More precisely, a metal layer 6 and a backside electrode 9 are formed on a rear surface of the n+-conducting substrate 1.

[0055] Furthermore, the resist structure 13 is removed, and the protective ring injection layer 3 is partially covered, so that a metal layer 5 is formed.

[0056] Furthermore, a surface electrode 7 is formed on the metal layer 5, and polyimide 8 is formed over the metal layer 5, the protective ring injection layer 3 and the n-conducting epitaxial layer 3.

[0057] As described above, in the method for manufacturing a semiconductor device according to the present embodiment, a structure is used in which the edge region 21 of the recess structure 14, as the termination structure to be formed, is sufficiently surrounded by the protective ring injection layer 3.

[0058] For this reason, it is difficult to generate a high electric field. Furthermore, the edge region 21 is formed at an obtuse angle, which reduces the electric field concentration in the edge region 21. In addition, a stable dielectric strength can be ensured. A-2. Effects

[0059] According to an embodiment of the present invention, the method for manufacturing a semiconductor device comprises the following steps: (a) Providing an n+-conducting substrate 1 as a basis, which is formed by a silicon carbide semiconductor of a first conductivity type; (b) Forming a depression structure 14 surrounding an element region on the n+-conducting substrate 1 using a resist structure 13, and (c) Forming a protective ring injection layer 3 as a dopant layer of a second conductivity type in a well bottom surface 15 and a well side surface 20 in the well structure 14 by dopant injection through the resist structure 13, wherein an edge region of the well structure 14 is covered with the dopant layer 3.

[0060] Even when using SiC, which hardly causes diffusion of the injected dopants, it is therefore possible to form a structure in which the edge region 21 is sufficiently covered by the protective ring injection layer 3. In this way, a stable dielectric strength can be maintained in the semiconductor device.

[0061] Furthermore, in the method for manufacturing a semiconductor device according to the embodiment of the present invention, step (b) for forming the depression structure 14, which surrounds an element region, on the n+-conducting semiconductor substrate 1 using a resist structure 13 is a step in which the depression structure 14 is formed such that it assumes a chamfered shape on the depression side surface 20 by using the resist structure 13 which assumes a chamfered shape at one end.

[0062] Consequently, the edge region 21 of the depression structure 14 is shaped such that it has an obtuse angle. In this way, an electric field concentration in the edge region 21 can be prevented.

[0063] Furthermore, in the method for manufacturing a semiconductor device according to the embodiment of the present invention, step (b) for forming the depression structure 14, which surrounds an element region, on the n+-conducting semiconductor substrate 1 using a resist structure 13 is a step for forming the depression structure 14 in which the depth of the depression is equal to or greater than 0.1 µm and the width of the chamfer shape is equal to or greater than 0.2 µm. As a result, a stable dielectric strength can be achieved.

[0064] Furthermore, in the method for manufacturing a semiconductor device according to the embodiment of the present invention, step (b) for forming the depression structure 14, which surrounds an element region, on the n+-conducting semiconductor substrate 1 using a resist structure 13 is a step for forming the depression structure 14 with the edge region 21 where the radius of curvature is equal to or greater than 0.1 µm. Thus, it is possible to achieve a stable dielectric strength. B. Second embodiment B-1. Manufacturing process

[0065] Although the protective ring injection layer 3 is formed as a termination structure in the first embodiment, another stress-resistance structure, such as a field limiting ring (an FLR or field limiting injection layer 16), can also be formed.

[0066] The formation of epitaxial layer 2 in Fig. 2 is carried out in the same way, and then an alignment marker and a termination structure are formed using a resist structure 13.

[0067] Fig. Figure 5 shows a situation of structuring for a resist in the termination structure according to a second embodiment of the present invention. In this case, a resist is also structured in an area where the alignment mark is to be formed.

[0068] In the same way as in the first embodiment, one end of the resist structure 13 is formed such that it assumes a chamfered shape. Furthermore, the selectivity ratio for etching to carry out a reactive ion etching process is reduced such that a depression side surface 20 of a depression structure 14 assumes a chamfered shape.

[0069] As in Fig. As shown in Figure 6, the FLR injection layer 16 is next formed by implanting Al ions at room temperature with an energy of 40 keV to 800 keV, for example to achieve an implantation amount of 1 × 10 17 up to 8 × 10 17 cm -3 and to specify an implantation depth of 0.6 µm to 1.0 µm.

[0070] In the second embodiment, the recess side surface 20 assumes an appropriate chamfered shape, as shown in Fig. Figure 6 shows that even when using SiC, which hardly causes diffusion of dopants, such a shape can be created that an edge region 21 of the depression structure 14 is sufficiently covered with the FLR injection layer 16.

[0071] Furthermore, by defining the edge region 21 with an obtuse angle, it is possible to prevent an electric field concentration in the edge region 21. Consequently, the maintenance of a stable dielectric strength in the semiconductor device can be achieved.

[0072] Following this, a semiconductor device 200 with a Fig. The cross-sectional structure shown in section 7 was completed using the same manufacturing process as in the prior art.

[0073] In particular, a metal layer 6 and a backside electrode 9 are formed on a backside surface of an n+-conducting substrate 1.

[0074] Furthermore, the resist structure 13 is removed, and the FLR injection layer 16 is partially covered, so that a metal layer 5 is formed.

[0075] Furthermore, a surface electrode 7 is formed on the metal layer 5, and polyimide 8 is formed over the metal layer 5, the FLR injection layer 3 and the n-conducting epitaxial layer 2.

[0076] As described above, the method for manufacturing a semiconductor device according to the present embodiment uses a structure in which the edge region 21 of the recess structure 14 is sufficiently covered with the FLR injection layer 16, as shown in Fig. Figure 7 shows that it is difficult to generate a strong electric field. Furthermore, the edge region 21 is formed at an obtuse angle. This prevents an electric field concentration.

[0077] Although the number of FLR injection layers is 16 in Fig. Since the number of FLR injection layers is four (four circles), the present invention is not limited with respect to the number of FLR injection layers. If a desired dielectric strength can be ensured, the number of FLR injection layers 16 is preferably reduced in order to reduce the element size.

[0078] In contrast, a high number of FLR injection layers 16 are required for high dielectric strength. In this case, there is a risk that the element size may increase. However, in the semiconductor device according to the present invention, a chamfer etching is used for the resist structure 13.

[0079] For this reason, it is possible to create a structure using closely spaced slots, which is conventionally difficult. In other words, it is possible to reduce the formation interval between the FLR injection layers. This makes it possible to suppress element growth.

[0080] Although Fig. Figure 7 shows a uniform formation interval between the FLR injection layers 16. Furthermore, it is also possible to design the FLR injection layer interval to increase towards the outer periphery of an element region. This design tends to reduce the apparent dopant concentration towards the outer periphery, which is suitable for achieving a stable tensile strength.

[0081] It should be noted that even in the first embodiment, where the protective ring injection layer 3 is formed, it is possible to reduce the formation interval or to design the formation in such a way that the formation interval increases towards the outer periphery. The same effects can therefore be achieved. B-2. Effects

[0082] In the method for manufacturing a semiconductor device according to the embodiment of the present invention, step (b) for forming the depression structure 14 surrounding an element region on the n+-conducting semiconductor substrate 1 using the resist structure 13 is further a step for forming a plurality of depression structures 14 surrounding the element region on the n+-conducting substrate 1 using the resist structure 13, wherein step (b) is further a step for forming a plurality of depression structures 14 such that the spacing interval between the depression structures 14 increases towards the outer periphery of the element region. As a result, the apparent dopant concentration tends to decrease towards the outer periphery, so that a stable dielectric strength can be achieved. C. Third embodiment example C-1. Manufacturing process

[0083] The injection of the dopant into the termination structure according to the first or the second embodiment can be carried out such that a surface of a recess structure 14 receives a low concentration and the concentration gradually increases from the surface, as is the case in Fig. Figure 8 shows. In other words, the dopant injection is carried out in two stages, and a low-concentration dopant injection layer 17 is formed in an area near a well bottom surface 15 and a well side surface 20 in the well structure 14, and a high-concentration dopant injection layer 18 is formed on an inside of the same, i.e., on a surface located away from the surface of the well structure 14.

[0084] In this embodiment of the structure, the edge region 21, which causes an electric field concentration, exhibits a low concentration in the recessed structure 14. Thus, the electric field concentration can be attenuated, and furthermore, the maintenance of a stable dielectric strength characteristic can be expected.

[0085] Fig. Figure 8 shows a view illustrating an application with a protective ring injection layer 3, and furthermore, an application with an FLR injection layer 16 as in the second embodiment is also possible. The number of FLR injection layers 16 can be increased / decreased as required, and the spacing between the FLR injection layers 16 can be the same or different, as described in the second embodiment. Furthermore, the present invention can also be applied to a fourth, fifth, and sixth embodiment, as described below. C-2. Effects

[0086] In the method for manufacturing a semiconductor device according to the embodiment of the present invention, step (c) for forming the guard ring injection layer 3 as a dopant layer of a second conductivity type in a well bottom surface 15 and a well side surface 20 in the well structure 14 by dopant injection through a resist structure 13 is a step for forming a dopant layer which is formed by the dopant injection layer 17 with low concentration and by the dopant injection layer 18 having a high dopant concentration of a second conductivity type by dopant injection in two stages.

[0087] Consequently, the edge region 21 of the depression structure 14, which causes the electric field concentration, exhibits a low concentration in a simple manner. Thus, the electric field concentration can be attenuated, and furthermore, the maintenance of a stable dielectric strength characteristic can be expected. D. Fourth embodiment D-1. Manufacturing process

[0088] Fig. Figure 10 shows a view illustrating the structure of a termination region in a semiconductor device according to a fourth embodiment. As an example, in the illustrated structure, the guard ring is provided as a termination structure at one end of a Schottky diode formed using a silicon carbide (SiC) semiconductor.

[0089] The semiconductor device is formed using an epitaxial substrate comprising an n-type SiC substrate 201 and an n-type SiC drift layer 202, which is subjected to an epitaxial growth process. An anode electrode 203 for Schottky junction with the SiC drift layer 202 is provided on an upper surface of the SiC drift layer 202. A cathode electrode 204 for ohmic junction with the SiC substrate 201 is provided on a lower surface of the SiC substrate 201.

[0090] In the present embodiment, a silicide layer 205 is provided between the SiC substrate 201 and the cathode electrode 204 to reduce the connection resistance between them. Furthermore, the cathode electrode 204 has a two-layer structure comprising a Ni layer 241 and an Au layer 242. The anode electrode 203 also has a two-layer structure with a titanium (Ti) layer 231 and an aluminum (Al) layer 232, the upper layer serving as a terminal electrode for connection to wiring.

[0091] A protective ring 206, comprising a p-type dopant region for suppressing electric field concentrations below one end of the anode electrode 203, is formed in a region that includes an area located below the end of the anode electrode 203 in a surface region of the SiC drift layer 202. As shown in Fig. As shown in Figure 10, the protective ring 206 is formed in a lower part of a depression structure 207, which is provided on the SiC drift layer 202, wherein the end of the anode electrode 203 is extended into the depression structure 207.

[0092] This structure increases the distance between a lower end of the protective ring 206 and a surface of the SiC drift layer 202. This allows an electric field in the surface region of the SiC drift layer 202 to be weakened.

[0093] The protective ring 206 extends not only to the bottom portion of the depression structure 207 but also to its outer edge portion. As a result, the longitudinal cross-sectional area of ​​the protective ring 206 is increased, allowing the electric field concentration at the bottom end of the protective ring 206 to be attenuated even further.

[0094] An alignment marker 208 for use in aligning different masks is formed on the surface of the SiC drift layer 202. In a method for fabricating a semiconductor device according to the present embodiment, the same p-type dopant region 206a as the guard ring 206 is also formed in a lower part of the alignment marker 208, as will be described in detail below.

[0095] The Fig. Figures 11 to 17 show views illustrating steps in the process for manufacturing the Schottky diode and its termination structure, as described in Fig. Figure 1 is shown. Based on these drawings, the method for manufacturing a semiconductor device according to the present embodiment is described below.

[0096] First, an n-conducting (n+-conducting) SiC substrate 201 with a relatively high dopant concentration is provided, and an n-conducting (n - -conductive) SiC drift layer 202 with a relatively low dopant concentration is subjected to epitaxial growth on this ( Fig. 11) In this process, the SiC drift layer 202 with a thickness of 5 µm to 15 µm is subjected to epitaxial growth on the SiC substrate 201 with a thickness of 300 µm to 400 µm.

[0097] Subsequently, a photoresist is applied to a surface of the SiC drift layer 202, and the respective treatments, i.e., heating, structure transfer by photolithographic methods, and development using an alkaline developing solution, are then carried out sequentially. As a result, a resist structure 210 is formed in which training areas for a depression structure 207 and an alignment mark 208 are open ( Fig. 12). The height of the resist structure 210 is specified as 3.7 µm to 5.3 µm.

[0098] In the present embodiment, the resist structure 210 to be used should have a particularly precise right-angled cross-sectional shape (an angle formed by a side surface of the resist structure 210 and a surface of the SiC drift layer 202 is almost perpendicular).

[0099] For example, a positive photoresist can be used as the material for resist structure 210. This photoresist contains photosensitive material, a base resin, and an organic solvent as its main components and exhibits a high degree of perpendicularity in the cross-sectional shape formed after etching. The photoresist is used for heat treatment at 100 °C for 60 seconds, development for 100 seconds using tetramethylammonium hydroxide in a 2.8 wt% solution as the developer, and cleaning for 60 seconds with pure water.

[0100] The resulting resist structure 210 has a side surface that forms an angle of approximately 88° with respect to the surface of the SiC drift layer 202 and exhibits a high right-angle property.

[0101] Subsequently, a reactive ion etching (RIE) process is carried out using the resist structure 210 as a mask to simultaneously form the depression structure 207 and the alignment mark 208, each having a depth of approximately 0.2 µm to 0.4 µm ( Fig. 13).

[0102] Regarding the conditions for the reactive ion etching process, sulfur hexafluoride (SF6) is used as the etching gas, a gas pressure of 1 Pa is specified, a gas flow rate of 50 sccm is specified, a radio frequency power of 800 W is specified, and a substrate bias power of 50 W is specified. In this case, the ratio of the etch rate of a resist to the etch rate of SiC (etch selectivity ratio) is approximately 0.5.

[0103] In the present embodiment, the resist structure 210 with particularly precise rectangular properties is used. Even in cases where the etch selectivity ratio is not high, it is therefore possible to reduce variations in a structural dimension caused by the etching process.

[0104] Subsequently, an isotropic dry etching process is performed over the resist structure 210 to reduce (shrink) the width of the resist structure 210. Fig. 14) In other words, an opening in the resist structure 210 is enlarged. The side surface of the resist structure 210 is retracted by approximately 0.3 µm to 0.6 µm through the dry etching process. The height of the resist structure 210 after the shrinkage treatment is approximately 3 µm to 4 µm.

[0105] For example, oxygen (O2) is used as the etching gas for the etching process, the gas pressure is set to 1 Pa, the gas flow rate is set to 50 sccm, the radio frequency power is set to 800 W, and the substrate bias power is set to zero. The substrate bias power is set to zero to ensure isotropic dry etching.

[0106] By ion implantation using the shrunken resist structure 210 as a mask, Al ions are implanted as p-type dopants into the SiC drift layer 210 to form a protective ring 206. The opening of the shrunken resist structure 210 has a greater width than the depression structure 207. For this reason, the protective ring 206 is formed in an outer rim part of the depression structure 207 in addition to a bottom part of the same.

[0107] In the case where the side surface of the resist structure 210 is relocated by about 0.3 µm to 0.6 µm by the shrinkage treatment, the protective ring 206 is formed in extension of an outer edge region from the end of the depression structure 207 by about 0.3 µm to 0.6 µm.

[0108] Furthermore, in addition to the depression structure 207, an opening is also formed in the alignment mark 208 in the resist structure 210. For this reason, the Al ions are also implanted in the area of ​​the alignment mark 208 (the base part and the outer edge part), so that a dopant region 206a is formed.

[0109] When the Al ions are implanted in the area of ​​the alignment mark 208, a light and shadow area is created between the alignment mark 208 and the surrounding area. This offers the advantage that the recognition rate of the alignment mark 208 can be improved if a device is used to perform the alignment process using an image processing method.

[0110] The resist structure 210 is then removed. This removal can be achieved using the same isotropic dry etching process as described above. Additionally, a heat treatment (activation post-treatment) at 1800 °C to 2000 °C is performed to activate the implanted Al ions.

[0111] Subsequently, the nickel (Ni) layer 241, with a thickness of approximately 500 nm to 800 nm, is formed on the back surface of the SiC substrate 210 using a sputtering process, and a rapid thermal annealing (RTA) is performed at approximately 1000 °C for approximately 5 minutes. As a result, the NiSi silicide layer 205 is formed at an interface between the SiC substrate and the Ni layer 241 ( Fig. 16).

[0112] Furthermore, the Ti layer 231 with a thickness of 100 to 300 nm is formed on the SiC drift layer 202 using the sputtering process, and furthermore the Al layer 232 with a thickness of 4.5 µm to 5.5 µm is formed on the Ti layer 231, so that the anode electrode 203 is formed ( Fig. 17).

[0113] To stabilize the height ϕB of a Schottky barrier (a difference between a work function of a metal and an electron affinity of a semiconductor), it is also possible to perform a heat treatment at about 600 °C after forming the Ti layer 231.

[0114] Finally, the Au layer 242, with a thickness of approximately 100 to 300 nm, is formed on a lower surface of the Ni layer 241 using the sputtering process. As a result, a Schottky diode with the structure shown is obtained. Fig. 10.

[0115] As described above, in the present embodiment, the etching mask used to form the depression structure 207 is shrunk to obtain an injection mask for use in forming the protective ring 206. In other words, the depression structure 207 and the wider protective ring 206 can be formed using the same mask (the resist structure 210).

[0116] Thus, it is possible to further reduce the number of masks compared to the prior art. In the present embodiment, the recess structure 207 and the alignment marking 208 are formed using the same mask (the resist structure 210). This allows the Fig. The structure shown can be formed using a single mask.

[0117] Although the present embodiment uses the resist structure 210, whose side surface is substantially perpendicular to the surface of the SiC drift layer 202, it is also possible to use a resist structure with an inclined side surface that assumes a chamfered shape. When performing the reactive ion etching (RIE) process using the chamfered resist structure 210 as a mask, the respective shapes of the recess structure 207 and the alignment mark 208 are chamfered in the same way as in a fifth embodiment described below. D-2. Effects

[0118] The method for manufacturing a semiconductor device according to this embodiment further comprises a step (d) for performing a shrinkage treatment for a resist structure between the step (b) for forming the well structure 14 surrounding an element region on the n+-conducting substrate 1 using the resist structure 13 and the step (c) for forming the guard ring injection layer 3 as a dopant layer of a second conductivity type in the well bottom surface 15 and the well side surface 20 in the well structure 14 by dopant injection through the resist structure 13.

[0119] By shrinking the etching mask used to form the depression structure 207, it becomes possible to create the injection mask for use in forming the protective ring 206, thus reducing the number of masks required. E. Fifth embodiment

[0120] Fig. Figure 18 shows a view illustrating the structure of a termination region in a semiconductor device according to a fifth embodiment. Fig. 18 are elements with the same functions as in Fig. The 10 elements shown are designated with the same reference symbols, and therefore a further detailed description of them is omitted.

[0121] In the semiconductor device in Fig. 18 is also a Schottky diode, which is manufactured using SiC in the same way as in Fig. 10 is formed and a protective ring 206 is formed as a termination structure at one end of an anode electrode 203 thereof. However, the semiconductor device differs according to Fig. 18 of the in Fig. 10 in that the respective shapes of the depression structure 207 and the alignment marking 208 are chamfered over a greater width in the upper parts than in the lower parts.

[0122] Fig. Figures 19 to 24 show views illustrating the steps in a process for manufacturing the Schottky diode and its termination structure, as shown in [reference]. Fig. 18. Based on the aforementioned drawings, a method for manufacturing a semiconductor device according to the present embodiment is described below.

[0123] First, in the same way as in the fourth embodiment, a n - -conducting SiC drift layer 202 an epitaxial growth over a n + -conducting SiC substrate 201 ( Fig. 19) is subjected to a resist structure 210, in which training areas for a depression structure 207 and an alignment marker 208 are opened, on a surface of the SiC drift layer 202 ( Fig. 20). The height of the resist structure 210 is specified as 3.4 µm to 4.8 µm.

[0124] In the present embodiment, the resist structure 210 to be used should have a chamfer shape with a smaller width in an upper region than in a lower region. An angle of approximately 80° is specified between a side face of the resist structure 210 and a surface of the SiC drift layer 202.

[0125] For example, a positive photoresist can be used as the material for the resist structure 210, which contains a photosensitive material, a base resin and an organic solvent as main components and has a relatively low rectangular property with respect to a cross-sectional shape formed after etching.

[0126] The photoresist is subjected to a heat treatment for 60 seconds at 110 °C, a development treatment for 100 seconds using an alkaline development solution containing 2.8 wt% tetramethylammonium hydroxide, and a cleaning treatment with pure water for 60 seconds. The resulting resist structure 210 has a side surface forming an angle of approximately 82° with respect to the surface of the SiC drift layer 202.

[0127] Subsequently, a reactive ion etching process is carried out using the resist structure 210 as a mask to simultaneously form the depression structure 207 and the alignment mark 208, each having a depth of approximately 0.2 µm to 0.4 µm ( Fig. 21).

[0128] The conditions for the reactive ion etching process specify, for example, the use of sulfur hexafluoride (SF6) as the etching gas, with a gas pressure of 1 Pa, a flow rate of approximately 50 sccm, a radio frequency power of 800 W, and a substrate bias power of 50. In this case, an etch rate ratio of approximately 0.5 is specified for resist to SiC.

[0129] In the present embodiment, the side surface of the beveled resist structure 210 is inclined to a certain extent. During the reactive ion etching process, the side surface of the resist structure 210 is also subjected to the etching process, causing the resist structure 210 to shrink.

[0130] When the depression structure 207 and the alignment mark 208, each having a depth of about 0.2 µm to 0.4 µm, are formed under the aforementioned conditions, the side surface of the resist structure 210 is displaced by about 0.4 µm to 0.8 µm.

[0131] Furthermore, the recess structure 207 and the alignment mark 208 are chamfered. In the recess structure 207 and the alignment mark 208, the width of an inclination of an inner wall (a width in the radial direction of a recess) is essentially equal to the width of the recession of the resist structure 210. Additionally, the height of the shrunken resist structure 210 reaches approximately 3 µm to 4 µm.

[0132] By ion implantation using the shrunken resist structure 210 as a mask, Al ions are implanted as p-conducting dopants into the SiC drift layer 202 to form a protective ring 206 ( Fig. 22). The opening of the shrunken resist structure 210 has a greater width than the bottom area of ​​the depression structure 207. For this reason, the protective ring 206 is formed in an outer edge part, i.e., on an inner wall part of the depression structure 207, in addition to the bottom part of the same.

[0133] In the case where the side surface of the resist structure 210 is retracted by approximately 0.4 µm to 0.8 µm due to the shrinkage treatment, the width of the inclination of the inner wall in the depression structure 207 corresponds to this value. In this way, the protective ring 206 is formed extending from a bottom end of the depression structure 207 by approximately 0.4 µm to 0.8 µm towards an outer region.

[0134] In the present embodiment, an opening is also formed at the alignment mark 208 in addition to the recess structure 207 in the resist structure 210. Thus, a dopant area 206a is also formed in the region of the alignment mark 208 (the base part and the inner wall part). Consequently, light and shadow are formed between the alignment mark 208 and the surrounding area.

[0135] The resist structure 210 is then removed. This removal is achieved by dry etching, using, for example, oxygen (O2) as the etching gas, a gas pressure of 1 Pa, a gas flow rate of 50 sccm, and a radio frequency power of 800 W. This is followed by an activation post-treatment of the Al ions at 1800 °C to 2000 °C.

[0136] Subsequently, a nickel (Ni) layer 241 with a thickness of approximately 500 nm to 800 nm is formed on a back surface of the SiC substrate 201 using a sputtering process, and an RTA process is carried out at approximately 1000 °C for approximately 5 minutes. As a result, a NiSi silicide layer 205 is formed on a SiC substrate 201 and the Ni layer 241 ( Fig. 23).

[0137] In the same way as in the fourth embodiment, a Ti layer 231 and an Al layer 232 are then formed successively on the SiC drift layer 202 ( Fig. 24), and an Au layer 242 is formed on a lower surface of the Ni layer 241. In this way, a Schottky diode is obtained with the in Fig. Structure shown in 18.

[0138] As described above, in the present embodiment the etching mask used to form the recess structure 207 is shrunk to obtain an injection mask which is to be used to form the protective ring 206 in the same way as in the fourth embodiment.

[0139] In other words, the recessed structure 207 and the wider protective ring 206 can be formed using the same mask (the resist structure 210). Furthermore, the shrinking of the resist structure 210 is achieved through the etching process used to form the recessed structure 207. Therefore, no separate process for shrinking the resist structure 210 is required. This allows for a further reduction in the number of steps compared to the fourth embodiment.

[0140] Although the resist structure 210 is used, which in the present embodiment has an inclined side surface with a shape that assumes a chamfer from the outset, it is also possible to use a resist structure (a vertical resist) with a side surface that, during formation, assumes a substantially right-angled shape to the surface of the SiC drift layer 202.

[0141] In the reactive ion etching process for forming the depression structure 207, the vertical resist is formed with a bevel during the execution of the reactive ion etching process when oxygen gas is added or the pressure is changed to increase the isotropy of the etching process.

[0142] In the method for producing a semiconductor device according to the embodiment of the present invention, step (b) for forming the depression structure 207, which surrounds an element area, on the SiC substrate 201 using the resist structure 210 is a step using the resist structure 210 for forming the depression structure 207 by shrinking the resist structure 210, which at the end assumes a chamfered shape.

[0143] As a result, the edge region of the depression structure 207 is modified such that it has an obtuse angle. In this way, an electric field concentration in the edge region can be prevented. F. Sixth Example

[0144] Although the fourth and fifth embodiments describe an example in which the present invention is used in the step of forming the guard ring, the present invention can also be used in forming the field limiting ring (FLR).

[0145] Fig. Figure 25 shows a view illustrating the structure of a termination region of a Schottky diode, which features a field-limiting ring as its termination structure. The field-limiting ring has, broadly speaking, the same structure as a protection ring, except that it is formed by a plurality of p-type dopant regions 206a with the same dopant concentration.

[0146] If in the step to form the resist structure 210 according to the fourth or fifth embodiment ( Fig. 12 or Fig. 20) if a large number of ring-shaped openings are formed on the resist structure 210 at equal intervals or at intervals that increase towards the outer periphery, the field limiting ring can thus be formed.

[0147] Since the remaining steps can be the same as in the fourth or fifth embodiment, they will not be described again. In this case, a semiconductor device 30 is completed as described in the Fig. 27 is shown.

[0148] Although the Schottky diode has been illustrated as a semiconductor element in the preceding description, the present invention can also be applied to a termination structure such as a MOSFET.

[0149] Although the invention has been presented and described in detail, the foregoing description serves only for illustrative purposes and is not to be understood as limiting. For example, the present invention is not limited to the material quality, the materials themselves, the execution conditions, and the like of the respective components described. It is therefore understood that numerous modifications and variations within the scope of the invention are possible. Reference symbol list 1 n+-conducting substrate 2 n-conducting epitaxial layer 3 Protective ring injection layer 5 metal layer 6 metal layer 7 Surface electrode 8 Polyimid 9 Backside electrode 13 Resist structure 14. In-depth structure 15 depression floor area 16 FLR injection layer 17 Low-concentration dopant implantation layer 18 High-concentration dopant implantation layer 20 recessed side surface 21 edge area 100 semiconductor devices 101 n+-conducting substrate 103 Protective ring injection layer 104 JTE injection layer 105 metal layer 106 Metal layer 107 Surface electrode 108 Polyimid 109 Backside electrode 110 thermal oxide layer 111 ohmic post-treatment 113 Resist retreat 200 semiconductor devices 201 SiC substrate 202 SiC drift layer 203 Anode electrode 204 Cathode electrode 205 Silicide layer 206 Protective ring 206a Doping area 207 In-depth structure 208 Alignment marker 210 Resist structure 231 Ti layer 232 Al layer 241 Ni layer 242 Au layer 300 semiconductor device

Claims

[1] A method of manufacturing a semiconductor device, the method comprising the steps of: (a) providing a base (1) formed by a silicon carbide semiconductor of a first conductivity type; forming a resist pattern (210) as a mask, wherein a photoresist is used as the resist pattern (210); (b) forming a recess structure (207) surrounding an element region on the base (1) using the resist structure (210); . (d) performing a shrinkage treatment over the resist structure (210) after step (b); and (c) forming a guard ring (206) of a second conductivity type in a recess bottom surface (15) and a recess side surface (20) in the recess structure (207) by dopant injection through the resist structure (210) after step (d), wherein an edge region of the recess structure (207) is covered with the protective ring (206), and wherein the recess structure (207) and the guard ring (206) are formed using the resist structure (210) as a single mask. [2] The method according to claim 1, wherein step (d) is a step in which the shrinkage treatment is carried out by isotropic etching over the resist pattern (210). [3] The method of claim 1, wherein a side surface of the resist structure (210) and the substrate are substantially perpendicular to each other when forming the resist structure (210). [4] The method according to claim 1, wherein a side surface of the resist structure (210) is shifted back by 0.3 µm to 0.6 µm by the shrinkage treatment. [5] The method according to claim 1, wherein the step (b) is a step of forming the recess structure (14) having a tapered shape at the recess side surface (20) using the resist structure (13) having a tapered shape at one end. [6] The method according to claim 1, wherein step (c) is a step of forming the guard ring (206) formed by a low concentration dopant layer (17) and a high concentration dopant layer (18) of a second conductivity type by two-stage dopant injection. [7] The method according to claim 5, wherein the step (b) is a step of forming the recess structure (14) in which the depth of the recess is equal to or greater than 0.1 µm and the width of the chamfer shape is equal to or greater than 0.2 µm. [8] The method according to claim 5, wherein step (b) is a step of forming the recess structure (14) having an edge portion (21) in which the radius of curvature is equal to or greater than 0.1 µm. [9] The method according to claim 1, wherein step (b) is a step of simultaneously forming an alignment mark in addition to the recess structure (207). [10] The method according to claim 1, wherein step (c) is a step of forming a guard ring injection layer (3) of a second conductivity type or a field confinement ring injection layer (16) of a second conductivity type as the dopant layer. [11] The method according to claim 1, wherein the step (b) is a step of forming a plurality of recess structures (207) surrounding an element region on the base (1) using the resist pattern (13), and wherein the step (b) is a step of forming a plurality of the recess structures (207) such that a pitch interval between the recess structures (207) increases toward an outer periphery of the element region. [12] The method according to claim 1, further comprising a step (e) of forming a Schottky electrode in at least a part of an inner region of the recess structure (14) after the step (b).

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