Non-planar wraparound gate circuit

Abstract

A semiconductor device comprising: a substrate (102, 301) with a surface (104) with a first lattice constant; epitaxial source (106, 338) and drain regions (107, 339) which are applied to the surface (104) of the substrate (102, 301) and are separated from each other in a first lateral direction, said epitaxial source (106, 338) and drain regions (107, 339) have a second lattice constant which differs from the first lattice constant; a plurality of channel nanowires (110, 343) with a third lattice constant that differs from the first lattice constant, said plurality of channel nanowires (110, 343) is coupled to the epitaxial source (106, 338) and drain (107, 339) regions, and said plurality of channel nanowires (110, 343) includes a bottommost channel nanowire (115, 344); a dielectric gate layer (116, 350) applied to and surrounding all channel nanowires (110, 343), and a gate electrode (118) formed on the dielectric gate layer (116, 350) and enclosing all channel nanowires (110, 343); the plurality of channel nanowires (110, 343) are not in direct contact with each other, and wherein the surface (104) defines a fin-shaped portion of the substrate (102, 301), and the fin is arranged in a second lateral direction perpendicular to the first lateral direction between and adjacent to a trench insulation layer (105), and the extent of the fin along the first lateral direction is greater than the extent of the fin along the second lateral direction, and wherein the epitaxial source (106, 338) and drain regions (107, 339) <111> are faceted, and wherein the epitaxial source area (106, 338) has a first width (122) at a top of the trench insulation layer (105) and a second width (124) at an upper end of the epitaxial source area (106, 338), the first width (122) being larger than the second width (124) and the width of the epitaxial source area (106,338) decreases from the first width (122) to the second width (124).

Description

BACKGROUND1) TECHNICAL AREA

[0001] The embodiments of this invention relate to the field of semiconductor devices and in particular to a non-planar wrap-around gate circuit. 2) DESCRIPTION OF RELATED TECHNOLOGY

[0002] Semiconductor manufacturers are continuously shrinking transistor feature sizes to achieve higher packing density and power output. This necessitates increasing transistor currents while simultaneously reducing short-channel effects such as parasitic capacitance and reverse bias for next-generation devices. One approach to increasing transistor currents is to use more mobile semiconductor materials to shape the channel. Increased carrier mobility within the channel supports higher transistor currents. Carrier mobility is a measure of the speed at which carriers flow within semiconductor materials under the electric field of an external device. Process-induced loading (also known as stress) on the semiconductor body is another way to increase drive currents. Inducing stress on the semiconductor body increases carrier mobility and, consequently, the drive currents in the transistors.

[0003] Non-planar transistors, such as the tri-gate transistor, are a recent development in semiconductor manufacturing for controlling short-channel effects. In tri-gate transistors, the gate borders three sides of the channel region. Because the gate structure surrounds the fin on three surfaces, the transistor effectively has three gates that control the current flow through the fin or channel region. These three gates allow for more comprehensive discharge in the fin and, due to steeper subthreshold current oscillations and smaller drain-induced threshold dips, result in fewer short-channel effects. Unfortunately, the fourth side, the lower part of the channel, is far from the gate electrode and is therefore not tightly controlled by the gate. As the size of transistors continues to shrink to sub-20-25 nm technology nodes, parasitic shunt paths between the source and drains become problematic for tri-gate transistors.Examples of transistors are known from the publications US 2011 / 0 062 417 A1, US 2010 / 0 155 827 A1, US 2009 / 0 065 850 A1, US 2008 / 0 102 586 A1, US 2011 / 0 210 404 A1 and US 2011 / 0 079 829 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The various embodiments of the present invention are illustrated by way of example and in no way limiting in the figures of the accompanying drawings, and in which: The Fig. Figures 1A to 1D illustrate a non-planar gate wrap-around device with embedded epitaxial source and drain regions according to an embodiment of the present invention. Fig. 1E is an illustration of a non-planar gate wraparound device without integrated source and drain areas. Fig. Figure 2 is a flowchart showing the steps of a method for constructing a non-planar gate wrap-around device according to an embodiment of the present invention. The Fig. Figures 3A to 3M show the three-dimensional and two-dimensional views that represent the steps of a method for constructing a non-planar gate wrap-around component according to an embodiment of the present invention. Fig. Figure 4 shows a computing element 400 according to an implementation of this invention. DETAILED DESCRIPTION

[0005] The present invention is defined in claim 1 and is a novel gate-enclosed transistor. Numerous specific details are given in the following description to enable a comprehensive understanding of the present invention. However, it is obvious to a person skilled in the art that the present invention can be operated without some of these specific details. In other cases, well-known semiconductor processing methods and features have not been specifically described in detail so as not to unnecessarily obscure the present invention. References in this description to "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention.Therefore, the appearance of the phrase "in one embodiment" at different points in the description does not necessarily always refer to the same embodiment. Furthermore, the specific features, structures, or characteristics can be combined in any suitable way in one or more embodiments. For example, a first embodiment can be combined anywhere with a second embodiment; the two embodiments are not mutually exclusive.

[0006] The embodiments include a non-planar gate wrap-around transistor with channel nanowires wound around a dielectric gate layer and a gate electrode. The gate electrode, which completely surrounds the channel nanowires, enhances gate control and results in improved short-channel effects, as parasitic shunt paths are completely eliminated. The channel nanowires are located between the source and drain regions. In one or more embodiments of the present invention, the channel nanowires consist of undoped germanium, and the grid is subjected to uniaxial stress. The undoped germanium offers higher carrier mobility than conventional silicon, and the uniaxial stress on the grid further increases the carrier mobility of the channel nanowires, thereby enabling very high transistor currents.In one embodiment of the present invention, the source and drain regions are formed by etching a fin adjacent to the channel nanowires. Subsequently, the “embedded epitaxial” source and drain regions are formed by epitaxial growth of a semiconductor material from the substrate. Embedded epitaxial source and drain regions provide either additional energy or anchors for the channel nanowires, thereby supporting the increase or maintenance, or the increase and maintenance, of the uniaxial loading of the grid. Furthermore, in one embodiment of the present invention, the gate wrap-around transistor includes an insulating layer at the lower gate, formed between the substrate and the lower channel nanowire, so that the gate electrode can be formed completely around the lower channel nanowire without capacitive coupling to the substrate.One or more embodiments include a non-planar gate wrap-around transistor with one of the embedded epitaxial source and drain regions or an insulating layer at the bottom gate formed between the substrate and the bottom channel nanowire, or both.

[0007] Fig. Figures 1A to 1D illustrate a non-planar gate wrap-around component 100 according to an embodiment of the present invention. Fig. 1A is a three-dimensional view from above / from the side of the component 100 within the dielectric layer 101, Fig. 1B is a cross-section through the integrated epitaxial source 106 and drain 107, and Fig. 1C is a cross-section through the gate electrode 118. Fig. 1D is a three-dimensional top / side view of the device 100, excluding the dielectric layer 101. The device 100 contains a substrate 102 with a top surface 104. The epitaxial source region 106 and the drain region 107 are located on the top surface 104 of the substrate 102, and the channel nanowires 110 are coupled between the embedded epitaxial source region 106 and the drain region 107. The integrated epitaxial source region 106 and the drain region 107 can be collectively referred to as an integrated epitaxial source / drain pair. A dielectric gate layer 116 is formed on and around each channel nanowire 110, except for the ends of the channel nanowires 110, where the channel nanowires 110 are coupled to the embedded epitaxial source region 106 and drain region 107. A gate electrode 118 is formed on the dielectric layer 116 and completely surrounds each channel nanowire 110.

[0008] In one embodiment, the surface 104 of the substrate 102, the embedded source 106 and drain regions 107, and the channel nanowires 110 each comprise a material with a lattice constant. The lattice constant of the surface 104 differs from the lattice constants of the embedded epitaxial source 106 and drain regions 107 and the channel nanowires 110. In a particular embodiment, the lattice constants of the embedded epitaxial source 106 and drain regions 107 and the channel nanowires 110 are greater than the lattice constant of the surface 104. In such an embodiment, the surface 104 of the substrate 102 consists of silicon germanium, the channel nanowires 110 of undoped germanium, and the integrated epitaxial source region 106 and drain region 107 of germanium. The lattice mismatch (e.g.,The mismatch of the lattice constant between the embedded epitaxial source region 106 and drain region 107, the channel nanowires 110, and the surface 104 leads to lattice loading on the channel nanowires 110 and the embedded epitaxial source region 106 and drain region 107. In one embodiment, the lattices of the channel nanowires 110 and the integrated epitaxial source region 106 and drain region 107 are subjected to uniaxial stress in a direction parallel to the length 120 of the channel nanowires 110, and the lattices are relieved in a perpendicular direction to the length 120 of the nanowires 110. In one embodiment, the lattice mismatch between the surface 104 and the embedded epitaxial source 106 and drain regions 107 also results in the embedded epitaxial source 106 and drain regions 107 supplying energy to the channel nanowires 110.The energy can support the maintenance of the uniaxial lattice loading of the channel nanowires 110.

[0009] In one embodiment, the channel nanowires 110 can comprise a single crystalline material that possesses greater carrier mobility than crystalline bulk silicon. This greater carrier mobility enables the device 100 to achieve higher drive currents and greater power. In a particular embodiment, the channel nanowires 110 consist of undoped germanium (Ge). The absence of dopants minimizes charge carrier scattering and helps maximize the carrier mobility of the channel nanowires 110.

[0010] As in Fig. 1A and Fig. As shown in Figure 1B, in one embodiment of the present invention, the embedded epitaxial source 106 and drain regions 107 can be formed in a source / drain trench 108, wherein the surface 104 of the substrate 102 is recessed below the surface of the flat trench insulating layer 105. The formation of the embedded source 106 and drain region 107 in the source / drain trench 108 supports the containment of the growth of the embedded epitaxial source 106 and drain regions 107. The embedded source 106 and drain regions 107 need not necessarily be formed in a trench and can be located on the surface 104 of the substrate 102, which is planar to or above the insulating region 103.Integrated epitaxial source-106 and drain-107 areas can <111> -be faceted, wherein the width 122 at the lower end is greater than the width 124 at the upper end of the embedded epitaxial source 106 and drain regions 107. In such an embodiment, the area corresponding to the side walls 126 and 128 is the <111> -Grid alignment of the embedded epitaxial source-106 and drain regions 107.

[0011] In one embodiment, component 100 includes a lower gate insulation 114, which is attached to the surface 104 of the substrate 102 and beneath the lowest channel nanowire 115. The lower gate insulation 114 serves as a capacitive isolation barrier to prevent parasitic coupling of the surface 104 of the substrate 102 by the gate electrode 118. The effectiveness of the lower gate insulation 114 as a capacitive isolation barrier depends on the material from which it is formed and its thickness. In one embodiment, the lower gate insulation 114 consists of any dielectric material (silicon oxide, silicon nitride, silicon oxynitride, low-K dielectric materials, etc.) that prevents parasitic coupling of the surface 104 of the substrate 102 by the gate electrode 118. In a specific embodiment, the lower gate insulation 114 consists of a silicon oxide layer.In one embodiment, the thickness of the lower gate insulation is sufficient to insulate the surface 104 of the substrate 102 against capacitive coupling by the gate electrode 118. In a particular embodiment, the lower gate insulation 114 is between 10 and 30 nm thick. The lower gate insulation 114 allows the bottommost channel nanowire 115 to be completely wrapped around the gate electrode 118. If the lower gate insulation 114 were not present, the bottom channel nanowire 115 would have to be controlled by a tri-gate or similar structure to prevent capacitive coupling between the gate electrode 118 and the surface 104 of the substrate 102 and to prevent the formation of an unwanted conductive channel in the substrate when the device is "switched on".

[0012] In one embodiment of the present invention, substrate 102 can comprise one or more epitaxially grown single-crystal semiconductor layers (e.g., silicon, germanium, silicon-germanium, gallium arsenide, indium phosphide, indium gallium arsenide, aluminum gallium arsenide, etc.) growing on a specific crystalline substrate (silicon, germanium, gallium arsenide, sapphire, etc.). In such an embodiment, the epitaxially grown semiconductor layers are one or more buffer layers 109 whose lattice constants differ from those of the individual crystalline substrate. The buffer layers 109 can thus increase the lattice constant from that of the individual crystalline substrate to the surface 104. For example, substrate 102 can comprise epitaxially grown silicon-germanium (SiGe) buffer layers 109 on an individual crystalline silicon substrate.The germanium concentration of the SiGe buffer layers 109 can increase from 30% germanium in the lowest buffer layer to 70% germanium in the uppermost buffer layer, with the lattice constant being increased stepwise.

[0013] Shallow trench regions (STI) 103 can be constructed on substrate 102 in one embodiment. The shallow trench regions (STI) 103 serve to reduce current leakage between adjacent components 100. A trench layer (STI) 105 can be present in the STI regions 103. The STI layer 105 can comprise any well-known dielectric material, such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-K dielectric material, or any combination thereof.

[0014] As in Fig. As shown in Figure 1B, the channel nanowires are formed above the surface 104 of the substrate 102 and between the embedded epitaxial source 106 and drain regions 107. The channel nanowires 110 can be formed from any known material such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, InP, and carbon nanotubes. The channel nanowires 110 can be formed from any known material that can be reverse-changed from an insulating to a conductive state by applying external electric fields. Ideally, to achieve higher device performance in one embodiment, the channel nanowires 110 are formed from an undoped, single-crystal, lattice-loaded semiconductor material whose carrier mobility is higher than that of single-crystal silicon.As explained above, the absence of dopant minimizes charge carrier scattering and promotes the maximization of carrier mobility, thereby increasing the driver current. The grid loading in the channel nanowires 110 increases the carrier mobility and improves the device's performance. Typically, channel nanowires 110 are subjected to compression to increase hole mobility in P-type transistors and to tension in N-type transistors to increase electron mobility. In one embodiment, the grids of the channel nanowires 110 are subjected to uniaxial stress in a direction parallel to their length 120 and are unloaded in a direction perpendicular to their length 120. In another embodiment, the channel nanowires 110 can be doped single-crystal semiconductor material. For example, the channel nanowires 110 can be formed from doped single-crystal silicon.When the channel nanowires 110 are doped, they are normally doped to a P-type conductivity when forming an NMOS transistor element, and to an N-type conductivity when forming a PMOS transistor element.

[0015] As in Fig. As shown in Figure 1B, channel nanowires 110 can run parallel to the surface 104 and form a vertical array of channel nanowires 110. In one embodiment, the number of channel nanowires between the embedded epitaxial source 106 and drain 107 regions is between 3 and 6. A higher number of channel nanowires 110 allows a stronger driver current to be conducted through the device 100. The channel nanowires 110 have a thickness 130, a width 132, and a length 120. In one embodiment of the present invention, the thickness 130 is between approximately 5 and 30 nm, the width 132 is between approximately 5 and 50 nm, and the length 120 is between 10 and 100 nm. In another embodiment, the nanowires 110 can be loop-shaped nanowires whose width 132 is greater than the thickness 130 of the channel nanowires. In another embodiment, the cross-section of the channel nanowires 110 can be circular or oval instead of square.The length 120 of the channel nanowires essentially defines the length of the gate (Lg) of the transistor element 100. The effective "width" of the gate (Wg) of a channel nanowire 110 is the circumference of the channel nanowire 110. For example, the effective "width" of the gate of the channel nanowire 110, in the case of a channel nanowire with a square cross-section, is the sum of twice the width 132 and twice the thickness 130 of the channel nanowire 110. The effective "width" of the gate (Wg) of a transistor element 100 is the sum of the circumferences of the channel nanowires 110.

[0016] As in Fig. As shown in Figure 1B, the embedded epitaxial source 106 and drain regions 107 are formed at opposite ends of the channel nanowires 110 and are coupled to the channel nanowires 110. The embedded epitaxial source 106 and drain regions 107 can be formed from any known material possessing a lattice constant. Ideally, the embedded source 106 and drain regions 107 are formed from an epitaxially grown, single-crystal semiconductor such as, but not limited to, Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In one embodiment, the embedded epitaxial source 106 and drain regions 107 are formed from a single-crystal semiconductor material with a lattice constant that differs from the surface 104 of the substrate 102.As described above, the mismatch of the lattice constant between the embedded epitaxial source 106 and drain regions 107 and the surface 104 of the substrate 102 generates a lattice loading in the embedded epitaxial source 106 and drain regions 107, thus improving the electron mobility and the performance of the transistor. In one embodiment, the embedded epitaxial source 106 and drain regions 107 are stressed uniaxially in a direction parallel to the length 120, but the lattices are unloaded in a perpendicular direction to the length 120.The mismatch of the lattice constant between the embedded epitaxial source 106 and drain regions 107 and the surface 104 of the substrate 102 also causes the embedded epitaxial source 106 and drain regions 107 to exert a force on the channel nanowires 110, thereby supporting the maintenance of lattice stress in the channel nanowires 110. In one embodiment, the embedded epitaxial source 106 and drain regions 107 are formed from the same single-crystal semiconductor material used to form the channel nanowires 110.

[0017] In a particular embodiment, the lattice constant of the embedded epitaxial source 106 and drain regions 107 is greater than the lattice constant of the surface 104 of the substrate 102. In such an embodiment, the embedded epitaxial source 106 and drain regions 107 are subjected to compressive stress and exert a compressive force on the channel nanowires 110. In a specific embodiment, the embedded epitaxial source 106 and drain regions 107 are formed from epitaxial single-crystal germanium, and the surface 104 of the substrate 102 is formed from epitaxial single-crystal silicon germanium. The germanium source 106 and drain regions 107 exert a compressive force on the channel nanowire 110. In one embodiment, the surface 104 of the semiconductor substrate 102 can be formed from a semiconductor material (e.g. silicon-germanium) that has a first lattice constant, and the channel nanowires 110 from a second semiconductor material (e.g.germanium) which has a second lattice constant that is larger than the first lattice constant; and the embedded epitaxial source 106 and drain regions 107 can be formed from a third semiconductor material (e.g. gallium arsenide (GaAs)) which has a third lattice constant that is larger than the lattice constant of the channel nanowires 110 (second lattice constant) and can further increase the compressive stress in the channel nanowires 110.

[0018] In another embodiment, the lattice constant of the embedded epitaxial source 106 and drain regions 107 is smaller than the lattice constant of the surface 104 of the substrate 102. In such an embodiment, the embedded epitaxial source 106 and drain regions 107 are subjected to tensile stress and exert a tensile force on the channel nanowires 110. In one embodiment, the surface 104 of the semiconductor substrate 102 can be made of a single-crystal semiconductor material having a first lattice constant, and the channel nanowires 110 can be made of a second semiconductor material having a second lattice constant. The embedded epitaxial source 106 and drain regions 107 can be made of a third semiconductor material having a third lattice constant that is smaller than the lattice constant of the channel nanowires 110 (second lattice constant) in order to further increase the tensile force in the channel nanowires.

[0019] Normally, the embedded epitaxial source 106 and drain regions 107 are formed into an N-type conductivity type when forming an NMOS transistor and into a P-type conductivity type when forming a PMOS transistor. In one embodiment of the present invention, the embedded epitaxial source 106 and drain regions 107 have a doping concentration between 1E18 atoms / cm³ and 1E21 atoms / cm³. The embedded epitaxial source 106 and drain regions 107 can be formed with a uniform concentration or include sub-regions of different concentrations or dopant profiles. In an embodiment in which the device 100 is formed as a symmetrical transistor, the embedded epitaxial source 106 and drain regions 107 have the same doping concentration and the same profile.In another embodiment, in which the component 100 is formed as an asymmetric transistor, the doping concentration profile of the embedded epitaxial source 106 and drain regions 107 can be varied to achieve certain electrical characteristics, as is well known to the experts.

[0020] The source 106 and drain regions 107 are considered “integrated epitaxial” source and drain regions because, as detailed below, they are formed by removing portions of the fin used to create the claimed channel nanowires 110 and subsequently growing the source and drain pair. For example, in one embodiment, the portions of the fin used to construct the claimed channel nanowires 110 are removed, and the source and drain pair is then grown from the surface 104 of the substrate 102. The lattice of the epitaxially deposited source and drain pair extends from the lattice of the surface 104 of the substrate. That is, the lattice of the underlying substrate dictates the lattice direction and growth of the overlying embedded epitaxial source 106 and drain regions 107.The use of the embedded epitaxial source 106 and drain 107 regions improves the device's performance by providing additional force to the channel nanowires and by providing anchors for the channel nanowires to support the maintenance of the uniaxial stress on the channel nanowires 110, which is already present from previous processes, such as fin transfer. The embedded epitaxial source and drain regions are stressed and therefore further stress the adjacent nanowire channels. The stress on the channel nanowires can be further increased by using a semiconductor material with a different constant than the semiconductor material used to form the channel nanowires.

[0021] Furthermore, although the semiconductor device 100 ideally comprises integrated epitaxial source 106 and drain regions 107 to increase the stress on the channel nanowires 110, the embodiments do not necessarily include integrated epitaxial source and drain regions. In one embodiment of the present invention, as shown in Fig. As shown in Figure 1E, a transistor 150 can comprise a source 156 and a drain 157, which consist of a stack of fin films used to create the uniaxially stressed channel nanowires 110. For example, the source 156 and drain 157 can consist of alternating layers of the semiconductor material 160 and the sacrificial material 170 (e.g., germanium or silicon-germanium) and the substrate 102, which is used to form the stressed channel nanowires 110. In this case, the source 156 and drain 157 are formed from a heterogeneous stack of single-crystal semiconductor films. The source 156 and drain 157 can be doped to a desired conductivity type and level, as is known in the field.Furthermore, if desired, increased source and drain areas can be formed by depositing additional epitaxial semiconductor material (not shown) on the source 156 and drain areas 157 to increase the strength of the source and drain areas, reduce current crowding, and thus lower the contact resistance of the device. The transistor 150 includes the gate insulation 114 to isolate the gate 118 below the lowest nanowire 115 from capacitive coupling with the substrate 102.

[0022] As in the Fig. 1B and Fig. As shown in Figure 1C, the dielectric layer 116 is formed on and around all channel nanowires 110. The dielectric gate layer 116 can be any known dielectric gate layer, such as, but not limited to, SiO₂, SiON₂, and SiN. In one embodiment, the dielectric gate layer is a high-k dielectric gate layer such as a metal oxide dielectric (e.g., Ta₂O₅, TiO₂, HfO₂, HfSiOx, ZrO₂, etc.). The dielectric gate layer 116 can also consist of other types of high-k dielectric layers, such as, but not limited to, PZT and BST. The dielectric gate layer can also consist of any combination of the above-mentioned dielectric materials. The dielectric gate layer 116 can be formed with a thickness of approximately 10–60 A. In a specific embodiment, the dielectric gate layer 116 consists of HfO2 and was formed with a thickness of about 1 - 6 nanometers.

[0023] A gate electrode 118 is formed on the dielectric layer 116 and completely surrounds each channel nanowire 110. The gate electrode 118 runs perpendicular to the length 120 of the channel nanowires 110. The gate electrode 118 can be formed from a suitable gate electrode material. In one embodiment, the gate electrode 118 can be a metal gate electrode made of, for example, but not limited to, Ti, TiN, TaN, W, Ru, TiAl, and all combinations thereof. In an embodiment in which the device 100 is an NMOS transistor, the gate electrode 118 can be formed from a material with an output power between 3.9 and 4.2 eV. In an embodiment in which the component 100 is a PMOS transistor, the gate electrode 118 can be made of a material with a work function between 4.8 and 5.2 eV.In one embodiment, where the channel nanowires 110 in the device 100 are undoped or very lightly doped, the gate electrode 118 can be made of a material with a mid-gap work function between 4.3 and 4.7 eV. In one specific embodiment, the gate electrode 118 is made of TiAl.

[0024] Since the gate electrode 118 and the dielectric gate layer 116 completely enclose each channel nanowire 110, the device 100 can be a transistor operating in a completely depleted state. When switched on ("ON"), the channel nanowires 110 become completely depleted, thus providing the advantageous electrical properties and performance of a completely depleted transistor. When the device 100 is switched on, a space charge region and an inversion layer form on the surface of each channel nanowire 110. The inversion layer has the same conductivity types as the embedded epitaxial source 106 and drain regions 107 and forms a conductive channel between them, allowing current to flow. The space charge region depletes the free carriers beneath the inversion layers.The carriers in each channel nanowire 110 are depleted, except for the inversion layer; therefore, the transistor can be considered a "fully depleted" transistor. Fully depleted transistors exhibit improved electrical performance characteristics compared to partially or not fully depleted transistors. When a transistor is operated as a fully depleted transistor, it acquires an ideal or very steep subthreshold slope. A very steep subthreshold slope leads to improved short-channel effects, such as improved drain-induced threshold (DIBL) reductions.

[0025] Fig. Figure 2 is a flowchart 200 that shows the steps of a method for constructing a non-planar gate wrap-around device according to an embodiment of the present invention. Fig. Figures 3A to 3M show the three-dimensional and two-dimensional cross-sections that illustrate steps of a method for fabricating a non-planar gate-enclosed device according to an embodiment of the present invention. The method begins with step 202 in flowchart 200 by providing a substrate 301 with a fin 304 formed thereon. The substrate 301 is the material on which the non-planar gate-enclosed device is formed. The substrate 301 has a surface 303 with a lattice constant. In one embodiment, the substrate 301 comprises a single-crystal layer with a lattice constant. In such an embodiment, the substrate 301 can comprise one or more buffer layers 311 that are grown between an individual crystalline substrate and the uppermost single-crystal layer.The buffer layers 311 can serve to stepwise change the lattice constant from that of the individual crystalline substrate to that of the uppermost single-crystal layer. The buffer layers 311 can be formed from an epitaxially grown, single-crystal semiconductor material such as, but not limited to, Si, Ge, GeSn, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. The single-crystal substrate on which the buffer layers 311 are formed can be any single-crystal material with a lattice constant (e.g., silicon, germanium, gallium arsenide, sapphire, etc.). In a particular embodiment, substrate 301 can comprise epitaxially grown silicon-germaninium (SiGe) buffer layers on an individual single-crystal silicon substrate.The germanium concentration of the SiGe buffer layers can increase from 30% germanium in the bottom buffer layer to stress-free 70% germanium in the top buffer layer, with the lattice constant being increased stepwise.

[0026] In one embodiment, the fin 304 is formed with alternating layers of a semiconductor material 308 and a sacrificial material 310. The layers of semiconductor material 308 are then formed into channel nanowires 343. Due to a mismatch of the lattice constant with the layers of semiconductor material 308, the layers of sacrificial material 310 induce a lattice stress on the layers of semiconductor material 308. In one embodiment, the layers of semiconductor material 308 and the layers of sacrificial material 310 can be formed from any known material possessing a lattice constant. Ideally, the layers of semiconductor material 308 and the layers of sacrificial material 310 are formed from a single-crystal semiconductor material such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP.In one embodiment, the layers of semiconductor material 308 have a different lattice constant than the lattice constant of the layers of sacrificial material 310 and the surface 303 of the substrate 301. Due to the lattice mismatch between the surface 303, the layers of semiconductor material 308, and the layers of sacrificial material 310, the fin 304 is subjected to lattice stress. In a further embodiment, the layers of semiconductor material 308 have a larger lattice constant than the lattice constant of the layers of sacrificial material 310 and the surface 303. For example, the layers of semiconductor material 308 can be undoped germanium, the surface 303 can be silicon-germanium with a 70% germanium concentration, and the layers of sacrificial material 310 can be silicon-germanium with a 70% germanium concentration.In one embodiment, the lattice mismatch between the materials causes the layers of semiconductor material 308 in the fin 304 to be subjected to compressive stress. In another embodiment, the layers of semiconductor material 308 have a smaller lattice constant than the lattice constant of the layers of sacrificial material 310 and the surface 303. The layers of semiconductor material 308 can be, for example, silicon, the surface 303 can be silicon-germanium, and the layers of sacrificial material 310 can be silicon-germanium. In this embodiment, the lattice mismatch between the materials causes the layers of semiconductor material 308 in the fin 304 to be subjected to tensile stress.Since the sacrificial material layer 310 and the semiconductor material layer 308 alternate and have different lattice constants, the semiconductor material layers are subjected to biaxial stress by the underlying sacrificial material layer 310.

[0027] The fin 304 can be formed by first uniformly depositing alternating layers of the semiconductor material 308 and the sacrificial material 310 onto the surface 303 of the substrate 301 using conventional epitaxial vapor deposition methods. Then, the uniform layers of the semiconductor material 308 and the sacrificial material 310 are structured using conventional photolithography and etching methods. In one embodiment of the present invention, the substrate 301 is also etched, so that the lower part of the fin 304 has a substrate portion 309, as shown in Fig. Figure 3A shows that the substrate portion 309 of the fin represents the lower sacrificial material 310 of the fin 304. In one embodiment, the substrate portion 309 of the fin 304 is made thicker than the sacrificial material layers 310 to provide additional space between the substrate and the lowermost channel nanowire, allowing a lower gate separator film and a gate electrode / gate dielectric to be formed between the substrate and the lower channel nanowires. During structuring, the substrate 301 can also be structured to form a substrate region 312 continuous with the fin 304 and the flat trench insulating region (STI region) 315 in one embodiment. The STI region 315 serves to reduce current leakage between adjacent non-planar gate wrap-around devices.In one embodiment, at least a portion of the substrate region 312 extending to the fin 304 can comprise the buffer layers 311 of the substrate 301. In another embodiment, the STI regions 315 are filled with a dielectric STI layer 305. The dielectric STI layer 305 can comprise any known dielectric layer, such as, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-K dielectric, or any combination thereof. The dielectric STI layer 305 is formed by first uniformly depositing a dielectric STI layer 305 onto substrate 301 and over fin 304 using conventional chemical vapor deposition methods. The dielectric STI layer 305 is initially deposited with a greater thickness than the combined thickness of the fin 304 and the substrate region 312.Subsequently, the dielectric STI layer 305 is planarized using a conventional chemical-mechanical planarization process. The dielectric STI layer 305 is then recessed using a conventional etching process to expose fin 304, as shown in [reference]. Fig. Figure 3A shows that in one embodiment, the STI dielectric is embedded below the surface 303 of the substrate 301, so that the lower part of the fin 304 is formed from the substrate 301, as shown in Fig. Figure 3A illustrates this. In this way, fin 304 comprises a substrate portion 309, which forms the lower sacrificial material 310 of fin 304. In one embodiment, the substrate portion 309 of fin 304 is made thicker than the sacrificial material layers 310 to provide additional space between the substrate and the bottommost channel nanowire, allowing a bottom gate separator film and a gate electrode / gate dielectric to be formed between the substrate and the bottom channel nanowires. Alternatively, a separate sacrificial layer can be formed between the surface 303 and the bottommost semiconductor material layer 308.

[0028] The fin 304 has side walls 302 and 306, a fin height 316, a fin width 318, and a fin length 320. During the formation of the fin 304, the side walls 302 and 306 are unbounded planes, allowing the fin 304 to experience lattice stress relief in a perpendicular direction to the fin length 320. This means that during fin formation, the biaxially stressed layers described above are reduced to essentially uniaxially stressed layers. In one embodiment, the fin 304 is stressed uniaxially in a direction parallel to the fin length 320, but the lattices are relieved in a perpendicular direction to the length 320. In another embodiment, the fin 304 is formed with a fin width 318 of less than 30 nm, and ideally less than 25 nm.In one embodiment, the fin height 316 is less than the height, which leads to integration problems such as fin tilting, fin profile distortion, and low uniformity of the critical fin dimensions. In a particular embodiment, the fin height 316 is between 30 and 75 nm.

[0029] The thickness of the layers of semiconductor material 308 and the layers of sacrificial material 310 influence the electrical properties of the channel nanowires 343 and the integration and performance of the device 100. In one embodiment, the layers of semiconductor material 308 are sufficiently thick to prevent the formation of channel nanowires 343 with excessive surface scattering and thus high channel resistance and low carrier mobility. The layers of semiconductor material 308 are therefore sufficiently thin to form channel nanowires 343 that allow the device 100 to operate in a fully depleted state. The thickness of the layers of sacrificial material 310 influences the subsequent spacing between the channel nanowires 343 and thus the ability of the dielectric gate layer 350 and the gate electrode 352 to fully form around each channel nanowire 343.In one embodiment, the layers of sacrificial material 310 are sufficiently thick to allow the dielectric gate layer 350 to subsequently form completely around the channel nanowires 343, and for the gate electrode 352 to form on the dielectric gate layer 350 to completely enclose the channel nanowires 343. The thickness of the layers of semiconductor material 308 and the layers of sacrificial material 310 also influences the fin height 316. In one embodiment, the layers of semiconductor material 308 and the layers of sacrificial material 310 are sufficiently thin to achieve a fin height 316 that is below the height at which integration problems begin to occur. In a particular embodiment, the layers of semiconductor material 308 are formed with a thickness of approximately 5 to 50 nm, and the layers of sacrificial material 310 are formed with a thickness of approximately 5 to 30 nm.

[0030] The total number of alternating layers of semiconductor material 308 and sacrificial material 310 influences the fin height 316 and the drive current capacitance of the device. The number of layers of semiconductor material 308 corresponds to the number of channel nanowires 343 subsequently formed. A higher number of channel nanowires 343 enables a higher drive current capacitance of the device 100. However, too many layers of semiconductor material 308 and sacrificial material 310 result in a fin height 316 that cannot be integrated. In one embodiment, the number of layers 308 and 310 is sufficiently low to achieve an integrable fin height 316. In a particular embodiment, the fin 304 has approximately 3-6 layers of semiconductor material 308 and approximately 3-6 layers of sacrificial material 310.

[0031] Referring to step 204 in flowchart 200 and the corresponding Fig. 3B and Fig. In 3C, a gate sacrificial electrode 352 is formed over the region 328 of the fin 304. The gate sacrificial electrode 352 defines the channel region of the transistor. The gate sacrificial electrode 352 is formed by uniformly applying a dielectric gate sacrificial layer 322 to the fin 304. The dielectric gate sacrificial layer 322 is applied to the surface and the side walls 302, 306 of the fin 304. The dielectric gate sacrificial layer 322 can be applied with a thickness of approximately 10–50 µm. As shown in Fig. As shown in Figure 3B, a gate sacrificial layer 324 is then uniformly applied to the dielectric gate sacrificial layer 322 and over the fin 304. The gate sacrificial layer 324 is applied with a greater thickness than the fin thickness 316. The gate sacrificial layer 324 can be planarized using a conventional chemical-mechanical planarization process. As shown in Figure 3B, a gate sacrificial layer 324 is applied uniformly to the dielectric gate sacrificial layer 322 and over the fin 304. Fig. Following the representation in 3C, the sacrificial gate 326 is subsequently formed by structuring the gate sacrificial layer 324 using conventional photolithography and etching processes. The gate sacrificial electrode 326 is formed over the channel region 328 of the fin 304 and has a thickness 329 that is greater than the fin height 316. The gate sacrificial electrode 326 then serves to protect the channel region 328 of the fin 304 during the removal of the sacrificial portions 332 of the fin 304.

[0032] During the structuring of the gate sacrificial electrode, the dielectric gate sacrificial layer 322 is exposed on the sacrificial portions 332 of the fin 304 on opposite sides of the gate sacrificial electrode 352. The dielectric gate sacrificial layer 322 serves as an etch stop during the structuring and formation of the gate sacrificial electrode 326, thus preventing damage to the fin 304. In one embodiment, the dielectric gate sacrificial layer 322 and the gate sacrificial layer 324 are formed from materials with sufficiently different etch selectivities, with the dielectric gate sacrificial layer 322 serving as an etch stop for etching the gate sacrificial layer 324. In a particular embodiment, the dielectric gate sacrificial layer 322 is a dielectric layer (e.g., silicon oxide, silicon nitride, and silicon oxynitride), and the gate sacrificial layer 324 is formed from a semiconductor material (e.g., polysilicon).The dielectric gate sacrificial layer 322 and the gate sacrificial layer 324 can be deposited using conventional chemical vapor deposition methods. Subsequently, the dielectric gate sacrificial layer 322 is removed from the surface and the side walls 302, 306 of the sacrificial portion 332 of the fin 304 using a conventional wet etching process to expose the sacrificial portions 332 of the fin 304. In the embodiment in which the dielectric gate sacrificial layer 322 is a silicon oxide layer, the dielectric gate sacrificial layer 322 is removed using a dilute HF in a wet etching process.

[0033] Referring to step 206 in flowchart 200 and the corresponding Fig. In 3C, a sidewall spacer pair 330 is formed on the opposite sidewalls 334 of the gate sacrificial electrode 326. The sidewall spacer pair 330 can be formed using conventional methods known to the art for forming selective spacers. In one embodiment, a conformal dielectric spacer layer, such as silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof, is first applied uniformly to all structures, including the fin 304 and the gate sacrificial electrode 326. The dielectric spacer layer is applied conformally so that it is essentially the same thickness on both vertical surfaces, such as the sidewalls 302, 306, 334, and the horizontal surfaces, such as the surface of the gate sacrificial electrode 326.The dielectric spacer layer can be deposited using conventional chemical vapor deposition (CVD) processes such as low-pressure galvanic vapor deposition (LPCVD) and plasma-enhanced galvanic vapor deposition (PECVD). In one embodiment, the dielectric spacer layer is deposited with a thickness between approximately 2 and 10 nanometers. Subsequently, an unstructured, anisotropic etching process is performed on the dielectric spacer layer using conventional anisotropic etching techniques, such as reactive ion etching (RIE). During the anisotropic etching process, the majority of the dielectric spacer layer is removed from the horizontal surfaces, while the dielectric spacer layer remains on the vertical surfaces, such as the sidewalls 334 of the gate sacrificial electrode 326 and the sidewalls 302, 306 of the fin 304.Since the thickness 329 of the gate sacrificial electrode 326 is greater than the fin height 316, the thickness of the remaining dielectric spacer layer after anisotropic etching is greater on the side walls 334 of the gate sacrificial electrode 326 than on the side walls 302, 306 of the fin 304. It is this thickness difference that enables the selective formation of the side wall spacers 330 on the side walls 334 of the gate sacrificial electrode 326. Subsequently, an unstructured isotropic etching process is carried out to remove the remaining dielectric spacer layer from the side walls 302, 306 of the fin 304, leaving a pair of side wall spacers 330 on the opposite side walls 334 of the gate sacrificial electrode 326. In one embodiment, the isotropic etching process is a wet etching process.In a specific embodiment where the spacer layer consists of silicon nitride or silicon oxide, a wet etching solution comprising phosphoric acid (H3PO4) or a buffered etching oxide (BOE) is used for the isotropic etching process. In an alternative embodiment, the isotropic etching process is a dry etching process. In such an embodiment, NF3 is used in the downstream plasma reactor to isotropically etch the dielectric spacer layers.

[0034] Referring to step 208 in flowchart 200 and the corresponding Fig. In 3D, the sacrificial portions 332 of the fin 304 are removed to expose the source / drain region 334 of the substrate 301. The sacrificial portion 332 of the fin 304 can be removed using conventional etching methods such as wet etching or plasma dry etching. In an embodiment in which the fin 304 comprises alternating layers of germanium 308 and silicon germanium 310, a wet etching solution such as ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) is used to selectively remove the sacrificial portions 332 of the fin 304. The channel region 328 of the fin 304 is protected from etching by the sacrificial gate 326 and the sidewall spacer pair 330. In one embodiment, the surface 303 of the substrate 301 is left uncovered during the removal of the sacrificial portion 332 of the fin 304 to form a source / drain trench 336.The source / drain trench 336 serves to accommodate the subsequent growth of the embedded epitaxial source 338 and drain regions 339. In one embodiment, the source / drain trench 336 is formed with a depth between 20 and 40 nm. Alternatively, the sacrificial portions 332 of the fin 304 are removed, so that the surface 303 of the substrate 301 lies above or planar to the dielectric STI layer 305.

[0035] Referring to step 210 in flowchart 200 and the corresponding Fig. In 3E, the embedded epitaxial source 338 and drain regions 339 are formed on the source / drain regions 334 of the substrate 301. In one embodiment, the embedded epitaxial source 338 and drain regions 339 are formed using conventional epitaxial deposition methods such as low-pressure vapor deposition, vapor-phase epitaxy, and molecular beam epitaxy. In another embodiment, the embedded epitaxial source 338 and drain regions 339 form in the source / drain channel 336. The embedded epitaxial source 338 and drain regions 339 couple to the channel regions 328 of the fin 304 and rise above the surface of the dielectric STI layer 305. The embedded epitaxial source 338 and drain regions 339 can be formed from any known material that possesses a lattice constant.Ideally, the embedded source 338 and drain regions 339 are formed from an epitaxially grown, single-crystal semiconductor such as, but not limited to, Si, Ge, SiGe, GeSn, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, GaP, and InP. In one embodiment, the embedded epitaxial source 338 and drain regions 339 are formed from a single-crystal semiconductor material with a lattice constant that differs from the lattice constant of the surface 303 of the substrate 301. In a particular embodiment, the lattice constant of the embedded epitaxial source 338 and drain regions 339 is greater than the lattice constant of the surface 303 of the substrate 301.

[0036] In one specific embodiment, the embedded epitaxial source 338 and drain regions 339 are formed from germanium, and the surface 303 of the substrate 301 is formed from silicon germanium. In another embodiment, the embedded epitaxial source 338 and drain regions 339 are formed from the same single-crystal semiconductor material (e.g., Ge) used to form the channel nanowires. In yet another embodiment of the present invention, the embedded epitaxial source 338 and drain regions 339 are formed from a material (e.g., GaAs) whose lattice constant is greater than that of the semiconductor material (e.g., SiGe) on the surface 303 of the substrate 301 and greater than the lattice constant of the semiconductor material (e.g., Ge) 308 used to form the channel nanowires, in order to further increase the uniaxial lattice stress in the channel nanowires.

[0037] In another specific embodiment, the embedded epitaxial source 338 and drain regions 339 are formed from silicon, and the surface 303 of the substrate 301 is formed from silicon-germanium. In one embodiment of the present invention, the embedded epitaxial source 338 and drain regions 339 are formed from the same single-crystal semiconductor material (e.g., Si) used to form the channel nanowires. In another embodiment of the present invention, the embedded epitaxial source 338 and drain regions 339 are formed from a material (e.g., silicon carbide or carbon-doped silicon) whose lattice constant is smaller than that of the semiconductor material (e.g., SiGe) on the surface 303 of the substrate 301 and smaller than the lattice constant of the semiconductor material (e.g., SiGe).Si) 308, which is used to form the channel nanowires in order to further increase the uniaxial tensile load in the channel nanowires.

[0038] The mismatch of the lattice constant between the embedded epitaxial source 338 and drain regions 339 and the surface 303 of the substrate 301 generates a lattice load, whereby the embedded epitaxial source 338 and drain regions 339 are subjected to uniaxial lattice stress in a direction parallel to the length 320 of the fin 304. The integrated epitaxial source 338 and drain regions 339 are lattice-unloaded in a direction perpendicular to the length 329 of the fin 304, since the surfaces belonging to the side walls 335 and 337 remain unloaded during the formation of the embedded epitaxial source 338 and drain regions 339. The mismatch of the lattice constant also causes the embedded epitaxial source 338 and drain regions 339 to exert a force on the channel region 328 of the fin 304.Since the layers of semiconductor material 308 in the channel region 328 of the fin 304 subsequently form the channel nanowires 343, the embedded epitaxial source 338 and drain regions 339 then exert a force on the channel nanowires 343, which can support the maintenance of the lattice stress in the channel nanowires 343. In one embodiment, the lattice constant of the embedded epitaxial source 338 and drain regions 339 is greater than the lattice constant of the surface 303 of the substrate 301. In such an embodiment, the embedded epitaxial source 338 and drain regions 339 are subjected to compressive stress and provide a compressive force on the channel nanowires 343. In another embodiment, the lattice constant of the embedded epitaxial source 338 and drain regions 339 is smaller than the lattice constant of the surface 303 of the substrate 301.In such an embodiment, the embedded epitaxial source 338 and drain regions 339 are subjected to tensile stress and provide a tensile force on the channel nanowires 343.

[0039] In one embodiment, during the structuring of a stack of nanowire-forming layers and intervening sacrificial layers, a first uniaxial stress is applied along the channel regions of the nanowire-forming layers. The embedded source and drain regions are then formed by etching away the outer portions of the fin and subsequently forming the epitaxial source and drain regions in their place. In such an embodiment, the embedded epitaxial source and drain regions are grown from a crystalline surface of a substrate beneath the fin. If the removed outer portions with the alternating nanowire-forming layers are heterogeneous and the intervening sacrificial layers have a different composition, the replacement with embedded source and drain regions by epitaxial growth replaces the heterogeneous portions with homogeneously composed regions.Thus, a new lattice mismatch is added to both sides of the etched fin. The embedded epitaxial source and drain regions further increase the uniaxial stress of the existing nanowire-forming layers. Moreover, after the subsequent removal of the intervening sacrificial layers, the embedded epitaxial source and drain regions act as anchors for the discrete nanowires then formed. Since the embedded epitaxial source and drain regions are epitaxially grown from the underlying substrate, the anchoring is effective in maintaining the uniaxial stress of the initial nanowire-forming layers during fin structuring. The embedded epitaxial source and drain regions maintain and increase the uniaxial stress of the ultimately formed nanowire channel segments.It should be noted that the replacement of the heterogeneous layers with a homogeneous layer described above can also be carried out using the same material as used for the nanowire-forming layers. However, in another embodiment, to further increase the uniaxial stress, a different material than all the materials used in the heterogeneous layer stack can be epitaxially grown to form the embedded epitaxial source and drain regions. For example, in one embodiment, the epitaxial source and drain regions are formed from a material with a higher lattice constant than all the materials in the heterogeneous fin. In this embodiment, the uniaxial compressive stress in the ultimately formed nanowire channel segments is further increased.In another embodiment, the epitaxial source and drain regions are formed from a material with a smaller lattice constant than all materials in the heterogeneous fin. In this embodiment, the uniaxial tensile stress in the resulting nanowire channel segments is further increased.

[0040] In one embodiment, the surface 303 of the source / drain regions 334 of the substrate 301 is a single-crystal material with a <100> -orientation, which serves as a seedbed for the epitaxial growth of the embedded epitaxial Source-338 and Drain-regions 339. The embedded Source-338 and Drain-regions 339 thus grow in a <100> -Orientation. The one belonging to side walls 335 and 337 <111> The area can grow at a more favorable rate during the formation of the embedded epitaxial source 338 and drain regions 339, resulting in the embedded epitaxial source 338 and drain regions 339 <111> -are faceted.

[0041] It must be acknowledged that this is not necessary, although desirable, to create the embedded epitaxial source 338 and drain regions 339 by etching away the sacrificial portion 332 of the fin 304 and subsequent epitaxial growth to form the source and drain regions, as shown in the Fig. 3D and Fig. 3D shown, to form in order to increase the stress on the channel nanowires. In an alternative embodiment, the sacrificial portions 332 of the fin 304 are not etched away but retained to form the source and drain regions for the device, as shown in Fig. Figure 1E shows that the sacrificial portions 332 of the fin 304 can be doped at this time using known techniques such as ion implantation to form the source and drain regions of a desired conductivity type and concentration level. Furthermore, an epitaxial semiconductor film can be grown on the surface and sidewalls of the sacrificial portions 334 of the fin 304 to optionally form raised source and drain regions to reduce current crowding.

[0042] Then, with reference to Fig. In 3F, an interlayer dielectric layer (ILD) 340 is uniformly applied to all structures, including the raised source 338 and drain regions 339, the gate sacrificial electrode 326, and the sidewall spacer pair 334. The dielectric spacer layer 340 can be applied using conventional chemical vapor deposition (e.g., low-pressure galvanic vapor deposition (LPCVD) and plasma-enhanced galvanic vapor deposition (PECVD) processes. In one embodiment, the ILD layer 340 is formed from any known dielectric material, such as, but not limited to, undoped silicon dioxide, doped silicon dioxide (e.g., BPSG, PSG), silicon nitride, and silicon oxynitride. The ILD layer 340 is then processed using a conventional chemical-mechanical planarization process to expose the top part of the gate sacrificial electrode 326 and the top part of the side wall spacer pair 334.

[0043] Referring to step 212 in flowchart 200 and the corresponding Fig. 3G and Fig. 3H the gate sacrificial electrode 326 is removed to expose the channel area 328 of the fin 304. Fig. 3H is the corresponding two-dimensional cross-section of the Fig. 3H. The ILD layer 340 protects the embedded source 338 and drain regions 339 during the removal of the gate sacrificial electrode 326. The gate sacrificial electrode 326 can be removed using conventional etching methods such as wet etching or plasma dry etching. In an embodiment where the gate sacrificial electrode 326 is made of polysilicon and the ILD layer 340 is made of silicon dioxide, a wet etching solution such as TMAH can be used for the selective removal of the gate sacrificial electrode 326. The dielectric gate sacrificial layer 322 on the channel region 328 of the fin 304 serves as an etch stop and protects the channel region 328 of the fin 304 during the removal of the gate sacrificial electrode 326. Subsequently, the dielectric gate sacrificial layer 322 is removed using a conventional etching process to expose the channel region 328 of the fin 304 prior to step 214 in flowchart 200.In the embodiment in which the dielectric gate sacrificial layer 322 is a silicon oxide layer, the dielectric gate sacrificial layer 322 is removed using a dilute HF in a wet etching process.

[0044] Referring to step 214 in flowchart 200 and the corresponding Fig. 3I The layers of sacrificial material 310 between the layers of semiconductor material 308 in the channel region 328 of the fin 304 are removed to form the channel nanowires 343. The layers of sacrificial material 310 can be removed with any known etchants that act selectively on the layers of semiconductor material 308, the etchant etching the layers of sacrificial material 310 at a significantly higher rate than the layers of semiconductor material 308. In one embodiment, the etchant selectively etches the layers of semiconductor material 308, while the layers of sacrificial material 310 remain unetched.In an embodiment in which the layers of the semiconductor material 308 consist of germanium and the layers of the sacrificial material 310 consist of silicon-germanium, the layers of the sacrificial material 310 can be selectively removed with a wet etching agent such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solutions. In an embodiment in which the layers of the semiconductor material 308 consist of silicon and the layers of the sacrificial material 310 consist of silicon-germanium, the layers of the sacrificial material 310 can be selectively removed with a wet etching agent such as, but not limited to, aqueous carboxylic acid / nitric acid / HF solution and aqueous citric acid / nitric acid / HF solution. The removal of the layers of the sacrificial material 310 leaves cavities 342 between the layers of the semiconductor material 308.The cavities 342 between the layers of semiconductor material 308 are between approximately 5 and 30 nm thick. The remaining layers of semiconductor material 310 form a vertical array of channel nanowires 343, which are coupled to the embedded epitaxial source 338 and drain regions 339. The formed channel nanowires 343 are between approximately 5 and 50 nm thick. The channel nanowires 343 run parallel to the surface 303 and are aligned to form a single column of channel nanowires 343 with a bottommost channel nanowire 344 at the bottom of the column.

[0045] In one embodiment as in Fig. As shown in Figure 3I, all sacrificial material 310 between the embedded epitaxial source and drain regions, including the portions below the sidewall spacers 330, is removed. Etching the portions between the spacers simplifies the fabrication process, as the removal of the sacrificial material 310 can be based on the selectivity of the etching with respect to the sacrificial material and the embedded epitaxial source and drain regions, thus allowing over-etching to be used for sacrificial material removal. However, removing the sacrificial material 310 below the spacers 330 can result in a slightly enlarged opening between the spacer 330 above the topmost channel nanowire 343. This can cause the subsequently formed gate electrode to have a slightly larger gate length between the channel nanowires compared to the gate length above the topmost channel nanowire.In one embodiment, etching is time-controlled, so that after etching, a portion of the sacrificial material 310 adjacent to the embedded source and drain regions remains between the spacers 330 to form the channel nanowires 343. This allows the subsequently formed gate electrode to have the same gate length on all surfaces of the channel nanowires.

[0046] Referring to step 216 in flowchart 200 and the corresponding Fig. 3 years and Fig. In 3K, a lower gate insulation 348 is formed on the surface 303 of the substrate 301 and under the lowest channel nanowire 344. The lower gate insulation 348 is formed by first applying a dielectric layer 346 uniformly around and over the channel nanowires 343, as shown in Fig. Figure 3J illustrates this. The dielectric layer 346 completely fills the cavities 342 between the channel nanowires 343, including the area between the lowest channel nanowire 344 and the surface 303 of the substrate 301. The dielectric layer 346 also forms the surface of the ILD layer 340. In one embodiment, the dielectric layer 346 is formed from any known dielectric material, such as, but not limited to, silicon dioxide, silicon oxide, silicon nitride, and silicon oxynitride. In a specific embodiment, the dielectric layer 346 is formed from silicon dioxide. Ideally, the dielectric layer 346 is applied using a highly conformal deposition method, such as low-pressure kinetic vapor deposition (LPCVD), ALD technologies, or a spin deposition process, to ensure that the cavities 342 between the channel nanowires 343 are completely filled. Subsequently, as shown in Fig. Figure 3K shows the dielectric layer 346 being etched from top to bottom using a conventional isotopic dielectric etching process. In a particular embodiment where the dielectric layer 346 consists of silicon oxide, a time-delayed RF wet etching process is used to etch the dielectric layer. During the etching process, the majority of the dielectric layer 346 is removed, leaving a thin layer on the surface 303 of the substrate 301 and beneath the bottommost channel nanowire 344, which forms the bottom gate insulation 348. The thickness of the bottom gate insulation 348 depends on the length of time the dielectric layer 346 is etched.In one embodiment, the recess is long enough to achieve a lower gate insulation thickness sufficient to insulate the surface 303 of the substrate 301 against capacitive coupling by the gate electrode 352. In another embodiment, the recess is made for a sufficiently long period of time to achieve a lower gate insulation thickness that is sufficiently thin, such that the cavity between the bottommost channel nanowire 344 and the lower gate insulation 348 is large enough for the dielectric gate layer 350 to completely enclose the bottommost channel nanowire and for the gate electrode 352 to form around the bottommost channel nanowire 344.In one embodiment, the thickness of the lower gate insulation 348 is sufficiently thick to protect the surface 303 of the substrate 301 against capacitive coupling by the gate electrode 352 and sufficiently thin to allow the dielectric gate layer 350 and the gate electrode 352 to completely enclose the bottom channel nanowire 344. In a particular embodiment, the thickness of the lower gate insulation 348 is between approximately 100 and 300 Ω.

[0047] Referring to steps 218 and 220 of flowchart 200 and the corresponding Fig. 3L and Fig. 3M, a dielectric gate layer 350 is formed around each channel nanowire 343 and a gate electrode 352 is formed on the dielectric gate layer 350, which surrounds all channel nanowires 343. Fig. 3M is the corresponding three-dimensional cross-section of Fig. 3L. The dielectric gate layer 350 can be formed from any known dielectric gate material, as described above. The dielectric gate layer 350 is formed using a highly conformal deposition process, such as an ALD process, to ensure that the dielectric gate layer has a uniform thickness around each channel nanowire 343. In one particular embodiment, the dielectric gate layer consists of HfO2 and is deposited with a thickness of 1 to 6 nanometers. The dielectric gate layer 350 is uniformly deposited and also forms the surface of the ILD layer 340. Subsequently, a gate electrode is uniformly deposited onto the dielectric gate layer 350 to form the gate electrode 352. The gate electrode 352 can be formed from any known gate electrode material, as described above.The gate electrode material is applied using a conformal deposition process, such as an ALD method, to ensure that the gate electrode 352 is deposited on the dielectric gate layer 350 as well as around and between all channel nanowires 343. The electrode material uniformly deposited on the surface of the ILD layer 340 and the dielectric gate layer 350 are then chemically and mechanically planarized until the surface of the ILD layer 340, as shown in the [reference], is [reference]. Fig. 3L and Fig. 3M is shown, exposed. The resulting component 300, which is manufactured using the method described in flowchart 200, is a non-planar gate wrap-around component according to an embodiment of the present invention.

[0048] Fig.Figure 4 shows a computing element 400 according to one implementation of this invention. The computing element 400 houses a printed circuit board 402. The printed circuit board 402 can comprise a number of components, including, but not limited to, a processor 404 and at least one communication chip 406. The processor 404 is physically and electrically coupled to the printed circuit board 402. In some implementations, at least one communication chip 406 is also physically and electrically coupled to the printed circuit board 402. In other implementations, the communication chip 406 is part of the processor 404.

[0049] Depending on its applications, the computing element 400 may include other components, which may or may not be physically and electrically coupled to the circuit board 402. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a cryptoprocessor, a chipset, an antenna, a screen, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a GPS satellite navigation system, a compass, an accelerometer, a gyroscope, a loudspeaker, a camera, and a mass storage device (such as a hard disk drive, compact disc (CD), digital versatile disc (DVD), and so on).

[0050] The Communications Chip 406 enables wireless communication for the transmission of data to and from the Computing Element 400. The term "wireless" can be used to describe circuits, devices, systems, procedures, techniques, communication channels, etc., that communicate data through a non-solid medium using modulated electromagnetic radiation. The term does not imply that the connected devices do not contain any wires, although this may be the case in some embodiments. The Communications Chip 406 can implement any number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, and any other wireless protocols referred to as 3G, 4G, 5G, and beyond.The 400 computing element can contain a variety of 406 communication chips. For example, a first 406 communication chip can be used for short-range wireless communication such as Wi-Fi and Bluetooth, and a second 406 communication chip can be used for longer-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

[0051] The processor 404 of the computing element 400 comprises an integrated circuit dielectric packed within the processor 404. In some implementations of the invention, the integrated circuit dielectric of the processor includes one or more components, such as non-planar gate wrap-around devices, formed according to the implementations of the invention. The term "processor" can refer to all components or parts of a component that process electronic data from registers and / or memories in order to convert this electronic data into other electronic data that can be stored in registers and / or memories.

[0052] The communication chip 406 also includes an integrated circuit dielectric packed within the communication chip 406. According to another implementation of the invention, the integrated circuit dielectric of the communication chip comprises one or more devices such as non-planar gate wrap-around devices, which are formed according to the implementations of the invention.

[0053] In further implementations of the invention, another component housed by the computing element 400 can include an integrated circuit dielectric containing one or more components such as non-planar gate wrap-around components formed according to the implementations of the invention.

[0054] The Computing Element 400 can be a laptop, netbook, notebook, ultrabook, smartphone, tablet, personal digital assistant (PDA), ultra mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, or digital video recorder. In other implementations, the Computing Element 400 can be any other electronic data-processing device.

[0055] One or more embodiments of the present invention include a non-planar gate wrap-around transistor with one of the embedded epitaxial source and drain regions or an insulating layer at the bottom gate formed between the substrate and the bottom channel nanowire, or both.

Claims

[1] A semiconductor device comprising: a substrate (102, 301) with a surface (104) with a first lattice constant; epitaxial source (106, 338) and drain regions (107, 339) which are applied to the surface (104) of the substrate (102, 301) and are separated from each other in a first lateral direction, said epitaxial source (106, 338) and drain regions (107, 339) have a second lattice constant which differs from the first lattice constant; a plurality of channel nanowires (110, 343) with a third lattice constant that differs from the first lattice constant, said plurality of channel nanowires (110, 343) is coupled to the epitaxial source (106, 338) and drain (107, 339) regions, and said plurality of channel nanowires (110, 343) includes a bottommost channel nanowire (115, 344); a dielectric gate layer (116, 350) applied to and surrounding all channel nanowires (110, 343), and a gate electrode (118) formed on the dielectric gate layer (116, 350) and enclosing all channel nanowires (110, 343); the plurality of channel nanowires (110, 343) are not in direct contact with each other, and wherein the surface (104) defines a fin-shaped portion of the substrate (102, 301), and the fin is arranged in a second lateral direction perpendicular to the first lateral direction between and adjacent to a trench insulation layer (105), and the extent of the fin along the first lateral direction is greater than the extent of the fin along the second lateral direction, and wherein the epitaxial source (106, 338) and drain regions (107, 339) <111> are faceted, and wherein the epitaxial source area (106, 338) has a first width (122) at a top of the trench insulation layer (105) and a second width (124) at an upper end of the epitaxial source area (106, 338), the first width (122) being larger than the second width (124) and the width of the epitaxial source area (106,338) decreases from the first width (122) to the second width (124). [2] The semiconductor device according to the preceding claim, wherein the plurality of channel nanowires (110, 343) are formed from the same single-crystal semiconductor material as the epitaxial source (106, 338) and drain regions (107, 339). [3] Semiconductor device according to claim 1, wherein the second lattice constant is larger than the first lattice constant.

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