METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Abstract

A method for manufacturing a semiconductor device comprising the following steps: (a) Producing an epitaxial SiC substrate (10) in which an epitaxially grown SiC layer (2) with a defect concentration equal to or less than 1 / 10,000 of that of the SiC support substrate (1) and with a thickness of 50 µm or more is arranged on a SiC support substrate (1); (b) Forming a defect region forming a semiconductor element by selectively implanting defect ions into a first principal surface of the epitaxial SiC substrate (10); (c) Forming an ion implantation area (6) which controls the curvature of the epitaxial SiC substrate (10) by implanting predetermined ions into a second principal surface of the epitaxial SiC substrate (10); and (d) Heating the epitaxial SiC substrate (10) after step (b) and step (c).

Description

Technical field

[0001] The present invention relates to a method for manufacturing a semiconductor device. It relates in particular to a manufacturing method for the stable production of a silicon carbide semiconductor device. State of the art

[0002] In a semiconductor device with an ultra-high breakdown voltage (10 kV or more) achieved through the use of silicon carbide (SiC), a drift layer is designed to have a low impurity concentration and a large thickness to ensure the breakdown voltage. The drift layer typically consists of an epitaxially grown SiC layer formed on a high-concentration SiC support substrate via epitaxial growth, with the epitaxially grown SiC layer exhibiting a low impurity concentration.

[0003] The impurity concentration of SiC is generally controlled by changing the doping concentration of nitrogen atoms when the conductivity type is n-type. The nitrogen atom can replace the carbon atom in its position within the SiC crystal, acting as a donor. The nitrogen atom has a smaller atomic radius than the carbon atom. Therefore, when the SiC crystal is doped with nitrogen, the lattice spacing decreases.

[0004] When an epitaxially grown SiC layer with a low impurity concentration is formed on a SiC support substrate with a high impurity concentration, a lattice mismatch occurs due to the difference in lattice spacing between the SiC support substrate and the epitaxially grown SiC layer, resulting in a large warping or bulging in an epitaxial SiC substrate that includes the SiC support substrate and the epitaxially grown SiC layer.

[0005] More precisely: As a result of compressive stress on the epitaxially grown SiC layer, the epitaxial SiC substrate becomes convexly bulged, protruding towards the epitaxially grown SiC layer. If the bulging of the epitaxial SiC substrate is large, it can crack during the manufacturing process of a SiC semiconductor device, particularly in steps involving thermal shock from heat treatment, etc.

[0006] Furthermore, a problem arises in that if the breakdown voltage of the SiC semiconductor device is increased, an epitaxially grown SiC layer with a lower impurity concentration and greater thickness is required. Therefore, the curvature of the epitaxial SiC substrate increases further.

[0007] The following has already been proposed, as disclosed, for example, in patent document 1: A buffer layer with a gradually inclined structure, wherein the impurity concentration is gradually changed, or with a continuously inclined structure in which the impurity concentration is continuously changed, is formed between a SiC support substrate and an epitaxially grown SiC layer to reduce a lattice mismatch between the SiC support substrate and the epitaxially grown SiC layer.

[0008] Patent document 2 discloses a technique in which, in a group III nitride semiconductor substrate, the curvature of the substrate is reduced by implanting ions from each of the two surfaces of the substrate to form an ion implantation area having a predetermined depth on both main surface sides of the substrate.

[0009] In a process in which a buffer layer is formed between a SiC support substrate and an epitaxially grown SiC layer as in patent document 1, the curvature after the formation of the epitaxially grown SiC layer (before the formation of a semiconductor element) is reduced, but the curvature of the epitaxial SiC substrate, which occurs under the conditions during the formation of the semiconductor element (for example, under ion implantation conditions), cannot be avoided.

[0010] The method disclosed in patent document 2, i.e., a method in which an ion implantation area is formed on both main surfaces of a semiconductor substrate to control the substrate's curvature, can prevent substrate curvature before the formation of a semiconductor element. However, it is doubtful whether substrate curvature can be prevented after the semiconductor element has formed.

[0011] Patent document 3 discloses a high-voltage semiconductor device with a SiC substrate.

[0012] Patent document 4 discloses a method for manufacturing a silicon carbide semiconductor device with a p-type collector layer. State-of-the-art documents, patent documents Patent document 1: International publication WO 2011 / 083552 A1 Patent document 2: Japanese patent application disclosure JP 2011-100860A Patent document 3: US 7,947,988 B2 Patent document 4: US 2013 / 0 078 771 A1 Summary of the invention Problems to be solved with the invention

[0013] As described above, the occurrence of bulges in an epitaxial SiC substrate due to a lattice mismatch between a SiC support substrate and an epitaxially grown SiC layer is undesirable, and a technique to prevent bulging of the epitaxial SiC substrate is necessary. In particular, when fabricating a semiconductor device with an ultra-high breakdown voltage, an epitaxially grown SiC layer is used that has an impurity concentration equal to or less than 1 / 10,000 of that of a SiC support substrate with low resistance and a high impurity concentration, and which has a thickness of 50 µm or more. Therefore, bulging of the epitaxial SiC substrate is not noticeable.

[0014] The present invention was designed to solve the problems described above. It is therefore an object of the present invention to provide a method for manufacturing a semiconductor device which is suitable for the stable fabrication of a SiC semiconductor device, while preventing the epitaxial SiC substrate from cracking during the fabrication process of the SiC semiconductor device. Ways to solve the problem

[0015] The problem is solved by a method for manufacturing a semiconductor device with the features of claim 1. Advantageous further developments are set out in dependent claims 2 to 10. Effects of the invention

[0016] A method for fabricating a semiconductor device according to the present invention comprises a step in which an ion implantation region is formed, which controls the curvature of an epitaxial SiC substrate. Consequently, the curvature of the epitaxial SiC substrate caused by a lattice mismatch between a SiC support substrate and an epitaxially grown SiC layer is prevented, so that a nearly flat epitaxial SiC substrate can be obtained. Even after subsequent heat treatment, the epitaxial SiC substrate does not crack, and consequently, a stable SiC semiconductor device can be obtained.

[0017] Since ion implantation to control the curvature of the epitaxial SiC substrate is applied to a surface of the epitaxial SiC substrate on a side opposite the first principal surface, optimal implantation conditions for controlling the curvature can be selected without considering the conditions for forming a semiconductor element on the first principal surface of the epitaxial SiC substrate and the thickness and defect concentration of the epitaxially grown SiC layer. Brief description of the drawings Fig. Figure 1 is a sectional view showing a configuration of a (non-inventive) SiC MOSFET formed by a method for fabricating a semiconductor device according to embodiment 1 according to the present invention. Fig. Figure 2 is a view showing the top-view shape of the SiC MOSFET formed by the method for manufacturing a semiconductor device according to embodiment 1 according to the present invention. Fig. Figure 3 is a sectional view illustrating the method for manufacturing a semiconductor device according to embodiment 1 of the present invention. Fig. Figure 4 is a sectional view illustrating the method for manufacturing a semiconductor device according to embodiment 1 of the present invention. Fig. Figure 5 is a sectional view illustrating the method for manufacturing a semiconductor device according to embodiment 1 of the present invention. Fig. Figure 6 is a cross-sectional view showing an epitaxial SiC substrate equipped with a buffer layer. Fig. Figure 7 is a sectional view illustrating a modification of the method for manufacturing a semiconductor device according to embodiment 1 according to the present invention. Fig. Figure 8 is a top view illustrating a modification of the method for manufacturing a semiconductor device according to embodiment 1 according to the present invention. Fig. Figure 9 is a top view illustrating a modification of the method for manufacturing a semiconductor device according to embodiment 1 according to the present invention. Fig. Figure 10 is a perspective view showing a change in the shape of the epitaxial SiC substrate in a wafer state. Fig. Figure 11 is a perspective view showing a change in the shape of the epitaxial SiC substrate in a wafer state. Fig. Figure 12 is a perspective view showing a change in the shape of the epitaxial SiC substrate in a wafer state. Fig. Figure 13 is a sectional view illustrating a method for manufacturing a semiconductor device according to embodiment 2 of the present invention. Fig. Figure 14 is a cross-sectional view showing an epitaxial SiC substrate equipped with a buffer layer. Fig. Figure 15 is a sectional view illustrating a method for manufacturing a semiconductor device according to embodiment 3 of the present invention. Fig. Figure 16 is a cross-sectional view showing an epitaxial SiC substrate equipped with a buffer layer. Fig. Figure 17 is a sectional view illustrating a method for manufacturing a semiconductor device according to embodiment 4 of the present invention. Fig. Figure 18 is a sectional view illustrating a method for manufacturing a semiconductor device according to embodiment 5 of the present invention. Fig. Figure 19 is a sectional view illustrating the method for manufacturing a semiconductor device according to embodiment 5 of the present invention. Fig. Figure 20 is a cross-sectional view showing an epitaxial SiC substrate equipped with a buffer layer. Fig. Figure 21 is a sectional view illustrating a method for manufacturing a semiconductor device according to embodiment 6 of the present invention. Description of the embodiments: Embodiment 1

[0018] Fig. Figure 1 is a sectional view showing the configuration of a (non-inventive) SiC MOSFET (metal oxide semiconductor field-effect transistor) 100, which has been formed by means of a method for producing a semiconductor device according to embodiment 1 according to the present invention.

[0019] For the conductivity type of the defects, the n-type is defined as a "first conductivity type" and the p-type as a "second conductivity type" in the description below, but the conductivity types of the defects may also be defined in reverse. Device configuration

[0020] As in Fig. As shown in Figure 1, the SiC MOSFET 100 is formed on an epitaxial SiC substrate 10, wherein an epitaxially grown SiC layer 2 of the first conductivity type is arranged on the Si atomic plane or on the C atomic plane of a SiC support substrate 1 of the first conductivity type (n-type).

[0021] More precisely: A plurality of trough areas 3 of the second conductivity type (of the p-type) are selectively arranged on the upper layer of the epitaxially grown SiC layer 2 of the epitaxial SiC substrate 10, a trough contact area 5 of the second conductivity type is arranged in the area of ​​each trough area 3, and a source area 4 of the first conductivity type is arranged to surround the trough contact area 5. An ion implantation area 6 is arranged on a main surface of the SiC support substrate 1 on a side opposite the surface on which the epitaxially grown SiC layer 2 is arranged.

[0022] The top view of a SiC MOSFET 100 is shown below with reference to Fig. 2 described. Fig. Figure 2 is a top view of a SiC MOSFET 100 viewed from the sides of the well area 3, and as shown in Fig. As shown in Figure 2, the source area 4 surrounds the periphery of the trough contact area 5, which has an essentially tetragonal outer shape, and furthermore the outer periphery of the source area 4 is surrounded by the trough area 3.

[0023] A gate insulating layer, configured to extend from the top of a portion of the source region 4 to the top of the well region 3, and from the top of the epitaxially grown SiC layer 2 to the top of a portion of the source region 4 of the adjacent well region 3 between adjacent well regions 3, a gate electrode configured to cover the top of the gate insulating layer, a drain electrode formed on the SiC support substrate 1, etc., are not shown. Fig. 1 corresponds to a cross-section along line AA in Fig. 2. Manufacturing process

[0024] A method for manufacturing a semiconductor device according to embodiment 1 of the present invention is described below with reference to the Fig. Sections 3 to 5 describe which are sectional views that explain the manufacturing steps in sequence.

[0025] First, in the Fig. In step 3, the epitaxially grown SiC layer 2 of the first conductivity type is formed by epitaxial growth on the Si atomic plane or the C atomic plane of the SiC support substrate 1 of the first conductivity type to obtain the epitaxial SiC substrate 10. This step is referred to as a step to produce an epitaxial SiC substrate.

[0026] The defect concentration of the epitaxially grown SiC layer 2 is lower than the defect concentration of the SiC support substrate 1. For example, if the defect concentration of the SiC support substrate 1 has a value of 1 × 10 19cm -3 If so, then the defect concentration of the epitaxially grown SiC layer 2 has a value of 1 × 10 14 cm -3 Nitrogen is used as the dopant for the SiC support substrate 1 and the epitaxially grown SiC layer 2 when the conductivity type is controlled to be the n-type, and aluminum is used when the conductivity type is controlled to be the p-type.

[0027] The impurity concentration of the SiC support substrate 1 is preferably in the range of 1 × 10 17 cm -3 up to 1 × 10 21 cm -3 , and the defect concentration of the epitaxially grown SiC layer 2 is preferably in the range of 1 × 10 13 cm -3 up to 1 × 10 16 cm -3The thickness of the epitaxially grown SiC layer 2 is preferably 50 µm to 500 µm. As a result of compressive stresses on the epitaxially grown SiC layer 2, the epitaxial SiC substrate 10 inevitably warps so that it protrudes in the direction of the epitaxially grown SiC layer 2.

[0028] Subsequently, selective ion implantation is performed on a major surface (a first major surface) of the epitaxial SiC substrate 10 on the side of the epitaxially grown SiC layer 2 to form the trough region 3 of the second conductivity type, the source region 4 of the first conductivity type, and the trough contact region 5 of the second conductivity type on the part of the upper layer of the epitaxially grown SiC layer 2, as shown in Fig. 4 shown.

[0029] More precisely: A plurality of basin areas 3 is selectively formed by ion implantation of defects of the second conductivity type (of the p-type) on the part of the upper layer of the epitaxially grown SiC layer 2 through an implantation mask which is provided with a pattern in a predetermined shape.

[0030] Subsequently, the source area 4 is selectively formed by implanting ions from first conductivity type (n-type) defects into the surface of each basin area 3 through an implantation mask which is provided with a pattern in a predetermined shape.

[0031] Furthermore, the trough contact area 5 is selectively formed by ion implantation of defects of the second conductivity type in each source area 4 through an implantation mask which is provided with a pattern in a predetermined shape.

[0032] For example, a photoresist for a photolithographic process or a silicon dioxide layer can be used as an implantation mask.

[0033] The sequence for forming the trough area 3, the source area 4 and the trough contact area 5 is not limited to the sequence above.

[0034] Ion implantation can be performed with a single implantation energy, or it can be performed with a gradually changing implantation energy, for example from a high energy to a low energy.

[0035] Nitrogen or phosphorus are used as impurities of the first conductivity type to be ion-implanted. Aluminum or boron are used as impurities of the second conductivity type. The implantation area density (dose) of the implantation ions during ion implantation is preferably in the range of 1 × 10⁻⁶. 13cm -2 up to 1 × 10 16 cm -2 , and the implantation energy is preferably in the range of 10 keV to 10 MeV.

[0036] For example, the impurity concentrations of the trough area 3, the source area 4 and the trough contact area 5 are preferably located in the following areas: 1 × 10 17 cm -3 up to 1 × 10 19 cm -3 , 1 × 10 18 cm -3 up to 1 × 10 20 cm -3 or 1 × 10 19 cm -3 up to 1 × 10 21 cm -3 .

[0037] The depths of the basin area 3, the source area 4 and the basin contact area 5 are preferably in the following ranges: 0.5 µm to 3 µm, 0.2 µm to 1 µm and 0.2 µm to 1 µm respectively.

[0038] During ion implantation, the temperature of the epitaxial SiC substrate is set within the range of 10 °C to 1000 °C. Consequently, it is possible to a certain extent to eliminate crystal defects (implantation defects) that are created during ion implantation.

[0039] Subsequently, ion implantation is performed on a major surface (a second major surface) of the epitaxial SiC substrate 10 on the side of the SiC support substrate 1 to form the ion implantation area 6 over the entire major surface of the SiC support substrate 1, as shown in Fig. 5 shown. Ion implantation can be performed with a single implantation energy, or it can be performed with a gradually changing implantation energy, for example from a high energy to a low energy.

[0040] The implantation area density (the dose) of the implantation ions during ion implantation is preferably in the range of 1 × 10 13 cm -2 up to 1 × 10 16 cm -2 , and the implantation energy is preferably in the range of 10 keV to 10 MeV. When the ion implantation is carried out under the above conditions, the concentration of the implanted element in the ion implantation area 6 is higher, by one digit or more, than in other areas in the SiC support substrate 1.

[0041] During ion implantation, the temperature of the epitaxial SiC substrate is set within the range of 10 °C to 1000 °C. Consequently, it is possible to a certain extent to eliminate crystal defects (implantation defects) that are created during ion implantation.

[0042] The thickness of the ion implantation area 6 is preferably in the range of 0.1 µm to 10 µm, and the element to be used for ion implantation is preferably an element that acts as a non-doper that is inert with respect to SiC, such as carbon, silicon, hydrogen, helium, or argon. However, a doper, such as aluminum, boron, phosphorus, or nitrogen, can also be used.

[0043] More precisely: An element with a conductivity type identical to that of the SiC support substrate 1 of the first conductivity type (n-type), for example, an n-type dopant such as phosphorus or nitrogen, can also be used. In this case, the impurity concentration of the ion implantation area 6 can be equal to or higher than the impurity concentration of the SiC support substrate 1. Consequently, the contact resistance can be reduced when forming a metal electrode on the second main surface of the epitaxial SiC substrate 10.

[0044] On the other hand, an element with a conductivity type (p-type) opposite to that of the SiC support substrate 1, which has the first conductivity type (n-type), can also be used, for example, a p-type dopant such as aluminum or boron. In this case, the impurity concentration of the ion implantation area 6 can be equal to or higher than the impurity concentration of the SiC support substrate 1.

[0045] Therefore, the ion implantation area 6 can be used as a collector layer in a SiC IGBT (bipolar transistor with an insulated gate). When this configuration is used, a SiC IGBT is obtained instead of a SiC MOSFET, and the configuration is effective when a SiC IGBT is fabricated.

[0046] When ions are implanted into a crystalline substance, the implantation layer is generally expanded cubically due to the impurity atom packing effect and the generation of radiation defects. The substrate resists this cubic expansion, resulting in the induction of compressive stress parallel to the ion implantation area.

[0047] This phenomenon occurs regardless of the type of implanted ions, and when a dopant is implanted, the conductivity-type control effect and the contact resistance reduction effect are simultaneously obtained. However, it is preferable to implant a non-doper if the sole purpose is to prevent substrate warping.

[0048] Finally, the epitaxial SiC substrate 10 is heat-treated to activate the implantation ions, resulting in the SiC MOSFET 100, which is used in Fig. Figure 1 shows the heating temperature of the epitaxial SiC substrate 10, preferably in the range of 1000 °C to 2000 °C, and even more preferably in the range of 1400 °C to 1800 °C.

[0049] Since the epitaxial SiC substrate 10 is heat-treated (activation-tempered) after ion implantation into the first main surface of the epitaxial SiC substrate 10 to form defect areas, such as the trough area 3, the source area 4 and the trough contact area 5, and ion implantation into the second main surface to control the curvature of the epitaxial SiC substrate 10, the curvature of the epitaxial SiC substrate 10 is prevented, so that an almost flat epitaxial SiC substrate 10 is obtained.

[0050] Since ion implantation is used to control the curvature at the second major surface of the epitaxial SiC substrate 10, which is located on one side opposite the first major surface, optimal implantation conditions for controlling the curvature can be selected without considering the conditions for forming a semiconductor element on the first major surface of the epitaxial SiC substrate 10 (e.g. the ion-ion implantation conditions) and the defect concentration of the epitaxially grown SiC layer 2.

[0051] Subsequently, the curvature of the epitaxial SiC substrate, which occurs as a result of a lattice mismatch between the SiC support substrate and the epitaxially grown SiC layer, is prevented, and the curvature of the epitaxial SiC substrate, which occurs through the step to form the defect region that forms a semiconductor element, is prevented.

[0052] The result is a nearly flat epitaxial SiC substrate 10, and even after subsequent heat treatment resulting in thermal shock, the epitaxial SiC substrate 10 does not break. Consequently, a stable SiC semiconductor device can be fabricated.

[0053] In the epitaxial SiC substrate 10, which is in Fig. As shown in Figure 3, the SiC support substrate 1 and the epitaxially grown SiC layer 2 are in direct contact with each other. However, the epitaxial SiC substrate can also be replaced by an epitaxial SiC substrate 11 in which a buffer layer BF of the first conductivity type is formed between the SiC support substrate 1 and the epitaxially grown SiC layer 2, as shown in Figure 3. Fig. Figure 6 shows the buffer layer, which reduces the difference in carrier concentration between the epitaxial layer and the substrate, and its thickness is adjusted to approximately 0.5 to 10 µm (500 nm to 10,000 nm). Modification 1

[0054] A metal, such as nickel, can be used as an ion-ion implantation element for the ion implantation area 6. In this case, the following applies: By heat-treating the epitaxial SiC substrate 10 at a temperature in the range of 1000 °C to 2000 °C, preferably in the range of 1400 °C to 1800 °C, implantation ions for the defect area are activated, and the ion implantation area 6 is formed as a nickel silicide layer 16.

[0055] Fig. Figure 7 shows a SiC MOSFET 100A in which a nickel silicide layer 16 is formed on a main surface of the SiC support substrate 1 on a side opposite the surface on which the epitaxially grown SiC layer 2 is arranged.

[0056] When the nickel silicide layer 16 is formed as described above, curvature of the epitaxial SiC substrate 10 is prevented, and the contact resistance with the metal electrode during the formation of the metal electrode on the second main surface of the epitaxial SiC substrate 10 can be reduced.

[0057] A group IV element, such as germanium, can be used as an ion implantation element. In this case, the band gap in the ion implantation region 6 is smaller compared to SiC, and therefore the contact resistance between the second main surface of the epitaxial SiC substrate 10 and the metal electrode can be reduced. Modification 2

[0058] In the embodiment 1 described above, the ion implantation area 6 is formed over the entire second main surface of the epitaxial SiC substrate 10, but the ion-ion implantation can also be performed selectively through an implantation mask. For example, a photoresist for a photolithographic process or a silicon oxide layer can be used as the implantation mask.

[0059] Fig. Figure 8 shows a configuration in which the ion implantation area 6 on the second main surface is formed in such a way that the shape in the top view is a ring shape, as an example of selective ion implantation.

[0060] More precisely: Fig. Figure 8 shows a top view of the epitaxial SiC substrate 10 in a wafer state when viewed from the sides of the second main surface, where the ion implantation area 6 is formed in a ring shape on the SiC support substrate 1.

[0061] The ion implantation area 6 can be formed on the second main surface in such a way that the shape in the top view is a lattice shape, as shown in Fig. 9 shown.

[0062] More precisely: Fig. Figure 9 shows a top view of the epitaxial SiC substrate 10 in a wafer state when viewed from the sides of the second main surface, where the ion implantation area 6 is formed in a lattice shape on the SiC support substrate 1.

[0063] If the ion implantation area 6 is selectively shaped such that its top-view form is a geometric shape as described above, then a difference in compressive stresses exists between an ion-implanted area and a non-ion-implanted area, allowing the curvature of the epitaxial SiC substrate 10 to be controlled. The top-view shape of the ion implantation area 6 can be determined according to the curvature caused by the ion implantation into the first principal surface.

[0064] As in Fig. 8 and Fig. As shown in Figure 9, alignment flats OF1 and OF2 are provided as markers indicating the orientation of the crystal on the side face of the epitaxial SiC substrate 10 in a wafer state. Both alignment flats are configured such that their position ratio forms an angle of 90°.

[0065] More precisely: The epitaxial SiC substrate 10 has an alignment flat OF1 parallel to the (11-20) direction and an alignment flat OF2 which intersects the (11-20) direction and has a length which is different from that of the alignment flat OF1.

[0066] When these alignment flattenings OF1 and OF2 are used, a directivity in the selective formation of the ion implantation area 6 can be determined, and the ion implantation area 6 can be formed with a top-view shape that more effectively prevents the bulging of the epitaxial SiC substrate 10. The top-view shape of the ion implantation area 6 is not limited to the shape shown above and can also be a more complex geometric shape.

[0067] If the ion implantation area 6 is selectively formed, then the only purpose is to prevent the bulging of the epitaxial SiC substrate 10, and it is preferred to remove the entire ion implantation area 6 after the activation annealing has been carried out, either when the ion implantation area 6 is formed using a non-doping agent, or when the ion implantation area 6 is formed using a doping agent. Modification 3

[0068] In the embodiment 1 described above, the impurity concentration of the ion implantation area 6 is uniform across the entire second main surface of the epitaxial SiC substrate 10, but the impurity concentration of the ion implantation area 6 can be varied in the second main surface.

[0069] For example, if an area satisfying r=0 to 0.5R is an “inner peripheral area” and the remaining area is an “outer peripheral area”, where R is the radius of the epitaxial SiC substrate 10 and r (r ≤ R) is the distance from the center of the epitaxial SiC substrate 10, then the defect concentration in the outer peripheral area can be made relatively high and in the inner peripheral area relatively low, or conversely, the defect concentration can be made relatively low in the outer peripheral area and relatively high in the inner peripheral area.

[0070] Consequently, a difference in compressive stress exists between the inner peripheral region and the outer peripheral region, allowing the curvature of the epitaxial SiC substrate 10 to be controlled. Whether the defect concentration is high or low in the outer peripheral region can be determined according to the state of the curvature caused by ion-ion implantation into the first main surface.

[0071] In the embodiment 1 described above, the depth of the ion implantation area 6 is uniform over the entire second main surface of the epitaxial SiC substrate, but the depth of the ion implantation area 6 can be varied over the entire second main surface of the epitaxial SiC substrate.

[0072] For example, the depth of the ion implantation area 6 can be made relatively large in the outer peripheral area and relatively small in the inner peripheral area of ​​the epitaxial SiC substrate 10, or conversely, the depth of the ion implantation area 6 can be made relatively small in the outer peripheral area and relatively large in the inner peripheral area of ​​the epitaxial SiC substrate 10.

[0073] Consequently, there is a difference in compressive stresses between the inner peripheral region and the outer peripheral region, allowing the curvature of the epitaxial SiC substrate 10 to be controlled. Whether the depth of the ion implantation area 6 is made small or large in the outer peripheral region can be determined according to the state of the curvature caused by the ion implantation into the first main surface. Effect

[0074] A change in the shape of the epitaxial SiC substrate 11 in a wafer state ( Fig. 6) When performing an experiment in which the curvature of an epitaxial 3-inch SiC substrate is controlled using the method for fabricating a semiconductor device according to embodiment 1, as described above, with reference to the Fig. 10 to 12 described.

[0075] During this experiment, the impurity concentration of the SiC support substrate 1 was reduced to 1 × 10 19 cm -3 The defect concentration of the epitaxially grown SiC layer 2 was adjusted to 5 × 10 14 cm -3 The SiC substrate 11 was set in the epitaxial substrate. The thickness of the epitaxially grown SiC layer 2 was 142 µm.

[0076] The buffer layer BF between the SiC support substrate 1 and the epitaxially grown SiC layer 2 had a defect concentration of 1 × 10 18cm -3 and a thickness of 1 µm. The conductivity type of each of SiC support substrate 1, epitaxially grown SiC layer 2 and buffer layer BF was the n-type.

[0077] The wafer form of the epitaxial SiC substrate 11 is in Fig. 10 shown. As in Fig. As shown in Figure 10, the epitaxial SiC substrate 11 had a convex shape with respect to the Si atomic plane, and it had a SORI of 9.3 µm.

[0078] Here, the "SORI" is the difference between the maximum and minimum values ​​of the distance between the best-fitting reference plane (the plane calculated using a least-squares method) of the wafer area and the wafer area in a non-adsorbed state. Subsequently, ion implantation to form a semiconductor device was applied to the first principal surface of the epitaxial SiC substrate 11. For ion implantation to form a semiconductor device, aluminum was used for p-type defects and nitrogen was used for n-type defects.

[0079] The wafer shape after performing ion implantation to form a semiconductor element is shown in Fig. 11 shown. In the wafer form after performing the ion implantation to form a semiconductor element, the protrusion with respect to the Si atomic plane was more noticeable, as in Fig. Figure 11 showed that the SORI increased to 27.4 µm. The reason why ion implantation causes an increase in SORI may be that a pressure stress is generated by the ion implantation.

[0080] Subsequently, the ion implantation area 6 was formed to control the curvature of the epitaxial SiC substrate 11 across the entire second main surface of the epitaxial SiC substrate 11. Carbon was used as the element for ion implantation. The implantation area density for ion implantation was set to 5 × 10 15 cm -2 adjusted, and the temperature of the epitaxial SiC substrate 11 was set to 600 °C.

[0081] The wafer shape after the formation of the ion implantation area 6 is in Fig. 12 shown. As in Fig. As shown in Figure 12, the wafer shape after the formation of the ion implantation area 6 was convex with respect to the Si atomic plane, but the SORI decreased to 8.7 µm. This can be attributed to the compressive stress generated by the ion implantation area 6, which extends over the entire second main surface of the epitaxial SiC substrate 11.

[0082] Then the epitaxial SiC substrate 11, which is in Fig. 12 shows that the epitaxial SiC substrate 11 was heat-treated at 1700 °C in an inert atmosphere to activate implantation ions, but it did not crack.

[0083] When, in turn, the epitaxial SiC substrate 11, which is in Fig. 11, which was heat-treated in a similar manner without performing ion implantation to control the curvature of the epitaxial SiC substrate 11 for comparison, then the epitaxial SiC substrate 11 broke.

[0084] The experimental results above demonstrate that, to ensure the epitaxial SiC substrate does not crack and consequently a SiC semiconductor device is stably fabricated, it is effective to obtain a flat epitaxial SiC substrate by applying ion-ion implantation to control the curvature on a major surface on one side opposite a major surface on which a semiconductor element is formed. If the SORI is in the range of 0 µm to 10 µm, it is possible to prevent the epitaxial SiC substrate from cracking during a thermal cycle. Design 2

[0085] While the epitaxial SiC substrate 10, in which the epitaxially grown SiC layer 2 of the first conductivity type is formed on the SiC support substrate 1 of the first conductivity type, is used in the method for manufacturing a semiconductor device in the first embodiment 1 described above, an epitaxial SiC substrate 10A, in which an additional epitaxially grown SiC layer 7 of the first conductivity type is formed on an epitaxially grown SiC layer 2 in an epitaxial SiC substrate 10, is used as described in Fig. 13 shown, used in a method for manufacturing a semiconductor device according to embodiment 2 according to the present invention.

[0086] The impurity concentration of the additional epitaxially grown SiC layer 7 is preferably lower than the impurity concentration of a SiC support substrate 1 and higher than the impurity concentration of the epitaxially grown SiC layer 2. For example, the impurity concentration of the additional epitaxially grown SiC layer 7 is preferably in the range of 1 × 10 16 cm -3 up to 1 × 10 18 cm -3 .

[0087] The depth of the additional epitaxially grown SiC layer 7 is preferably in the range of 0.5 µm to 5 µm.

[0088] Subsequently, selective ion implantation is performed to form a semiconductor element on a major surface (a first major surface) of the epitaxial SiC substrate 10A on the side of the additional epitaxially grown SiC layer 7. Ion implantation to control the curvature of the substrate is performed on a major surface (a second major surface) of the epitaxial SiC substrate 10A on the side of the SiC support substrate 1, and heat treatment is carried out to activate the defects. Since these manufacturing steps are the same as in embodiment 1, their re-description is omitted.

[0089] In the method for fabricating a semiconductor device according to embodiment 2, as described above, ion implantation is performed to control the curvature of the epitaxial SiC substrate 10A on the second major surface of the epitaxial SiC substrate 10A. Therefore, even after the ion implantation has been performed to form a semiconductor device, the epitaxial SiC substrate 10A is nearly flat, so that even if subsequent heat treatment is performed that causes thermal shock, the epitaxial SiC substrate 10A does not crack. Consequently, a SiC semiconductor device can be fabricated in a stable manner.

[0090] The resistance of the JFET (Junction FET) can be reduced by forming the epitaxially grown SiC layer 7. More precisely, when a semiconductor switching element, such as an IGBT, is prepared, p-type well regions are formed separately with respect to a first main area of ​​an epitaxial SiC substrate. However, in a semiconductor device with an ultra-high breakdown voltage (a breakdown voltage of 10 kV or more), the impurity concentration of a drift layer (the epitaxially grown SiC layer) is set low.

[0091] Therefore, the resistance of a region (a JFET region) sandwiched between the trough regions increases significantly. If a layer (the additional epitaxially grown SiC layer) is formed with a higher impurity concentration than that of the drift layer, and if a trough region forms within this additional epitaxially grown SiC layer, the JFET resistance can be reduced. Because the additional epitaxially grown SiC layer has a higher impurity concentration than that of the drift layer, a tensile stress is generated to help reduce the warping of the epitaxial SiC substrate.

[0092] The epitaxial SiC substrate 10A, which is in Fig. As shown in Figure 13, the SiC support substrate 1 and the epitaxially grown SiC layer 2 are in direct contact with each other, and the epitaxially grown SiC layer 2 and the additional epitaxially grown SiC layer 7 are in direct contact with each other.

[0093] However, the epitaxial SiC substrate can also be replaced by an epitaxial SiC substrate 11A, in which a buffer layer BF1 of the first conductivity type is formed between the SiC support substrate 1 and the epitaxially grown SiC layer 2, and in which a buffer layer BF2 of the first conductivity type is formed between the epitaxially grown SiC layer 2 and the additional epitaxially grown SiC layer 7, as shown in Fig. 14 shown.

[0094] The buffer layer is a layer which reduces a lattice mismatch resulting from a difference in carrier concentration between the epitaxial layer and the substrate, and the thickness is adjusted to approximately 0.5 µm to 10 µm (500 nm to 10000 nm). embodiment 3

[0095] While the epitaxial SiC substrate 10, in which the epitaxially grown SiC layer 2 of the first conductivity type is formed on the SiC support substrate 1 of the first conductivity type, is used in the method for manufacturing a semiconductor device in the first embodiment 1 described above, an epitaxial SiC substrate 10B, in which an epitaxially grown SiC layer 2 of the first conductivity type is formed on a SiC support substrate 8 of the second conductivity type, is used as described in Fig. 15 shown, used in a method for manufacturing a semiconductor device according to embodiment 3 according to the present invention.

[0096] The impurity concentration of the SiC support substrate 8 is preferably in the range of 1 × 10 17 cm -3 up to 1 × 10 21 cm -3 , and a SiC-IGBT can be obtained with the SiC support substrate 8 as a collector layer.

[0097] Subsequently, selective ion implantation is performed to form a semiconductor element on a major surface (a first major surface) of the epitaxial SiC substrate 10B on the side of the epitaxially grown SiC layer 2. Ion implantation to control the curvature of the substrate is performed on a major surface (a second major surface) of the epitaxial SiC substrate 10B on the side of the SiC support substrate 1. Finally, heat treatment is performed to activate the defects. Since these manufacturing steps are the same as in embodiment 1, their description is omitted.

[0098] In the method for fabricating a semiconductor device according to embodiment 3, as described above, ion implantation is performed to control the curvature of the epitaxial SiC substrate 10B on the second major surface of the epitaxial SiC substrate 10B. Therefore, even after the ion implantation has been performed to form a semiconductor device, the epitaxial SiC substrate 10B is nearly flat, so that even if subsequent heat treatment is performed that causes thermal shock, the epitaxial SiC substrate 10B does not crack. Consequently, a SiC semiconductor device can be fabricated in a stable manner.

[0099] In embodiment 3, an additional epitaxially grown SiC layer 7 of the first conductivity type can also be formed on the epitaxially grown SiC layer 2, as in the case of embodiment 2.

[0100] The epitaxial SiC substrate 10B, which is in Fig. As shown in Figure 15, the SiC support substrate 8 and the epitaxially grown SiC layer 2 are in direct contact with each other. However, the epitaxial SiC substrate can also be replaced by an epitaxial SiC substrate 11B, in which a buffer layer BF3 of the second conductivity type and a buffer layer BF4 of the first conductivity type are formed between the SiC support substrate 8 and the epitaxially grown SiC layer 2, as shown in Figure 15. Fig. 16 shown.

[0101] The buffer layer is a layer that reduces a lattice mismatch resulting from a difference in carrier concentration between the epitaxial layer and the substrate, and the thickness is adjusted to approximately 0.5 µm to 10 µm (500 nm to 10000 nm). Design 4

[0102] While the epitaxial SiC substrate 10, in which the epitaxially grown SiC layer 2 of the first conductivity type is formed on the SiC support substrate 1 of the first conductivity type, is used in the method for fabricating a semiconductor device in the first embodiment 1 described above, an epitaxial SiC substrate 10C, which has only one epitaxially grown SiC layer 2 of the first conductivity type, as in Fig. 17 shown, used in a method for manufacturing a semiconductor device according to embodiment 4 according to the present invention.

[0103] The epitaxial SiC substrate 10C is obtained by removing the SiC support substrate 1 from the epitaxial SiC substrate 10 mechanically, chemically, or by any other method, as described in Fig. Figure 3 shows the epitaxial SiC substrate 10C, which has only one epitaxially grown layer obtained in this way, is referred to as a "freestanding substrate (self-supporting substrate)", and the step to produce a freestanding substrate is referred to as the step to produce an epitaxial SiC substrate.

[0104] Since the epitaxial SiC substrate 10C is a free-standing substrate, no compressive stress is exerted on the epitaxially grown SiC layer 2. Consequently, the curvature of the epitaxial SiC substrate 10C is smaller than that of the epitaxial SiC substrates 10, 10A, and 10B, which are described in Fig. 3, Fig. 13 or Fig. 15 are shown.

[0105] Subsequently, selective ion implantation is performed to form a semiconductor element on one major surface (a first major surface) of the epitaxial SiC substrate 10C, ion implantation to control the curvature of the substrate is performed on the other major surface (a second major surface) of the epitaxial SiC substrate 10C, and heat treatment is performed to activate the defects.

[0106] Since these manufacturing steps are the same as in embodiment 1, their description is omitted. The concentration of the implanted element in the ion implantation area for controlling the curvature of the substrate is higher, by one digit or more, than in other areas in the epitaxially grown SiC layer 2.

[0107] If, during the formation of the ion implantation region for controlling the curvature of the substrate, the element used for ion implantation is carbon, then the density of charge carrier traps is lower, at least in the region implanted with carbon, by one order of magnitude or more, than in other regions in the epitaxially grown SiC layer 2. The underlying principle is described below.

[0108] Carbon defects are currently specified as electrically active defects (charge carrier traps) that act as lifetime destroyers in the SiC crystal. Carbon is ion-implanted into the SiC crystal to introduce additional interstitial carbon atoms in the carbon-implanted region. Furthermore, the SiC crystal is heated to diffuse the additional interstitial carbon atoms into the deeper regions, thus electrically inactivating the charge carrier traps in the SiC crystal. Consequently, the charge carrier trap density is lower, at least in the carbon-implanted region, by one order of magnitude or more, than in other regions of the epitaxially grown SiC layer 2.

[0109] In the method for fabricating a semiconductor device according to embodiment 4, as described above, ion implantation is performed to control the curvature of the epitaxial SiC substrate 10C on the second major surface of the epitaxial SiC substrate 10C. Therefore, even after the ion implantation has been performed to form a semiconductor device, the epitaxial SiC substrate 10C is nearly flat, so that even if subsequent heat treatment is performed that causes thermal shock, the epitaxial SiC substrate 10C does not crack. Consequently, a SiC semiconductor device can be fabricated in a stable manner.

[0110] Consequently, the manufacturing process according to embodiment 4 differs clearly from the process disclosed in patent document 2. In the heat treatment, the support substrate 1 is not present, and the semiconductor substrate (the epitaxial SiC substrate) itself is not heat-treated.

[0111] The epitaxial SiC substrate 10C can be used to manufacture both types of semiconductor devices, a SiC MOSFET and a SiC IGBT.

[0112] In embodiment 3, an additional epitaxially grown SiC layer 7 of the first conductivity type can also be formed on the epitaxially grown SiC layer 2, as in the case of embodiment 2. Design 5

[0113] While the epitaxial SiC substrate 10A, in which the additional epitaxially grown SiC layer 7 of the first conductivity type is further formed on the epitaxially grown SiC layer 2 in the SiC support substrate 10, is used in the method for manufacturing a semiconductor device in the first embodiment 2 described above, an epitaxial SiC substrate 10D, in which an additional epitaxially grown SiC layer 9 of the second conductivity type is further formed on an epitaxially grown SiC layer 2 in an epitaxial SiC substrate 10, is used as described in Fig. 18 shown, used in a method for manufacturing a semiconductor device according to embodiment 5 according to the present invention.

[0114] The defect concentration of the additional epitaxially grown SiC layer 9 is preferably higher than the defect concentration of the epitaxially grown SiC layer 2. For example, the defect concentration of the additional epitaxially grown SiC layer 9 is preferably in the range of 1 × 10 16 cm -3 up to 1 × 10 21 cm -3 .

[0115] The thickness of the additional epitaxially grown SiC layer 9 is preferably in the range of 0.5 µm to 300 µm.

[0116] Subsequently, the SiC support substrate 1 is mechanically or chemically or by another method removed from the epitaxial SiC substrate 10D to form an epitaxial SiC substrate 10E which has the additional epitaxially grown SiC layer 9 and the epitaxially grown SiC layer 2, as shown in Fig. 19 shown.

[0117] In the epitaxial SiC substrate 10E, the first principal surface is a principal surface of the epitaxially grown SiC layer 2, and the second principal surface is a principal surface of the additional epitaxially grown SiC layer 9.

[0118] Subsequently, selective ion implantation is performed to form a semiconductor element on the first major surface of the epitaxial SiC substrate 10E, ion implantation to control the curvature of the substrate is performed on the second major surface of the epitaxial SiC substrate 10E, and heat treatment is carried out to activate the defects. Since these manufacturing steps are the same as in embodiment 1, their description is omitted.

[0119] In the method for fabricating a semiconductor device according to embodiment 5, as described above, ion implantation is performed to control the curvature of the epitaxial SiC substrate 10E on the second major surface of the epitaxial SiC substrate 10E. Therefore, even after the ion implantation has been performed to form a semiconductor device, the epitaxial SiC substrate 10E is obtained in a nearly flat state, so that even if subsequent heat treatment is performed that causes thermal shock, the epitaxial SiC substrate 10E does not crack. Consequently, a SiC semiconductor device can be fabricated in a stable manner.

[0120] The additional epitaxially grown SiC layer 9 has a conductivity profile opposite to that of the drift layer (the epitaxially grown SiC layer 2). Therefore, it can be configured to act as a collector layer, supplying the drift layer with minority charge carriers, thus enabling the formation of a SiC IGBT. Since the additional epitaxially grown SiC layer 9 has a higher impurity concentration than the drift layer, a tensile stress is generated, contributing to the reduction of the curvature of the epitaxial SiC substrate.

[0121] The epitaxial SiC substrate 10E, which is in Fig. As shown in Figure 19, the additional epitaxially grown SiC layer 9 and the epitaxially grown SiC layer 2 are in direct contact with each other. However, the epitaxial SiC substrate can also be replaced by an epitaxial SiC substrate 11E in which a buffer layer BF5 of the second conductivity type and a buffer layer BF6 of the first conductivity type are formed between the additional epitaxially grown SiC layer 9 and the epitaxially grown SiC layer 2, as shown in Figure 19. Fig. 20 shown.

[0122] The buffer layer is a layer that reduces a lattice mismatch resulting from a difference in carrier concentration between the epitaxial layer and the substrate, and the thickness is adjusted to approximately 0.5 µm to 10 µm (500 nm to 10,000 nm). Design 6

[0123] While an epitaxial SiC substrate obtained by mechanically or chemically removing the SiC support substrate 1 or by any other method is used in the method for fabricating a semiconductor device in the embodiment 4 described above, an epitaxial SiC substrate 10F, in which - as in Fig. 21 shows - a SiC support substrate 1 is partially removed mechanically or chemically or by another process, such that the SiC support substrate has a thickness that is less than that of the SiC support substrate of the epitaxial SiC substrate 10, which is in Fig. 3 is used in the method for manufacturing a semiconductor device according to embodiment 6 according to the present invention.

[0124] Consequently, the method for manufacturing a semiconductor device according to embodiment 6 of the present invention further comprises the step in which the SiC support substrate 1 is partially removed from the second main surface, in addition to the method for manufacturing a semiconductor device in embodiment 1 described above. In this step, the thickness of the SiC support substrate 1 is adjusted to approximately 20% to 70% of the thickness of the epitaxial SiC substrate 10.

[0125] For example, if the thickness of the SiC support substrate 1 of the epitaxial SiC substrate 10 is 350 µm, then the thickness of the SiC support substrate 1 of the epitaxial SiC substrate 10F will be between 70 µm and 250 µm. Making the SiC support substrate 1 thinner, as described above, reduces the on-resistance and thermal resistance, and thus the variations in the on-resistance and thermal resistance of the SiC support substrate 1 decrease when the SiC MOSFET or SiC IGBT is fabricated.

[0126] The step in which the SiC support substrate 1 is partially removed from the second main surface corresponds, for example, to thinning the semiconductor device. In the case of the epitaxial SiC substrate 10F, which undergoes thinning, a large curvature occurs as a result of stresses caused by a machining-influenced layer that forms on a surface from which the SiC support substrate 1 has been removed.

[0127] In the case of the epitaxial SiC substrate 10F, which exhibits a large curvature as described above, ion implantation is performed to control the curvature on the surface from which the SiC support substrate 1 has been removed. This reduces the stresses caused by the machining-affected layer from which the SiC support substrate 1 has been removed, resulting in a smaller curvature compared to that of the epitaxial SiC substrate 10F.

[0128] In the method for fabricating a semiconductor device according to embodiment 6, as described above, the curvature of the epitaxial SiC substrate 10F, which is caused by the partial removal of the SiC support substrate 1 from the second main surface, can be controlled by ion implantation performed on the surface from which the SiC support substrate 1 has been removed. Therefore, a nearly flat epitaxial SiC substrate is obtained. Consequently, the epitaxial SiC substrate does not crack, and a stable SiC semiconductor device can be fabricated.

[0129] The epitaxial SiC substrate 10F can be used to manufacture both semiconductor devices, namely a SiC MOSFET and the SiC IGBT.

[0130] In embodiment 6, an additional epitaxially grown SiC layer 7 of the first conductivity type can also be formed on the epitaxially grown SiC layer 2, as in the case of embodiment 2. modification

[0131] In the embodiments 1 to 6 described above, the basin area 3, the source area 4, and the basin contact area 5 are formed by means of ion implantation processes. However, some or all of the areas can also be formed using epitaxial growth and an etching technique.

[0132] For example, a portion of the drift layer can be etched, followed by epitaxial growth of a layer with a conductivity type opposite to that of the drift layer, and removal of any unnecessary epitaxially grown layer from the aforementioned defect regions by chemical-mechanical polishing (CMP), etc. Semiconductor devices that have defect regions formed by epitaxial growth also include IEMOS (implantation and epitaxial MOSFETs). Further application examples

[0133] Embodiments 1 to 6 are described above, with a method for fabricating a SiC MOSFET or a SiC IGBT being given as an example. However, the present invention can also be used to fabricate SiC semiconductor devices, such as SBDs (Schottky diodes), PiN diodes (P-intrinsic-N), JFETs (junction FETs), thyristors, GTOs (gate-switched thyristors), and BJTs (bipolar junction transistors).

[0134] The crystal type and conductivity type of SiC and suitable ranges for the values ​​of specific layer thicknesses as well as depths and defect concentrations of the defect regions are well known to a person skilled in the art, and the ranges described in embodiments 1 to 5 of the present invention can be modified in a suitable manner.

[0135] The present invention is described in detail. However, the above descriptions are for illustrative purposes only, and the present invention is not limited to them. It is understood that an unlimited number of modifications not specifically illustrated can be implemented without deviating from the scope of the present invention.

[0136] In the present invention, the embodiments can be freely combined, or the embodiments can be appropriately modified and omitted, within the scope of the invention. Reference symbol list 1 SiC support substrate 2 epitaxially grown SiC layers 6 ion injection area 7 additional epitaxially grown SiC layers 8 SiC support substrate 9 additional epitaxially grown SiC layers

Claims

[1] A method of manufacturing a semiconductor device comprising the following steps: (a) producing an epitaxial SiC substrate (10) in which an epitaxially grown SiC layer (2) with an impurity concentration equal to or less than 1 / 10,000 of that of the SiC carrier substrate (1) and with a thickness of 50 µm or more is arranged on a SiC carrier substrate (1); (b) forming an impurity region constituting a semiconductor element by selectively implanting impurity ions into a first main surface of the epitaxial SiC substrate (10); (c) forming an ion implantation region (6) which controls the warpage of the epitaxial SiC substrate (10) by implanting predetermined ions into a second main surface of the epitaxial SiC substrate (10); and (d) heating the epitaxial SiC substrate (10) after step (b) and step (c). [2] A method of manufacturing a semiconductor device according to claim 1, further comprising the steps of: Removing the SiC carrier substrate (1) of the epitaxial SiC substrate (10) between step (a) and step (b), wherein a main surface of the epitaxially grown SiC layer (2) is the first main surface of the epitaxial SiC substrate (10), and wherein another main surface of the epitaxially grown SiC layer (2) is the second main surface of the epitaxial SiC substrate (10). [3] A method of manufacturing a semiconductor device according to claim 1, further comprising the steps of: partially removing the SiC carrier substrate (1) of the epitaxial SiC substrate (10) from one side of the second main surface. [4] A method of manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the step (a) comprises a step in which the impurity concentration of the epitaxially grown SiC layer (2) is within a range of 1 × 10 13 cm -3 up to 1 × 10 16 cm -3 is set. [5] A method of manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the step (c) comprises a step of implanting the predetermined ions at an implantation area density of 1 × 10 13 cm -2 up to 1 × 10 16 cm -2 be injected. [6] A method of manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the step (c) comprises a step in which the predetermined ions are injected into the second main surface of the epitaxial SiC substrate (10) in such a manner as to produce a geometric shape as a shape in plan view. [7] A method of manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the step (c) comprises a step in which the predetermined ions are selected from carbon, silicon, hydrogen, helium, argon, aluminum, boron, phosphorus, nitrogen, nickel and germanium. [8] A method of manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the step (c) comprises a step of generating a difference in the impurity concentration or the depth of the ion implantation region (6) between an inner peripheral region within a predetermined distance from the center of the epitaxial SiC substrate (10) and an outer peripheral region which is a region different from the inner peripheral region. [9] A method of manufacturing a semiconductor device according to any one of claims 1 to 3, wherein step (d) comprises a step of heating the epitaxial SiC substrate (10) to 1400°C to 1800°C. [10] A method of manufacturing a semiconductor device according to any one of claims 1 to 3, wherein step (a) comprises a step in which an additional epitaxially grown SiC layer (7) is formed on the epitaxially grown SiC layer (2) after the formation of the epitaxially grown SiC layer (2) on the SiC carrier substrate (1), and wherein an exposed main surface of the additional epitaxially grown SiC layer (7) is the first main surface of the epitaxial SiC substrate (10).

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