Stacked chip package with through-the-mold thermally conductive structures between a lower chip and a thermally conductive material

Abstract

Device comprising: a first semiconductor chip (202); a second semiconductor chip (201) stacked on the first semiconductor chip (202), the first semiconductor chip (201) having a larger surface area than the second semiconductor chip (202) such that there is an edge region (210) of the first semiconductor chip (201) that is not covered by the second semiconductor chip (202); thermally conductive material (205) over the second semiconductor chip (202); a bonding mold (204) between the thermally conductive material and both the second semiconductor chip (201) and the edge region of the first semiconductor chip (202); and a thermally conductive structure (211) extending through the composite mold (204) which thermally couples the edge region (210) to the thermally conductive material (205), wherein the composite mold (204) comprises a thermally insulating filler.

Description

Field of the InventionThe field of the invention relates generally to semiconductor technology, and more particularly to a stacked chip package having through-die thermal conductive structures between a bottom chip and a thermal conductive material.BackgroundSemiconductor technology has ever been challenging to integrate electronic functionality into as small a volume as possible. Stacking chips has recently emerged as a popular packaging technology for integrating a plurality of semiconductor chips into one and the same semiconductor package. However, one problem is heat dissipation that a plurality of chips can generate within the package.US 2015 069 635 A1 discloses a semiconductor package and a method for producing the same. The method may include mounting a first semiconductor chip including chip and heat transfer regions and a lower heat transfer pattern disposed on the heat transfer region on a substrate, mounting a second semiconductor chip on the chip region of the first semiconductor chip, forming a mold layer on the substrate to include the first and second semiconductor chips, forming an opening in the mold layer to expose at least a portion of the lower heat transfer pattern, forming a heat transfer pattern in the opening, and forming a heat dissipating portion on the second semiconductor chip and the mold layer to be connected to the heat transfer pattern.WO 2009 111 186 A1 discloses semiconductor assemblies having reduced heat spreading resistance and methods for producing the same. In one example, a semiconductor device includes a primary integrated circuit (IC) and at least one secondary IC chip mounted on the primary IC chip. A heat dissipation member includes a base mounted to the semiconductor device such that each of the at least one secondary IC chips is interposed between the primary IC chip and the heat dissipation member. At least one dummy fill is adjacent to the at least one secondary IC chip, and each thermally connects the primary IC chip to the heat dissipation member.FIGS. FiguresThe present invention will be more fully understood from the following detailed description taken in conjunction with the following drawings, wherein: FIG. 1 shows a prior art stacked chip package; FIG. 2 shows an improved housing from the prior art; FIGS. 3 ato 3 i show a process flow for producing the improved housing from the prior art from FIG. 2 ; FIG. 4 shows a methodology of the process flow of FIGS. 3a-3i; FIG. 5 shows a computer system.DETAILED DESCRIPTIONFIG. 1 shows a standard stacked chip structure comprising an upper semiconductor chip 101 stacked on top of a lower semiconductor chip 102. The upper die 101 may be electrically and mechanically attached to the lower die 102, e.g., by a land grid array structure or micro bumps. Likewise, the bottom die 102 is electrically and mechanically coupled to a substrate 103, e.g., a land grid array or microbumps. A ball grid array may be provided on the bottom surface of the package substrate 103 forming the I / O (inputs / outputs) of the package.The stack die structure is surrounded by a molding compound 104 covered by a thermally conductive interface material 105. The resulting structure is encapsulated with a lid 106, which may also serve as a heat spreader. The thermal interface material 105 is a layer of thermal conductive material (e.g., silicone polymer resin filled with a thermal conductive filler, a polymer-based thermal grease, etc.) and is used to distribute the heat generated by the stacked die 101, 102 to the bottom surface area of the housing cover 106. The lid 106 can more effectively remove heat from the stacked chip 101, 102 by uniformly distributing the heat generated from the stacked chip structure over its surface.As seen in FIG. 1, the thermal conductive interface material 105 is positioned in close proximity to the top surface of the top die 101. Additionally, the thermal conductivity between the top die 101 and the thermally conductive interface material 105 may be reduced, e.g., with a thermally conductive adhesive between the top die 101 and the thermally conductive interface material 105 and / or thermally conductive pads / balls / bumps formed on the top surface of the top die 101 that are in contact with the thermally conductive interface material 105.A higher thermal conductivity may also be present between the portion 107 of the lower die 102 that is directly below the upper die 101. As with the interface between the upper die 101 and the thermally conductive interface material 105, the interface between the upper die 101 and the lower die portion 107 may be configured to exhibit high thermal conductivity with, e.g., a thermally conductive adhesive and / or pads / balls / studs mechanically coupled between the two dies 101, 102.However, one problem concerns the regions 110 of the top surface of the bottom die 102 that are not directly below the top die 101. The thermal conductivity between these regions 110 and the thermally conductive interface material 105 is primarily determined by the thermal conductivity of the molding compound 104 located between these regions 110 and the thermally conductive interface material 105.Conventional molding compositions, such as silica filler molds, typically have a thermal conductivity of less than 2.0 W / mK (e.g., about 1.0 W / mK) because the silica or other traditional molding composition filler is thermally insulating. Unfortunately, conventional composite molds with thermally insulating fillers do not have a thermal conductivity high enough to adequately remove heat from the regions 110, particularly when the bottom die 102 exhibits a "hot spot" in the regions 110. A hot spot is, for example, a surface area of a semiconductor chip that generates substantially more heat than other surface regions of the chip (e.g., because the chip includes high voltage, high current, and / or high frequency transistors directly below the hot spot).There are non-traditional molding compounds with higher thermal conductivities because they have fillers that are substantially thermally conductive (e.g., alumina preforms, copper preforms, etc., that exhibit thermal conductivities of at least about 4.0 W / mk). However, these compounds are unfortunately more costly than traditional molding compositions and exhibit a higher coefficient of thermal expansion. In addition to the higher undesirable cost, the higher coefficient of thermal expansion may cause reliability problems because stresses are introduced within the housing while the joint conducts heat.FIG. 2 shows an improved stack die structure with thermally conductive structures 211 intentionally placed between the outer regions 210 of the top surface of the bottom die 202 and the thermally conductive interface material 205. The thermally conductive structures 211 are configured to thermally couple the regions 210 to the thermally conductive interface material 205 to substantially reduce the thermal resistance present between the respective regions 110 and the thermally conductive interface material 105 of FIG. 1.In various embodiments, the thermally conductive structures 211 are strategicly placed directly over a known hot spot of the bottom die 202. Here, the designers of the bottom die 202 can understand from its design which regions of the die surface will generate heat corresponding to a hot spot (e.g., because they know which transistors are operating at high voltage, high current, and / or higher frequency).Using knowledge where such hot spots will occur in the outer regions 210, the designers of the package can strategicly "deposit" one or more thermally conductive structures 211 directly over each such hot spot. Alternatively or in combination, thermally conductive structures may be randomly and / or uniformly disposed at various locations around the perimeter of the top surface of the bottom die 202 along the regions 210 to remove general heat from the surface of the bottom die around the regions 210.Figures 3a-3i show a method of manufacturing the stack package configuration of Figure 2. As seen in Figure 3a, in one embodiment, a semiconductor wafer 322 containing multiple portions of the bottom die 302_1, 302_2, etc. is mounted on a carrier wafer 313 (e.g., with a removable adhesive). In an alternative process, instead of attaching a complete wafer of the bottom die to the carrier wafer 313, the singulated bottom die is individually placed and attached to the carrier wafer. For simplicity, the remainder of the discussion will refer to a process in which a full wafer of the bottom die is attached to the carrier wafer 313.As seen in FIG. 3 b, a respective upper die 301_ 1, 301_ 2, etc. is appropriately positioned and attached to a corresponding corresponding one of the lower dies 302_ 1, 302_ 2. In one embodiment, micro bumps are used to electrically and mechanically couple the upper chips 301_ 1, 301_ 2 to their respective lower chips 302_ 1, 302_ 2.In the case of microbump coupling, microbumps of solder are attached to the surfaces of one of the upper and lower chips 301, 302. The pads on the other chip are aligned with the bumps. When the two chips are mated, the solder bumps are coupled to their respective pads and reflowed to form a plurality of microbump junctions. For simplicity, FIG. 3 bdoes not show any micro bumps and instead suggests a land grid array interface between the lower and upper die 301, 302. Any type of joint may be used to provide an electrical and / or thermally conductive coupling between the upper and lower die 301, 302.As seen in FIG. 3 c, after the top die 301 is attached to the bottom die 302, a conventional molding compound 304 is formed over the stack die array as described above.For example, as seen in FIG. 3 d, the mold 304 is etched at strategic locations over expected hot spots of the bottom die 302_ 1, 302_ 2 that extend beyond (i.e., are not covered by each of) the surface area of the top die 301_ 1, 301_ 2. The etching can be carried out, for example, by laser ablation. In laser ablation, laser light is directed to the mold 304 just above a hot spot region of the bottom die, and the molding material is continuously removed until the top surface of the bottom die 302_ 1, 302_ 2 is obtained.As seen in Figure 3e, a stencil 315 is then placed on the surface of the mold 304, and the thermally conductive paste 316 (e.g., solder paste is a possible paste) is pressed through apertures in the stencil 315 that are aligned with the apertures just previously formed in the mold 304. After the deposited solder paste 316 fills the openings in the mold 304 appropriately, the paste 316 is sintered (cured) by applying an elevated temperature. Alternative thermally conductive materials and / or filling techniques may be used to fill the mold openings. For example, copper or another metal or metal alloy may be plated into the openings.As seen in FIG. 3 f, after the mold openings have been filled with thermally conductive material 316, the resulting structure is thinned to about the top surface of the top die 301_ 1, 301_ 2. Here, various polishing or other planarization techniques may be used to form a substantially flat top surface 317 that extends at about the same height as the top surface of the top die 301_ 1, 301_ 2.As seen in FIG. 3 g, the carrier wafer 313 is removed and the bottom die wafer 322 is scribe and broken or sawn to separate the array of stack die structures that are present since the end of the processing of FIG. 3 f.As can be seen in FIG. 3 h, a singulated stack chip structure is mechanically and electrically attached to a package substrate 303. Here, the bottom surface of the bottom die 302 is electrically and mechanically coupled to the package substrate 303 via a land grid interface, a micro bump interface, and / or a via / stud interface. The electrical connections formed between the bottom side of the lower die 302 and the package substrate 303 correspond to the I / O of the stack structure. Therefore, electrical conductive traces within the package substrate 303 travel, e.g., to conductive balls 318 of a ball grid array package interface.As seen in FIG. 3 i, the thermal interface material 305 is attached to the top surface of the top die 301, and a lid 306 is placed over the thermal interface material 305 and attached to the package substrate 303 to encapsulate the stack die structure. In alternative embodiments, the thermally conductive interface material 305 may be placed on the structure of FIG. 3 fbefore singulation. Thermal conductivity between the top die 301 and the thermally conductive interface material 305 may be reduced, e.g., with a thermally conductive adhesive between the top die 301 and the thermally conductive interface material 305 and / or thermally conductive pads / bumps formed on the top surface of the top die 301 that are in contact with the thermally conductive interface material 305.FIG. 4 illustrates a method outlined by the process flow just described above. As seen in FIG. 4, the method includes stacking 401 a second semiconductor chip on a first semiconductor chip to form a stacked semiconductor chip structure, wherein the first semiconductor chip has a larger surface area than the second semiconductor chip, such that there is an edge region of the first semiconductor chip that is not covered by the second semiconductor chip. The method also includes forming 402 a composite mold over the stacked semiconductor die structure. The method also includes creating 403 an opening in the composite shape over the edge region. The method includes inserting 404 the first thermally conductive material into the opening. The method includes forming 405 a second thermally conductive material over the composite mold, the first thermally conductive material thermally coupling the second thermally conductive material and the edge region.FIG. 5 shows a diagram of an example computer system 500, such as a personal computer system (e.g., a desktop or laptop) or a mobile or handheld computer system, such as a tablet device or smartphone, or a larger computer system, such as a server computer system.As seen in FIG. 5, the simple computer system may include a central processing unit 501 (e.g., which may include a plurality of general purpose processing cores and a main memory controller located on an application processor or a multi-core processor), a system memory 502, a display 503 (e.g., touch screen, flat panel display), a point-to-point local wired connection (e.g., USB) interface 04, various network I / O functions 505 (e.g., an Ethernet interface and / or a cellular modem subsystem), a wireless local area network interface (e.g., WiFi) 506, a wireless point-to-point connection (e.g., Bluetooth) interface 507 and a global positioning system interface 508, various sensors 509_ 1 to 509_N (e.g., one or more of a gyroscope, an accelerometer, a magnetometer, a temperature sensor, a pressure sensor, a humidity sensor, etc.), a camera 510, a battery 511, a power management controller 512, a speaker and microphone 513, and an audio encoder / decoder 514.An application processor or multi-core processor 550 may include one or more general-purpose processor cores 515 within its CPU 501, one or more graphics processing units 516, a memory management function 517 (e.g., a memory controller), and an I / O control function 518. General purpose processing cores 515 typically execute the computer system's operating system and application software. Graphics processing units 516 typically perform graphics intensive functions to generate, for example, graphics information that is presented on display 503. The memory control function 517 interfaces with the system memory 502. System memory 502 may be a multi-level system memory.The computer system may include a stacked chip package as described above. For example, the upper die may be a system memory die and the lower die may be a system-on-die having the processing cores (and, e.g., the memory controller and / or the I / O controller).Each of touch screen display 503, communication interfaces 504- 507, GPS interface 508, sensors 509, camera 510, and speaker / microphone codec 513, 514 may all be viewed as various forms of I / O (input and / or output) with respect to the entire computer system, including an integrated peripheral device (e.g., camera 510) as appropriate. Depending on the implementation, various of these I / O components may be integrated into the application processor / multi-core processor 550 or may be located off-chip or off-package of the application processor / multi-core processor 550.Embodiments of the invention may include various processes as set forth above. The processes may be embodied as machine-executable instructions. The instructions may be used to cause a general purpose or special purpose processor to perform certain processes. Alternatively, these processes may be performed by specific hardware components that include hardwired logic for performing processes, or by any combination of programmed computer components and custom hardware components.Elements of the present invention may also be provided as a machine readable medium for storing the machine executable instructions. The machine-readable medium may include, but is not limited to, floppy disks, optical disks, CD-ROMs, and magneto-optical disks, FLASH memories, ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, propagation media, or any other type of media / machine-readable medium suitable for storing electronic instructions. For example, the present invention may be downloaded as a computer program that may be transmitted from a remote computer (e.g., a server) to a requesting computer (e.g., a client) via data signals embodied in a carrier wave or other propagation medium via a communication link (e.g., a modem or network link).In the foregoing description, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broad spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.A device has been described that comprises a first semiconductor chip. A second semiconductor chip is stacked on the first semiconductor chip. The first semiconductor chip has a larger surface area than the second semiconductor chip, such that there is an edge region of the first semiconductor chip that is not covered by the second semiconductor chip. The device includes thermally conductive material over the second semiconductor chip. The device has a composite shape between the thermally conductive material and both the second semiconductor chip and the edge region of the first semiconductor chip. The device includes a thermally conductive structure extending through the composite mold that thermally couples the edge region to the thermally conductive material.In one embodiment, the composite mold comprises a heat insulating filler. In yet another embodiment, the composite mold does not comprise a substantially heat insulating filler. In yet another embodiment, the composite mold comprises a thermal conductivity of less than 2.0 W / mk. In yet another embodiment, the thermally conductive structure is formed from a thermally conductive paste. In yet another embodiment, the thermally conductive structure is disposed over a hot spot of the first semiconductor chip. In yet another embodiment, the apparatus includes a second thermally conductive structure over the hot spot, the thermally conductive structure extending through the composite mold thermally coupling the hot spot to the edge region. In yet another embodiment, the device includes a second thermally conductive structure extending through the composite mold that thermally couples the edge region to the thermally conductive material.A method has been described that includes stacking a second semiconductor chip on a first semiconductor chip to form a stacked semiconductor chip structure. The first semiconductor chip has a larger surface area than the second semiconductor chip, such that there is an edge region of the first semiconductor chip that is not covered by the second semiconductor chip. The method further includes forming a composite shape over the stacked semiconductor chip structure. The method further includes creating an opening in the composite shape over the edge region. The method further includes inserting the first thermally conductive material into the opening. The method further includes forming a second thermally conductive material over the composite mold, the first thermally conductive material thermally coupling the second thermally conductive material and the edge region.In one embodiment, the composite mold comprises a silica filler. In another embodiment, the composite form does not comprise an alumina or copper filler. In another embodiment, the composite mold comprises a thermal conductivity of less than 2.0 W / mk. In another embodiment, the first thermally conductive material comprises solder paste. In another embodiment, the first thermally conductive material is disposed over a hot spot of the first semiconductor chip.A computer has also been described that includes a plurality of processing cores coupled to a memory controller. The memory controller is coupled to system memory and a peripheral control node. The computer further includes a first semiconductor chip and a second semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip. The first semiconductor chip has a larger surface area than the second semiconductor chip, such that there is an edge region of the first semiconductor chip that is not covered by the second semiconductor chip. A thermally conductive material is located over the second semiconductor chip. A bond form is present between the thermally conductive material and both the second semiconductor die and the edge region of the first semiconductor die. A thermally conductive structure extends through the composite mold that thermally couples the edge region to the thermally conductive material.In one embodiment, the composite mold comprises a heat insulating filler. In yet another embodiment, the composite mold does not comprise a substantially thermally conductive filler. In yet another embodiment, the composite mold comprises a thermal conductivity of less than 2.0 W / mk. In an embodiment, the thermally conductive structure is formed of solder paste. In an embodiment, the second semiconductor die is a system memory die and the first semiconductor die is a semiconductor die that includes the plurality of processing cores.

Claims

An apparatus comprising: a first semiconductor chip (202); a second semiconductor chip (201) stacked on the first semiconductor chip (202), the first semiconductor chip (201) having a larger surface area than the second semiconductor chip (202) such that there is an edge region (210) of the first semiconductor chip (201) not covered by the second semiconductor chip (202); thermally conductive material (205) over the second semiconductor chip (202); a bond form (204) between the thermally conductive material and both the second semiconductor chip (201) and the edge region of the first semiconductor chip (202); and a thermally conductive structure (211) extending through the bond form (204) that thermally couples the edge region (210) to the thermally conductive material (205), wherein the bond form (204) comprises a thermally insulating filler.The apparatus of claim 1, wherein the composite mold (204) comprises a thermal conductivity of less than 2.0 W / mk.The apparatus of claim 1, wherein the thermally conductive structure is formed from a thermally conductive paste.The apparatus of claim 1, wherein the thermally conductive structure is disposed over a hot spot of the first semiconductor chip (202).The apparatus of claim 5, further comprising a second thermally conductive structure over the hot spot, the thermally conductive structure extending through the composite mold (204) thermally coupling the hot spot to the edge region (210).The apparatus of claim 1, further comprising a second thermally conductive structure extending through the composite mold (204) that thermally couples the edge region (210) to the thermally conductive material.A method comprising: stacking (401) a second semiconductor chip on a first semiconductor chip to form a stacked semiconductor chip structure, the first semiconductor chip having a larger surface area than the second semiconductor chip such that there is an edge region of the first semiconductor chip not covered by the second semiconductor chip; forming (402) a composite mold over the stacked semiconductor chip structure, the composite mold comprising a thermally insulating filler; creating (403) an opening in the composite mold over the edge region; inserting (404) the first thermally conductive material into the opening; and forming (405) a second thermally conductive material over the composite mold, the first thermally conductive material thermally coupling the second thermally conductive material and the edge region.The method of claim 8, wherein the composite form comprises a silica filler.The method of claim 8, wherein the composite form does not comprise an alumina or copper filler.The method of claim 8, wherein the composite mold comprises a thermal conductivity of less than 2.0 W / mk.The method of claim 8, wherein the first thermally conductive material comprises solder paste.The method of claim 8, wherein the first thermally conductive material is disposed over a hot spot of the first semiconductor chip.A computer comprising: a plurality of processing cores coupled to a memory controller, the memory controller coupled to a system memory and a peripheral control node, the computer further comprising: a first semiconductor die; a second semiconductor die stacked on the first semiconductor die, the first semiconductor die having a larger surface area than the second semiconductor die such that there is an edge region of the first semiconductor die not covered by the second semiconductor die; thermally conductive material over the second semiconductor die; a bond form between the thermally conductive material and both the second semiconductor die and the edge region of the first semiconductor die, the bond form comprising a thermally insulating filler; and a thermally conductive structure extending through the bond form that thermally couples the edge region to the thermally conductive material.The computer of claim 13, wherein the composite mold comprises a thermal conductivity of less than 2.0 W / mk.The computer of claim 13, wherein the thermally conductive structure is formed of solder paste.The computer of claim 13, wherein the second semiconductor die is a system memory die and the first semiconductor die is a semiconductor die comprising the plurality of processing cores.

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