Method for manufacturing a semiconductor device

Abstract

Method for manufacturing a semiconductor device, comprising the steps of: Formation of an oxide semiconductor film (109) at a first temperature; Processing the oxide semiconductor film (109) into an island shape (108); subsequent deposition of a material (112) that becomes a source electrode (112a) and a drain electrode (112b) by a sputtering process over the oxide semiconductor film (108), without carrying out a process at a temperature higher than the first temperature; Processing the material (112) to form the source electrode (112a) and the drain electrode (112b); subsequent formation of an insulating protective film (114, 116) over the oxide semiconductor film (108), the source electrode (112a) and the drain electrode (112b); subsequent formation of a first barrier film (131) over the insulating protective film (114, 116); Adding excess oxygen or an oxygen radical to the insulating protective film (116) via the first barrier film (131); Performing a heat treatment at a second temperature below 400 °C to diffuse the excess oxygen or oxygen radical into the oxide semiconductor film (108); Removal of the first barrier film (131) or part of the first barrier film and part of the insulating protective film (116) by wet setting; and subsequent formation of a second barrier film (118) over the insulating protective film (116).

Description

Technical area

[0001] One embodiment of the present invention relates to a semiconductor device including an oxide semiconductor film and a display device including the semiconductor device. Another embodiment of the present invention relates to a manufacturing method of a semiconductor device including an oxide semiconductor film.

[0002] It should be noted that an embodiment of the present invention is not limited to the above technical field. The technical field of an embodiment of the invention disclosed in this specification and the like relates to an article, a method, or a manufacturing method. Furthermore, the present invention relates to a process, a machine, a fabrication, or a composition of matter. In particular, an embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, a driving method thereof, or a manufacturing method thereof.

[0003] In this specification and the like, a semiconductor device generally refers to a device that can operate by utilizing semiconductor properties. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are each an embodiment of a semiconductor device. An imaging device, a display device, a liquid crystal display device, a light-emitting device, an electro-optical device, a power generation device (including a thin-film solar cell, an organic thin-film solar cell, and the like), and an electronic device may include a semiconductor device. State of the art

[0004] Attention has focused on a technique for fabricating a transistor using a semiconductor thin film formed over a substrate with an insulating surface (also called a field-effect transistor (FET) or thin-film transistor (TFT)). Such transistors are used in a wide range of electronic devices, such as an integrated circuit (IC) and an image display device (display device). A semiconductor material, typically silicon, is widely known as a semiconductor thin film material that can be used for a transistor. Another material that has attracted attention is an oxide semiconductor.

[0005] A highly reliable semiconductor device in which a transistor using an oxide semiconductor has stable electrical properties is disclosed (see, for example, Patent Document 1). In the semiconductor device, oxide semiconductor films with different compositions are stacked such that an oxide semiconductor film containing a large amount of In is provided on the channel side, and an oxide semiconductor film containing a large amount of stabilizers such as Ga is provided on the back channel side. [Reference][Patent document]

[0006] [Patent Document 1] Japanese Patent Laid-Open No. JP 2013-175715 A

[0007] US 2013 / 0161610 A1 provides a semiconductor device and a method for manufacturing the same. A transistor containing an oxide semiconductor layer is shown as an example of the semiconductor device. A layer with barrier properties, i.e., with a high shielding effect (blocking effect), is used as the metal oxide layer, which prevents the penetration of oxygen and impurities such as hydrogen and moisture.

[0008] US 2011 / 0062435 A1 deals with a semiconductor device and a method for its production. A thin film made of a material consisting of InMO3(ZnO) m (m>0) is formed using an oxide semiconductor described in the specification, and a thin-film transistor containing the thin film as the oxide semiconductor layer is fabricated. Note that m is not always an integer. M represents one or more metal elements. Disclosure of the invention

[0009] An oxide semiconductor film containing a large amount of In could have a small energy band gap (E g ) (for example, less than 3.0 eV). Such an oxide semiconductor film with a small E g is more strongly affected by light than an oxide semiconductor film with a large E g (for example, greater than or equal to 3.0 eV and less than or equal to 3.5 eV). For example, if a transistor comprising an oxide semiconductor film with a small E g contains, is subjected to a bias temperature stress test in which a negative bias is applied and light irradiation is performed (negative gate bias temperature (GBT) stress test with light irradiation), the reliability of the transistor is reduced in some cases.

[0010] The negative GBT stress test with light irradiation is a type of accelerated test and can quickly evaluate the change in the characteristics of transistors exposed to light irradiation caused by long-term use. In particular, the amount of change between the threshold voltage (ΔV th ) of the transistor before and after a negative GBT stress test with light irradiation is an important indicator for investigating the reliability of the transistor. The smaller the amount of change between the threshold voltage (ΔV th ) of the transistor before the negative GBT stress test with light irradiation and that after, the higher the reliability of the transistor.

[0011] In the case where a glass substrate is used to manufacture a semiconductor device including an oxide semiconductor film, the glass substrate may be distorted if the process temperature is high. A glass substrate is particularly likely to be noticeably distorted if it has any of the following sizes: the sixth generation (1500 mm × 1850 mm), the seventh generation (1870 mm × 2200 mm), the eighth generation (2200 mm × 2400 mm), the ninth generation (2400 mm × 2800 mm), and the tenth generation (2950 mm × 3400 mm). Accordingly, the temperature in the process for manufacturing the semiconductor device should be low.

[0012] In view of the foregoing, an object of an embodiment of the present invention is to suppress a change in electrical characteristics and improve the reliability of a transistor including an oxide semiconductor film with a large amount of In. Another object of an embodiment of the present invention is to provide a semiconductor device with low power consumption. Another object of an embodiment of the present invention is to provide a novel semiconductor device. Another object of an embodiment of the present invention is to provide a method for manufacturing a novel semiconductor device. Another object of an embodiment of the present invention is to provide a method for manufacturing a highly reliable semiconductor device at a relatively low temperature.Another object of an embodiment of the present invention is to provide a method for manufacturing a novel display device.

[0013] It should be noted that the description of the above objects does not affect the existence of other objects. In one embodiment of the present invention, it is unnecessary to fulfill all of the objects. Objects other than the above objects will become apparent from the explanation of the description and the like and can be derived therefrom.

[0014] One embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the steps of: forming an oxide semiconductor film at a first temperature; then processing the oxide semiconductor film into an island shape; then depositing a material that will become a source electrode and a drain electrode by a sputtering method without performing a process at a temperature higher than the first temperature; processing the material to form the source electrode and the drain electrode; then forming at least one of a first insulating protective film and a second insulating protective film, and then forming a first barrier film; adding excess oxygen or an oxygen radical to the second insulating protective film via the first barrier film;Performing a heat treatment at a second temperature lower than 400°C to diffuse the excess oxygen or oxygen radical into the oxide semiconductor film; and removing the first barrier film or a part of the first barrier film and a part of the second insulating protective film by wet etching and then forming a second barrier film.

[0015] In the above embodiment, the first barrier film is preferably an indium tin oxide film, an indium tin silicon oxide film, or an indium oxide film.

[0016] In the above embodiment, the second barrier film is preferably a silicon nitride oxide film or a silicon nitride film.

[0017] Another embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the steps of: forming an oxide semiconductor film at a first temperature; then processing the oxide semiconductor film into an island shape; then depositing a material that will become a source electrode and a drain electrode by a sputtering method without performing a process at a temperature higher than the first temperature; processing the material to form the source electrode and the drain electrode; then forming a first insulating protective film and / or a second insulating protective film, and then forming a metal oxide film as a first barrier film by a sputtering method to add excess oxygen or an oxygen radical to the second insulating protective film;and performing a heat treatment at a second temperature lower than 400 °C to diffuse the excess oxygen or oxygen radical into the oxide semiconductor film;

[0018] In the above embodiment, the metal oxide film is preferably an aluminum oxide film, a hafnium oxide film or an yttrium oxide film.

[0019] In the above embodiment, the oxide semiconductor film preferably has a multilayer structure of a first oxide semiconductor film having an atomic ratio of In:M (aluminum, gallium, yttrium or tin):Zn = 4:α1 (1.5 ≤ α1 ≤ 2.5):α2 (2.5 ≤ α2 ≤ 3.5) and a second oxide semiconductor film having an atomic ratio of In:M:Zn = 1:β1 (0.8 ≤ β1 ≤ 1.2):β2 (0.8 ≤ β2 ≤ 1.2).

[0020] In the above embodiment, the oxide semiconductor film preferably comprises a CAAC-OS.

[0021] In the above embodiment, the second temperature is preferably lower than 375°C. In the above embodiment, the second temperature is preferably higher than or equal to 340°C and lower than or equal to 360°C.

[0022] Another embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the steps of: forming an oxide semiconductor film at a first temperature; processing the oxide semiconductor film into an island shape; depositing a material that will become a source electrode and a drain electrode by a sputtering method over the oxide semiconductor film; processing the material to form the source electrode and the drain electrode; forming a first insulating protective film and a second insulating protective film over the oxide semiconductor film, the source electrode, and the drain electrode; heating the first insulating protective film and the second insulating protective film at a second temperature higher than the first temperature; forming a first barrier film over the second insulating protective film;Adding excess oxygen or an oxygen radical to the second insulating protective film over the first barrier film; removing a portion of the first barrier film and a portion of the second insulating protective film by wet etching; and forming a second barrier film over the second insulating protective film at a third temperature higher than the first temperature. The second temperature and / or the third temperature are / is the highest in a process of the steps.

[0023] In the above embodiment, the oxide semiconductor film preferably has a multilayer structure of a first oxide semiconductor film having an atomic ratio of In:M (aluminum, gallium, yttrium or tin):Zn = 4:α1(1.5 ≤ α1 ≤ 2.5):α2(2.5 ≤ α2 ≤ 3.5) and a second oxide semiconductor film having an atomic ratio of In:M:Zn = 1:β1(0.8 ≤ β1 ≤ 1.2):β2(0.8 ≤ β2 ≤ 1.2).

[0024] In the above embodiment, the oxide semiconductor film preferably includes a crystal part, and the crystal part preferably has an orientation with respect to the c-axis.

[0025] In the above embodiment, the first temperature is preferably lower than 340°C. In the above embodiment, the first temperature is preferably higher than or equal to 100°C and lower than or equal to 200°C.

[0026] In the above embodiment, the second temperature is preferably lower than 375°C. In the above embodiment, the second temperature is preferably higher than or equal to 340°C and lower than or equal to 360°C.

[0027] Another embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the steps of: forming an oxide semiconductor film at a first temperature; processing the oxide semiconductor film into an island shape; depositing a material that will become a source electrode and a drain electrode by a sputtering method over the oxide semiconductor film; processing the material to form the source electrode and the drain electrode; forming a first insulating protective film and a second insulating protective film over the oxide semiconductor film, the source electrode, and the drain electrode; heating the first insulating protective film and the second insulating protective film at a second temperature higher than the first temperature;Forming a metal oxide film over the second insulating protective film to add excess oxygen or an oxygen radical to the second insulating protective film; and heating the second insulating protective film at a third temperature higher than the first temperature to diffuse the excess oxygen or the oxygen radical into the oxide semiconductor film. The second temperature and / or the third temperature are / is the highest in a process of the steps.

[0028] Another embodiment of the present invention is a method for manufacturing a semiconductor device, comprising the steps of: forming an oxide semiconductor film at a first temperature; processing the oxide semiconductor film into an island shape; depositing a material that will become a source electrode and a drain electrode by a sputtering method over the oxide semiconductor film; processing the material to form the source electrode and the drain electrode; forming a first insulating protective film and a second insulating protective film over the oxide semiconductor film, the source electrode, and the drain electrode; heating the first insulating protective film and the second insulating protective film at a second temperature higher than the first temperature;and forming a metal oxide film over the second insulating protective film at a third temperature higher than the first temperature to add excess oxygen or an oxygen radical to the second insulating protective film and diffuse oxygen, the excess oxygen, or the oxygen radical in the second insulating protective film into the oxide semiconductor film. The second temperature and / or the third temperature are / is the highest in a process of the steps.;

[0029] In the above embodiment, the metal oxide film is preferably an aluminum oxide film, a hafnium oxide film or an yttrium oxide film.

[0030] In the above embodiment, the oxide semiconductor film preferably has a multilayer structure of a first oxide semiconductor film having an atomic ratio of In:M (aluminum, gallium, yttrium or tin):Zn = 4:α1(1.5 ≤ α1 ≤ 2.5):α2(2.5 ≤ α2 ≤ 3.5) and a second oxide semiconductor film having an atomic ratio of In:M:Zn = 1:β1(0.8 ≤ β1 ≤ 1.2):β2(0.8 ≤ β2 ≤ 1.2).

[0031] In the above embodiment, the oxide semiconductor film preferably includes a crystal part, and the crystal part preferably has an orientation with respect to the c-axis.

[0032] In the above embodiment, the first temperature is preferably lower than 340°C. In the above embodiment, the first temperature is preferably higher than or equal to 100°C and lower than or equal to 200°C.

[0033] In the above embodiment, the second temperature and / or the third temperature are / is preferably lower than 375°C. In the above embodiment, the second temperature and / or the third temperature are / is preferably higher than or equal to 340°C and lower than or equal to 360°C.

[0034] According to an embodiment of the present invention, a change in electrical characteristics can be suppressed and the reliability of a semiconductor device using a transistor including an oxide semiconductor can be improved. According to an embodiment of the present invention, a semiconductor device with low power consumption can be provided. According to an embodiment of the present invention, a novel semiconductor device can be provided. According to an embodiment of the present invention, a method for manufacturing a novel semiconductor device can be provided. According to an embodiment of the present invention, a method for manufacturing a highly reliable semiconductor device at a relatively low temperature can be provided.According to an embodiment of the present invention, a novel display device can be provided.

[0035] It should be noted that the description of these effects does not preclude the existence of other effects. In one embodiment of the present invention, it is unnecessary to achieve all of the effects listed above. Other effects will become apparent from and can be derived from the explanation of the specification, the drawings, the claims, and the like. Short description of the drawings Fig. 1A to Fig. 1C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. Fig. 2A to Fig. 2C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. Fig. 3A to Fig. 3C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. Fig. 4A to Fig. 4C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. Fig. 5A to Fig. 5C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device, and cross-sectional views and a plan view of an embodiment of a semiconductor device. Fig. 6A and Fig. 6B are top plan and cross-sectional views illustrating one embodiment of a semiconductor device. Fig. 7A to Fig. 7C are cross-sectional views illustrating an example of a manufacturing process of a semiconductor device. Fig. 8 shows a band structure. Fig. 9A and Fig. 9B are cross-sectional views illustrating embodiments of a semiconductor device. Fig. 10A to Fig. Figure 10D are Cs-corrected high-resolution TEM images of a cross-section of a CAAC-OS and a schematic cross-sectional view of a CAAC-OS. Fig. 11A to Fig. Figure 11D are Cs-corrected high-resolution TEM images of one plane of a CAAC-OS. Fig. 12A to Fig. 12C show structural analyses of a CAAC-OS and a single-crystal oxide semiconductor by XRD. Fig. 13A and Fig. 13B shows electron diffraction patterns of a CAAC-OS. Fig. Figure 14 shows changes in crystal parts of In-Ga-Zn oxides exposed to electron irradiation. Fig. 15A and Fig. 15B are schematic views showing deposition models of a CAAC-OS and an nc-OS. Fig. 16A to Fig. 16C show an InGaZnO4 crystal and a pellet. Fig. 17A to Fig. 17D are schematic views showing a deposition model of a CAAC-OS. Fig. 18 is a plan view illustrating an embodiment of a display device. Fig. 19 is a cross-sectional view illustrating an embodiment of a display device. Fig. 20 is a cross-sectional view illustrating one embodiment of a display device. Fig. 21A to Fig. 21C are a block diagram and circuit diagrams illustrating a display device. Fig. 22 represents a display module. Fig. 23A to Fig. 23G represent electronic devices. Fig. 24 illustrates a circuit configuration of a semiconductor device. Fig. 25A to Fig. 25C show I d -V g-Properties of transistors of an example. Best mode for carrying out the invention

[0036] Embodiments are described below with reference to the drawings. The embodiments can be implemented in various modes. It will be readily understood by those skilled in the art that modes and details can be changed in various ways.

[0037] In the drawings, the size, layer thickness, or area is exaggerated in some cases for clarity. Therefore, embodiments of the present invention are not limited to such a size ratio. It should be noted that the drawings are schematic views showing ideal examples, and embodiments of the present invention are not limited to the shapes or values ​​shown in the drawings.

[0038] It should be noted that in this description, ordinal numbers such as "first", "second", and "third" are used to avoid confusion between components, and the terms do not limit the number of components.

[0039] Please note that in this specification, terms such as "above," "above," "below," and "below" are used for convenience when describing a positional relationship between components based on drawings. The positional relationship between components will be further adjusted as needed according to the direction in which each component is described. Therefore, the positional relationship is not limited to the terms in this specification and may be appropriately explained using a different term depending on the circumstances.

[0040] In this specification and the like, a transistor is an element that has at least three terminals: a gate, a drain, and a source. The transistor includes a channel region between the drain (a drain terminal, a drain region, or a drain electrode) and the source (a source terminal, a source region, or a source electrode), and a current can flow through the drain, the channel region, and the source. Note that in this specification and the like, a channel region refers to a region through which current mainly flows.

[0041] Furthermore, when, for example, transistors with different polarities are used or when a current flow direction is changed during circuit operation, the functions of a source and a drain may be interchanged. Therefore, the terms "source" and "drain" may be interchanged in this description and the like.

[0042] Note that the term "electrically connected" in this specification and the like includes the case where components are connected via an "object having an electrical function." There is no particular limitation on an "object having an electrical function" as long as electrical signals can be sent and received between components connected via the object. Examples of an "object having an electrical function" include, in addition to an electrode and a wire, a switching element such as a transistor, a resistor, a coil, a capacitor, and elements with various functions.

[0043] It should be noted that in this specification and the like, a "silicon oxynitride film" means a film in which the proportion of oxygen is higher than that of nitrogen, and a "silicon nitride oxide film" means a film in which the proportion of nitrogen is higher than that of oxygen.

[0044] When describing structures of the invention with reference to the drawings in this specification and the like, the same reference numerals are commonly used for the same portions in different drawings.

[0045] In this specification and the like, the term "parallel" indicates that the angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and therefore also includes the case where the angle is greater than or equal to -5° and less than or equal to 5°. The term "substantially parallel" indicates that the angle formed between two straight lines is greater than or equal to -30° and less than or equal to 30°. Furthermore, the term "perpendicular" indicates that the angle formed between two straight lines is greater than or equal to -80° and less than or equal to 100°, and therefore also includes the case where the angle is greater than or equal to 85° and less than or equal to 95°.The term “substantially perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 60° and less than or equal to 120°.

[0046] In this description and the like, the terms "film" and "layer" may be interchanged as appropriate. For example, in some cases, the term "conductive layer" may be replaced with the term "conductive film." Likewise, in some cases, the term "insulating film" may be replaced with the term "insulating layer." (Embodiment 1)

[0047] In this embodiment, a semiconductor device which is an embodiment of the present invention and a manufacturing method of the semiconductor device are described with reference to Fig. 1A to Fig. 1C, Fig. 2A to Fig. 2C, Fig. 3A to Fig. 3C, Fig. 4A to Fig. 4C, Fig. 5A to Fig. 5C, Fig. 6A and Fig. 6B, Fig. 7A to Fig. 7C, Fig. 8 and Fig. 9A and Fig. 9B. <Strukturbeispiel 1 der Halbleitervorrichtung>

[0048] Fig. 5C is a plan view of a transistor 100, which is a semiconductor device of one embodiment of the present invention. Fig. 5B is a cross-sectional view taken along the dashed line X1-X2 in Fig. 5C and a cross-sectional view along the dashed line Y1-Y2 in Fig. 5C. It should be noted that Fig. 1A to Fig. 1C, Fig. 2A to Fig. 2C, Fig. 3A to Fig. 3C, Fig. 4A to Fig. 4C and Fig. 5A are cross-sectional views illustrating a manufacturing process of the transistor 100 in Fig. 5B. Fig. 1A to Fig. 1C, Fig. 2A to Fig. 2C, Fig. 3A to Fig. 3C, Fig. 4A to Fig. 4C and Fig. 5A and Fig. 5B represent a cross-sectional view along the dashed line X1-X2 and a cross-sectional view along the dashed line Y1-Y2 on the left and right sides, respectively.

[0049] It should be noted that in Fig. 5C, some components of the transistor 100 (e.g., an insulating film serving as a gate insulating film) are not shown to avoid complexity. The direction of the dashed line X1-X2 may be referred to as the channel length direction, and the direction of the dashed line Y1-Y2 may be referred to as the channel width direction. In plan views of the transistors described below, as shown in Fig. 5C in some cases some components are not shown.

[0050] The transistor 100 includes a conductive film 104 serving as a gate electrode over a substrate 102, an insulating film 106 over the substrate 102 and the conductive film 104, an insulating film 107 over the insulating film 106, an oxide semiconductor film 108 over the insulating film 107, a conductive film 112a serving as a source electrode and electrically connected to the oxide semiconductor film 108, and a conductive film 112b serving as a drain electrode and electrically connected to the oxide semiconductor film 108. Insulating films 114, 116, and 118 are provided over the transistor 100, specifically, over the conductive films 112a and 112b and the oxide semiconductor film 108. The insulating films 114, 116, and 118 serve as insulating protective films of the transistor 100. The insulating films 114, 116, and 118 are also referred to as the first insulating protective film, the second insulating protective film, and the third insulating protective film, respectively.

[0051] The oxide semiconductor film 108 includes a first oxide semiconductor film 108a on the side of the conductive film 104 and a second oxide semiconductor film 108b over the first oxide semiconductor film 108a. Note that the conductive film 104 serves as a gate electrode. Furthermore, the insulating films 106 and 107 serve as gate insulating films of the transistor 100.

[0052] For the oxide semiconductor film 108, an In-M (M is aluminum, gallium, yttrium, or tin) oxide or an In-M-Zn oxide can be used. Specifically, an In-M-Zn oxide is preferably used for the oxide semiconductor film 108.

[0053] The first oxide semiconductor film 108a preferably has an atomic ratio of In:M:Zn = 4:α1(1.5 ≤ α1 ≤ 2.5):α2(2.5 ≤ α2 ≤ 3.5). The second oxide semiconductor film 108b preferably has an atomic ratio of In:M:Zn = 1:β1(0.8 ≤ β1 ≤ 1.2):β2(0.8 ≤ β2 ≤ 1.2).

[0054] When the first oxide semiconductor film 108a has the above atomic ratio, that is, a composition in which the atomic proportion of In is higher than that of M, the field-effect mobility (also referred to simply as mobility or µFE) of the transistor 100 can be improved. In particular, the field-effect mobility of the transistor 100 can be 10 cm 2 / Vs, preferably 30 cm 2 / Vs, exceed.

[0055] For example, the use of the transistor having a high field-effect mobility for a gate driver that generates a gate signal (in particular, a demultiplexer connected to an output terminal of a shift register included in a gate driver) enables a semiconductor device or a display device to have a narrow frame.

[0056] It should be noted that when the first oxide semiconductor film 108a has a composition in which the atomic fraction of In is higher than that of M, the electrical characteristics of the transistor 100 are easily changed by light irradiation. However, in the semiconductor device of one embodiment of the present invention, the second oxide semiconductor film 108b is formed over the first oxide semiconductor film 108a. The atomic fraction of In in the second oxide semiconductor film 108b is lower than that in the first oxide semiconductor film 108a, and thus the second oxide semiconductor film 108b has a larger E g than the first oxide semiconductor film 108a. Therefore, the oxide semiconductor film 108, which has a multilayer structure of the first oxide semiconductor film 108a and the second oxide semiconductor film 108b, has high resistance to a negative bias stress test with light irradiation.

[0057] The amount of light absorbed by the oxide semiconductor film 108 having the above multilayer structure can be reduced during light irradiation. This can reduce changes in the electrical characteristics of the transistor 100 due to light irradiation.

[0058] When oxygen vacancies are formed in the oxide semiconductor film 108 included in the transistor 100, electrons are generated to serve as charge carriers; consequently, the transistor 100 tends to be normally on. Note that a normally on transistor refers to a transistor in which a current (e.g., a current between a drain and a source (I ds )) at a gate voltage V gof 0 V. Therefore, for stable transistor properties, it is important to reduce oxygen vacancies in the oxide semiconductor film 108, particularly oxygen vacancies in the first oxide semiconductor film 108a. In the structure of the transistor of one embodiment of the present invention, excess oxygen is introduced into an insulating film above the oxide semiconductor film 108, here the insulating film 114 and / or the insulating film 116 above the oxide semiconductor film 108, so that oxygen migrates from the insulating film 114 and / or the insulating film 116 into the oxide semiconductor film 108 to fill oxygen vacancies in the oxide semiconductor film 108, particularly in the first oxide semiconductor film 108a.Alternatively, during the formation of a first barrier film formed over the insulating film 116, excess oxygen is introduced into the insulating film 116 so that the oxygen migrates from the insulating film 116 to the oxide semiconductor film 108 to fill oxygen vacancies in the oxide semiconductor film 108, particularly in the first oxide semiconductor film 108a.

[0059] The insulating films 114 and 116 preferably each include a region containing oxygen in excess of the stoichiometric composition (excess oxygen region). In other words, the insulating films 114 and 116 are insulating films capable of releasing oxygen. Note that the excess oxygen region in the insulating films 114 and 116 is formed, for example, by introducing oxygen into the insulating films 114 and 116 after deposition. The method for introducing oxygen may include an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, or the like.

[0060] To fill the oxygen vacancies in the first oxide semiconductor film 108a, a channel region in the second oxide semiconductor film 108b and its vicinity preferably has a small thickness. For example, the thickness of the channel region in the second oxide semiconductor film 108b and its vicinity is preferably greater than or equal to 1 nm and less than or equal to 20 nm, more preferably greater than or equal to 3 nm and less than or equal to 10 nm.

[0061] To fill the oxygen vacancies in the first oxide semiconductor film 108a, the second oxide semiconductor film 108b preferably has high oxygen permeability. When the second oxide semiconductor film 108b has high oxygen permeability, excess oxygen in the insulating films 114 and 116 can be advantageously diffused into the first oxide semiconductor film 108a.

[0062] As described above, in a semiconductor device of one embodiment of the present invention, an oxide semiconductor film has a multilayer structure, and an insulating film in contact with the oxide semiconductor film contains excess oxygen; thus, the reliability of the semiconductor device can be high. Furthermore, the temperature during the manufacturing process of the semiconductor device of one embodiment of the present invention can be low (typically lower than 400°C or lower than 375°C (preferably higher than or equal to 340°C and lower than or equal to 360°C)). Note that the manufacturing process of the semiconductor device will be described later.

[0063] Other components of the semiconductor device of this embodiment will be described in detail below. <substrat>

[0064] There is no particular limitation on a material and the like of the substrate 102, as long as the material has heat resistance high enough to withstand at least one heat treatment that will be performed later. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used as the substrate 102. Alternatively, a single-crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon, silicon carbide, or the like, a compound semiconductor substrate made of silicon germanium or the like, an SOI substrate, or the like can be used as the substrate 102. As a further alternative, any of these substrates provided with a semiconductor element can be used as the substrate 102.When a glass substrate is used as substrate 102, a glass substrate of any of the following sizes can be used: sixth generation, seventh generation, eighth generation, ninth generation, and tenth generation. Thus, a large display device can be manufactured. Such a large substrate is preferably used because it can reduce manufacturing costs.

[0065] Alternatively, a flexible substrate may be used as substrate 102, and the transistor 100 may be provided directly on the flexible substrate. Alternatively, a separation layer may be disposed between the substrate 102 and the transistor 100. The separation layer may be used when part or all of the semiconductor device formed over the separation layer is separated from the substrate 102 and transferred to another substrate. In such a case, the transistor 100 may be transferred to a substrate with low heat resistance or to a flexible substrate. <Leitender Film, der als Gate-Elektrode und Source- und Drain-Elektrode dient>

[0066] The conductive film 104 serving as a gate electrode, the conductive film 112a serving as a source electrode, and the conductive film 112b serving as a drain electrode can each be formed using a metal element selected from chromium (Cr), copper (Cu), aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), and cobalt (Co), an alloy containing any of these metal elements as its component, an alloy combining any of these metal elements, or the like.

[0067] The conductive films 104, 112a, and 112b may further have a single-layer structure or a multi-layer structure composed of two or more layers. For example, the following structures may be provided: a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is layered over an aluminum film, a two-layer structure in which a titanium film is layered over a titanium nitride film, a two-layer structure in which a tungsten film is layered over a titanium nitride film, a two-layer structure in which a tungsten film is layered over a tantalum nitride film or a tungsten nitride film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are layered in this order, and the like.Alternatively, an alloy film or a nitride film can be used in which aluminum and one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium and scandium are combined.

[0068] The conductive films 104, 112a and 112b may be formed using a light-transmitting conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide has been added.

[0069] A Cu-X alloy film (X represents Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can be used for the conductive films 104, 112a, and 112b. By using a Cu-X alloy film, manufacturing costs can be reduced because a wet etching process can be used during processing. <Isolierender Film, der als Gate-isolierfilm dient>

[0070] For each of the insulating films 106 and 107 serving as gate insulating films of the transistor 100, an insulating layer comprising at least one of the following films formed by a plasma enhanced chemical vapor deposition (PECVD) method, a sputtering method, or the like may be used: a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film.It should be noted that instead of a multi-layer structure of the insulating films 106 and 107, a single-layer insulating film formed using a material selected from the above materials or an insulating film of three or more layers may be used.

[0071] The insulating film 106 serves as a barrier film that prevents oxygen from entering. For example, if excess oxygen is supplied to the insulating film 107, the insulating film 114, the insulating film 116, and / or the oxide semiconductor film 108, the insulating film 106 can prevent oxygen from entering.

[0072] Note that the insulating film 107 in contact with the oxide semiconductor film 108 serving as the channel region of the transistor 100 is preferably an insulating oxide film and preferably includes a region containing more oxygen than the stoichiometric composition (excess oxygen region). In other words, the insulating film 107 is an insulating film capable of releasing oxygen. To provide the excess oxygen region in the insulating film 107, for example, the insulating film 107 is formed in an oxygen atmosphere. Alternatively, the excess oxygen region may be formed by introducing oxygen into the insulating film 107 after deposition.As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment or the like can be used.

[0073] When hafnium oxide is used for the insulating film 107, the following effect is achieved. Hafnium oxide has a higher dielectric constant than silicon oxide and silicon oxynitride. Thus, the insulating film 107 using hafnium oxide can have a greater thickness than the insulating film 107 using silicon oxide; thus, a leakage current due to a tunnel current can be low. This means that it is possible to provide a transistor with a low off-state current. In addition, hafnium oxide with a crystalline structure has a higher dielectric constant than hafnium oxide with an amorphous structure. Accordingly, it is preferable to use hafnium oxide with a crystalline structure to provide a transistor with a low off-state current. Examples of the crystalline structure include a monoclinic crystal structure and a cubic crystal structure.It should be noted that an embodiment of the present invention is not limited to the above examples.

[0074] In this embodiment, a silicon nitride film is formed as the insulating film 106, and a silicon oxide film is formed as the insulating film 107. A silicon nitride film has a higher dielectric constant than a silicon oxide film and requires a greater thickness to achieve a capacitance equal to that of the silicon oxide film. Therefore, when a silicon nitride film is used as the gate insulating film of the transistor 100, the physical thickness of the insulating film can be increased. This makes it possible to reduce a decrease in the withstand voltage of the transistor 100 and further increase the withstand voltage, thereby reducing damage to the transistor 100 due to electrostatic discharge. <oxidhalbleiterfilm>

[0075] The oxide semiconductor film 108 can be formed using any of the materials described above. When the oxide semiconductor film 108 contains an In-M-Zn oxide, the atomic ratio of the metal elements of a sputtering target used to form the In-M-Zn oxide preferably satisfies In≥M and Zn≥M. As the atomic ratio of the metal elements of such a sputtering target, In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, and In:M:Zn = 4:2:4.1 are suitable. When the oxide semiconductor film 108 contains an In-M-Zn oxide, a target containing polycrystalline In-M-Zn oxide is preferably used as the sputtering target. The use of the target containing a polycrystalline In-M-Zn oxide facilitates the formation of the oxide semiconductor film 108 having crystallinity.It should be noted that the atomic ratio of the metal elements of the deposited oxide semiconductor film 108 may deviate from the above atomic ratio of the metal elements of the sputtering target within an error range of ±40%. For example, if a sputtering target with an atomic ratio of In:Ga:Zn = 4:2:4.1 is used, the atomic ratio of In to Ga and Zn in the oxide semiconductor film 108 may be approximately 4:2:3.

[0076] The first oxide semiconductor film 108a can be formed using the sputtering target having an atomic ratio of In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:4.1, or the like. Preferably, the first oxide semiconductor film 108a has an atomic ratio of In:M:Zn = 4: α1 (1.5≤α1≤2.5): α2 (2.5≤α2≤3.5).

[0077] The second oxide semiconductor film 108b can be formed using the sputtering target having an atomic ratio of In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, or the like. Preferably, the second oxide semiconductor film 108b has an atomic ratio of In:M:Zn = 1:β1(0.8≤β1≤1.2):β2(0.8≤β2≤1.2). Note that the atomic ratio of the metal elements in the sputtering target used to form the second oxide semiconductor film 108b does not necessarily have to satisfy In≥M and Zn≥M, but may satisfy In<M or Zn<M. For example, the sputtering target can have an atomic ratio of In:M:Zn = 1:3:2, In:M:Zn = 1:3:4, or In:M:Zn = 1:3:6.

[0078] The energy gap of the oxide semiconductor film 108 is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. Using an oxide semiconductor film with a large energy gap can reduce the off-state current of the transistor 100. Specifically, an oxide semiconductor film with an energy gap of more than or equal to 2 eV, preferably more than or equal to 2 eV and less than or equal to 3.0 eV, is preferably used as the first oxide semiconductor film 108a, and an oxide semiconductor film with an energy gap of more than or equal to 2.5 eV and less than or equal to 3.5 eV is preferably used as the second oxide semiconductor film 108b. Furthermore, the second oxide semiconductor film 108b preferably has a larger energy gap than the first oxide semiconductor film 108a.

[0079] The thicknesses of the first oxide semiconductor film 108a and the second oxide semiconductor film 108b are each greater than or equal to 3 nm and less than or equal to 200 nm, preferably greater than or equal to 3 nm and less than or equal to 100 nm, more preferably greater than or equal to 3 nm and less than or equal to 50 nm.

[0080] As the first oxide semiconductor film 108a, a low carrier density oxide semiconductor film is used, whereby the carrier density of the first oxide semiconductor film 108a is higher than or equal to 1 × 10 -9 / cm 3 and lower than 8 × 10 11 / cm 3 , preferably higher than or equal to 1 × 10 -9 / cm 3 and lower than 1 × 10 11 / cm 3 , more preferably higher than or equal to 1 × 10 -9 / cm 3 and lower than 1 × 10 10 / cm 3 As the second oxide semiconductor film 108b, a low carrier density oxide semiconductor film is used, whereby the carrier density of the second oxide semiconductor film 108b is 1 × 10 17 / cm 3 or less, preferably 1 × 10 13 / cm 3 or less, more preferably 1 × 10 13 / cm 3 or less and even more preferably 1 × 10 11 / cm 3 or less.

[0081] Note that the composition is not limited to the above, and an oxide semiconductor film with a suitable composition can be used depending on the required semiconductor properties and electrical properties (e.g., field-effect mobility and threshold voltage) of a transistor. To obtain the required semiconductor properties of a transistor, it is preferable to set the carrier density, impurity concentration, defect density, atomic ratio of a metal element to oxygen, atomic spacing, density, and the like of the first oxide semiconductor film 108a and the second oxide semiconductor film 108b to appropriate values.

[0082] Note that, for each of the first oxide semiconductor film 108a and the second oxide semiconductor film 108b, it is preferable to use an oxide semiconductor film in which the impurity concentration is low and the density of defect states is low, so that the transistor can exhibit excellent electrical characteristics. Here, the state in which the impurity concentration is low and the density of defect states is low (the amount of oxygen vacancies is low) is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic." A high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has few carrier generation sources and can therefore exhibit a low carrier density. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film rarely has a negative threshold voltage (is rarely normally on).A high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film exhibits, in some cases, a low density of defect states and thus a low density of trap states. Furthermore, a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film exhibits a very low off-state current. The off-state current of an element with a channel width of 1 × 10 6 µm and a channel length L of 10 µm can be less than or equal to the measurement limit of a semiconductor parameter analyzer, i.e. less than or equal to 1 × 10 -13 A at a voltage (drain voltage) between a source electrode and a drain electrode of 1 V to 10 V.

[0083] Consequently, a transistor in which a channel region is formed in a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film can exhibit low fluctuations in electrical properties and high reliability. Charges trapped by the trap states in the oxide semiconductor film take a long time to be released and may behave like stationary charges. Therefore, in some cases, a transistor in which a channel region is formed in an oxide semiconductor film with a high density of trap states exhibits unstable electrical properties. Examples of impurities include hydrogen, nitrogen, an alkali metal, and an alkaline earth metal.

[0084] Hydrogen contained in the oxide semiconductor film reacts with oxygen bonded to a metal atom to form water, and oxygen vacancies are also formed in a lattice from which oxygen is released (or in a portion from which oxygen is released). As a result of hydrogen entering the oxygen vacancies, electrons serving as charge carriers are generated in some cases. Furthermore, in some cases, bonding of a portion of hydrogen with oxygen bonded to a metal atom causes the generation of an electron serving as a charge carrier. Therefore, a transistor including a hydrogen-containing oxide semiconductor film is likely to exhibit a self-conducting behavior. Accordingly, it is preferable that hydrogen in the oxide semiconductor film 108 be reduced as much as possible.Specifically, the hydrogen concentration in the oxide semiconductor film 108 measured by SIMS is less than or equal to 2 × 10. 20 atoms / cm 3 , preferably less than or equal to 5 × 10 19 atoms / cm 3 , more preferably less than or equal to 1 × 10 19 atoms / cm 3 , more preferably less than or equal to 5 × 10 18 atoms / cm 3 , even more preferably lower than or equal to 1 × 10 18 atoms / cm 3 , more preferably less than or equal to 5 × 10 17 atoms / cm 3 , more preferably less than or equal to 1 × 10 16 atoms / cm 3 .

[0085] The first oxide semiconductor film 108a preferably includes a region where the hydrogen concentration is lower than that in the second oxide semiconductor film 108b. When the first oxide semiconductor film 108a includes the region where the hydrogen concentration is lower than that in the second oxide semiconductor film 108b, the semiconductor device can be highly reliable.

[0086] When silicon or carbon, which is one of the elements belonging to Group 14, is contained in the first oxide semiconductor film 108a, oxygen vacancies in the first oxide semiconductor film 108a proliferate, and the first oxide semiconductor film 108a becomes an n-type film. Consequently, the silicon or carbon concentration (the concentration is measured by SIMS) in the first oxide semiconductor film 108a or the silicon or carbon concentration (the concentration is measured by SIMS) in the vicinity of an interface with the first oxide semiconductor film 108a is set to less than or equal to 2 × 10 18 atoms / cm 3 , preferably less than or equal to 2 × 10 17 atoms / cm 3 set.

[0087] Further, the alkali metal or alkaline earth metal concentration in the first oxide semiconductor film 108a measured by SIMS is less than or equal to 1 × 10 18 atoms / cm 3 , preferably less than or equal to 2 × 10 16 atoms / cm 3 An alkali metal and an alkaline earth metal could generate charge carriers when bonded to an oxide semiconductor, in which case the transistor's off-state current could increase. Therefore, the alkali metal or alkaline earth metal concentration in the first oxide semiconductor film 108a is preferably reduced.

[0088] When the first oxide semiconductor film 108a further contains nitrogen, it readily exhibits n-type conductivity due to the generation of electrons serving as carriers and the increase in carrier density. Consequently, a transistor including a nitrogen-containing oxide semiconductor film is likely to exhibit a normally-on behavior. For this reason, nitrogen in the oxide semiconductor film is preferably reduced as much as possible; for example, the nitrogen concentration measured by SIMS is preferably set to less than or equal to 5 × 10 18 atoms / cm 3 set.

[0089] The first oxide semiconductor film 108a and the second oxide semiconductor film 108b may each have, for example, a non-single-crystalline structure. The non-single-crystalline structure includes, for example, a c-axis aligned crystalline oxide semiconductor (CAAC-OS), which will be described later, a polycrystalline structure, a microcrystalline structure, or an amorphous structure. Among the non-single-crystalline structures, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

[0090] Here, a band structure including the oxide semiconductor film 108 and the insulating films in contact with the oxide semiconductor film 108 is shown by Fig. 8 described.

[0091] Fig. Fig. 8 shows an example of a band structure along the thickness direction of a layer arrangement including the insulating film 107, the first oxide semiconductor film 108a, the second oxide semiconductor film 108b, and the insulating film 114. For better understanding, the energy level of the conduction band minimum (E c ) of the insulating film 107, the first oxide semiconductor film 108a, the second oxide semiconductor film 108b and the insulating film 114 in the band structure, respectively.

[0092] In the band structure of the Fig. 8, a silicon oxide film is used for each of the insulating films 107 and 114, an oxide semiconductor film formed using a metal oxide target having a metal element atomic ratio of In:Ga:Zn = 4:2:4.1 is used as the first oxide semiconductor film 108a, and a metal oxide film formed using a metal oxide target having a metal element atomic ratio of In:Ga:Zn = 1:1:1.2 is used as the second oxide semiconductor film 108b.

[0093] As in Fig. As shown in Figure 8, the energy level of the conduction band minimum between the first oxide semiconductor film 108a and the second oxide semiconductor film 108b changes continuously. In other words, the energy level of the conduction band minimum changes continuously or is continuously continuous. To achieve such a band structure, no impurity forming a defect state, such as a trap center or a recombination center, is present at the interface between the first oxide semiconductor film 108a and the second oxide semiconductor film 108b.

[0094] In order to form a continuous transition between the first oxide semiconductor film 108a and the second oxide semiconductor film 108b, the films are successively formed without exposing them to the air using a multi-chamber deposition apparatus (sputtering apparatus) including a load-lock chamber.

[0095] The band structure in Fig. 8, the first oxide semiconductor film 108a serves as a well, and a channel region is formed in the first oxide semiconductor film 108a of the transistor having the multilayer structure.

[0096] In the case where the second oxide semiconductor film 108b is not provided, trap states may be formed in the first oxide semiconductor film 108a. However, in the above multilayer structure, the trap states may be formed in the second oxide semiconductor film 108b. Thus, the trap states can be kept away from the first oxide semiconductor film 108a.

[0097] In addition, the trap states could be further away from the vacuum level than the energy level of the conduction band minimum (E c ) of the first oxide semiconductor film 108a, which serves as a channel region, so that electrons are likely to accumulate in the trap states. When the electrons are accumulated in the trap states, the electrons become negative stationary electric charges, so that the threshold voltage of the transistor shifts in the positive direction. Accordingly, it is preferable that the energy level of the trap states be closer to the vacuum level than the energy level of the conduction band minimum (E c ) of the first oxide semiconductor film 108a. Such a structure prevents the accumulation of electrons in the trap states. Consequently, the forward current and field-effect mobility of the transistor can be increased.

[0098] In Fig. 8, the energy level of the conduction band minimum of the second oxide semiconductor film 108b is closer to the vacuum level than that of the first oxide semiconductor film 108a. Typically, the energy difference between the conduction band minimum of the first oxide semiconductor film 108a and the conduction band minimum of the second oxide semiconductor film 108b is 0.15 eV or more, or 0.5 eV or more, and 2 eV or less, or 1 eV or less. That is, the difference between the electron affinity of the second oxide semiconductor film 108b and the electron affinity of the first oxide semiconductor film 108a is 0.15 eV or more, or 0.5 eV or more, and 2 eV or less, or 1 eV or less.

[0099] In such a structure, the first oxide semiconductor film 108a serves as the main current path and functions as a channel region. Furthermore, since the second oxide semiconductor film 108b contains one or more metal elements contained in the first oxide semiconductor film 108a, interfacial scattering is less likely to occur at the interface between the first oxide semiconductor film 108a and the second oxide semiconductor film 108b, where a channel region is formed. Consequently, the transistor can have high field-effect mobility because the movement of charge carriers is not restricted at the interface.

[0100] To prevent the second oxide semiconductor film 108b from serving as part of a channel region, a material having a sufficiently low conductivity is used for the second oxide semiconductor film 108b. Alternatively, a material having a lower electron affinity (a difference in energy level between the vacuum level and the conduction band minimum) than the first oxide semiconductor film 108a and having a conduction band minimum that is different from that of the first oxide semiconductor film 108a (band deviation) is used for the second oxide semiconductor film 108b.Furthermore, the second oxide semiconductor film 108b is preferably formed using a material whose energy level of the conduction band minimum is closer to the vacuum level by 0.2 eV or more, preferably by 0.5 eV or more, than that of the first oxide semiconductor film 108a in order to prevent a difference between the threshold voltages from occurring due to the value of the drain voltage.

[0101] Preferably, the second oxide semiconductor film 108b does not have a spinel crystal structure. This is because if the second oxide semiconductor film 108b has a spinel crystal structure, a constituent element of the conductive films 112a and 112b may diffuse into the first oxide semiconductor film 108a at the interface between the spinel crystal structure and another region. Note that the second oxide semiconductor film 108b is preferably a CAAC-OS, which will be described later, because in this case, a higher barrier performance against constituent elements of the conductive films 112a and 112b, such as copper, is obtained.

[0102] The thickness of the second oxide semiconductor film 108b is large enough to prevent the diffusion of the constituent elements of the conductive films 112a and 112b into the first oxide semiconductor film 108a, and small enough to not prevent the supply of oxygen from the insulating film 114 to the first oxide semiconductor film 108a. For example, when the thickness of the second oxide semiconductor film 108b is greater than or equal to 10 nm, the constituent elements of the conductive films 112a and 112b can be prevented from diffusing into the first oxide semiconductor film 108a. When the thickness of the second oxide semiconductor film 108b is less than or equal to 100 nm, oxygen can be effectively supplied from the insulating films 114 and 116 to the first oxide semiconductor film 108a. <Isolierende Filme, die als isolierende Schutzfilme des Transistors dienen>

[0103] The insulating films 114 and 116 each have a function of supplying oxygen to the oxide semiconductor film 108. The insulating film 118 serves as an insulating protective film for the transistor 100. The insulating films 114 and 116 contain oxygen. Furthermore, the insulating film 114 is an insulating film that allows oxygen to pass through. Note that the insulating film 114 also serves as a film that limits damage to the oxide semiconductor film 108 during the formation of the insulating film 116 in a later step.

[0104] A silicon oxide film, a silicon oxynitride film, or the like having a thickness of greater than or equal to 5 nm and less than or equal to 150 nm, preferably greater than or equal to 5 nm and less than or equal to 50 nm can be used as the insulating film 114.

[0105] In addition, the number of defects in the insulating film 114 is preferably small; typically, according to an ESR measurement, the spin density corresponding to a signal appearing due to an open bond of silicon at g = 2.001 is less than or equal to 3 × 10 17 Spins / cm 3 This is because when the density of defects in the insulating film 114 is high, oxygen is bound to the defects and the amount of oxygen permeating the insulating film 114 decreases.

[0106] Note that not all of the oxygen entering the insulating film 114 from the outside migrates to the outside of the insulating film 114, and some oxygen remains in the insulating film 114. Furthermore, in some cases, the migration of oxygen in the insulating film 114 occurs such that oxygen enters the insulating film 114 and oxygen contained in the insulating film 114 migrates to the outside of the insulating film 114. When an oxide insulating film that permeates oxygen is formed as the insulating film 114, oxygen released from the insulating film 116 provided above the insulating film 114 can migrate through the insulating film 114 to the oxide semiconductor film 108.

[0107] The insulating film 114 can be formed using an insulating oxide film having a low density of nitrogen oxide-induced states. Note that the density of nitrogen oxide-induced states can be between the energy of the valence band maximum (E v_os ) and the energy of the conduction band minimum (E c_os ) of the oxide semiconductor film. A silicon oxynitride film that emits less nitrogen oxide, an aluminum oxynitride film that emits less nitrogen oxide, or the like can be used as the insulating oxide film.

[0108] It should be noted that a silicon oxynitride film that releases less nitrogen oxide is a film that releases more ammonia than nitrogen oxide in a thermal desorption spectroscopy analysis; the number of released ammonia molecules from the silicon oxynitride film is typically greater than or equal to 1 × 10 18 / cm 3 and less than or equal to 5 × 10 19 / cm 3 . It should be noted that the number of ammonia molecules released from a film is the number of ammonia molecules released during a heat treatment in which the surface temperature of the film becomes higher than or equal to 50 °C and lower than or equal to 650 °C, preferably higher than or equal to 50 °C and lower than or equal to 550 °C.

[0109] Nitric oxide (NO x ; x is greater than or equal to 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2), typically NO2 or NO, for example, forms levels in the insulating film 114. The level lies in the energy gap of the oxide semiconductor film 108. Therefore, when nitrogen oxide diffuses into the interface between the insulating film 114 and the oxide semiconductor film 108, an electron is trapped by the level on the insulating film 114 side. Consequently, the trapped electron remains in the vicinity of the interface between the insulating film 114 and the oxide semiconductor film 108; therefore, the threshold voltage of the transistor is shifted in the positive direction.

[0110] Nitrogen oxide reacts with ammonia and oxygen during heat treatment. Since nitrogen oxide contained in the insulating film 114 reacts with ammonia contained in the insulating film 116 during heat treatment, the nitrogen oxide contained in the insulating film 114 is reduced. Therefore, an electron is hardly trapped at the interface between the insulating film 114 and the oxide semiconductor film 108.

[0111] By using the above insulating oxide film for the insulating film 114, a shift in the threshold voltage of the transistor can be reduced, resulting in less change in the electrical characteristics of the transistor.

[0112] It should be noted that in an ESR spectrum at 100 K or less of the insulating film 114 by the heat treatment of a manufacturing process of the transistor, typically a heat treatment at a temperature lower than 400 °C or lower than 375 °C (preferably higher than or equal to 340 °C and lower than or equal to 360 °C), a first signal appearing at a g-factor of greater than or equal to 2.037 and less than or equal to 2.039, a second signal appearing at a g-factor of greater than or equal to 2.001 and less than or equal to 2.003, and a third signal appearing at a g-factor of greater than or equal to 1.964 and less than or equal to 1.966 are observed. The slit width of the first and second signals and the slit width of the second and third signals obtained by ESR measurement using an X-band are each about 5 mT.The sum of the spin densities of the first signal occurring at a g-factor greater than or equal to 2.037 and less than or equal to 2.039, the second signal occurring at a g-factor greater than or equal to 2.001 and less than or equal to 2.003, and the third signal occurring at a g-factor greater than or equal to 1.964 and less than or equal to 1.966 is less than 1 × 10. 18 Spins / cm 3 , typically greater than or equal to 1 × 10 17 Spins / cm 3 and less than 1 × 10 18 Spins / cm 3 .

[0113] In the ESR spectrum at 100 K or lower, the first signal appearing at a g-factor greater than or equal to 2.037 and less than or equal to 2.039, the second signal appearing at a g-factor greater than or equal to 2.001 and less than or equal to 2.003, and the third signal appearing at a g-factor greater than or equal to 1.964 and less than or equal to 1.966 correspond to signals attributable to nitric oxide (NO x ; x is greater than or equal to 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2). Typical examples of nitrogen oxide include nitrogen monoxide and nitrogen dioxide. In other words, the lower the total spin density of the first signal appearing at a g-factor of greater than or equal to 2.037 and less than or equal to 2.039, the second signal appearing at a g-factor of greater than or equal to 2.001 and less than or equal to 2.003, and the third signal appearing at a g-factor of greater than or equal to 1.964 and less than or equal to 1.966, the lower the nitrogen oxide content in the insulating oxide film.

[0114] The nitrogen concentration in the above insulating oxide film measured by SIMS is less than or equal to 6 × 10 20 atoms / cm 3 .

[0115] A dense and hard film can be formed by forming the above insulating oxide film by a PECVD method using silane and nitrous oxide at a substrate temperature higher than or equal to 220 °C and lower than or equal to 350 °C.

[0116] The insulating film 116 is formed using an oxide insulating film containing oxygen in excess of that in the stoichiometric composition. A portion of the oxygen is released from the oxide insulating film, which contains oxygen in excess of that in the stoichiometric composition, by heating. The oxide insulating film containing oxygen in excess of the stoichiometric composition is an oxide insulating film in which the amount of released oxygen converted into oxygen atoms is greater than or equal to 1.0 × 10 19 atoms / cm 3 , preferably greater than or equal to 3.0 × 10 20 atoms / cm 3 in the TDS analysis. It should be noted that the temperature of the film surface in the TDS analysis is preferably higher than or equal to 100 °C and lower than or equal to 700 °C, or preferably higher than or equal to 100 °C and lower than or equal to 500 °C.

[0117] As the insulating film 116, a silicon oxide film, a silicon oxynitride film, or the like having a thickness of more than or equal to 30 nm and less than or equal to 500 nm, preferably more than or equal to 50 nm and less than or equal to 400 nm can be used.

[0118] Preferably, the number of defects in the insulating film 116 is small; typically, according to an ESR measurement, the spin density corresponding to a signal appearing due to an open bond of silicon at g = 2.001 is lower than 1.5 × 10 18 Spins / cm 3 , preferably less than or equal to 1 × 10 18 Spins / cm 3 Note that the insulating film 116 is disposed at a greater distance from the oxide semiconductor film 108 than the insulating film 114; therefore, the insulating film 116 may have a higher defect density than the insulating film 114.

[0119] Furthermore, the insulating films 114 and 116 may be formed using insulating films made of the same types of materials; therefore, an interface between the insulating films 114 and 116 may not be clearly visible in some cases. Therefore, in this embodiment, the interface between the insulating films 114 and 116 is shown by a dashed line. Although a two-layer structure of the insulating films 114 and 116 is described in this embodiment, the present invention is not limited to this structure. For example, a single-layer structure of either the insulating film 114 or 116 may be used.

[0120] The insulating film 118 has a function of blocking oxygen, hydrogen, water, an alkali metal, an alkaline earth metal, and the like. By providing the insulating film 118, the diffusion of oxygen from the oxide semiconductor film 108 to the outside, the diffusion of oxygen contained in the insulating films 114 and 116 to the outside, and the entry of hydrogen, water, or the like into the oxide semiconductor film 108 from the outside can be prevented. For example, an insulating nitride film can be used as the insulating film 118. The insulating nitride film is formed using silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, or the like. In particular, a silicon nitride oxide film or a silicon nitride film is preferably used as the insulating film 118, in which case the diffusion of oxygen to the outside can be prevented.

[0121] Note that, instead of the nitride insulating film having a barrier effect against oxygen, hydrogen, water, an alkali metal, an alkaline earth metal, and the like, an oxide insulating film having a barrier effect against oxygen, hydrogen, water, and the like may be provided as the insulating film 118. As the oxide insulating film having a barrier effect against oxygen, hydrogen, water, and the like, an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, a gallium oxynitride film, a yttrium oxide film, a yttrium oxynitride film, a hafnium oxide film, a hafnium oxynitride film, and the like can be cited. As the oxide insulating film having a barrier effect against oxygen, hydrogen, water, and the like, an aluminum oxide film, a hafnium oxide film, or a yttrium oxide film is particularly preferable.

[0122] Although the various films, such as the conductive films, insulating films, and oxide semiconductor films described above, can be formed by a sputtering method or a PECVD method, such films can also be formed by another method, such as a thermal chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method. As an example of a thermal CVD method, a metal organic chemical vapor deposition (MOCVD) method can be cited.

[0123] A thermal CVD process has the advantage that no defects are caused by plasma damage, since no plasma is used to form a film.

[0124] Deposition over a substrate by a thermal CVD process can be carried out by simultaneously supplying a source gas and an oxidant to a chamber, adjusting the pressure in the chamber to atmospheric pressure or reduced pressure, and allowing the source gas and the oxidant to react with each other near or above the substrate.

[0125] Deposition by an ALD method can be carried out as follows: The pressure in a chamber is adjusted to atmospheric pressure or a reduced pressure, source gases for the reaction are sequentially introduced into the chamber, and then the gas introduction sequence is repeated. For example, two or more types of source gases are sequentially supplied to the chamber by switching the respective switching valves (also called high-speed valves). For example, a first source gas is introduced, an inert gas (e.g., argon or nitrogen) or the like is introduced simultaneously with or after the introduction of the first gas so that the source gases do not mix, and then a second source gas is introduced.It should be noted that in the case where the first source gas and the inert gas are introduced simultaneously, the inert gas serves as a carrier gas, and the inert gas can also be introduced simultaneously with the second source gas. Alternatively, the first source gas can be exhausted by vacuum extraction instead of introducing the inert gas, and then the second source gas can be introduced. The first source gas is adsorbed on the surface of the substrate to form a first layer; then, the second source gas is introduced to react with the first layer; as a result, a second layer is disposed over the first layer, so that a thin film is formed. The sequence of gas introduction is repeated several times until a required thickness is achieved, whereby a thin film with excellent step coverage can be formed.The thickness of the thin film can be controlled by the number of repetitions of the gas injection sequence, therefore an ALD process allows a thickness to be precisely controlled and is thus suitable for fabricating a very small FET.

[0126] The various films, such as conductive films, insulating films, oxide semiconductor films, and metal oxide films, of this embodiment can be formed by a thermal CVD method such as a MOCVD method. For example, in the case where an In-Ga-Zn-O film is formed, trimethylindium, trimethylgallium, and dimethylzinc are used. Note that the chemical formula of trimethylindium is In(CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3. The chemical formula of dimethylzinc is Zn(CH3)2. Without being limited to the above combination, triethylgallium (chemical formula: Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (chemical formula: Zn(C2H5)2) can be used instead of dimethylzinc.

[0127] For example, in the case where a hafnium oxide film is formed with a deposition device using an ALD method, two types of gases are used, i.e., ozone (O3) as an oxidizer and a source gas obtained by evaporating a liquid containing a solvent and a hafnium precursor compound (e.g., a hafnium alkoxide or a hafnium amide, typically tetrakis(dimethylamide)hafnium (TDMAH). It should be noted that the chemical formula of tetrakis(dimethylamide)hafnium is Hf[N(CH3)2]4. Examples of another liquid material include tetrakis(ethylmethylamide)hafnium.

[0128] For example, in the case where an aluminum oxide film is formed with a deposition device using an ALD method, two types of gases are used, such as H2O as an oxidizer and a source gas obtained by evaporating a liquid containing a solvent and an aluminum precursor compound (e.g., trimethylaluminum (TMA)). Note that the chemical formula of trimethylaluminum is Al(CH3)3. Examples of other liquid materials include tris(dimethylamide)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate).

[0129] For example, in the case where a silicon oxide film is formed with a deposition device using an ALD method, hexachlorodisilane is adsorbed on a surface on which a film is formed, chlorine contained in the adsorbate is removed, and radicals of an oxidizing gas (e.g., O2 or nitrous oxide) are supplied to react with the adsorbate.

[0130] For example, in the case where a tungsten film is formed with a deposition device using an ALD method, a WF6 gas and a B2H6 gas are sequentially introduced multiple times to form an initial tungsten film, and then a WF6 gas and an H2 gas are used to form a tungsten film. Note that an SiH4 gas can be used instead of a B2H6 gas.

[0131] For example, in the case where an oxide semiconductor film, such as an In-Ga-Zn-O film, is formed with a deposition apparatus using an ALD method, an In(CH3)3 gas and an O3 gas are sequentially introduced multiple times to form an InO layer, a Ga(CH3)3 gas and an O3 gas are simultaneously introduced to form a GaO layer, and then a Zn(CH3)2 gas and an O3 gas are used to form a ZnO layer. Note that the order of these layers is not limited to this example. A mixed compound layer, such as an In-Ga-O layer, an In-Zn-O layer, or a Ga-Zn-O layer, can be formed by mixing these gases. It should be noted that although an H2O gas obtained by bubbling (effervescing or effervescing) with an inert gas such as Ar can be used instead of an O3 gas, it is preferable to use an O3 gas because it does not contain H.Additionally, an In(C2H5)3 gas can be used instead of an In(CH3)3 gas. A Ga(C2H5)3 gas can be used instead of a Ga(CH3)3 gas. Furthermore, a Zn(CH3)2 gas can be used. <Strukturbeispiel 2 der Halbleitervorrichtung>

[0132] A structural example that differs from that of transistor 100 in Fig. 5B and Fig. 5C is determined by Fig. 6A and Fig. 6B. Note that in the case where a portion has a function similar to that described above, the same hatching pattern is used for the portion, and the portion is not specifically assigned a reference numeral in some cases.

[0133] Fig. 6A is a plan view of a transistor 170, which is a semiconductor device of one embodiment of the present invention. Fig. 6B is a cross-sectional view taken along the dashed line X1-X2 in Fig. 6A and a cross-sectional view along the dashed line Y1-Y2 in Fig. 6A. In Fig. 6B, the cross-sectional view along the dashed line X1-X2 and the cross-sectional view along the dashed line Y1-Y2 are shown on the left side and the right side, respectively.

[0134] The transistor 170 includes the conductive film 104 serving as a first gate electrode over the substrate 102, the insulating film 106 over the substrate 102 and the conductive film 104, the insulating film 107 over the insulating film 106, the oxide semiconductor film 108 over the insulating film 107, the insulating film 114 over the oxide semiconductor film 108, the insulating film 116 over the insulating film 114, the conductive film 112a serving as a source electrode electrically connected to the oxide semiconductor film 108, the conductive film 112b serving as a drain electrode electrically connected to the oxide semiconductor film 108, the insulating film 118 over the insulating film 116, a conductive film 120a over the insulating film 118, and a conductive film 120b over the insulating film 118. The insulating films 114, 116, and 118 serve as second gate insulating films of the transistor 170.The conductive film 120a is electrically connected to the conductive film 112b via an opening 142c provided in the insulating films 114, 116, and 118. The conductive film 120a in the transistor 170 serves, for example, as a pixel electrode used for a display device. The conductive film 120b in the transistor 170 serves as a second gate electrode (also referred to as a backgate electrode).

[0135] The conductive film 120b is, as shown in the cross-sectional view on the right in Fig. 6B, is connected to the conductive film 104 serving as the first gate electrode via openings 142a and 142b provided in the insulating films 106, 107, 114, 116, and 118. Accordingly, the same potential is applied to the conductive film 120b and the conductive film 104.

[0136] Note that, although the structure in which the openings 142a and 142b are provided so that the conductive film 120b and the conductive film 104 are connected to each other is described in this embodiment, an embodiment of the present invention is not limited thereto. For example, a structure in which only one of the openings 142a and 142b is provided so that the conductive film 120b is connected to the conductive film 104, or a structure in which the openings 142a and 142b are not provided and the conductive film 120b and the conductive film 104 are not connected to each other may be employed. Note that in the case where the conductive film 120b and the conductive film 104 are not connected to each other, it is possible to apply different potentials to the conductive film 120b and the conductive film 104.

[0137] As shown in the cross-sectional view on the left in Fig. As shown in Figure 6B, the oxide semiconductor film 108 is arranged to face both the conductive film 104 serving as the first gate electrode and the conductive film 120b serving as the second gate electrode, and is sandwiched between the two conductive films serving as gate electrodes. The lengths of the conductive film 120b serving as the second gate electrode in the channel length direction and the channel width direction are longer than those of the oxide semiconductor film 108 in the channel length direction and the channel width direction. The entire oxide semiconductor film 108 is covered with the conductive film 120b, with the insulating films 114, 116, and 118 positioned therebetween.Since the conductive film 120b serving as the second gate electrode is connected to the conductive film 104 serving as the first gate electrode via the openings 142a and 142b provided in the insulating films 106, 107, 114, 116, and 118, a side surface of the oxide semiconductor film 108 in the channel width direction faces the conductive film 120b serving as the second gate electrode with the insulating films 114, 116, and 118 positioned therebetween.

[0138] In other words, in the channel width direction of the transistor 170, the conductive film 104 serving as the first gate electrode and the conductive film 120b serving as the second gate electrode are connected to each other via the openings provided in the insulating films 106 and 107 serving as the first gate insulating films and in the insulating films 114, 116, and 118 serving as the second gate insulating films; the conductive film 104 and the conductive film 120b surround the oxide semiconductor film 108, with the insulating films 106 and 107 serving as the first gate insulating films and the insulating films 114, 116, and 118 serving as the second gate insulating films positioned therebetween.

[0139] In such a structure, electric fields of the conductive film 104 serving as the first gate electrode and the conductive film 120b serving as the second gate electrode can electrically surround the oxide semiconductor film 108 included in the transistor 170. A transistor device structure such as that of the transistor 170, in which electric fields of a first gate electrode and a second gate electrode electrically surround an oxide semiconductor film in which a channel region is formed, can be referred to as a surrounded-channel (s-channel) structure.

[0140] Since the transistor 170 has the s-channel structure, an electric field for inducing a channel can be effectively applied to the oxide semiconductor film 108 through the conductive film 104 serving as the first gate electrode; therefore, the current driving capability of the transistor 170 can be improved, and high forward current characteristics can be achieved. Since the forward current can be increased, it is possible to reduce the size of the transistor 170. In addition, the mechanical strength of the transistor 170 can be increased because the transistor 170 has a structure in which the oxide semiconductor film 108 is surrounded by the conductive film 104 serving as the first gate electrode and the conductive film 120b serving as the second gate electrode.

[0141] It should be noted that the other components of the transistor 170 are the same as those of the transistor 100 described above, and an effect similar to that of the transistor 100 can be obtained.

[0142] The structures of the transistors of this embodiment can be freely combined. For example, the transistor 100 shown in Fig. 5A and Fig. 5B can be used as a transistor in a pixel of a display device, and the transistor 170 shown in Fig. 6A and Fig. 6B can be used as a transistor in a gate driver of a display device. <Verfahren 1 zum Herstellen der Halbleitervorrichtung>

[0143] Next, a method of manufacturing the transistor 100, which is a semiconductor device of one embodiment of the present invention, will be described with reference to Fig. 1A to Fig. 1C, Fig. 2A to Fig. 2C, Fig. 3A to Fig. 3C, Fig. 4A to Fig. 4C and Fig. 5A. It should be noted that 1A to Fig. 1C, Fig. 2A to Fig. 2C, Fig. 3A to Fig. 3C, Fig. 4A to Fig. 4C and Fig. 5A are cross-sectional views illustrating the method of manufacturing the semiconductor device.

[0144] First, a conductive film is formed over the substrate 102 and processed through a lithography process and an etching process, thereby forming the conductive film 104 serving as a gate electrode. Subsequently, the insulating films 106 and 107 serving as gate insulating films are formed over the conductive film 104 (see Fig. 1A).

[0145] In this embodiment, a glass substrate is used for the substrate 102, and a 100 nm thick tungsten film is formed by a sputtering method as the conductive film 104 serving as the gate electrode. A 400 nm thick silicon nitride film and a 50 nm thick silicon oxynitride film are formed by a PECVD method as the insulating film 106 and the insulating film 107, respectively.

[0146] Note that the insulating film 106 may have a multilayer structure of silicon nitride films. Specifically, the insulating film 106 may have a three-layer structure of a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film. The following is an example of the three-layer structure.

[0147] For example, the first silicon nitride film can be formed to have a thickness of 50 nm under the following conditions: silane at a flow rate of 200 sccm, nitrogen at a flow rate of 2000 sccm, and an ammonia gas at a flow rate of 100 sccm are supplied to a reaction chamber of a PECVD apparatus as a source gas, the pressure in the reaction chamber is set to 100 Pa, and a power of 2000 W is supplied using a 27.12 MHz high-frequency power source.

[0148] The second silicon nitride film can be formed to have a thickness of 300 nm under the following conditions: silane at a flow rate of 200 sccm, nitrogen at a flow rate of 2000 sccm, and an ammonia gas at a flow rate of 2000 sccm are supplied to the reaction chamber of the PECVD apparatus as a source gas, the pressure in the reaction chamber is set to 100 Pa, and a power of 2000 W is supplied using a 27.12 MHz high-frequency power source.

[0149] The third silicon nitride film can be formed to have a thickness of 50 nm under the following conditions: silane at a flow rate of 200 sccm and nitrogen at a flow rate of 5000 sccm are supplied to the reaction chamber of the PECVD apparatus as source gas, the pressure in the reaction chamber is set to 100 Pa, and a power of 2000 W is supplied using a 27.12 MHz high-frequency power source.

[0150] It should be noted that the first silicon nitride film, the second silicon nitride film, and the third silicon nitride film can each be formed at a substrate temperature of 350 °C.

[0151] For example, when the insulating film 106 has the three-layer structure of the silicon nitride films, in the case where a conductive film containing copper (Cu) is used as the conductive film 104, the following effect can be obtained.

[0152] The first silicon nitride film can prevent the diffusion of copper (Cu) from the conductive film 104. The second silicon nitride film has a hydrogen-releasing function and can improve the withstand voltage of the insulating film serving as the gate insulating film. The third silicon nitride film releases a small amount of hydrogen and can prevent the diffusion of hydrogen released from the second silicon nitride film.

[0153] The insulating film 107 is preferably an insulating film containing oxygen in order to improve the properties of an interface with the oxide semiconductor film 108 (particularly, the first oxide semiconductor film 108a) formed at a later time.

[0154] Next, an oxide semiconductor film 109 is formed over the insulating film 107 at a first temperature. The oxide semiconductor film 109 is formed such that a first oxide semiconductor film 109a is first formed and then a second oxide semiconductor film 109b is formed (see Fig. 1B).

[0155] The first temperature at which the oxide semiconductor film 109 is formed is higher than or equal to room temperature and lower than 340°C, preferably higher than or equal to room temperature and lower than or equal to 300°C, more preferably higher than or equal to 100°C and lower than or equal to 250°C, and even more preferably higher than or equal to 100°C and lower than or equal to 200°C. The oxide semiconductor film 109 is formed while performing a heat treatment, so that the crystallinity of the oxide semiconductor film 109 can be improved. In the case where a large glass substrate (for example, a 6th to 10th generation glass substrate) is used as the substrate 102, the substrate 102 sometimes deforms when the first temperature is higher than or equal to 150°C and lower than 340°C.However, even if a large glass substrate is used, deformation of the glass substrate can be prevented if the first temperature is higher than or equal to 100 °C and lower than 150 °C.

[0156] The first oxide semiconductor film 109a and the second oxide semiconductor film 109b are formed either at the same substrate temperature or at different substrate temperatures. Preferably, the first oxide semiconductor film 109a and the second oxide semiconductor film 109b are formed at the same substrate temperature because this can reduce manufacturing costs.

[0157] In this embodiment, the first oxide semiconductor film 109a is formed by a sputtering method using an In-Ga-Zn metal oxide target (with an atomic ratio of In:Ga:Zn = 4:2:4.1), and then the second oxide semiconductor film 109b is successively formed in a vacuum by a sputtering method using an In-Ga-Zn metal oxide target (with an atomic ratio of In:Ga:Zn = 1:1:1.2). The first oxide semiconductor film 109a and the second oxide semiconductor film 109b are formed at a substrate temperature of 170°C.

[0158] In the case where the oxide semiconductor film 109 is formed by a sputtering method, a rare gas (typically argon), oxygen, or a mixed gas of a rare gas and oxygen is appropriately used as the sputtering gas. When using the mixed gas of a rare gas and oxygen, it is preferable to increase the proportion of oxygen with respect to a rare gas. Furthermore, it is necessary to increase the purity of a sputtering gas. For example, as the oxygen gas or argon gas used for a sputtering gas, a gas that has been highly purified to have a dew point of -40°C or lower, preferably -80°C or lower, more preferably -100°C or lower, furthermore preferably -120°C or lower is used, whereby the ingress of moisture or the like into the oxide semiconductor film 109 can be reduced as much as possible.

[0159] In the case where the oxide semiconductor film 109 is formed by a sputtering method, a chamber of a sputtering device is preferably made high vacuum (to about 5 × 10 -7 Pa to 1 × 10 -4 Pa) to remove water or the like, which serves as a contaminant to the oxide semiconductor film 109, as much as possible. Alternatively, a turbomolecular pump and a cold trap are preferably combined to prevent backflow of a gas, particularly a carbon- or hydrogen-containing gas, from an exhaust system into the chamber.

[0160] Subsequently, the oxide semiconductor film 109 is processed to form the island-shaped oxide semiconductor film 108. Note that the first oxide semiconductor film 109a is processed into the first island-shaped oxide semiconductor film 108a, and the second oxide semiconductor film 109b is processed into the second island-shaped oxide semiconductor film 108b (see Fig. 1C).

[0161] Subsequently, a conductive film 112, which will become the source electrode and the drain electrode, is formed by a sputtering method over the insulating film 107 and the oxide semiconductor film 108 (see Fig. 2A), and no heat treatment is performed at a temperature higher than the first temperature. In other words, the temperature of steps after processing the oxide semiconductor film 109 to form the island-shaped oxide semiconductor film 108 and before forming the conductive film 112 is lower than or equal to the first temperature.

[0162] In this embodiment, a multilayer film is formed as the conductive film 112, in which a 50 nm thick tungsten film and a 400 nm thick aluminum film are sequentially stacked by a sputtering method. Although the conductive film 112 of this embodiment has a two-layer structure, an embodiment of the present invention is not limited to this. For example, the conductive film 112 may have a three-layer structure in which a 50 nm thick tungsten film, a 400 nm thick aluminum film, and a 100 nm thick titanium film are sequentially stacked.

[0163] Next, masks 136a and 136b are formed in required areas over the conductive film 112 (see Fig. 2B).

[0164] The masks 136a and 136b of this embodiment are formed such that a photosensitive resin film is formed over the conductive film 112 and patterned by a lithography process.

[0165] Subsequently, an etchant 138 is applied from above the conductive film 112 and the masks 136a and 136b, so that the conductive film 112 is processed, thereby forming the conductive films 112a and 112b which are separated from each other (see Fig. 2C).

[0166] In this embodiment, the conductive film 112 is processed with a dry etching device. Note that a method for processing the conductive film 112 is not limited to this. For example, the conductive film 112 and the second oxide semiconductor film 108b may be processed with a wet etching device using a chemical solution as the etchant 138. Note that a finer pattern can be formed when a dry etching device is used to process the conductive film 112 instead of a wet etching device. However, the manufacturing cost can be reduced more significantly when a wet etching device is used to process the conductive film 112 instead of a dry etching device.

[0167] Subsequently, an etchant 139 is applied from above the second oxide semiconductor film 108b, the conductive films 112a and 112b, and the masks 136a and 136b to clean a surface of the second oxide semiconductor film 108b (on the back channel side) (see Fig. 3A).

[0168] For example, cleaning may be performed using a chemical solution such as phosphoric acid. Cleaning using a chemical solution such as phosphoric acid can remove impurities (e.g., elements contained in the conductive films 112a and 112b) adhering to the surface of the second oxide semiconductor film 108b. Note that cleaning is not necessarily performed; in some cases, cleaning may not be required.

[0169] By forming and / or cleaning the conductive films 112a and 112b, a region of the second oxide semiconductor film 108b not covered with the conductive film 112a or 112b becomes thinner than the first oxide semiconductor film 108a in some cases.

[0170] However, by forming and / or cleaning the conductive films 112a and 112b, the portion of the second oxide semiconductor film 108b not covered with the conductive film 112a or 112b may, in some cases, not become thinner than a portion of the second oxide semiconductor film 108b covered with the conductive film 112a or 112b. Fig. 9A and Fig. 9B provide examples of such a case. Fig. 9A and Fig. 9B are cross-sectional views illustrating examples of a semiconductor device. Fig. 9A and Fig. 9B respectively represent a cross-sectional view along the chain line X1-X2 and a cross-sectional view along the chain line Y1-Y2 on the left and right sides. Fig. 9A illustrates an example in which the second oxide semiconductor film 108b of the transistor 100 shown in Fig. 5B, does not become thinner than the area of ​​the second oxide semiconductor film 108b covered with the conductive film 112a or 112b. Fig. 9B illustrates an example in which the thickness of the second oxide semiconductor film 108b is made smaller than that of the first oxide semiconductor film 108a in advance, and the thickness of the region not covered with the conductive film 112a or 112b is substantially the same as that in the transistor 100 shown in Fig. 5B.

[0171] Then, the masks 136a and 136b are removed, forming the conductive film 112a serving as a source electrode and the conductive film 112b serving as a drain electrode over the second oxide semiconductor film 108b. The oxide semiconductor film 108 has a multilayer structure of the first oxide semiconductor film 108a and the second oxide semiconductor film 108b (see Fig. 3B).

[0172] Next, the insulating film 114 serving as a first insulating protective film and the insulating film 116 serving as a second insulating protective film are formed over the oxide semiconductor film 108 and the conductive films 112a and 112b, and then a first barrier film 131 is formed (see Fig. 3C).

[0173] Note that after the insulating film 114 is formed, the insulating film 116 is preferably formed successively without exposure to air. After the insulating film 114 is formed, the insulating film 116 is successively formed without exposure to air by regulating the flow rate of a source gas, the pressure, the high-frequency power, and / or the substrate temperature. This allows the impurity concentration due to the atmospheric component at the interface between the insulating film 114 and the insulating film 116 to be reduced, and oxygen in the insulating films 114 and 116 can migrate to the oxide semiconductor film 108; accordingly, the proportion of oxygen vacancies in the oxide semiconductor film 108 can be reduced.

[0174] As the insulating film 114, for example, a silicon oxynitride film can be formed by a PECVD method. In this case, a deposition gas containing silicon and an oxidizing gas are preferably used as the source gas. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and silane fluoride. Examples of the oxidizing gas include dinitrogen monoxide and nitrogen dioxide. An insulating film containing nitrogen and having a small number of defects can be formed as the insulating film 114 by a PECVD method under the following conditions: the proportion of the oxidizing gas is higher than 20 times and lower than 100 times, preferably higher than or equal to 40 times and lower than or equal to 80 times that of the deposition gas, and the pressure in a treatment chamber is lower than 100 Pa, preferably lower than or equal to 50 Pa.

[0175] In this embodiment, a silicon oxynitride film is formed as the insulating film 114 by a PECVD method under the following conditions: the substrate 102 is kept at a temperature of 220°C; silane with a flow rate of 50 sccm and nitrous oxide with a flow rate of 2000 sccm are used as the source gas, the pressure in the treatment chamber is 20 Pa; and a high-frequency power of 100 W at 13.56 MHz (1.6 × 10 -2 W / cm 2 as power density) is fed to parallel plate electrodes.

[0176] As the insulating film 116, a silicon oxide film or a silicon oxynitride film is formed under the following conditions: the substrate placed in a vacuum-evacuated treatment chamber of the PECVD apparatus is maintained at a temperature higher than or equal to 180°C and lower than or equal to 350°C; the pressure when introducing a source gas into the treatment chamber is higher than or equal to 100 Pa and lower than or equal to 250 Pa, preferably higher than or equal to 100 Pa and lower than or equal to 200 Pa; and a high-frequency power of higher than or equal to 0.17 W / cm 2 and less than or equal to 0.5 W / cm 2 , preferably higher than or equal to 0.25 W / cm 2 and less than or equal to 0.35 W / cm 2 is fed to an electrode provided in the treatment chamber.

[0177] Regarding the deposition conditions of the insulating film 116, high-frequency power having the above power density is supplied to a reaction chamber having the above pressure, thereby increasing the decomposition efficiency of the source gas in the plasma, increasing oxygen radicals, and promoting the oxidation of the source gas. Therefore, the oxygen content in the insulating film 116 becomes higher than that in the stoichiometric composition. On the other hand, in the film formed at a substrate temperature within the above temperature range, the bond between silicon and oxygen is weak, and consequently, a part of the oxygen in the film is released by heat treatment in a later step.Therefore, it is possible to form an insulating oxide film that contains more oxygen than the stoichiometric composition and from which part of the oxygen is released when heated.

[0178] Note that in the step of forming the insulating film 116, the insulating film 114 serves as a protective film for the oxide semiconductor film 108. Consequently, the insulating film 116 can be formed using high-frequency power with a high power density while reducing damage to the oxide semiconductor film 108.

[0179] It should be noted that, under the deposition conditions of the insulating film 116, the number of defects in the insulating film 116 can be reduced by increasing the flow rate of the silicon-containing deposition gas relative to the oxidizing gas. Typically, it is possible to form an insulating oxide layer in which the number of defects is small; that is, in an ESR measurement, the spin density of a signal appearing at g = 2.001 and originating from an open bond of silicon is lower than 6 × 10 17 Spins / cm 3 , preferably less than or equal to 3 × 10 17 Spins / cm 3 , more preferably less than or equal to 1.5 × 10 17 Spins / cm 3 As a result, the reliability of the transistor can be improved.

[0180] After the insulating films 114 and 116 have been formed (that is, after the insulating film 116 has been formed and before the first barrier film 131 is formed), a heat treatment may be performed. The heat treatment can reduce nitrogen oxide contained in the insulating films 114 and 116. Through the heat treatment, a portion of the oxygen contained in the insulating films 114 and 116 can migrate to the oxide semiconductor film 108, so that the amount of oxygen vacancies in the oxide semiconductor film 108 can be reduced.

[0181] The temperature of the heat treatment performed on the insulating films 114 and 116 is typically less than or equal to 400°C, preferably less than 375°C, more preferably greater than or equal to 150°C and less than 360°C, and even more preferably greater than or equal to 350°C and less than 360°C. The heat treatment can be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air in which the water content is 20 ppm or less, preferably 1 ppm or less, more preferably 10 ppb or less), or a rare gas (argon, helium, or the like). Note that an electric furnace, an RTA device, or the like, in which hydrogen, water, and the like are preferably not contained in the nitrogen, oxygen, ultra-dry air, or the rare gas, can be used for the heat treatment.

[0182] The first barrier film 131 contains oxygen and a metal (indium and / or zinc and / or titanium and / or aluminum and / or tungsten and / or tantalum and / or molybdenum and / or hafnium and / or yttrium). Indium tin oxide (also referred to as ITO), indium tin silicon oxide (In-Sn-Si oxide, hereinafter also referred to as ITSO), or indium oxide is preferably used for the first barrier film 131 because unevenness can be advantageously covered.

[0183] The first barrier film 131 can be formed by a sputtering method. When the first barrier film 131 is thin, it is sometimes difficult to prevent oxygen from being released from the insulating film 116 to the outside. In contrast, when the first barrier film 131 is thick, oxygen may not be advantageously added to the insulating film 116 in some cases. Accordingly, the thickness of the first barrier film 131 is preferably greater than or equal to 1 nm and less than or equal to 20 nm, or greater than or equal to 2 nm and less than or equal to 10 nm. In this embodiment, a 5 nm thick ITSO film is formed as the first barrier film 131.

[0184] Subsequently, oxygen 140 is added to the insulating film 116, which serves as a second insulating protective film, via the first barrier film 131. In Fig. 4A, oxygen added to the insulating film 116 is shown as oxygen 140a.

[0185] As a method for adding oxygen 140 to insulating film 116 via first barrier film 131, an ion doping method, an ion implantation method, a plasma treatment method, or the like can be used. The oxygen 140 can be excess oxygen, oxygen radicals, or the like. By applying a bias voltage to the substrate side when adding oxygen 140, oxygen 140 can be effectively added to insulating film 116. As a bias voltage, for example, the power density can be greater than or equal to 1 W / cm 2 and less than or equal to 5 W / cm 2 When the first barrier film 131 is provided over the insulating film 116 and oxygen is subsequently added, the first barrier film 131 serves as a protective film for preventing the release of oxygen from the insulating film 116. Thus, a larger amount of oxygen can be added to the insulating film 116.

[0186] Subsequently, a heat treatment is carried out at a second temperature of lower than 400 °C, whereby the excess oxygen or oxygen radicals can be diffused into the oxide semiconductor film 108 (see Fig. 4B).

[0187] In Fig. 4B, the heat treatment at the second temperature is schematically shown by arrows 141. The second temperature is lower than 400°C, preferably lower than 375°C, more preferably higher than or equal to 340°C, and lower than 360°C. The heat treatment at the second temperature can be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air in which the water content is 20 ppm or less, preferably 1 ppm or less, more preferably 10 ppb or less), or a rare gas (argon, helium, or the like). Note that an electric furnace, an RTA device, or the like can be used for the heat treatment, in which preferably neither hydrogen nor water, etc., are contained in the nitrogen, oxygen, ultra-dry air, or the rare gas.

[0188] In this embodiment, as the heat treatment at the second temperature, a heat treatment is performed at 350°C for 1 hour in a nitrogen atmosphere. Note that the second temperature at which the heat treatment is performed should be the highest in the manufacturing process of the transistor 100; however, a heat treatment may be performed in another step at a temperature substantially equal to the second temperature. For example, the substrate temperature during the formation of the insulating films 106, 107, 114, 116, and 118 may be equal to the second temperature.

[0189] Next, the first barrier film 131 or a part thereof and a part of the insulating film 116 serving as a second insulating protective film are removed using an etchant 142 (see Fig. 4C).

[0190] As a method for removing the first barrier film 131 and a portion of the insulating film 116 serving as a second insulating protective film, a dry etching method, a wet etching method, a combination of a dry etching method and a wet etching method, and the like can be specified. Note that the etchant 142 is an etching gas in the case of a dry etching method, and a chemical solution in the case of a wet etching method. In this embodiment, a wet etching method is preferably used to remove the first barrier film 131 because it can reduce manufacturing costs.

[0191] Subsequently, the insulating film 118 is formed as a second barrier film over the insulating film 116 (see Fig. 5A).

[0192] When a PECVD method is used to form the insulating film 118, the substrate temperature is lower than 400°C, preferably lower than 375°C, more preferably higher than or equal to 150°C and lower than 360°C, even more preferably higher than or equal to 350°C and lower than 360°C; in this case, a dense insulating film 118 can be formed. Note that if the substrate temperature during the formation of the insulating film 118 is within any of the above ranges, the heat treatment at the second temperature after the formation of the first barrier film 131 can be omitted.

[0193] For example, in the case where a silicon nitride film is formed as the insulating film 118 by a PECVD method, a deposition gas containing silicon, nitrogen, and ammonia are preferably used as the source gas. The amount of ammonia is smaller compared to the amount of nitrogen, whereby ammonia is dissociated in the plasma and activated species are generated. The activated species cleave a bond between silicon and hydrogen contained in a deposition gas containing silicon, as well as a triple bond between nitrogen molecules. As a result, a dense silicon nitride film can be formed that has few defects, in which bonds between silicon and nitrogen are promoted and bonds between silicon and hydrogen are few.On the other hand, when the amount of ammonia is large relative to the amount of nitrogen, the decomposition of a deposition gas containing silicon and the decomposition of nitrogen are not promoted, resulting in the formation of a leaky or coarse silicon nitride film in which bonds between silicon and hydrogen remain and defects proliferate. Therefore, the flow rate ratio of nitrogen to ammonia in the source gas is set to be greater than or equal to 5:1 and less than or equal to 50:1, preferably greater than or equal to 10:1 and less than or equal to 50:1.

[0194] In this embodiment, a 50 nm thick silicon nitride film is formed as the insulating film 118 using a PECVD apparatus, with silane, nitrogen, and ammonia used as source gases. The silane flow rate is 50 sccm, the nitrogen flow rate is 5000 sccm, and the ammonia flow rate is 100 sccm. The pressure in the treatment chamber is 100 Pa, the substrate temperature is 350°C, and a high-frequency power of 1000 W is supplied to parallel plate electrodes using a 27.12 MHz high-frequency power source. Note that the PECVD apparatus is a parallel-plate PECVD apparatus, with an electrode area of ​​6000 cm 2 and where the power per unit area (power density), into which the supplied power is converted, is 1.7 × 10 -1 W / cm 2 amounts.

[0195] Note that a heat treatment may be performed after the insulating film 118 serving as a second barrier film is formed. By performing the heat treatment at the second temperature before forming the insulating film 118 or by performing the heat treatment after forming the insulating film 118, the excess oxygen or oxygen radicals contained in the insulating film 116 can diffuse into the oxide semiconductor film 108 to fill oxygen vacancies in the oxide semiconductor film 108. Alternatively, the insulating film 118 may be formed while performing a heat treatment, so that the oxygen radicals or excess oxygen contained in the insulating film 116 can diffuse into the oxide semiconductor film 108 to fill oxygen vacancies in the oxide semiconductor film 108.

[0196] Through the above process, the transistor 100, which is in Fig. 5B. <Verfahren 2 zum Herstellen der Halbleitervorrichtung>

[0197] Next, a method of manufacturing the transistor 100, which is different from the manufacturing method described by Fig. 1A to Fig. 1C, Fig. 2A to Fig. 2C, Fig. 3A to Fig. 3C, Fig. 4A to Fig. 4C and Fig. 5A, is described below.

[0198] First, as with the<Verfahren 1 zum Herstellen der Halbleitervorrichtung> , the steps described in Fig. 1A to Fig. 1C, Fig. 2A to Fig. 2C and Fig. 3A to Fig. 3C. The Fig. 4A to 4C and Fig. 5A are not subsequently carried out. In other words, the structure shown in Fig. 3C has a function similar to that of transistor 100 shown in Fig. 5B and Fig. 5C is similar.

[0199] In the case where the steps described in Fig. 4A to Fig. 4C and Fig. 5A are not performed, a metal oxide film is used for the first barrier film 131 in the structure shown in Fig. 3C; the metal oxide film is preferably deposited in the form of aluminum oxide, hafnium oxide, or yttrium oxide.

[0200] When aluminum oxide, hafnium oxide, or yttrium oxide is deposited as the first barrier film 131 by a sputtering method, a sputtering gas preferably contains at least oxygen. In plasma, oxygen for the sputtering gas for forming the first barrier film 131 sometimes becomes oxygen radicals, and the oxygen and / or oxygen radicals may be added to the insulating film 116. In this case, the step of adding oxygen 140 described in Fig. 4A can be omitted. That is, the step of forming the first barrier film 131 can also serve as an oxygen addition treatment. The first barrier film 131 has a function of adding oxygen during its formation (particularly in the initial stage of deposition); whereas it has a function of blocking oxygen after its formation.

[0201] In the case where aluminum oxide is deposited by a sputtering method as the first barrier film 131, in some cases, a mixture layer is formed near the interface between the insulating film 116 and the first barrier film 131. When the insulating film 116 is a silicon oxynitride film, in some cases, Al x Si y O z formed as a mixed layer.

[0202] In the case where aluminum oxide, hafnium oxide or yttrium oxide is used for the first barrier film 131, neither the step of removing the first barrier film 131 described in Fig. 4C, nor the step of forming the insulating film 118 shown in Fig. 5A, because aluminum oxide, hafnium oxide, and yttrium oxide have high insulating properties and high oxygen barrier properties. Thus, the first barrier film 131 has the same function as the insulating film 118.

[0203] Note that the first barrier film 131 is formed while performing a heat treatment at a substrate temperature lower than 400°C (i.e., the second temperature), whereby excess oxygen or oxygen radicals added to the insulating film 116 can diffuse into the oxide semiconductor film 108. Alternatively, a heat treatment is performed after forming the first barrier film 131 at the second temperature lower than 400°C, whereby excess oxygen or oxygen radicals added to the insulating film 116 can diffuse into the oxide semiconductor film 108.

[0204] By using aluminum oxide, hafnium oxide, or yttrium oxide for the first barrier film 131, the manufacturing process of the semiconductor device can be shortened, thereby saving manufacturing costs. <Verfahren 3 zum Herstellen der Halbleitervorrichtung>

[0205] Next, a method of manufacturing the transistor 170, which is an embodiment of the present invention, will be described with reference to Fig. 7A to Fig. 7C described. Fig. 7A to Fig. 7C are cross-sectional views illustrating the method of manufacturing the semiconductor device. Fig. 7A to Fig. 7C show a cross-sectional view along the dashed line X1-X2 and a cross-sectional view along the dashed line Y1-Y2 on the left and right sides, respectively.

[0206] First, steps are performed that are similar to those of the manufacturing process of the transistor 100 (the steps described in Fig. 1A to Fig. 1C, Fig. 2A to Fig. 2C, Fig. 3A to Fig. 3C, Fig. 4A to Fig. 4C and Fig. 5A) that has been described above.

[0207] Next, a mask is formed over the insulating film 118 by a lithography process, and the opening 142c is formed in a desired region of the insulating films 114, 116, and 118. Furthermore, a mask is formed over the insulating film 118 by a lithography process, and the openings 142a and 142b are formed in desired regions of the insulating films 106, 107, 114, 116, and 118. Note that the opening 142c extends to the conductive film 112b. The openings 142a and 142b extend to the conductive film 104 (see Fig. 7A).

[0208] Note that the openings 142a and 142b and the opening 142c can be formed either in the same step or in different steps. In the case where the openings 142a and 142b and the opening 142c are formed in the same step, for example, a grayscale mask or a halftone mask can be used. Furthermore, the openings 142a and 142b can be formed in several steps. For example, the insulating films 106 and 107 are processed, and then the insulating films 114, 116, and 118 are processed.

[0209] Next, a conductive film 120 is formed over the insulating film 118 so as to cover the openings 142a, 142b and 142c (see Fig. 7B).

[0210] For example, a material containing one of indium (In), zinc (Zn), and tin (Sn) can be used for the conductive film 120. Specifically, the conductive film 120 can be formed using a light-transmitting conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (ITO), indium zinc oxide, or indium tin oxide to which silicon oxide has been added (ITSO). The conductive film 120 can be formed, for example, by a sputtering method. In this embodiment, a 110 nm thick ITSO film is formed by a sputtering method.

[0211] Next, a mask is formed over the conductive film 120 by a lithography process, and the conductive film 120 is processed into a required shape to form the conductive films 120a and 120b (see Fig. 7C).

[0212] For example, a dry etching process, a wet etching process, or a combination of a dry etching process and a wet etching process is used to form the conductive films 120a and 120b. A wet etching process is used in this embodiment to process the conductive film 120 into the conductive films 120a and 120b.

[0213] Through the above process, the transistor 170, which is in Fig. 6A and Fig. 6B.

[0214] The structures and methods described in this embodiment may be implemented in any suitable combination with any other structures and methods described in the other embodiments. (Embodiment 2)

[0215] In this embodiment, the structure of an oxide semiconductor film included in a semiconductor device of one embodiment of the present invention will be described in detail. <Struktur des Oxidhalbleiters>

[0216] An oxide semiconductor is classified into a single-crystalline oxide semiconductor and a non-single-crystalline oxide semiconductor. Examples of a non-single-crystalline oxide semiconductor include a c-axis aligned crystalline oxide semiconductor (CAAC-OS), a polycrystalline oxide semiconductor, a nanocrystalline oxide semiconductor (nc-OS), an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor.

[0217] From another perspective, an oxide semiconductor is divided into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Examples of a crystalline oxide semiconductor include a single-crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.

[0218] It is known that an amorphous structure is generally defined as follows: it is metastable, unpinned, isotropic, and does not exhibit a non-uniform structure. In other words, an amorphous structure exhibits a flexible bond angle and short-range but no long-range order.

[0219] This means that a fundamentally stable oxide semiconductor cannot be considered a completely amorphous oxide semiconductor. Furthermore, an oxide semiconductor that is not isotropic (e.g., an oxide semiconductor that exhibits a regular structure at a microscopic level) cannot be considered a completely amorphous oxide semiconductor. Note that an a-like oxide semiconductor, although it exhibits a regular structure at a microscopic level, simultaneously contains a void and exhibits an unstable structure. Therefore, an a-like oxide semiconductor exhibits physical properties similar to those of an amorphous oxide semiconductor. <caac-os>

[0220] First, a CAAC-OS is described.

[0221] A CAAC-OS is one of the oxide semiconductors that have a large number of crystal parts aligned with respect to the c-axis (also called pellets).

[0222] In a combined analysis image (also called a high-resolution TEM image) of a CAAC-OS obtained with a transmission electron microscope (TEM), a multitude of pellets can be observed. However, a boundary between pellets, i.e., a grain boundary, is not clearly observed in the high-resolution TEM image. Consequently, a reduction in electron mobility due to the grain boundary is less likely to occur in the CAAC-OS.

[0223] A CAAC-OS observed with a TEM is described below. Fig. Figure 10A shows a high-resolution TEM image of a cross-section of the CAAC-OS viewed in a direction substantially parallel to the sample surface. The high-resolution TEM image is obtained using a spherical aberration correction function. Specifically, the high-resolution TEM image obtained using a spherical aberration correction function is referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be acquired, for example, using a JEM-ARM200F atomic resolution analytical electron microscope manufactured by JEOL Ltd.

[0224] Fig. Figure 10B is an enlarged Cs-corrected high-resolution TEM image of an area (1) in Fig. 10A. Fig. Figure 10B shows that metal atoms are arranged in a layered manner in a pellet. Each metal atom layer has a configuration that reflects an unevenness of a surface over which the CAAC-OS is formed (hereinafter referred to as a formation surface) or a top surface of the CAAC-OS, and each metal atom layer is arranged parallel to the formation surface or the top surface of the CAAC-OS.

[0225] The CAAC-OS indicates, as in Fig. 10B, has a characteristic atomic arrangement. The characteristic atomic arrangement is indicated by an auxiliary line in Fig. 10C. Fig. 10B and Fig. Figure 10C demonstrates that the size of a pellet is greater than or equal to 1 nm or greater than or equal to 3 nm, and that the size of a space created by the tilting pellets is approximately 0.8 nm. Therefore, the pellet can also be referred to as a nanocrystal (nc). Note that the CAAC-OS can also be referred to as an oxide semiconductor containing c-axis aligned nanocrystals (CANC).

[0226] According to the Cs-corrected high-resolution TEM images, the schematic arrangement of pellets 5100 of a CAAC-OS over a substrate 5120 is shown here as such a structure in which bricks or blocks are arranged one on top of the other (see Fig. 10D). The part in which, as in Fig. 10C observed, the pellets tend, corresponds to an area 5161, which in Fig. 10D is shown.

[0227] Fig. Figure 11A shows a Cs-corrected high-resolution TEM image of a plane of the CAAC-OS viewed in a direction substantially perpendicular to the sample surface. Fig. 11B, Fig. 11C and Fig. 11D are enlarged Cs-corrected high-resolution TEM images of the respective areas (1), (2) and (3) in Fig. 11A. Fig. 11B, Fig. 11C and Fig. Figure 11D indicates that metal atoms are arranged in a triangular, quadrangular, or hexagonal configuration within a pellet. However, there is no regularity in the arrangement of the metal atoms between different pellets.

[0228] Next, a CAAC-OS analyzed by X-ray diffraction (XRD) is described. For example, when the structure of a CAAC-OS containing an InGaZnO4 crystal is analyzed by an out-of-plane method, a peak appears at a diffraction angle (2θ) of approximately 31°, as shown in Fig. 12A. This peak originates from the (009) plane of the InGaZnO4 crystal, indicating that crystals in the CAAC-OS have c-axis alignment and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or top of the CAAC-OS.

[0229] It should be noted that in the structure analysis of CAAC-OS by an out-of-plane method, in addition to the peak at 2θ of approximately 31°, another peak may appear when 2θ is approximately 36°. The peak at 2θ of approximately 36° indicates that a crystal without c-axis orientation is contained in a portion of the CAAC-OS. It is preferred that in the CAAC-OS analyzed by an out-of-plane method, a peak appears when 2θ is approximately 31°, but no peak appears when 2θ is approximately 36°.

[0230] On the other hand, in a structural analysis of the CAAC-OS by an in-plane method, in which an X-ray beam is incident on a sample in a direction substantially perpendicular to the c-axis, a peak appears when 2θ is approximately 56°. This peak originates from the (110) plane of the InGaZnO4 crystal. In the case of the CAAC-OS, as shown in Fig. 12B, no clear peak is observed when an analysis (ϕ-scan) is performed with 2θ set to approximately 56° and the sample rotated around a normal vector of the sample surface as the axis (ϕ-axis). In contrast, in the case of a single-crystal InGaZnO4 oxide semiconductor, as shown in Fig. As shown in Figure 12C, six peaks originating from the crystal planes corresponding to the (110) plane are observed when a ϕ scan is performed with 2θ set to approximately 56°. Accordingly, XRD structural analysis reveals that the a-axis and b-axis directions in the CAAC-OS are irregularly aligned.

[0231] Next, a CAAC-OS analyzed by electron diffraction is described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS with an InGaZnO4 crystal in a direction parallel to the sample surface, a Fig. 13A. This diffraction pattern (also referred to as a selected-area transmission electron diffraction pattern) shows points originating from the (009) plane of an InGaZnO4 crystal. Therefore, the electron diffraction also indicates that pellets contained in the CAAC-OS have an orientation with respect to the c-axis and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS. Meanwhile, Fig. 13B shows a diffraction pattern obtained by irradiating an electron beam with a probe diameter of 300 nm onto the same sample in a direction perpendicular to the sample surface. As in Fig. As shown in Figure 13B, a ring-shaped diffraction pattern is observed. Therefore, the electron diffraction also indicates that the a-axes and b-axes of the pellets contained in the CAAC-OS do not have a regular alignment. It is assumed that the first ring in Fig. 13B originates from the (010) plane, the (100) plane, and the like of the InGaZnO4 crystal. It is further assumed that the second ring in Fig. 13B comes from the (110) plane and the like.

[0232] As described above, CAAC-OS is a high-crystallinity oxide semiconductor. The ingress of impurities, the formation of defects, or the like could reduce the crystallinity of an oxide semiconductor. This means that CAAC-OS has only a small number of impurities and defects (e.g., oxygen vacancies).

[0233] Note that an impurity refers to an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element (especially silicon or the like) that has a higher bonding strength with oxygen than a metal element contained in an oxide semiconductor will extract oxygen from the oxide semiconductor, resulting in disorder of the atomic arrangement and reduced crystallinity of the oxide semiconductor. A heavy metal, such as iron or nickel, argon, carbon dioxide, or the like, has a large atomic radius (or molecular radius) and therefore disrupts the atomic arrangement of the oxide semiconductor and reduces crystallinity.

[0234] The properties of an oxide semiconductor containing impurities or defects could be altered by light, heat, or the like. Impurities contained in the oxide semiconductor could, for example, serve as charge carrier traps or charge carrier generation sources. Furthermore, oxygen vacancies in the oxide semiconductor serve as charge carrier traps or charge carrier generation sources when hydrogen is trapped therein.

[0235] A CAAC-OS, which contains only a small amount of impurities and oxygen vacancies, is an oxide semiconductor with a low carrier density. Such an oxide semiconductor is referred to as a high-purity intrinsic or essentially high-purity intrinsic oxide semiconductor. A CAAC-OS exhibits a low impurity concentration and a low density of defect states. Therefore, a CAAC-OS can be described as an oxide semiconductor with stable properties. <nc-os>

[0236] Next, an nc-OS is described.

[0237] In a high-resolution TEM image, an nc-OS has a region where a crystal part is observed and a region where a crystal part is not clearly observed. In most cases, the size of a crystal part included in the nc-OS is greater than or equal to 1 nm and less than or equal to 10 nm, or greater than or equal to 1 nm. Note that an oxide semiconductor having a crystal part whose size is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor. For example, in a high-resolution TEM image of the nc-OS, a grain boundary is not clearly observed in some cases. Note that there is a possibility that the origin of the nanocrystal is similar to that of a pellet in a CAAC-OS. Therefore, a crystal part of the nc-OS may be referred to as a pellet in the following description.

[0238] In the nc-OS, a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, particularly a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) exhibits a regular atomic arrangement. There is no regularity in the crystal alignment between different pellets in the nc-OS. Consequently, the alignment of the entire film is not observed. Therefore, depending on an analysis method, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor. For example, when the nc-OS is analyzed by an out-of-plane method using an X-ray beam with a diameter larger than the size of a pellet, no peak showing a crystal plane appears.In addition, a halo pattern-like diffraction pattern is observed when the nc-OS is subjected to electron diffraction using an electron beam with a probing diameter (e.g., 50 nm or larger) larger than the size of a pellet. Meanwhile, spots appear in a nanobeam electron diffraction pattern of the nc-OS when an electron beam with a probing diameter close to or smaller than the size of a pellet is used. In addition, in a nanobeam electron diffraction pattern of the nc-OS, high-luminance regions in a circular (ring) shape are sometimes shown. In a nanobeam electron diffraction pattern of the nc-OS, a plurality of spots in a ring-shaped region are also sometimes shown.

[0239] Since, as previously described, there is no regularity of crystal alignment between the pellets (nanocrystals), the nc-OS can also be referred to as an oxide semiconductor containing randomly aligned nanocrystals (RANC) or as an oxide semiconductor containing non-aligned nanocrystals (NANC).

[0240] The nc-OS is an oxide semiconductor that exhibits a high degree of regularity compared to an amorphous oxide semiconductor. Therefore, the nc-OS is likely to exhibit a lower density of defect states than an amorphous oxide semiconductor and an amorphous oxide semiconductor. Note that there is no regularity in the crystal alignment between different pellets in the nc-OS. Therefore, the nc-OS exhibits a higher density of defect states than the CAAC-OS. <a-ähnlicher OS>

[0241] An a-like OS has a structure that lies between that of the nc-OS and that of the amorphous oxide semiconductor.

[0242] In a high-resolution TEM image of the a-like OS, a void can be observed. Furthermore, in the high-resolution TEM image, there is an area where a crystal fragment is clearly observed and an area where no crystal fragment is observed.

[0243] The a-like OS exhibits an unstable structure because it contains a cavity. To demonstrate that an a-like OS exhibits an unstable structure compared to a CAAC-OS and an nc-OS, a structural change induced by electron irradiation is described below.

[0244] An a-like OS (referred to as Sample A), an nc-OS (referred to as Sample B), and a CAAC-OS (referred to as Sample C) are prepared as samples subjected to electron irradiation. Each of the samples is an In-Ga-Zn oxide.

[0245] First, a high-resolution cross-sectional TEM image of each sample is obtained. The high-resolution cross-sectional TEM images show that all samples contain crystal fragments.

[0246] It should be noted that the determination of which part is considered a crystal part is as follows. It is known that a unit cell of InGaZnO4 crystal has a structure in which nine layers, namely three In-O layers and six Ga-Zn-O layers, are stacked in the c-axis direction. The distance between adjacent layers is equal to the lattice spacing (also called the d value) on the (009) plane. This value is calculated from crystal structure analysis to be 0.29 nm. Therefore, a portion in which the lattice spacing between lattice fringes is greater than or equal to 0.28 nm and less than or equal to 0.30 nm is considered a crystal part of InGaZnO4. Each lattice fringes corresponds to the ab plane of the InGaZnO4 crystal.

[0247] Fig. Figure 14 shows the change in the average size of crystal fragments (at points 22 to 45) in each sample. Note that the size of a crystal fragment corresponds to the length of a lattice edge zone. Fig. 14 indicates that the size of a crystal part in the a-like OS increases with the increase of the cumulative electron dose. In particular, as in (1) in Fig. 14, a crystal part measuring approximately 1.2 nm at the beginning of the TEM observation (the crystal part is also called the initial nucleus) shrinks to a size of approximately 2.6 nm at a cumulative electron dose of 4.2 × 10 8 e - / nm 2 In contrast, the size of a crystal fragment in the nc-OS and the CAAC-OS changes only slightly from the beginning of electron irradiation up to a cumulative electron dose of 4.2 × 10 8 e - / nm 2 . In particular, as in (2) and (3) in Fig. As shown in Figure 14, the average crystal sizes in an nc-OS and a CAAC-OS are approximately 1.4 nm and approximately 2.1 nm, respectively, independent of the cumulative electron dose.

[0248] Thus, the growth of the crystal part in the a-like OS is stimulated by electron irradiation. In contrast, in the nc-OS and the CAAC-OS, the growth of the crystal part is hardly stimulated by electron irradiation. Therefore, the a-like OS exhibits an unstable structure compared to the nc-OS and the CAAC-OS.

[0249] The a-like OS has a lower density than the nc-OS and the CAAC-OS because it includes a void. Specifically, the density of the a-like OS is higher than or equal to 78.6% and lower than 92.3% of the density of the single-crystal oxide semiconductor with the same composition. The density of the nc-OS and that of the CAAC-OS are, respectively, higher than or equal to 92.3% and lower than 100% of the density of the single-crystal oxide semiconductor with the same composition. Note that it is difficult to deposit an oxide semiconductor with a density lower than 78% of the single-crystal oxide semiconductor.

[0250] For example, in the case of an oxide semiconductor with an atomic ratio of In:Ga:Zn = 1:1:1, the density of single-crystal InGaZnO4 with a rhombohedral crystal structure is 6.357 g / cm 3 Accordingly, in the case of the oxide semiconductor with an atomic ratio of In:Ga:Zn = 1:1:1, the density of the a-like OS is higher than or equal to 5.0 g / cm 3 and lower than 5.9 g / cm 3 . For example, in the case of the oxide semiconductor with an atomic ratio of In:Ga:Zn = 1:1:1, the density of the nc-OS and that of the CAAC-OS are each higher than or equal to 5.9 g / cm 3 and lower than 6.3 g / cm 3 .

[0251] It should be noted that there is a possibility that an oxide semiconductor with a certain composition cannot exist in a single-crystal structure. In this case, single-crystal oxide semiconductors with different compositions are combined in an appropriate ratio, which makes it possible to calculate the density corresponding to that of a single-crystal oxide semiconductor with the desired composition. The density of a single-crystal oxide semiconductor with the desired composition can be calculated from a weighted average according to the combination ratio of single-crystal oxide semiconductors with different compositions. It should be noted that it is preferable to use as few types of single-crystal oxide semiconductors as possible for calculating the density.

[0252] As described above, oxide semiconductors have various structures and different properties. It should be noted that an oxide semiconductor may be a layered arrangement comprising, for example, two or more of the following oxide semiconductors: an amorphous oxide semiconductor, an a-like oxide semiconductor, an nc-oxide semiconductor, and a CAAC-oxide semiconductor. <abscheidungsmodell>

[0253] Examples of deposition models of a CAAC-OS and an nc-OS are described below.

[0254] Fig. Figure 15A is a schematic diagram of the interior of a deposition chamber in which a CAAC-OS is deposited by a sputtering process.

[0255] A target 5130 is mounted on a backing plate. A plurality of magnets are provided facing the target 5130 with the backing plate sandwiched between them. The plurality of magnets generate a magnetic field. For the arrangement and structure of the magnets, refer to the above description of the deposition chamber. A sputtering method in which the deposition rate is increased using a magnetic field of magnets is called a magnetron sputtering method.

[0256] The target 5130 has a polycrystalline structure in which a cleavage plane is present in at least one crystal grain.

[0257] As an example, a cleavage plane of the target 5130, which contains an In-Ga-Zn oxide, is described. Fig. Figure 16A shows a structure of an InGaZnO4 crystal contained in the target 5130. It should be noted that Fig. Figure 16A shows a structure of the case where an InGaZnO4 crystal is observed from a direction parallel to the b-axis with the c-axis directed upwards.

[0258] Fig. Figure 16A shows that oxygen atoms in one Ga-Zn-O layer are positioned close to those in a neighboring Ga-Zn-O layer. The oxygen atoms have a negative electrical charge; therefore, the two Ga-Zn-O layers repel each other. As a result, the InGaZnO4 crystal exhibits a cleavage plane between the two neighboring Ga-Zn-O layers.

[0259] A substrate 5120 is placed facing the target 5130, and the distance d (also referred to as the target-substrate distance (TS distance)) is greater than or equal to 0.01 m and less than or equal to 1 m, preferably greater than or equal to 0.02 m and less than or equal to 0.5 m. The deposition chamber is mostly filled with a deposition gas (e.g., an oxygen gas, an argon gas, or a gas mixture containing 5 vol% or more oxygen), and the pressure in the deposition chamber is set to be higher than or equal to 0.01 Pa and lower than or equal to 100 Pa, preferably higher than or equal to 0.1 Pa and lower than or equal to 10 Pa. Here, a discharge starts by applying a voltage of a certain value or higher to the target 5130, and a plasma is observed. The magnetic field forms a high-density plasma region near the target 5130.In the high-density plasma region, the deposition gas is ionized to produce an ion 5101. Examples of the ion 5101 include an oxygen cation (O + ) and an argon cation (Ar + ).

[0260] The ion 5101 is accelerated toward the target 5130 by an electric field and then collides with the target 5130. In the process, a pellet 5100a and a pellet 5100b, which are flat, plate-shaped (pellet-shaped) sputtered particles, are separated from the cleavage plane and sputtered. Note that the structures of the pellet 5100a and the pellet 5100b may be distorted by the force of the collision of the ion 5101.

[0261] The pellet 5100a is a flat, plate-shaped (pellet-shaped) sputtered particle having a triangular plane, for example, a plane in the shape of an equilateral triangle. The pellet 5100b is a flat, plate-shaped (pellet-shaped) sputtered particle having a hexagonal plane, for example, a plane in the shape of an equilateral hexagon. Note that flat, plate-shaped (pellet-shaped) sputtered particles, such as the pellet 5100a and the pellet 5100b, are collectively referred to as pellets 5100. The shape of a flat plane of the pellet 5100 is not limited to a triangle or a hexagon. The flat plane may, for example, have a shape formed by combining two or more triangles. For example, a quadrilateral (e.g., rhombus) is formed by combining two triangles (e.g., equilateral triangles).

[0262] The thickness of the pellet 5100 is determined depending on the type of deposition gas and the like. The thicknesses of the pellets 5100 are preferably uniform; the reason for this will be described later. In addition, for the sputtered particle, a pellet shape with a small thickness is preferred over a cube shape with a large thickness. The thickness of the pellet 5100 is, for example, greater than or equal to 0.4 nm and less than or equal to 1 nm, preferably greater than or equal to 0.6 nm and less than or equal to 0.8 nm. In addition, the width of the pellet 5100 is, for example, greater than or equal to 1 nm. The pellet 5100 corresponds to the initial core in the description of (1) in Fig. 14. For example, in the case where the ion 5101 collides with the target 5130 containing an In-Ga-Zn oxide, the pellet 5100 is knocked out, which contains three layers, namely a Ga-Zn-O layer, an In-O layer and a Ga-Zn-O layer, as shown in Fig. 16B. It should be noted that Fig. Figure 16C shows the structure of pellet 5100 viewed from a direction parallel to the c-axis. Pellet 5100 therefore has a nanometer-sized sandwich structure, or layered structure, containing two Ga-Zn-O layers (bread slices) and one In-O layer (filling).

[0263] The pellet 5100 absorbs a charge as it passes through the plasma, so that its side surfaces become negatively or positively charged in some cases. The pellet 5100 includes an oxygen atom on its side surface, and the oxygen atom can be negatively charged. When the side surfaces are charged with the same polarity in this way, charges repel each other, and consequently, the pellet 5100 can maintain the shape of a flat plate. In the case of a CAAC-OS, an In-Ga-Zn oxide, there is a possibility that an oxygen atom bonded to an indium atom becomes negatively charged. Another possibility is that an oxygen atom bonded to an indium atom, a gallium atom, or a zinc atom becomes negatively charged. In addition, the pellet 5100 can grow by bonding to an indium atom, a gallium atom, a zinc atom, an oxygen atom, or the like as it passes through the plasma.This is one reason for a size difference between (2) and (1) in . Fig. 14. In the case where the temperature of the substrate 5120 is around room temperature, the pellet 5100 no longer grows; therefore, an nc-OS is formed (see Fig. 15B). An nc-OS can be deposited when the substrate 5120 has a large size because the deposition of an nc-OS is performed at room temperature. Note that it is effective to increase the deposition power during sputtering to allow the pellet 5100 to grow in the plasma. High deposition power can stabilize the structure of the pellet 5100.

[0264] As in Fig. 15A and Fig. As shown in Figure 15B, the pellet 5100 flies in the plasma like a kite and flutters toward the substrate 5120. Since the pellets 5100 are charged, repulsion is caused when the pellet 5100 approaches an area where another pellet 5100 has already been deposited. Here, a magnetic field in a direction parallel to the upward-facing surface of the substrate 5120 (also called a horizontal magnetic field) is generated above the substrate 5120. A potential difference is created between the substrate 5120 and the target 5130, and consequently, a current flows from the substrate 5120 to the target 5130. In this way, a force (Lorentz force) is imparted to the pellet 5100 on the upper surface of the substrate 5120 by an effect of the magnetic field and the current. This can be explained by Fleming's left-hand rule.

[0265] The mass of the pellet 5100 is greater than that of an atom. Therefore, to move the pellet 5100 above the upper surface of the substrate 5120, it is important to apply some external force to the pellet 5100. One type of force may be a force generated by the action of a magnetic field and a current. To increase the force applied to the pellet 5100, it is preferable to provide a region on the upper surface where the magnetic field in a direction parallel to the upper surface of the substrate 5120 is 10 G or higher, preferably 20 G or higher, more preferably 30 G or higher, and even more preferably 50 G or higher.Alternatively, a region in which the magnetic field in a direction parallel to the top surface of the substrate 5120 is 1.5 times or more, preferably twice or more, more preferably three times or more, even more preferably five times or more as high as the magnetic field in a direction perpendicular to the top surface of the substrate 5120 is preferably provided on the top surface.

[0266] In this process, magnet units and / or the substrate 5120 are moved or rotated relative to each other, constantly changing the direction of the horizontal magnetic field on the top side of the substrate 5120. The pellet 5100 can therefore move in different directions on the top side of the substrate 5120 by absorbing forces in different directions.

[0267] In addition, as in Fig. As shown in Figure 15A, the resistance between the pellet 5100 and the substrate 5120 is low due to friction or the like when the substrate 5120 is heated. As a result, the pellet 5100 slides above the top surface of the substrate 5120. The sliding of the pellet 5100 occurs in a state where its flat surface faces the substrate 5120. When the pellet 5100 reaches the side surface of another pellet 5100 that has already been deposited, the side surfaces of the pellets 5100 are then bonded. At this time, the oxygen atom on the side surface of the pellet 5100 is released. With the released oxygen atom, oxygen vacancies in a CAAC-OS are filled in some cases; therefore, the CAAC-OS has a low density of defect states.Note that the temperature of the upper surface of the substrate 5120 is, for example, higher than or equal to 100°C and lower than 500°C, higher than or equal to 150°C and lower than 450°C, higher than or equal to 170°C and lower than 400°C, or higher than or equal to 170°C and lower than 350°C. Therefore, it is possible to deposit a CAAC-OS even when the substrate 5120 has a large size.

[0268] Furthermore, the pellet 5100 on the substrate 5120 is heated, thereby rearranging atoms, and the structural distortion caused by the collision of the ion 5101 can be reduced. The pellet 5100 whose structural distortion has been reduced is essentially single-crystalline. Even if the pellets 5100 are heated after being bonded, expansion and contraction of the pellet 5100 itself, which are caused by the pellet 5100 becoming essentially single-crystalline, hardly occur. In this way, defects such as a grain boundary can be prevented from forming due to expansion of a space between the pellets 5100, and thus the generation of gaps can be prevented.

[0269] The CAAC-OS does not have a plate-like structure of a single-crystal oxide semiconductor, but rather an arrangement of a group of 5100 pellets (nanocrystals) like stacked bricks or blocks. Furthermore, there is no grain boundary between them. Therefore, local stress can be alleviated or distortion can be relaxed even if deformation of the CAAC-OS, such as shrinkage, occurs due to heating during deposition, heating, or bending after deposition. Therefore, this structure is suitable for a flexible semiconductor device. Note that the nc-OS has an arrangement in which 5100 pellets (nanocrystals) are randomly stacked.

[0270] When the target is bombarded with an ion, zinc oxide or the like may be ejected in addition to the pellets. The zinc oxide is lighter than the pellet and therefore reaches the top of the substrate 5120 sooner than the pellet. As a result, the zinc oxide forms a zinc oxide layer 5102 with a thickness of greater than or equal to 0.1 nm and less than or equal to 10 nm, greater than or equal to 0.2 nm and less than or equal to 5 nm, or greater than or equal to 0.5 nm and less than or equal to 2 nm. Fig. 17A to Fig. 17D are schematic cross-sectional views.

[0271] As in Fig. As shown in Figure 17A, a pellet 5105a and a pellet 5105b are deposited over the zinc oxide layer 5102. Here, side surfaces of the pellet 5105a and the pellet 5105b are in contact with each other. Furthermore, a pellet 5105c is deposited over the pellet 5105b and then slides over the pellet 5105b. Furthermore, a plurality of particles 5103, which are knocked out from the target together with the zinc oxide, are crystallized by heating the substrate 5120 to form a region 5105a1 on another side surface of the pellet 5105a. Note that the plurality of particles 5103 may contain oxygen, zinc, indium, gallium, or the like.

[0272] As in Fig. 17B, ​​the region 5105a1 then grows into a part of the pellet 5105a to form a pellet 5105a2. One side surface of the pellet 5105c is also in contact with another side surface of the pellet 5105b.

[0273] Next, as in Fig. As shown in Figure 17C, a pellet 5105d is deposited over the pellet 5105a2 and the pellet 5105b, and then slides over the pellet 5105a2 and the pellet 5105b. Furthermore, a pellet 5105e slides to another side surface of the pellet 5105c over the zinc oxide layer 5102.

[0274] As in Fig. 17D, the pellet 5105d is then placed such that one side surface of the pellet 5105d is in contact with one side surface of the pellet 5105a2. One side surface of the pellet 5105e is also in contact with another side surface of the pellet 5105c. A plurality of particles 5103, which are knocked out from the target along with the zinc oxide, are crystallized by heating the substrate 5120 to form a region 5105d1 on another side surface of the pellet 5105d.

[0275] As described above, deposited pellets are placed in contact with each other, and then crystal growth is caused on side surfaces of the pellets, thereby forming a CAAC-OS over the substrate 5120. Each pellet of the CAAC-OS is therefore larger than that of the nc-OS. This is one reason for a size difference between (3) and (2) in Fig. 14.

[0276] When gaps between pellets 5100 are very small, the pellets can form a large pellet. The large pellet has a single-crystal structure. The size of the large pellet, as viewed from the top, can be, for example, greater than or equal to 10 nm and less than or equal to 200 nm, greater than or equal to 15 nm and less than or equal to 100 nm, or greater than or equal to 20 nm and less than or equal to 50 nm. Therefore, when a channel formation region of a transistor is smaller than the large pellet, the region with a single-crystal structure can be used as the channel formation region. Moreover, when the size of the pellet is increased, the region with a single-crystal structure can be used as the channel formation region, source region, and drain region of the transistor.

[0277] In this way, when the channel formation region or the like of the transistor is formed in a region having a single-crystal structure, the frequency characteristics of the transistor can be improved in some cases.

[0278] As shown in such a model, it is assumed that the pellets 5100 are deposited on the substrate 5120. Therefore, a CAAC-OS can be deposited even if a formation surface does not have a crystal structure; this is different from film deposition by epitaxial growth. For example, a CAAC-OS can be formed even if the top surface (formation surface) of the substrate 5120 has an amorphous structure (e.g., even if the top surface is formed of amorphous silicon oxide).

[0279] In addition, it has been found that when forming the CAAC-OS, the pellets 5100 are arranged according to the shape of the upper surface of the substrate 5120, which is the formation surface, even if the formation surface has unevenness. For example, in the case where the surface of the substrate 5120 is flat at the atomic level, the pellets 5100 are arranged such that flat planes parallel to the ab plane face downward; thus, a layer with a uniform thickness, flatness, and high crystallinity is formed. By stacking n layers (n is a natural number), the CAAC-OS can be obtained.

[0280] In the case where the upper surface of the substrate 5120 has unevenness, a CAAC-OS is formed in which n layers (n is a natural number) are stacked, in which the pellets 5100 are each arranged along the convex surface. Since the substrate 5120 has unevenness, a gap is easily formed between the pellets 5100 in the CAAC-OS in some cases. Note that the pellets 5100 arrange themselves by intermolecular force such that a gap between the pellets is as small as possible even on the uneven surface. Therefore, a CAAC-OS with high crystallinity can be obtained even if the formation surface has unevenness.

[0281] Consequently, no laser crystallization is required to form a CAAC-OS, and a uniform film can be formed even over a large glass substrate.

[0282] Since a CAAC-OS is deposited according to such a model, the sputtered particle preferably has a pellet shape with a small thickness. Note that when the sputtered particles have a cube shape with a large thickness, the planes facing the substrate 5120 vary; therefore, the thicknesses and orientations of the crystals may not be uniform in some cases.

[0283] According to the deposition model described above, a CAAC-OS with high crystallinity can be formed even on a formation surface with an amorphous structure.

[0284] The structures described in this embodiment may be used in appropriate combination with any of the structures described in the other embodiments. (Embodiment 3)

[0285] In this embodiment, an example of a display device including one of the transistors described in the above embodiments will be described below with reference to Fig. 18, Fig. 19 and Fig. 20 described.

[0286] Fig. 18 is a plan view of an example of a display device. Fig. The display device 700 shown in Figure 18 includes a pixel portion 702 disposed over a first substrate 701, a source driver circuit portion 704 and a gate driver circuit portion 706 disposed over the first substrate 701, a sealant 712 disposed to surround the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706, and a second substrate 705 disposed to face the first substrate 701. The first substrate 701 and the second substrate 705 are sealed with the sealant 712. That is, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are sealed with the first substrate 701, the sealant 712, and the second substrate 705. Although in Fig. 18, a display element is provided between the first substrate 701 and the second substrate 705.

[0287] In the display device 700, a flexible printed circuit (FPC) terminal portion (FPC terminal portion) 708, which is electrically connected to the pixel portion 702, the source drive circuit portion 704, and the gate drive circuit portion 706, is provided in a region different from the region surrounded by the sealant 712 and positioned above the first substrate 701. Further, an FPC 716 is connected to the FPC terminal portion 708, and various signals and the like are supplied to the pixel portion 702, the source drive circuit portion 704, and the gate drive circuit portion 706 via the FPC 716. In addition, a signal line 710 is connected to the pixel portion 702, the source drive circuit portion 704, the gate drive circuit portion 706, and the FPC terminal portion 708.Various signals and the like are applied from the FPC 716 to the pixel section 702, the source drive circuit section 704, the gate drive circuit section 706, and the FPC terminal section 708 via the signal line 710.

[0288] A plurality of gate drive circuit sections 706 may be provided in the display device 700. An example of the display device 700 will be described in which the source drive circuit section 704 and the gate drive circuit section 706 are formed over the first substrate 701, over which the pixel section 702 is also formed; however, the structure is not limited to this. For example, only the gate drive circuit section 706 may be formed over the first substrate 701, or only the source drive circuit section 704 may be formed over the first substrate 701. In this case, a substrate over which a source drive circuit, a gate drive circuit, or the like is formed (e.g., a drive circuit substrate formed using a single-crystal semiconductor film or a polycrystalline semiconductor film) may be mounted on the first substrate 701.There is no particular limitation on the method for bonding a separately fabricated driver circuit substrate; a chip-on-glass (COG) method, a wire bonding method, or the like may be used.

[0289] The pixel section 702, the source driver circuit section 704, and the gate driver circuit section 706 included in the display device 700 include a plurality of transistors. Any of the transistors that are semiconductor devices of the embodiments of the present invention can be used as the plurality of transistors.

[0290] The display device 700 may include any of various elements. The element includes, for example, a liquid crystal element, an electroluminescent (EL) element (e.g., an EL element containing organic and inorganic materials, an organic EL element, or an inorganic EL element), an LED (e.g., a white LED, a red LED, a green LED, or a blue LED), a transistor (a transistor that emits light in response to current), an electron emitter, an electronic ink, an electrophoretic element, a grating light valve (GLV), a plasma display panel (PDP), a display element utilizing microelectromechanical systems (MEMS), a digital micromirror device (DMD), and / or a digital microshutter.digital microshutter (DMS) and / or MIRASOL (registered trademark) and / or an interferometric modulator (IMOD) element and / or an MEMS shutter display element and / or an optical interference-type MEMS display element and / or an electrowetting element and / or a piezoelectric ceramic display and / or a display element comprising a carbon nanotube. Furthermore, a display medium whose contrast, luminance, reflectivity, transmittance, or the like is changed by an electric or magnetic effect may be provided. Note that examples of display devices having EL elements include an EL display. Examples of display devices including electron emitters include a field emission display (FED) and a surface-conduction electron-emitter display (SED).Surface conduction electron-emitting display). Examples of display devices incorporating liquid crystal elements include a liquid crystal display (e.g., a transmissive liquid crystal display, a semitransmissive liquid crystal display, a reflective liquid crystal display, a direct-view liquid crystal display, or a projection liquid crystal display). An example of a display device incorporating electronic ink or electrophoretic elements is electronic paper. In the case of a semitransmissive liquid crystal display or a reflective liquid crystal display, some or all of the pixel electrodes serve as reflective electrodes. For example, some or all of the pixel electrodes are formed to contain aluminum, silver, or the like. In such a case, a memory circuit, such asan SRAM, can be arranged under the reflective electrodes, resulting in lower power consumption.

[0291] As the display method in the display device 700, a progressive scan method, an interlaced scan method, or the like can be used. Furthermore, color elements controlled in one pixel in color display are not limited to three colors: R, G, and B (R, G, and B correspond to red, green, and blue, respectively). For example, four pixels may be included: the R pixel, the G pixel, the B pixel, and a W (white) pixel. Alternatively, one color element may consist of two colors of R, G, and B as in the PenTile array. The two colors may differ between color elements. Alternatively, one or more colors of yellow, cyan, magenta, and the like may be added to R, G, and B. Note that the size of a display area may vary depending on the respective points of the color components.Embodiments of the disclosed invention are not limited to a display device for color display; the disclosed invention can also be applied to a display device for monochrome display.

[0292] A color layer (also called a color filter) can be used to achieve a full-color display device in which white light (W) is used for a backlight (e.g., an organic EL element, an inorganic EL element, an LED, or a fluorescent lamp). For example, red (R), green (G), blue (B), yellow (Y), or the like can be appropriately combined as the color layer. Using the color layer, higher color reproducibility can be achieved than in the case without a color layer. In this case, a region with the color layer and a region without a color layer are provided, allowing white light in the region without a color layer to be directly used for display.By partially providing the area without a color layer, a reduction in luminance due to the color layer can be suppressed, and power consumption can be reduced by 20% to 30% in some cases when displaying a high-luminance image. Note that when a full-color display is performed using a self-luminous element such as an organic EL element or an inorganic EL element, elements can emit light in their respective colors, R, G, B, Y, and W. Using a self-luminous element, power consumption can be further reduced in some cases compared to the case where the color layer is used.

[0293] In this embodiment, structures including a liquid crystal element and an EL element as display elements are described by Fig. 19 and Fig. 20. It should be noted that Fig. 19 a cross-sectional view along the dot-dash line QR in Fig. 18 and shows a structure comprising a liquid crystal element as a display element, while Fig. 20 a cross-sectional view along the dot-dash line QR in Fig. 18 and shows a structure including an EL element as a display element.

[0294] Common sections between Fig. 19 and Fig. 20 are described first, and then different sections are described. <Gemeinsame Abschnitte der Anzeigevorrichtungen>

[0295] The display device 700, each in Fig. 19 and Fig. 20 includes a lead portion 711, the pixel portion 702, the source driver circuit portion 704, and the FPC lead portion 708. Note that the lead portion 711 includes the signal line 710. The pixel portion 702 includes a transistor 750 and a capacitor 790. The source driver circuit portion 704 includes a transistor 752.

[0296] Any of the transistors described above can be used for transistors 750 and 752.

[0297] The transistors used in this embodiment each comprise a high-purity oxide semiconductor film in which oxygen vacancy formation is suppressed. In the transistors, the current in an off-state (off-state current) can be made small. Accordingly, an electrical signal such as an image signal can be maintained for a longer period of time, and a write interval in an on-state can be set longer. Accordingly, the refresh frequency can be reduced, resulting in an effect of suppressing power consumption.

[0298] Furthermore, the transistors used in this embodiment can have a relatively high field-effect mobility and are therefore suitable for high-speed operation. When such a transistor capable of operating at high speed is used for, for example, a liquid crystal display device, a switching transistor in a pixel portion and a driving transistor in a driving circuit portion can be formed over a substrate. That is, a semiconductor device formed using a silicon wafer or the like is not additionally required as a driving circuit, thereby reducing the number of components of the semiconductor device. In addition, the transistor capable of operating at high speed can also be used in the pixel portion, thereby providing a high-quality image.

[0299] The capacitor 790 has a structure in which a dielectric is provided between a pair of electrodes. Specifically, a conductive film formed by the same process as a conductive film serving as the gate electrode of the transistor 750 is used as one electrode of the capacitor 790, and the conductive film serving as the source electrode or drain electrode of the transistor 750 is used as the other electrode of the capacitor 790. Furthermore, an insulating film serving as the gate insulating film of the transistor 750 is used as the dielectric between the pair of electrodes.

[0300] In Fig. 19 and Fig. 20, insulating films 764, 766 and 768, an oxide semiconductor film 767 and an insulating planarization film 770 are formed over the transistor 750, the transistor 752 and the capacitor 790.

[0301] The insulating films 764, 766, and 768 can each be formed using materials and methods similar to those of the insulating films 114, 116, and 118 described in the above embodiment. The oxide semiconductor film 767 can be formed using a material and method similar to those of the oxide semiconductor film 108 described in the above embodiment. The insulating planarization film 770 can be formed using a heat-resistant organic material such as a polyimide resin, an acrylic resin, a polyimide-amide resin, a benzocyclobutene resin, a polyamide resin, or an epoxy resin. Note that the insulating planarization film 770 can be formed by stacking a plurality of insulating films made of these materials.Alternatively, a structure without the insulating planarization film 770 may be used.

[0302] The signal line 710 is formed by the same process as the conductive films serving as the source electrode and drain electrode of the transistor 750 or 752. Note that the signal line 710 may be formed using a conductive film formed by a process different from that of the source electrode and drain electrode of the transistor 750 or 752; for example, a conductive film serving as the gate electrode. When the signal line 710 is formed using a material containing copper, signal delay or the like due to line resistance is reduced, enabling display on a large screen.

[0303] The FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and the FPC 716. Note that the connection electrode 760 is formed by the same process as conductive films serving as the source electrode and drain electrode of the transistor 750 or 752. The connection electrode 760 is electrically connected to a terminal included in the FPC 716 via the anisotropic conductive film 780.

[0304] For example, a glass substrate can be used as the first substrate 701 and the second substrate 705. A flexible substrate can be used as the first substrate 701 and the second substrate 705. Examples of the flexible substrate include a plastic substrate.

[0305] A structural body 778 is provided between the first substrate 701 and the second substrate 705. The structural body 778 is a columnar spacer obtained by selectively etching an insulating film and is provided to control the distance (cell pitch) between the first substrate 701 and the second substrate 705. Note that a spherical spacer may be used as the structural body 778. Although the example in which the structural body 778 is provided on the first substrate 701 side is described in this embodiment, an embodiment of the present invention is not limited thereto. For example, the structural body 778 may be provided on the second substrate 705 side, or both the first substrate 701 and the second substrate 705 may be provided with the structural body 778.

[0306] Furthermore, an opaque film 738 serving as a black matrix, a color film 736 serving as a color filter, and an insulating film 734 are arranged in contact with the opaque film 738 and the color film 736 on the second substrate 705 side. <Strukturbeispiel der Anzeigevorrichtung, bei der ein Flüssigkristallelement als Anzeigeelement verwendet wird>

[0307] The Fig. The display device 700 shown in Figure 19 comprises a liquid crystal element 775. The liquid crystal element 775 comprises a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is arranged on the side of the second substrate 705 and serves as a counter electrode. The display device 700 in Fig. 19 can display an image such that transmission or non-transmission of light is controlled by changing the alignment state of the liquid crystal layer 776 depending on a voltage applied between the conductive film 772 and the conductive film 774.

[0308] The conductive film 772 is connected to the conductive film serving as a source electrode or drain electrode included in the transistor 750. The conductive film 772 is formed over the insulating planarization film 770 to serve as a pixel electrode, that is, an electrode of the display element. The conductive film 772 serves as a reflective electrode. The display device 700 in Fig. 19 is a so-called reflective color liquid crystal display device in which external light is reflected by the conductive film 772 to display an image through the color film 736.

[0309] A conductive film that transmits visible light or a conductive film that reflects visible light can be used for the conductive film 772. For example, a material containing an element selected from indium (In), zinc (Zn), and tin (Sn) is preferably used for the conductive film that transmits visible light. For example, a material containing aluminum or silver can be used for the conductive film that reflects visible light. In this embodiment, a conductive film that reflects visible light is used for the conductive film 772.

[0310] In the case where a conductive film that reflects visible light is used as the conductive film 772, the conductive film may have a multilayer structure. For example, a 100 nm thick aluminum film is formed as the bottom layer, and a 30 nm thick silver alloy film (e.g., an alloy film containing silver, palladium, and copper) is formed as the top layer. Such a structure makes it possible to obtain the following effects. (1) The adhesion between the base film and the conductive film 772 can be improved. (2) The aluminum film and the silver alloy film can be etched together depending on the chemical solution. (3) The conductive film 772 may have a favorable cross-sectional shape (e.g., a tapered shape).

[0311] The reasoning for (3) is as follows: the etching rate of the aluminum film with the chemical solution is lower than that of the silver alloy film, or the etching of the aluminum film constituting the bottom layer proceeds faster than that of the silver alloy film, because when the aluminum film constituting the bottom layer is exposed after the etching of the silver alloy film constituting the top layer, electrons are taken from the metal which is less noble than the silver alloy film, that is, aluminum, which is a metal with a high ionization tendency, and consequently, etching of the silver alloy film is suppressed.

[0312] It should be noted that projections and recesses in a part of the insulating planarization film 770 of the pixel portion 702 in the display device 700 in Fig. 19. The protrusions and recesses can be formed by forming the insulating planarization film 770 using an organic resin film or the like, and forming protruding portions or recessed portions on the surface of the organic resin film. The conductive film 772 serving as a reflective electrode is formed along the protrusions and recesses. Therefore, when external light is incident on the conductive film 772, the light is reflected at the surface of the conductive film 772 in a diffused manner, whereby visibility can be improved.

[0313] It should be noted that the Fig. 19 is exemplified by a reflective color liquid crystal display device; however, a display type is not limited thereto. For example, a transmissive color liquid crystal display device may be used, in which the conductive film 772 is a conductive film that transmits visible light. In the case of a transmissive color liquid crystal display device, projections and recesses are not necessarily provided on the planarization insulating film 770.

[0314] Although in Fig. 19, an alignment film may be provided on both the side of the conductive film 772 in contact with the liquid crystal layer 776 and the side of the conductive film 774 in contact with the liquid crystal layer 776. Although in Fig. 19, an optical element (optical substrate) such as a polarizing element, a retardation element, or an anti-reflection element, etc., may be provided as needed. For example, circular polarization can be implemented using a polarizing substrate and a retardation substrate. Furthermore, a backlight, a sidelight, or the like can be used as a light source.

[0315] When a liquid crystal element is used as a display element, thermotropic liquid crystal, low-molecular-weight liquid crystal, high-molecular-weight liquid crystal, polymer-dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, or the like can be used. Such a liquid crystal material exhibits a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, or the like, depending on the conditions.

[0316] In the case of a horizontal electric field mode, a blue-phase liquid crystal can be used, which does not require an alignment film. A blue phase is one of the liquid crystal phases that is generated just before a cholesteric phase changes to an isotropic phase as the temperature of the cholesteric liquid crystal increases. Since the blue phase only appears in a narrow temperature range, a liquid crystal composition mixed with several weight percent or more of a chiral material is used for the liquid crystal layer to improve the temperature range. The liquid crystal composition containing a blue-phase liquid crystal and a chiral material has a fast response time and optical isotropy.Furthermore, the liquid crystal composition containing a blue-phase liquid crystal and a chiral material does not require alignment treatment and exhibits low viewing angle dependence. An alignment film is not necessarily required, and rubbing treatment is therefore unnecessary. Consequently, damage caused by electrostatic discharge during the rubbing treatment can be prevented, and defects and damage to the liquid crystal display device during the manufacturing process can be reduced.

[0317] In the case where a liquid crystal element is used as the display element, a twisted nematic (TN) mode, an in-plane switching (IPS) mode, a fringe field switching (FFS) mode, an axially symmetric aligned micro-cell (ASM) mode, an optically compensated birefringence (OCB) mode, a ferroelectric liquid crystal (FLC) mode, an anti-ferroelectric liquid crystal (AFLC) mode, or the like may be used.

[0318] In addition, a normally black liquid crystal display device, such as a transparent liquid crystal display device, can also be used, using a vertical alignment (VA) mode. There are several examples of a vertical alignment mode; for example, a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, an ASV mode, or the like can be used. <Anzeigevorrichtung, bei der ein Licht emittierendes Element als Anzeigeelement verwendet wird>

[0319] The Fig. The display device 700 shown in Figure 20 comprises a light-emitting element 782. The light-emitting element 782 comprises a conductive film 784, an EL layer 786 and a conductive film 788. Fig. The display device 700 shown in Fig. 20 is capable of displaying an image by light emission from the EL layer 786 included in the light-emitting element 782.

[0320] The conductive film 784 is connected to the conductive film serving as a source electrode or drain electrode included in the transistor 750. The conductive film 784 is formed over the insulating planarization film 770 to serve as a pixel electrode, that is, an electrode of the display element. A conductive film that transmits visible light or a conductive film that reflects visible light can be used as the conductive film 784. For the conductive film that transmits visible light, for example, a material containing one type of element selected from indium (In), zinc (Zn), and tin (Sn) is preferably used. For the conductive film that reflects visible light, for example, a material containing aluminum or silver is preferably used.

[0321] At the Fig. In the display device 700 shown in FIG. 20, an insulating film 730 is provided over the planarization insulating film 770 and the conductive film 784. The insulating film 730 covers a part of the conductive film 784. Note that the light-emitting element 782 has a top-emission structure. Therefore, the conductive film 788 has a light transmittance property and transmits light emitted from the EL layer 786. Although the top-emission structure is described as an example in this embodiment, an embodiment of the present invention is not limited thereto. A bottom-emission structure in which light is emitted toward the conductive film 784 side, or a dual-emission structure in which light is emitted toward both the conductive film 784 side and the conductive film 788 side may be employed.

[0322] The color film 736 is arranged to overlap the light-emitting element 782, and the opaque film 738 is arranged to overlap the insulating film 730 and is included in the lead portion 711 and the source drive circuit portion 704. The color film 736 and the opaque film 738 are covered with the insulating film 734. A space between the light-emitting element 782 and the insulating film 734 is filled with a sealing film 732. Although the color film 736 is not covered in the example of the embodiment shown in Fig. 20, an embodiment of the present invention is not limited thereto. In the case where the EL layer 786 is formed by a separate coloring method, the color film 736 is not necessarily provided.

[0323] The structures described in this embodiment may be used in appropriate combination with any of the structures described in the other embodiments. (Embodiment 4)

[0324] In this embodiment, a display device including a semiconductor device of one embodiment of the present invention is described with reference to Fig. 21A to Fig. 21C described.

[0325] The display device, which is Fig. 21A includes a region including pixels of display elements (hereinafter, the region is referred to as a pixel section 502), a circuit section arranged outside the pixel section 502 and including a circuit for driving the pixels (hereinafter, the section is referred to as a drive circuit section 504), circuits each having a function of protecting an element (hereinafter, the circuits are referred to as protection circuits 506), and a terminal section 507. Note that the protection circuits 506 are not necessarily provided.

[0326] Preferably, part or all of the driver circuit section 504 is formed over a substrate over which the pixel section 502 is formed, in which case the number of components and the number of terminals can be reduced. If part or all of the driver circuit section 504 is not formed over the substrate over which the pixel section 502 is formed, part or all of the driver circuit section 504 can be assembled by COG or tape-automated bonding (TAB).

[0327] The pixel section 502 includes a plurality of circuits for driving display elements arranged in X rows (X is a natural number of 2 or more) and Y columns (Y is a natural number of 2 or more) (such circuits are hereinafter referred to as pixel circuits 501). The driver circuit section 504 includes driver circuits such as a circuit for supplying a signal (scanning signal) to select a pixel (the circuit is hereinafter referred to as a gate driver 504a) and a circuit for supplying a signal (data signal) to drive a display element in a pixel (the circuit is hereinafter referred to as a source driver 504b).

[0328] The gate driver 504a includes a shift register or the like. The gate driver 504a receives a signal for driving the shift register via the terminal portion 507 and outputs a signal. For example, the gate driver 504a receives a start pulse signal, a clock signal, or the like and outputs a pulse signal. The gate driver 504a has a function of controlling the potentials of lines to which scanning signals are supplied (such lines are referred to as scanning lines GL_1 to GL_X hereinafter). Note that a plurality of gate drivers 504a may be provided to separately control the scanning lines GL_1 to GL_X. Alternatively, the gate driver 504a has a function of supplying an initialization signal. Without being limited thereto, the gate driver 504a may supply another signal.

[0329] The source driver 504b includes a shift register or the like. The source driver 504b receives, in addition to a signal for driving the shift register, a signal (video signal) from which a data signal is derived via the terminal section 507. The source driver 504b has a function of generating a data signal based on the video signal, which is written into the pixel circuit 501. The source driver 504b additionally has a function of controlling the output of a data signal in response to a pulse signal generated by inputting a start pulse signal, a clock signal, or the like. Furthermore, the source driver 504b has a function of controlling the potentials of lines to which data signals are supplied (such lines are referred to as data lines DL_1 to DL_Y hereinafter). Alternatively, the source driver 504b has a function of supplying an initialization signal.Without limitation, the source driver 504b may supply another signal.

[0330] Source driver 504b includes, for example, a plurality of analog switches or the like. By sequentially turning on the plurality of analog switches, source driver 504b can output, as data signals, signals obtained by time-dividing the video signal. Source driver 504b may include a shift register or the like.

[0331] A pulse signal and a data signal are input to each of the plurality of pixel circuits 501 via one of the plurality of scanning lines GL to which scanning signals are supplied, and one of the plurality of data lines DL to which data signals are supplied, respectively. The writing and holding of the data signal to each of the plurality of pixel circuits 501 are controlled by the gate driver 504a. For example, to the pixel circuit 501 in the m-th row and the n-th column (m is a natural number less than or equal to X, and n is a natural number less than or equal to Y), a pulse signal is input from the gate driver 504a via the scanning line GL_m, and a data signal is input from the source driver 504b via the data line DL_n according to the potential of the scanning line GL_m.

[0332] The Fig. For example, the protection circuit 506 shown in FIG. 21A is connected to the scanning line GL between the gate driver 504a and the pixel circuit 501. The protection circuit 506 is alternatively connected to the data line DL between the source driver 504b and the pixel circuit 501. The protection circuit 506 may alternatively be connected to a line between the gate driver 504a and the terminal portion 507. The protection circuit 506 may alternatively be connected to a line between the source driver 504b and the terminal portion 507. Note that the terminal portion 507 denotes a portion having terminals through which power, control signals, and video signals from external circuits are input to the display device.

[0333] The protection circuit 506 is a circuit that electrically connects a line connected to the protection circuit to another line when a potential outside a certain range is applied to the line connected to the protection circuit.

[0334] As in Fig. As shown in FIG. 21A, the protection circuits 506 are provided for the pixel section 502 and the driver circuit section 504, so that the resistance of the display device to an overcurrent generated by electrostatic discharge (ESD) or the like can be improved. Note that the configuration of the protection circuits 506 is not limited thereto; for example, the protection circuit 506 may be configured to be connected to the gate driver 504a, or the protection circuit 506 may be configured to be connected to the source driver 504b. Alternatively, the protection circuit 506 may be configured to be connected to the terminal section 507.

[0335] In Fig. 21A shows an example in which the driver circuit section 504 includes the gate driver 504a and the source driver 504b; however, the structure is not limited to this. For example, only the gate driver 504a may be formed, and a separately fabricated substrate may be mounted over which a source driver circuit is formed (e.g., a driver circuit substrate formed of a single-crystal semiconductor film or a polycrystalline semiconductor film).

[0336] Each of the plurality of pixel circuits 501 in Fig. 21A can, for example, Fig. 21B.

[0337] The Fig. The pixel circuit 501 shown in Fig. 21B includes a liquid crystal element 570, a transistor 550, and a capacitor 560. For example, any of the transistors described in the above embodiments can be used as the transistor 550.

[0338] The potential of one of a pair of electrodes of the liquid crystal element 570 is adjusted as needed according to the specifications of the pixel circuit 501. The alignment state of the liquid crystal element 570 depends on the written data. A common potential may be applied to one of the pair of electrodes of the liquid crystal element 570 included in each of the plurality of pixel circuits 501. Furthermore, the potential applied to one of the pair of electrodes of the liquid crystal element 570 in the pixel circuit 501 in one row may be different from the potential applied to one of the pair of electrodes of the liquid crystal element 570 in the pixel circuit 501 in another row.

[0339] As examples of a driving method of the display device including the liquid crystal element 570, any of the following modes can be given: a TN mode, an STN mode, a VA mode, an axially symmetric aligned micro-cell (ASM) mode, an optically compensated birefringence (OCB) mode, a ferroelectric liquid crystal (FLC) mode, an antiferroelectric liquid crystal (AFLC) mode, an MVA mode, a patterned vertical alignment (PVA) mode, an IPS mode, an FFS mode, a transverse bend alignment (TBA) mode, and the like.Other examples of the driving method of the display device include an electrically controlled birefringence (ECB) mode, a polymer dispersed liquid crystal (PDLC) mode, a polymer network liquid crystal (PNLC) mode, and a guest-host mode. Note that the present invention is not limited to these examples, and various liquid crystal elements and driving methods can be used for the liquid crystal element and the driving method therefor.

[0340] In the pixel circuit 501 in the m-th row and the n-th column, either one source electrode or one drain electrode of the transistor 550 is electrically connected to the data line DL_n, and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. A gate electrode of the transistor 550 is electrically connected to the scanning line GL_m. The transistor 550 has a function of controlling whether a data signal is written by turning it on or off.

[0341] One of a pair of electrodes of the capacitor 560 is electrically connected to a line to which a potential is supplied (hereinafter referred to as a potential supply line VL), and the other is electrically connected to the other of the pair of electrodes of the liquid crystal element 570. The potential of the potential supply line VL is adjusted as needed according to the specifications of the pixel circuit 501. The capacitor 560 serves as a storage capacitor for storing the written data.

[0342] For example, in the display device using the pixel circuit 501 in Fig. 21B, the pixel circuits 501 are successively switched by the Fig. 21A, the gate driver 504a is selected row by row, turning on the transistors 550 and writing a data signal.

[0343] When transistors 550 are turned off, pixel circuits 501 in which data has been written are placed in a hold state. This operation is performed sequentially, line by line, allowing an image to be displayed.

[0344] Alternatively, each of the plurality of pixel circuits 501 in Fig. 21A for example the Fig. 21C.

[0345] The Fig. The pixel circuit 501 shown in Figure 21C includes transistors 552 and 554, a capacitor 562, and a light-emitting element 572. Any of the transistors described in the above embodiments may be used as transistor 552 and / or transistor 554.

[0346] Either a source electrode or a drain electrode of transistor 552 is electrically connected to a line to which a data signal is supplied (hereinafter referred to as a signal line DL_n). A gate electrode of transistor 552 is electrically connected to a line to which a gate signal is supplied (hereinafter referred to as a scan line GL_m).

[0347] The transistor 552 has a function of controlling whether a data signal is written by turning it on or off.

[0348] One of a pair of electrodes of the capacitor 562 is electrically connected to a line to which a potential is supplied (hereinafter referred to as a potential supply line VL_a), and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 552.

[0349] The capacitor 562 serves as a storage capacitor to store the written data.

[0350] Either a source electrode or a drain electrode of transistor 554 is electrically connected to the potential supply line VL_a. A gate electrode of transistor 554 is further electrically connected to the other of the source electrode and the drain electrode of transistor 552.

[0351] Either one anode or a cathode of the light-emitting element 572 is electrically connected to a potential supply line VL_b, and the other is electrically connected to the other of the source electrode and the drain electrode of the transistor 554.

[0352] For example, an organic electroluminescent element (also referred to as an organic EL element) or the like can be used as the light-emitting element 572. Note that the light-emitting element 572 is not limited to an organic EL element; an inorganic EL element containing an inorganic material can be used.

[0353] A high power supply potential VDD is supplied to either the potential supply line VL_a or the potential supply line VL_b, and a low power supply potential VSS is supplied to the other line.

[0354] For example, in the display device using the pixel circuit 501 in Fig. 21C, the pixel circuits 501 are successively switched by the Fig. 21A, the gate driver 504a is selected row by row, turning on the transistors 552 and writing a data signal.

[0355] When transistors 552 are turned off, pixel circuits 501 in which the data has been written are placed in a hold state. The magnitude of the current flowing between the source and drain electrodes of transistor 554 is further controlled according to the potential of the written data signal. Light-emitting element 572 emits light with a luminance corresponding to the magnitude of the flowing current. This operation is performed sequentially, line by line; thus, an image can be displayed.

[0356] The structures described in this embodiment may be used in appropriate combination with any of the structures described in the other embodiments. (Embodiment 5)

[0357] In this embodiment, a display module and electronic devices including a semiconductor device of one embodiment of the present invention are described with reference to Fig. 22 and Fig. 23A to Fig. 23G described.

[0358] For a display module 8000, which is in Fig. 22, a touch screen 8004 connected to an FPC 8003, a display panel 8006 connected to an FPC 8005, a backlight unit 8007, a frame 8009, a printed circuit board 8010, and a battery 8011 are provided between an upper cover 8001 and a lower cover 8002.

[0359] The semiconductor device of one embodiment of the present invention can be used for the display panel 8006, for example.

[0360] The shapes and sizes of the upper cover 8001 and the lower cover 8002 can be changed according to the sizes of the touch screen 8004 and the display panel 8006, respectively.

[0361] The touchscreen 8004 may be a resistive touchscreen or a capacitive touchscreen and may be formed to overlap the display panel 8006. A counter substrate (sealing substrate) of the display panel 8006 may have a touchscreen function. A photosensor may be provided in each pixel of the display panel 8006 to obtain an optical touchscreen.

[0362] The backlight unit 8007 includes light sources 8008. It should be noted that although a structure in Fig. 22, in which the light sources 8008 are provided above the backlight unit 8007, an embodiment of the present invention is not limited to this structure. For example, a structure may be adopted in which the light sources 8008 are arranged at one end portion of the backlight unit 8007 and a light diffusing plate is further provided. Note that in the case where a self-luminous light-emitting element such as an organic EL element is used, or in the case where a reflective screen or the like is employed, the backlight unit 8007 may not be required.

[0363] The frame 8009 protects the display panel 8006 and also serves as an electromagnetic shield to block electromagnetic waves generated by the operation of the printed circuit board 8010. The frame 8009 can also serve as a radiation plate.

[0364] The printed circuit board 8010 is provided with a power supply circuit and a signal processing circuit for outputting a video signal and a clock signal. As a power source for supplying power to the power supply circuit, an external AC power source or a power source using the separately provided battery 8011 can be used. The battery 8011 can be omitted if an AC power source is used.

[0365] The display module 8000 may additionally be provided with a component such as a polarizing plate, a retardation plate, or a prism sheet.

[0366] Fig. 23A to Fig. 23G represent electronic devices. These electronic devices may include a housing 9000, a display section 9001, a speaker 9003, an operation button 9005 (including a power button or an operation switch), a connection terminal 9006, a sensor 9007 (a sensor having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared ray), a microphone 9008, and the like.

[0367] The electronic devices used in Fig. 23A to Fig. 23G may have various functions, such as a function for displaying various information (a still image, a moving image, a text image, and the like) on the display section, a touchscreen function, a function for displaying a calendar, the date, time, and the like, a function for controlling processing with various types of software (programs), a wireless communication function, a function for connecting to various computer networks using a wireless communication function, a function for transmitting and receiving various data using a wireless communication function, a function for reading a program or data stored in a storage medium and displaying the program or data on the display section, and the like. It should be noted that functions of the electronic devices shown in Fig. 23A to Fig. 23G are not limited to these and the electronic devices may have additional functions. Although Fig. 23A to Fig. 23G, the electronic devices may include a plurality of display sections. The electronic devices may have a camera or the like, and a function for capturing a still image, a function for capturing a moving image, a function for storing the captured image in a storage medium (an external storage medium or a storage medium built into the camera), a function for displaying the captured image on the display section, or the like.

[0368] The electronic devices used in Fig. 23A to Fig. 23G are described in detail below.

[0369] Fig. 23A is a perspective view of a portable information terminal 9100. The display section 9001 of the portable information terminal 9100 is flexible and can therefore be installed along the curved surface of the housing 9000. The display section 9001 further includes a touch sensor, and an operation can be performed by touching the screen with a finger, a stylus, or the like. For example, by touching an icon displayed on the display section 9001, an application can be launched.

[0370] Fig. 23B is a perspective view of a portable information terminal 9101. The portable information terminal 9101 serves, for example, as one or more of a telephone, a laptop, an information search system, and the like. In particular, the portable information terminal 9101 can be used as a smartphone. It should be noted that the speaker 9003, the connection terminal 9006, the sensor 9007, and the like shown in Fig. 23B, in the portable information terminal 9101 as in the portable information terminal 9100 shown in Fig. 23A. The portable information terminal 9101 can display characters and image information on its plurality of surfaces. For example, three operation buttons 9050 (also referred to as operation icons, or simply as icons) may be displayed on one surface of the display section 9001. In addition, information 9051 represented by dashed rectangles may be displayed on another surface of the display section 9001. Examples of the information 9051 include a notification from a social networking service (SNS), an indication representing the arrival of an email or a call, the subject of the email, SNS, or the like, the sender of the email, SNS, or the like, the date, time, remaining battery power, and the reception strength of an antenna.Instead of the information 9051, the operation buttons 9050 or the like may be displayed at the position where the information 9051 is displayed.

[0371] Fig. 23C is a perspective view of a portable information terminal 9102. The portable information terminal 9102 has a function of displaying information on three or more surfaces of the display section 9001. Here, information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, a user of the portable information terminal 9102 can view the display (here, information 9053) with the portable information terminal 9102 placed in a breast pocket of his / her shirt. Specifically, the telephone number, name, or the like of a caller can be displayed in a position visible from above the portable information terminal 9102. Therefore, the user can view the display without removing the portable information terminal 9102 from the pocket and decide whether to answer the call.

[0372] Fig. 23D is a perspective view of a wristwatch-shaped portable information terminal 9200. The portable information terminal 9200 can run various applications, such as mobile phone calls, sending and receiving emails, displaying and editing text, playing music, Internet communication, and computer games. The display surface of the display section 9001 is curved, and images can be displayed on the curved display surface. The portable information terminal 9200 can utilize short-range communication according to an existing communication standard. For example, two-way communication can be performed between the portable information terminal 9200 and a headset capable of wireless communication, enabling hands-free telephone conversation.The portable information terminal 9200 further includes the connection port 9006, and data can be sent and received directly to / from another information terminal via a connecting element. Charging through the connection port 9006 is also possible. Note that charging can be performed without the connection port 9006 by wireless power supply.

[0373] Fig. 23E, Fig. 23F and Fig. 23G are perspective views of a foldable portable information terminal 9201, in which it is opened, from the open state to the folded state, or from the folded state to the open state, and folded, respectively. The portable information terminal 9201 is highly portable when folded. When the portable information terminal 9201 is opened, a seamless large display area is highly searchable. The display section 9001 of the portable information terminal 9201 is supported by three cases 9000 connected to each other by hinges 9055. By folding the portable information terminal 9201 at a junction between two cases 9000 at the hinges 9055, the shape of the portable information terminal 9201 can be reversibly changed from the open state to the folded state.For example, the portable information terminal 9201 can be bent with a radius of curvature greater than or equal to 1 mm and less than or equal to 150 mm.

[0374] The electronic devices described in this embodiment each include a display section for displaying certain types of data. However, a semiconductor device of one embodiment of the present invention can also be applied to an electronic device that does not have a display section. Furthermore, the display sections of the electronic devices described in this embodiment may be non-flexible and display images on a flat surface, without being limited to a flexible mode capable of displaying images on a curved display surface or a foldable mode.

[0375] The structures described in this embodiment may be used in appropriate combination with any of the structures described in the other embodiments. (Embodiment 6)

[0376] In this embodiment, an example of a circuit configuration of a semiconductor device that can retain stored data even without power supply and has no limitation on the number of write operations is explained with reference to Fig. 24 described. <schaltungskonfiguration>

[0377] Fig. 24 shows an example of a circuit configuration of a semiconductor device. In Fig. 24, a first line (1st line) is electrically connected to one of a source electrode and a drain electrode of a p-channel transistor 1280a. Furthermore, the other of the source electrode and the drain electrode of the p-channel transistor 1280a is electrically connected to one of a source electrode and a drain electrode of an n-channel transistor 1280b. Furthermore, the other of the source electrode and the drain electrode of the n-channel transistor 1280b is electrically connected to one of a source electrode and a drain electrode of an n-channel transistor 1280c.

[0378] A second line (2nd line) is electrically connected to one of a source electrode and a drain electrode of a transistor 1282. Furthermore, the other of the source electrode and the drain electrode of the transistor 1282, one electrode of a capacitor 1281, and a gate electrode of the n-channel transistor 1280c are electrically connected to each other.

[0379] A third line (3rd line) and gate electrodes of the p-channel transistor 1280a and the n-channel transistor 1280b are electrically connected to each other. Furthermore, a fourth line (4th line) is electrically connected to a gate electrode of the transistor 1282. Furthermore, a fifth line (5th line), the other electrode of the capacitor 1281, and the other of the source electrode and drain electrode of the n-channel transistor 1280c are electrically connected to each other. Furthermore, a sixth line (6th line), the other of the source electrode and drain electrode of the p-channel transistor 1280a, and one of the source electrode and drain electrode of the n-channel transistor 1280b are electrically connected to each other.

[0380] It should be noted that the transistor 1282 can be formed using an oxide semiconductor (OS). Accordingly, Fig. 24, "OS" is written next to the transistor 1282. Note that the transistor 1282 may be formed using a material other than an oxide semiconductor. The transistor 100 or the transistor 170 described in Embodiment 1 may be used as the transistor 1282.

[0381] Furthermore, Fig. 24 "FN" (floating node) is written at a junction of the other electrode of the source electrode and drain electrode of transistor 1282, one electrode of capacitor 1281, and the gate electrode of n-channel transistor 1280c. When transistor 1282 is turned off, the potentials supplied to the floating node, one electrode of capacitor 1281, and the gate electrode of n-channel transistor 1280c can be maintained.

[0382] The circuit configuration in Fig. 24 takes advantage of the following: The potential of the gate electrode of the n-channel transistor 1280c can be held, whereby writing, holding and reading of data can be performed as described below. <Schreiben und Halten von Daten>

[0383] First, data writing and holding will be described. The potential of the fourth wiring is set to a potential at which the transistor 1282 is turned on, so that the transistor 1282 is turned on. Accordingly, the potential of the second wiring is supplied to the gate electrode of the n-channel transistor 1280c and the capacitor 1281. That is, a certain charge is supplied to the gate electrode of the n-channel transistor 1280c (writing). After that, the potential of the fourth wiring is set to a potential at which the transistor 1282 is turned off, thereby turning the transistor 1282 off. Accordingly, a charge applied to the gate electrode of the n-channel transistor 1280c is held (holding).

[0384] Since the off-state current of transistor 1282 is very small, the charge on the gate electrode of n-channel transistor 1280c is maintained for a long time. <Lesen von Daten>

[0385] Next, data reading will be described. When the potential of the third wiring is a low-level potential, the p-channel transistor 1280a is turned on, and the n-channel transistor 1280b is turned off. At this time, the potential of the first wiring is applied to the sixth wiring. On the other hand, when the potential of the third wiring is a high-level potential, the p-channel transistor 1280a is turned off, and the n-channel transistor 1280b is turned on. At this time, the potential of the sixth wiring varies in response to the amount of charge held in the floating node (FN). Thus, the held data can be read (read) by measuring the potential of the sixth wiring.

[0386] The transistor 1282, in which a channel formation region is formed using an oxide semiconductor, has a very low off-state current. The off-state current of the transistor 1282 using an oxide semiconductor is lower than or equal to one hundred thousandth of that of a transistor formed using a silicon semiconductor or the like; thus, the loss of electric charge accumulated in the floating node (FN) due to current leakage of the transistor 1282 is small to negligible. This means that the transistor 1282 formed using an oxide semiconductor enables the realization of a non-volatile memory circuit that can retain data even without power supply.

[0387] By applying the semiconductor device having the above-described circuit configuration to a memory device such as a register or cache memory, data in the memory device can be prevented from being erased due to the cessation of the power supply voltage supply. Furthermore, the memory device can return to the state it was in before the power supply was stopped shortly after the power supply voltage is resumed. Thus, the power supply can be stopped for a short time even when the entire memory device or one or more logic circuits included in the memory circuit are in a standby mode, resulting in lower power consumption.

[0388] The structures, methods, and the like described in this embodiment may be used in appropriate combination with any of the structures, methods, and the like described in the other embodiments. [Example]

[0389] In this example, transistors were fabricated that correspond to the transistor 170 shown in Fig. 6A and Fig. 6B, and their I d - V g -Properties were evaluated.

[0390] Samples A1 to A3, described below, were formed and used for evaluation in this example. Note that samples A1 to A3 are each a sample of one embodiment of the present invention. A transistor of sample A1 has a channel length L of 6 µm and a channel width W of 5 µm; a transistor of sample A2 has a channel length L of 6 µm and a channel width W of 50 µm; and a transistor of sample A3 has a channel length L of 6 µm and a channel width W of 200 µm. 10 transistors, each having the corresponding above size, were formed as samples A1 to A3.

[0391] Samples A1 to A3 formed in this example are described below. Samples A1 to A3 were formed by the same process and differ from each other only in the channel width W of the transistor. Note that the reference numerals used for transistor 170 in Fig. 6A and Fig. 6B are also used in the following description. <Herstellungsverfahren der Proben A1 bis A3>

[0392] First, the conductive film 104 was formed over the substrate 102. A glass substrate was used as the substrate 102. Note that the size and thickness of the glass substrate were 600 mm × 720 mm and 0.7 mm, respectively. A 100 nm thick tungsten film was formed as the conductive film 104 using a sputtering device.

[0393] Next, insulating films 106 and 107 were formed over the substrate 102 and the conductive film 104. A 400 nm thick silicon nitride film was formed as the insulating film 106 using a PECVD device. A 50 nm thick silicon oxynitride film was formed as the insulating film 107 using a PECVD device.

[0394] The insulating film 106 was deposited as follows. First, a 50 nm thick silicon nitride film was deposited under the following conditions: The substrate temperature was 350 °C; a silane gas at a flow rate of 200 sccm, a nitrogen gas at a flow rate of 2000 sccm, and an ammonia gas at a flow rate of 100 sccm were introduced into a chamber; the pressure was set to 100 Pa; and an RF power of 2000 W was applied between parallel plate electrodes provided in a PECVD device. Then, the flow rate of an ammonia gas was changed to 2000 sccm to deposit a 300 nm thick silicon nitride film. Finally, the flow rate of an ammonia gas was changed to 100 sccm to deposit a 50 nm thick silicon nitride film.

[0395] The insulating film 107 was deposited under the following conditions: the substrate temperature was 350 °C; a silane gas at a flow rate of 20 sccm and a nitrous oxide gas at a flow rate of 3000 sccm were introduced into a chamber; the pressure was 40 Pa; and an RF power of 100 W was applied between parallel plate electrodes provided in a PECVD device.

[0396] Then, the oxide semiconductor film 108 was formed over the insulating film 107. The oxide semiconductor film 108 has a multilayer structure consisting of the first oxide semiconductor film 108a on the side of the conductive film 104 (which serves as the gate electrode) and the second oxide semiconductor film 108b over the first oxide semiconductor film 108a. A 10 nm thick IGZO film and a 15 nm thick IGZO film were formed as the first oxide semiconductor film 108a and the second oxide semiconductor film 108b, respectively.

[0397] Note that the first oxide semiconductor film 108a was deposited under the following conditions: the substrate temperature was 170 °C; an argon gas with a flow rate of 140 sccm and an oxygen gas with a flow rate of 60 sccm were introduced into a chamber; the pressure was 0.6 Pa; and an AC power of 2500 W was applied to a sputtering target made of polycrystalline metal oxide (with an atomic ratio of In:Ga:Zn = 4:2:4.1).

[0398] Note that the second oxide semiconductor film 108b was deposited under the following conditions: the substrate temperature was 170 °C; an argon gas with a flow rate of 100 sccm and an oxygen gas with a flow rate of 100 sccm were introduced into a chamber; the pressure was 0.6 Pa; and an AC power of 2500 W was applied to a sputtering target made of polycrystalline metal oxide (with an atomic ratio of In:Ga:Zn = 1:1:1.2).

[0399] Next, the conductive films 112a and 112b were formed over the insulating film 107 and the oxide semiconductor film 108. The conductive films 112a and 112b were formed by successively forming a 50 nm thick tungsten film, a 400 nm thick aluminum film, and a 100 nm thick titanium film in this order using a vacuum sputtering device.

[0400] Next, insulating film 114 and insulating film 116 were formed over insulating film 107, oxide semiconductor film 108, and conductive films 112a and 112b. A 50 nm thick silicon oxynitride film was formed as insulating film 114 using a PECVD device. A 400 nm thick silicon oxynitride film was formed as insulating film 116 using a PECVD device. Note that insulating film 114 and insulating film 116 were successively formed in a vacuum using a PECVD device.

[0401] The insulating film 114 was deposited under the following conditions: the substrate temperature was 220°C; a silane gas with a flow rate of 50 sccm and a nitrous oxide gas with a flow rate of 2000 sccm were introduced into a chamber; the pressure was 20 Pa; and an RF power of 100 W was applied between parallel plate electrodes provided in a PECVD device. The insulating film 116 was deposited under the following conditions: the substrate temperature was 220°C; a silane gas with a flow rate of 160 sccm and a nitrous oxide gas with a flow rate of 4000 sccm were introduced into a chamber; the pressure was 200 Pa; and an RF power of 1500 W was applied between parallel plate electrodes provided in a PECVD device.

[0402] Then, a first heat treatment was performed. The first heat treatment was carried out for 1 hour at 350 °C in a nitrogen gas atmosphere.

[0403] A 5 nm thick ITSO film was formed over the insulating film 116 using a sputtering device. The ITSO film was deposited under the following conditions: the substrate temperature was room temperature; an argon gas at a flow rate of 72 sccm and an oxygen gas at a flow rate of 5 sccm were introduced into a chamber; the pressure was 0.15 Pa; and a DC power of 1000 W was supplied to a metal oxide target (In2O3:SnO2:SiO2 = 85:10:5 [wt%]) provided in the sputtering device.

[0404] Next, an oxygen addition treatment was performed on the insulating film 116 over the ITSO film. The oxygen addition treatment was performed using an ashing device under the following conditions: the substrate temperature was 40 °C; an oxygen gas was introduced into a chamber at a flow rate of 250 sccm; the pressure was 15 Pa; and an RF power of 4500 W was applied for 120 seconds between parallel plate electrodes provided in the ashing device, so that a bias voltage was applied to the substrate side.

[0405] Subsequently, the ITSO film was removed to expose the insulating film 116. The ITSO film was removed using a wet etching device such that etching was performed for 300 seconds using an oxalic acid solution with a concentration of 5% and then etching was performed for 15 seconds using hydrofluoric acid with a concentration of 0.5%.

[0406] Next, the insulating film 118 was formed over the insulating film 116. A 100 nm thick silicon nitride film was formed as the insulating film 118 using a PECVD device. Note that the substrate temperature in the PECVD device during the deposition of the insulating film 118 was 350°C.

[0407] Next, the opening 142c reaching the conductive film 112b and the openings 142a and 142b reaching the conductive film 104 were formed. The openings 142a, 142b, and 142c were formed using a dry etching device.

[0408] Next, a conductive film was formed over the insulating film 118 to cover the openings 142a, 142b, and 142c, and processed to form the conductive films 120a and 120b. For the conductive films 120a and 120b, a 100 nm thick ITSO film was formed using a sputtering device. The composition of a target used to form the ITSO film was the same as that used to form the ITSO film described above.

[0409] A second heat treatment was then performed. The second heat treatment was carried out for 1 hour at 250 °C in a nitrogen gas atmosphere.

[0410] Samples A1 to A3 of this example were manufactured using the above process. Note that the highest temperature in the process for manufacturing samples A1 to A3 was 350 °C. d -V g -Properties of transistors>

[0411] Next, I d -V g -Properties of samples A1 to A3 formed in the above manner were measured. Fig. 25A to Fig. 25C show the I d -V g -Properties of samples A1 to A3. It should be noted that Fig. 25A the I d -V g -Properties of sample A1 shows, Fig. 25B the I d - V g -Properties of sample A2 and Fig. 25C the I d - V g -properties of sample A3. In Fig. 25A to Fig. 25C represents the first vertical axis I d (A), the second vertical axis µFE (cm 2 ​ / Vs) and the horizontal axis V g (V). It should be noted that the properties of the 10 transistors in Fig. 25A to Fig. 25C overlap each other.

[0412] A voltage applied to the conductive film 104 serving as the first gate electrode (hereinafter referred to as the gate voltage (V g )) and a voltage (V bg ) applied to the conductive film 120b serving as the second gate electrode were used to measure the I d -V g -Characteristics of the transistor 170 are changed from -15 V to +20 V in steps of 0.25 V. It should be noted that only in the case of the transistors of sample A3 V g and V bg were each changed from -15 V to +15 V in steps of 0.25 V. A voltage applied to the conductive film 112a, which serves as a source electrode (hereinafter the voltage is also referred to as the source voltage (V s )), was 0 V (common), and a voltage applied to the conductive film 112b serving as a drain electrode (hereinafter, the voltage is also referred to as drain voltage (V d )), was 0.1 V or 20 V. Regarding the field effect mobility (µFE), the results shown are those obtained at V d = 20 V were obtained.

[0413] The results in Fig. 25A to Fig. 25C reveal that the FET characteristics hardly depend on the channel width W, even in the case where the highest temperature in the process is relatively low, i.e., 350 °C, and the FETs achieve stable self-off properties. It should be noted that in this example, self-off properties of the transistor mean that a current per micrometer of channel width flowing between a drain and a source at V g = 0 V flows, 1 × 10 -20 A or less at room temperature, 1 × 10 -18 A or less at 85 °C, or 1 × 10 -16 A or less at 125 °C. The transistors of samples A1 to A3 of one embodiment of the present invention exhibited a high field-effect mobility. In particular, the transistors of samples A2 and A3 exhibited a high field-effect mobility of higher than 30 cm 2 / Vs on.

[0414] As described above, in the semiconductor device of one embodiment of the present invention, the oxide semiconductor film has a multilayer structure, which enables the semiconductor device to have excellent electrical characteristics (particularly, high reliability and high field effect mobility) even when the process temperature is relatively low (for example, 350 °C).

[0415] The structures described in this embodiment may be used in appropriate combination with any of the structures described in the other embodiments. Explanation of reference symbols

[0416] 100: transistor, 102: substrate, 104: conductive film, 106: insulating film, 107: insulating film, 108: oxide semiconductor film, 108a: oxide semiconductor film, 108b: oxide semiconductor film, 109: oxide semiconductor film, 109a: oxide semiconductor film, 109b: oxide semiconductor film, 112: conductive film, 112a: conductive film, 112b: conductive film, 114: insulating film, 116: insulating film, 118: insulating film, 120: conductive film, 120a: conductive film, 120b: conductive film, 131: barrier film, 136a: mask, 136b: mask, 138: etchant, 139: etchant, 140: Oxygen, 140a: Oxygen, 141: Arrow, 142: Etchant, 142a: Opening, 142b: Opening, 142c: Opening, 170: Transistor, 501: Pixel circuit, 502: Pixel section, 504: Driver circuit section, 504a: Gate driver, 504b: Source driver, 506: Protection circuit, 507: Terminal section, 550: Transistor, 552: Transistor, 554: Transistor, 560: Capacitor, 562: Capacitor, 570: Liquid crystal element, 572: Light-emitting element, 700: Display device,701: Substrate, 702: Pixel portion, 704: Source drive circuit portion, 705: Substrate, 706: Gate drive circuit portion, 708: FPC terminal portion, 710: Signal line, 711: Line portion, 712: Sealant, 716: FPC, 730: Insulating film, 732: Sealing film, 734: Insulating film, 736: Color film, 738: Opaque film, 750: Transistor, 752: Transistor, 760: Connection electrode, 764: Insulating film, 766: Insulating film, 767: Oxide semiconductor film, 768: Insulating film, 770: Insulating planarization film, 772: Conductive film, 774: Conductive film, 775: Liquid crystal element, 776: Liquid crystal layer, 778: structural body, 780: anisotropic conductive film, 782: light-emitting element, 784: conductive film, 786: EL layer, 788: conductive film, 790: capacitor, 1280a: p-channel transistor, 1280b: n-channel transistor, 1280c: n-channel transistor, 1281: capacitor, 1282: transistor, 5100: pellet, 5100a: pellet, 5100b: pellet, 5101: ion,5102: zinc oxide layer, 5103: particle, 5105a: pellet, 5105a1: region, 5105a2: pellet, 5105b: pellet, 5105c: pellet, 5105d: pellet, 5105d1: region, 5105e: pellet, 5120: substrate, 5130: target, 5161: region, 8000: display module, 8001: upper cover, 8002: lower cover, 8003: FPC, 8004: touch screen, 8005: FPC, 8006: display panel, 8007: backlight, 8008: light source, 8009: frame, 8010: printed circuit board, 8011: battery, 9000: housing, 9001: display section, 9003: Loudspeaker, 9005: Operation button, 9006: Connection terminal, 9007: Sensor, 9008: Microphone, 9050: Operation button, 9051: Information, 9052: Information, 9053: Information, 9054: Information, 9055: Joint, 9100: Portable information terminal, 9101: Portable information terminal, 9102: Portable information terminal, 9200: Portable information terminal, and 9201: Portable information terminal.< / schaltungskonfiguration> < / abscheidungsmodell> < / oxidhalbleiterfilm> < / substrat>

Claims

[1] A method of manufacturing a semiconductor device, comprising the steps of: Forming an oxide semiconductor film (109) at a first temperature; processing the oxide semiconductor film (109) into an island shape (108); subsequently depositing a material (112) that becomes a source electrode (112a) and a drain electrode (112b) by a sputtering method over the oxide semiconductor film (108) without performing a process at a temperature higher than the first temperature; processing the material (112) to form the source electrode (112a) and the drain electrode (112b); subsequently forming an insulating protective film (114, 116) over the oxide semiconductor film (108), the source electrode (112a) and the drain electrode (112b); subsequently forming a first barrier film (131) over the insulating protective film (114, 116); Adding excess oxygen or an oxygen radical to the insulating protective film (116) via the first barrier film (131); performing a heat treatment at a second temperature lower than 400 °C to diffuse the excess oxygen or oxygen radical into the oxide semiconductor film (108); Removing the first barrier film (131) or a part of the first barrier film and a part of the insulating protective film (116) by wet etching; and subsequently forming a second barrier film (118) over the insulating protective film (116). [2] A method of manufacturing the semiconductor device according to claim 1, wherein the first barrier film (131) is an indium tin oxide film, an indium tin silicon oxide film, or an indium oxide film. [3] A method of manufacturing the semiconductor device according to claim 1, wherein the second barrier film (118) is a silicon nitride oxide film or a silicon nitride film. [4] A method of manufacturing a semiconductor device, comprising the steps of: Forming an oxide semiconductor film (109) at a first temperature; processing the oxide semiconductor film (109) into an island shape (108); subsequently depositing a material (112) that becomes a source electrode (112a) and a drain electrode (112b) by a sputtering method without performing a process at a temperature higher than the first temperature; processing the material (112) to form the source electrode (112a) and the drain electrode (112b); subsequently forming an insulating protective film (114, 116) over the oxide semiconductor film (108), the source electrode (112a) and the drain electrode (112b); Forming a metal oxide film (131) as a first barrier film over the insulating protective film (114, 116) by a sputtering method to add excess oxygen or an oxygen radical to the insulating protective film; and performing a heat treatment at a second temperature lower than 400 °C to diffuse the excess oxygen or oxygen radical into the oxide semiconductor film (108); wherein the insulating protective film (114, 116) has a multi-layer structure comprising a first insulating protective film (114) and a second insulating protective film (116) over the first insulating protective film, and wherein a part of the second insulating protective film is removed by wet etching. [5] A method of manufacturing the semiconductor device according to claim 4, wherein the metal oxide film is an aluminum oxide film, a hafnium oxide film, or an yttrium oxide film. [6] A method of manufacturing a semiconductor device, comprising the steps of: Forming an oxide semiconductor film (109) at a first temperature; processing the oxide semiconductor film (109) into an island shape (108); Depositing a material (112) that becomes a source electrode (112a) and a drain electrode (112b) by a sputtering method over the oxide semiconductor film (108) after processing the oxide semiconductor film (108); processing the material (112) to form the source electrode (112a) and the drain electrode (112b); Forming a first insulating protective film (114) and a second insulating protective film (116) over the oxide semiconductor film (108), the source electrode (112a) and the drain electrode (112b); heating the first insulating protective film (114) and the second insulating protective film (116) at a second temperature higher than the first temperature; Forming a first barrier film (131) over the second insulating protective film (116) after heating the first insulating protective film (114) and the second insulating protective film (116); Adding excess oxygen or an oxygen radical to the second insulating protective film (116) via the first barrier film (131); Removing a part of the first barrier film (131) and a part of the second insulating protective film (116) by wet etching after adding the excess oxygen or the oxygen radical; and Forming a second barrier film (118) over the second insulating protective film (116) at a third temperature higher than the first temperature after removing the part of the first barrier film (131) and the part of the second insulating protective film (116), wherein the second temperature and / or the third temperature is / is the highest in a process of the steps. [7] A method of manufacturing the semiconductor device according to any one of claims 1, 4 and 6, wherein the oxide semiconductor film has a multilayer structure of a first oxide semiconductor film having an atomic ratio of In:M:Zn = 4:α1 (1.5 ≤ α1 ≤ 2.5):α2 (2.5 ≤ α2 ≤ 3.5) and a second oxide semiconductor film having an atomic ratio of In:M:Zn = 1:β1 (0.8 ≤ β1 ≤ 1.2):β2 (0.8 ≤ β2 ≤ 1.2), and where M is aluminum, gallium, yttrium or tin. [8] A method of manufacturing the semiconductor device according to any one of claims 1, 4 and 6, wherein the oxide semiconductor film comprises a crystal part, and wherein the crystal part has an orientation with respect to the c-axis. [9] A method of manufacturing the semiconductor device according to claim 6, wherein the first temperature is lower than 340°C. [10] A method of manufacturing the semiconductor device according to claim 6, wherein the first temperature is higher than or equal to 100°C and lower than or equal to 200°C. [11] A method of manufacturing the semiconductor device according to any one of claims 1, 4 and 6, wherein the second temperature is lower than 375°C. [12] A method of manufacturing the semiconductor device according to any one of claims 1, 4 and 6, wherein the second temperature is higher than or equal to 340 °C and lower than or equal to 360 °C. [13] A method of manufacturing a semiconductor device, comprising the steps of: Forming an oxide semiconductor film (109) at a first temperature; processing the oxide semiconductor film (109) into an island shape (108); depositing a material (112) that becomes a source electrode (112a) and a drain electrode (112b) by a sputtering process over the oxide semiconductor film (108); processing the material (112) to form the source electrode (112a) and the drain electrode (112b); Forming an insulating protective film (114, 116) over the oxide semiconductor film (108), the source electrode (112a) and the drain electrode (112b); heating the insulating protective film (114, 116) at a second temperature higher than the first temperature; Forming a metal oxide film (113) over the insulating protective film (116); and Heating the insulating protective film (114, 116) at a third temperature which is higher than the first temperature, wherein the second temperature and / or the third temperature is / is the highest in the process; and wherein the insulating protective film has a multi-layer structure including a first insulating protective film and a second insulating protective film over the first insulating protective film. [14] A method of manufacturing the semiconductor device according to claim 13, wherein excess oxygen or an oxygen radical is added to the insulating protective film when the metal oxide film is formed, and wherein the excess oxygen or oxygen radical diffuses into the oxide semiconductor film when heating the insulating protective film at the third temperature. [15] A method of manufacturing a semiconductor device, comprising the steps of: Forming an oxide semiconductor film (109) at a first temperature; processing the oxide semiconductor film (109) into an island shape (108); depositing a material (112) that becomes a source electrode (112a) and a drain electrode (112b) by a sputtering process over the oxide semiconductor film (108); processing the material (112) to form the source electrode (112a) and the drain electrode (112b); Forming an insulating protective film (114, 116) over the oxide semiconductor film (108), the source electrode (112a) and the drain electrode (112b); heating the insulating protective film (114, 116) at a second temperature higher than the first temperature; and Forming a metal oxide film (131) over the insulating protective film (116) at a third temperature which is higher than the first temperature, wherein the second temperature and / or the third temperature is / is the highest in the process; and wherein the insulating protective film has a multi-layer structure including a first insulating protective film and a second insulating protective film over the first insulating protective film. [16] A method of manufacturing the semiconductor device according to claim 13 or 15, wherein the metal oxide film is an aluminum oxide film, a hafnium oxide film or an yttrium oxide film. [17] A method for manufacturing the semiconductor device according to claim 13 or 15, wherein the oxide semiconductor film has a multilayer structure of a first oxide semiconductor film having an atomic ratio of In:M:Zn = 4:α1 (1.5 ≤ α1 ≤ 2.5):α2 (2.5 ≤ α2 ≤ 3.5) and a second oxide semiconductor film having an atomic ratio of In:M:Zn = 1:β1 (0.8 ≤ β1 ≤ 1.2):β2 (0.8 ≤ β2 ≤ 1.2), and wherein M is aluminum, gallium, yttrium or tin. [18] A method of manufacturing the semiconductor device according to claim 13 or 15, wherein the oxide semiconductor film comprises a crystal part, and wherein the crystal part has an orientation with respect to the c-axis. [19] A method of manufacturing the semiconductor device according to claim 13 or 15, wherein the first temperature is lower than 340°C. [20] A method of manufacturing the semiconductor device according to claim 13 or 15, wherein the first temperature is higher than or equal to 100°C and lower than or equal to 200°C. [21] A method of manufacturing the semiconductor device according to claim 13 or 15, wherein the second temperature and / or the third temperature is / is lower than 375°C. [22] A method of manufacturing the semiconductor device according to claim 13 or 15, wherein the second temperature and / or the third temperature is higher than or equal to 340°C and lower than or equal to 360°C. [23] A method of manufacturing the semiconductor device according to claim 15, wherein excess oxygen or an oxygen radical is added to the insulating protective film when the metal oxide film is formed, and wherein oxygen, the excess oxygen or the oxygen radical diffuses from the insulating protective film into the oxide semiconductor film when the metal oxide film is formed.

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