Method for polishing both sides of a wafer, method for producing an epitaxial wafer and use thereof, and epitaxial wafer

Abstract

A method for polishing both sides of a wafer simultaneously, comprising: inserting a wafer into a holding hole of a double-side polishing carrier arranged between an upper lapping plate and a lower lapping plate, each of which has a polishing cloth attached thereto; and rotating the upper lapping plate and the lower lapping plate in a state where the wafer and the double-side polishing carrier are sandwiched between the upper lapping plate and the lower lapping plate; forming a chamfered portion at least on one of an upper corner and a lower corner of the holding hole of the double-side polishing carrier; and simultaneously polishing both sides of the wafer such that an edge drop is formed on the back surface of the wafer facing the side on which the chamfered portion is formed on the double-side polishing carrier.is larger than an edge drop on the front surface of the wafer.

Description

Technical field

[0001] The present invention relates to a double-side polishing carrier used in a double-side polishing process of a wafer, and a method of double-side polishing a wafer using the same. Furthermore, the present invention relates to an epitaxial wafer using a wafer polished by the double-side polishing process as a substrate material, and a manufacturing method thereof. Technical background

[0002] Silicon epitaxial wafers are widely used as a substrate material for semiconductor devices. A silicon epitaxial wafer has a silicon epitaxial layer formed on the surface of a bulk silicon wafer, and its crystal integrity is high, allowing it to be used to manufacture high-quality and reliable semiconductor devices.

[0003] The bulk silicon wafer, used as the substrate material of the silicon epitaxial wafer, is manufactured by sequentially subjecting a single-crystal silicon ingot grown by the Czochralski method to steps such as peripheral grinding, slicing, lapping, etching, double-side polishing, single-side polishing, cleaning, and so on. The double-side polishing step is a necessary step to polish the wafer to a certain thickness and increase wafer flatness. It is performed using a double-side polishing device to simultaneously polish both sides of the wafer.

[0004] For example, as a technique for double-side polishing processing, in order to suppress deterioration of wafer flatness after polishing, such as outer peripheral dropouts, Patent Document 1 describes polishing both sides of the wafer while maintaining the flatness of an inner peripheral surface of a plastic inserter of a wafer-holding carrier at 100 μm or less and a verticality of the inner peripheral surface at 5° or less. Patent Document 2 describes using a titanium carrier as a carrier for a double-side polishing apparatus to reduce outer peripheral dropouts in wafers polished on both sides and improve flatness, and setting its surface roughness Ra to 0.14 μm or more.

[0005] Ensuring flatness is also one of the important tasks for silicon epitaxial wafers. For example, to improve the flatness of silicon epitaxial wafers, Patent Document 3 describes measuring the flatness of a silicon wafer subjected to a first planarization process before forming the epitaxial layer, the flatness of an epitaxial wafer after forming the epitaxial layer, and the thickness distribution of the epitaxial layer, feeding these measured values ​​forward, and subjecting the epitaxial wafer to a second planarization process. Patent Document 4 further describes adjusting the inclination angle of a reflection element so that magnetic waves from a heating lamp group in an epitaxial growth apparatus guide the end portion of the wafer. Citation list[Patent documents] Patent Document 1: Japanese Patent Laid-Open Publication JP 2014-50913 A Patent Document 2: Japanese Patent Laid-Open Publication JP 2008-23617 A Patent Document 3: Japanese Patent Laid-Open Publication JP 2011-23422 A Patent Document 4: Japanese Patent Laid-Open Publication JP 2011-146 537 A Brief description of the invention [Problem to be solved by the invention]

[0006] As already mentioned, a high level of flatness is also required from an epitaxial wafer. As in Fig. 11, however, source gas supplied to the front surface of a silicon wafer W in an epitaxial growth furnace passes to the back surface of the wafer W through small gaps between the edge of the back surface of the silicon wafer W and a susceptor 33, whereby silicon also accumulates on an outer peripheral portion of the back surface of the silicon wafer W.

[0007] This results in, as in Fig. 12, at the outer peripheral portion on the back surface S B of the silicon wafer W, a backside silicon layer Eb is formed, whereby the flatness of the outer peripheral portion of the backside surface S B of the silicon epitaxial wafer EW deteriorates.

[0008] The present invention therefore aims to provide a manufacturing method for an epitaxial wafer that can easily produce an epitaxial wafer with increased back surface flatness. Another aim is to provide a wafer double-sided polishing method that can produce a silicon wafer well-suited as a substrate material for an epitaxial wafer, and a double-sided polishing carrier using the same. [Means of solving the task]

[0009] The inventor has found through intensive research to solve the above-mentioned problem that a method is effective in which, while predicting an accumulation amount of epitaxial silicon accumulating on the outer peripheral portion of the wafer back surface, edge drop is induced on the back surface of the wafer in advance, so that the deterioration of the flatness of the outer peripheral portion of the epitaxial wafer can be suppressed by canceling the thickness increase at the outer peripheral portion of the wafer due to the epitaxial growth and the edge drop.

[0010] For example, a method for adjusting the edge drop-off amount involves changing the polishing pad conditioning or polishing pressure. However, adjusting the edge drop-off amount by changing the polishing pad conditioning or polishing pressure also requires changing the grinding recipe, which also involves changing the polishing rate. This changes the overall shape of the wafer and makes it difficult to ensure the desired quality, which poses a major obstacle to mass production.

[0011] The present invention was made based on these technical circumstances, and a method for double-side polishing a wafer according to the invention for simultaneously polishing both surfaces of the wafer by inserting a wafer into a holding hole of a carrier for double-side polishing arranged between an upper lapping plate and a lower lapping plate, to each of which a polishing cloth is attached, and in a state where the wafer and the carrier for double-side polishing are sandwiched between the upper lapping plate and the lower lapping plate, the upper lapping plate and the lower lapping plate are rotated, wherein a chamfer portion is formed at least at one of the upper corner and the lower corner of the holding hole of the carrier for double-side polishing, and both sides of the wafer are simultaneously polished such that an edge drop on the back surface of the wafer facing the sideat which the chamfer portion is formed on the carrier for double-side polishing is larger than an edge drop on the front surface of the wafer.,

[0012] According to the present invention, a desired edge bevel can be selectively induced on the back surface of a wafer during a double-side polishing process. When the wafer is used as a substrate material for a silicon epitaxial wafer, the final flatness of the epitaxial wafer product after formation of the epitaxial layer can be increased.

[0013] In the present invention, the height dimension of the chamfered portion of the carrier for both sides polishing is preferably half the thickness of the carrier or less. In this case, the width dimension of the chamfered portion of the carrier for both sides polishing is preferably equal to the height dimension of the chamfered portion, and the height dimension and the width dimension of the chamfered portion are preferably 0.2 mm or more and 0.4 mm or less, respectively. In this way, the desired edge drop can be formed on the wafer while ensuring the wafer-holding function of the carrier.

[0014] In the present invention, the double-side polishing carrier includes a metal carrier main body having a circular opening larger than the diameter of the wafer, and an annular plastic inserter arranged along the inner periphery of the opening of the carrier main body. Preferably, the holding hole is the inner opening of the plastic inserter, and the chamfer portion is formed at least at one of the upper corner and the lower corner of the inner opening of the plastic inserter. Thus, even in the double-side polishing carrier having the plastic inserter, the desired edge bevel can be formed on the wafer while ensuring the wafer holding function.

[0015] In the present invention, the double-side polishing carrier preferably comprises a plastic carrier main body having a circular opening. The opening of the carrier main body serves as the holding hole, and the chamfer portion is formed at the opening. Thus, even in the double-side polishing carrier that does not have a plastic inserter formed separately from the carrier main body, the desired edge bevel can be formed on the wafer while ensuring the wafer holding function.

[0016] A method for manufacturing an epitaxial wafer is characterized in that a first epitaxial layer is formed on the entire front surface of the wafer polished in the method for polishing both sides of a wafer having the above-mentioned features, and a second epitaxial layer is formed on parts of the outer peripheral portion of the back surface of the wafer.

[0017] In the present invention, the second epitaxial layer has a thickness distribution that compensates for the edge drop on the back surface of the wafer. The deterioration of the flatness of the outer peripheral portion of the epitaxial wafer can be prevented by canceling the thickness increase at the outer peripheral portion of the wafer due to epitaxial growth and the edge drop.

[0018] Furthermore, the epitaxial wafer according to the present invention comprises a wafer whose back-side edge drop is larger than its front-side edge drop, a first epitaxial layer formed on the entire front surface of the wafer, and a second epitaxial layer formed on parts of the outer peripheral portion of the back surface of the wafer, wherein the flatness of the outer peripheral portion of the wafer where the second epitaxial layer is formed is higher than the flatness of the outer peripheral portion of the wafer where the second epitaxial layer is not formed. According to the present invention, an epitaxial wafer can be provided whose final flatness is increased after forming the epitaxial layer.

[0019] In the present invention, the second epitaxial layer has a thickness distribution that compensates for the edge drop on the back surface of the wafer. The deterioration of the flatness of the outer peripheral portion of the epitaxial wafer can be prevented by canceling the thickness increase at the outer peripheral portion of the wafer due to epitaxial growth and the edge drop.

[0020] In the present invention, the wafer is preferably a silicon wafer, and the first and second epitaxial layers are silicon epitaxial layers. In this way, the flatness of the back surface of the silicon epitaxial wafer can be increased. [Effect of the invention]

[0021] According to the present invention, it is possible to provide a double-side polishing carrier and a wafer polishing method using the same, which can selectively induce a desired edge drop without substantially changing the polishing conditions, thereby increasing the flatness near the edge of the final wafer product after forming the epitaxial layer. According to the present invention, a method for producing an epitaxial wafer can be provided in which the flatness can be increased using a wafer polished by the wafer polishing method. Short description of the characters [ Fig. 1] Fig. 1 is a schematic side sectional view illustrating the structure of a double-sided polishing apparatus of an embodiment of the invention. [ Fig. 2] Fig. 2 is a plan view of the double-sided polishing device of Fig. 1. [ Fig. 3] Fig. 3 are views illustrating the structure of the carrier, where Fig. 3A a top view, Fig. 3B a lateral sectional view and Fig. 3C is an enlarged partial view near the inner peripheral surface of the holding hole. [ Fig. 4] Fig. 4 is a schematic view for explaining a mechanism for promoting edge waste by chamfering the holding hole of the carrier. [ Fig. 5] Fig. 5 is a sectional view illustrating the shape of a silicon wafer after double-side polishing. [ Fig. 6] Fig. 6 is a sectional view illustrating an example of the structure of an epitaxial growth apparatus used for manufacturing a silicon epitaxial wafer. [ Fig. 7] Fig. 7 is a sectional view of a silicon epitaxial wafer according to the present embodiment. [ Fig. 8] Fig. 8 is a graph illustrating the relationship between a chamfer shape of the holding hole and the flatness of the wafer. [ Fig. 9] Fig. 9A and Fig. 9B are graphs illustrating measurement results of ZDD of the front and back surfaces of wafer samples. [ Fig. 10] Fig. 10A and Fig. 10B are graphs illustrating height profiles of the back surface of the epitaxial wafer. [ Fig. 11] Fig. 11 is a schematic view for explaining an accumulation mechanism of silicon on the back surface of the wafer during epitaxial growth. [ Fig. 12] Fig. 12 is a sectional view illustrating the shape of a prior art silicon epitaxial wafer with deteriorated flatness of the outer peripheral portion. Detailed description of the embodiments

[0022] Preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0023] Fig. 1 is a schematic side sectional view illustrating the structure of a double-sided polishing apparatus of an embodiment of the invention. Fig. 2 is a plan view of the double-sided polishing device of Fig. 1, where Fig. 1 a sectional view along a line RR' from Fig. 2 is.

[0024] As in Fig. 1 and Fig. 2, the double-side polishing apparatus 1 includes an upper lapping plate 2 and a lower lapping plate 3 that oppose each other in the vertical direction, with polishing cloths 4 and 5 attached to the lower surface of the upper lapping plate 2 and the upper surface of the lower lapping plate 3, respectively. A sun gear 6 is provided in the central portion between the upper lapping plate 2 and the lower lapping plate 3, and a ring gear 7 is provided at the peripheral edge portion. A silicon wafer W is sandwiched between the upper lapping plate 2 and the lower lapping plate 3 in a state of being inserted into the holding hole 10a of the double-side polishing carrier 10.

[0025] As in Fig. 2, five carriers 10 are provided on the circumference of the sun gear 6, wherein outer peripheral teeth 10b of each carrier 10 engage with tooth portions on the sun gear 6 and the ring gear 7, and by rotationally driving the upper lapping plate 2 and the lower lapping plate 3 by a drive source (not shown), the carriers 10 rotate around the circumference of the sun gear 6. At this time, the silicon wafer W inserted into the holding hole 10a of the carrier 10 is held by the carrier 10 and polished simultaneously on both sides by contact with the polishing cloths 4, 5. During polishing, polishing liquid is discharged from a nozzle (not shown). As the polishing liquid, for example, an alkaline liquid in which colloidal silicon oxide is dispersed can be used.

[0026] Fig. 3 shows views illustrating the structure of the carrier 10, wherein (a) is a plan view, (b) is a side sectional view, and (c) is an enlarged partial view near the inner peripheral surface of the holding hole of the carrier 10.

[0027] As in Fig. 3A and Fig. 3B, the carrier 10 comprises a metal carrier main body 11 having a circular opening 11a larger than the silicon wafer W, and an annular plastic inserter 12 arranged along the inner circumference of the opening 11a of the carrier main body 11.

[0028] The carrier main body 11 is a round, disc-shaped member, and outer peripheral teeth 11b are provided on its outer peripheral portion. A representative material for the carrier main body 11 is SUS, but titanium or other metal materials may also be used. A thickness D of the carrier main body 11 is set based on a target thickness of the wafer W after double-side polishing. For example, the thickness of a carrier 10 for a wafer with a diameter of 300 mm is set to 0.8 mm, and a wafer W with a thickness of about 1 mm is subjected to a standard polishing process before processing until it is approximately the same thickness as the carrier 10.The center position of the opening 11a is offset from the center position of the carrier main body 11, and the wafer W inserted into the opening 11a moves eccentrically around the center of the carrier main body 11, thereby increasing the polishing efficiency and the uniformity of the polishing process.

[0029] The plastic inserter 12 is arranged between the outer peripheral surface of the wafer W and the inner peripheral surface of the opening 11a of the carrier main body 11 and serves to prevent contact between the two. An inner opening 12a of the plastic inserter 12 forms the holding hole 10a of the carrier 10 (see Fig. 2), and the outer peripheral surface of the wafer W is in contact with the inner peripheral surface of the plastic inserter 12. The width (ring width) of the plastic inserter 12 is, for example, 1.5 mm and is determined by taking into account the size of the opening 11a of the carrier main body 11 and the size of the wafer W. The thickness of the plastic inserter 12 preferably corresponds to the thickness D of the carrier main body 11.

[0030] As in Fig. 3C, is at a bottom corner C CB an inner peripheral portion of the inner opening 12a of the plastic inserter 12, a chamfered portion 12c is formed. In the present embodiment, only the bottom corner C CB the inner peripheral surface of the inner opening 12a of the plastic inserter 12 is chamfered, but the upper corner C CFchamfered. That is, the chamfered portion 12c may be formed at one of the upper and lower corners of the inner peripheral portion of the wafer holding hole 10a of the carrier 10. As explained in more detail below, by chamfering the wafer holding hole 10a in this way, the edge drop on a side surface of the wafer W can be selectively increased.

[0031] Preferably, the height dimension h1 and the width dimension h2 of the chamfered portion 12c are both set to 0.1 mm or more. If the height dimension h1 and the width dimension h2 are less than 0.1 mm, no effect can be achieved by the chamfered portion 12c, and chamfering processing is extremely difficult from the aspect of processing accuracy.

[0032] It is also preferable that the height dimension h1 of the chamfered portion 12c is half the thickness of the beam 10 or less (h ı≤D / 2), while the width dimension h2 is preferably equal to or smaller than the horizontal width of the plastic inserter 12. Therefore, when the thickness of the carrier 10 is, for example, 0.8 mm, the height dimension h1 of the chamfered portion 12c is preferably 0.4 mm or less, and when the horizontal width of the plastic inserter 12 is 1.5 mm, the width dimension h2 of the chamfered portion 12c is preferably 1.5 mm or less. If the height dimension h1 of the chamfered portion 12c is more than half the thickness D of the carrier 10, the edge drop becomes too large, so that the desired flatness cannot be ensured after forming the epitaxial layer, and there is also a risk of impairing the holding function of the wafer W.The reason for this is that when the width dimension h2 of the chamfer portion 12c is larger than the horizontal width of the plastic inserter 12, the thickness of the plastic inserter 12 decreases, thereby increasing the edge drop on the wafer W.

[0033] For the chamfer portion 12c, a chamfer of C0.2 to C0.4 is particularly preferred. By adjusting the height dimension h1 and the width dimension h2 to make the chamfer angle of the chamfer portion 12c 45 degrees, chamfering processing can be simplified and processing accuracy can be increased. By keeping the height dimension h1 and the width dimension h2 of the chamfer portion 12c both within a range of 0.2 to 0.4 mm, edge drop can be achieved, which compensates for the amount of silicon accumulation on the back surface of the wafer during the epitaxial process.

[0034] Fig. 4 is a schematic view for explaining a mechanism for promoting edge waste by chamfering the holding hole 10a of the carrier 10.

[0035] On the front surface S F of the wafer W, where the corner of the holding hole 10a is not chamfered, the edge drop of the wafer W is improved due to the holding action of the carrier 10 (counterforce with respect to the polishing cloth), as in a conventional carrier, so that the flatness of the outer peripheral portion of the wafer W is increased. On the back surface S BOn the other hand, at the portion of the wafer W where the corner of the holding hole 10a is chamfered, the holding effect decreases due to the presence of the chamfered portion 12c, thereby suppressing the edge drop improvement effect and decreasing the flatness of the outer peripheral portion of the wafer W. The upward arrow in the figure shows that the reaction force of the carrier 10 with respect to the polishing cloth 4 is high, and the downward arrow shows that the reaction force of the carrier 10 with respect to the polishing cloth 5 is low.

[0036] Fig. 5 is a schematic sectional view illustrating the shape of a silicon wafer W after double-side polishing.

[0037] As in Fig. 5, the outer peripheral portion shape of the silicon wafer W after the double-side polishing is such that the edge drop at the corner C WF on the front surface S F is low and the edge drop at corner C WBon the back surface S B is large. When such a wafer W is used as a substrate material for a silicon epitaxial wafer, the thickness increase can be compensated by the thickness increase formed on the outer peripheral portion of the back surface S B of the wafer W can be compensated, whereby the flatness of the outer peripheral portion of the back surface of the silicon epitaxial wafer can be increased.

[0038] Fig. 6 is a sectional view illustrating an example of the structure of an epitaxial growth apparatus used for manufacturing a silicon epitaxial wafer.

[0039] As in Fig. As shown in Figure 6, the epitaxial growth apparatus 30 is a single-processing type apparatus that processes one silicon wafer W at a time, and includes a chamber 31 formed of quartz glass and a lid member 32 covering the chamber 31 from above. A susceptor 33 for supporting the wafer and a preheating ring 34 are provided in the chamber 31, and the susceptor 33 is supported on a support shaft 35. A gas introduction port 36, a baffle 37, and a planarization member 38 are provided at one side portion of the chamber 31, and a gas exhaust port 39 is provided at the other, opposite end portion.

[0040] Above the lid member 32, an upper lamp 40 is provided, which heats the silicon wafer W arranged on the susceptor 33. Below the susceptor 33, a lower lamp 41 is provided, which heats the silicon wafer W from below.

[0041] In the production of an epitaxial wafer using the epitaxial growth apparatus 30 constructed in this way, the silicon wafer W is placed on the susceptor 33, whereupon the wafer W is heated by the upper lamp 40 and the lower lamp 41, while trichlorosilane (SiHCl3) or dichlorosilane (SiH2Cl2) or another source gas is introduced into the chamber 31 through the gas introduction port 36 while being vented through the gas outlet port 39.

[0042] The source gas passes from the gas introduction port 36 through the baffle 37 and the planarization member 38 and flows into the upper space 31a of the chamber 31. The upper lamp 40 and the lower lamp 41 heat the wafer W, the susceptor 33, and the preheating ring 34, and as the source gas flows along the front surface of the heated wafer W as a laminar flow, epitaxial growth occurs on the front surface of the wafer W, thereby forming an epitaxial layer.

[0043] As in Fig. As shown in Fig. 11, the edge of the back surface of the silicon wafer W is in line contact with the front surface of the susceptor 33, but small gaps formed by slight protrusions and depressions exist between the two. As source gas passes through these gaps to the back surface of a wafer W, silicon accumulates on the outer peripheral portion of the back surface of the wafer W. However, since the silicon accumulation on the outer peripheral portion of the wafer W is compensated by the edge drop of the wafer back surface, the outer peripheral portion of the back surface has a flat shape, so that even if silicon accumulates on the outer peripheral portion of the back surface of the wafer W, the flatness of the back surface of the wafer is not impaired.

[0044] Fig. 7 shows a sectional view of the silicon epitaxial wafer according to the present embodiment.

[0045] As in Fig. As shown in Figure 7, the silicon epitaxial wafer EW comprises a silicon wafer W whose edge drop on the back surface S B larger than on the front surface S F is (see Fig. 5), and a silicon epitaxial layer Ea, which is deposited on the entire front surface S F of the silicon wafer W. In addition, on parts of the outer peripheral portion of the back surface S B of the silicon wafer W, a backside silicon layer Eb is formed. By forming the backside silicon layer Eb in a suitable thickness distribution to reduce the edge drop on the backside surface S B of the silicon wafer W, the flatness of the outer peripheral portion on the back surface of the silicon epitaxial wafer EW is increased.

[0046] As explained above, in the double-side polishing carrier 10, the chamfered portion 12c is provided at the corner of the holding hole 10a so that a predetermined edge drop can be selectively introduced at the outer peripheral portion of the wafer W. In this way, when the wafer W whose edge drop has been adjusted on one side is used to manufacture the epitaxial wafer EW, the phenomenon of excessive thickness increase due to accumulation of epitaxial silicon at the outer peripheral portion of its back surface can be suppressed, whereby the flatness of the outer peripheral portion of the back surface of the silicon epitaxial wafer EW can be increased.

[0047] The above description has been made with reference to a preferred embodiment of the present invention, but it should be understood that the present invention is not limited to the described embodiment and various changes can be made thereto without departing from the scope of the present invention, and these changes are of course also within the scope of the present invention.

[0048] For example, in the above-described embodiment, the example of a carrier 10 having a metal carrier main body 11 and a plastic inserter 12 was cited, but the carrier main body 11 may also be made of plastic, and the plastic inserter 12 may be omitted. In this case, the opening 11a of the carrier main body 11 is the wafer holding hole 10a, and the corner of the opening 11a of the carrier main body 11 is chamfered.

[0049] In the above-described embodiment, a single carrier 10 has each holding hole 10a and holds a single wafer W, but a single carrier 10 may have multiple holding holes. In this case, the individual holding holes are subjected to chamfering. Also, the structure of the double-side polishing apparatus 1 is merely an example, and various types can be applied.

[0050] In the above-described embodiment, taking into account the increase in the flatness of the outer peripheral portion for the front surface S F of the silicon wafer W and the adhesion of silicon to the outer peripheral portion of the back surface in the epitaxial step for the back surface S Bof the wafer W, the corner on one side of the holding hole 10a (back surface of the wafer W) is chamfered, but the corners on both sides of the holding hole 10a may also be chamfered. This is an effective measure if the outer peripheral portion of the front surface S F of the wafer W tends to accumulate silicon.

[0051] In the embodiment described above, it was described that a silicon epitaxial wafer is manufactured using a silicon wafer that has been both-side polished using the both-side polishing carrier of the present invention, but the present invention is not limited to a both-side polishing processing of a silicon wafer, but can be applied to a both-side polishing processing of different wafers. [Example]

[0052] The influence of the chamfer shape of the holding hole 10a of the carrier 10 on the flatness of the silicon wafer W after polishing was evaluated. In the evaluation experiment, the GBIR (Global Back Reference Ideal Range) and ESFQD (Edge Site Flatness Front Reference Least Square Deviation) metrics were measured on a wafer sample of a comparative example, a silicon wafer with a diameter of 300 mm obtained by double-side polishing using a carrier 10 on which no chamfering was performed on the holding hole 10a. A flatness measuring device (WaferSight 2, manufactured by KLA-Tencor) was used for these measurements.

[0053] In addition, GBIR and ESFQD were also measured on wafer samples according to Example 1 and Example 2 obtained by both-side polishing under the same conditions as in Comparative Example except that a carrier 10 was used on whose holding hole 10a a chamfer of C0.2 and C0.3 had been performed, respectively.

[0054] GBIR is an index of the global flatness of the wafer, while ESFQD is an index of the local flatness at the outer peripheral portion of the wafer (edge). In the case of ESFQD, the outer peripheral portion of the wafer is divided into a plurality of (for example, 72) fan-shaped regions (sites). It is based on the inner area of ​​the sites, which is calculated from the data within the sites using the least-squares method. It is the maximum displacement amount, including the sign, from these site inner areas, and has one data set per site. That is, ESFQD is the SFQD value of each site (whichever is greater than the positive or negative deviation from the least-squares area within the site).From ESFQD sites, a region of 2 mm in the radial direction from the outermost circumference is excluded, and it is an approximately rectangular region surrounded by two straight lines with a sector length of 30 mm extending from the outer circumference reference end inside it in the radial direction to the center, and a circular arc corresponding to 5° (±2.5°) in the wafer outer circumference direction.

[0055] Fig. Figure 8 is a graph illustrating the relationship between a chamfer shape of the holding hole and wafer flatness. The horizontal axis represents the overall shape and the vertical axis represents ESFQD. The quadrilateral in the figure indicates the range where the target range for both the overall shape and ESFQD is satisfied. The overall shape is the GBIR value considering the unevenness concept. That is, the profile resulting from the GBIR measurement (overall shape) is observed. If it is convex, the curve turns to the positive side, and if it is concave, the curve turns to the negative side, thus representing the GBIR value on the horizontal axis.

[0056] As in Fig. As shown in Figure 8, in the wafer of Comparative Example, which was both-side polished using the carrier 10 whose holding hole 10a was not subjected to chamfering, it is difficult to keep both the overall shape and ESFQD within the target range. In contrast, in the wafers of Example 1 and Example 2, which were both-side polished using the carrier whose holding hole was subjected to chamfering of C0.2 and C0.3, it is possible to keep both the overall shape and ESFQD within the target range.

[0057] Next, ZDD (Z-height double differentiation) was measured on the front and back surfaces of the wafer sample after double-side polishing. ZDD is an index of the tilt change (curvature) near the edge, obtained from the second-order differential of the displacement profile of the wafer's top surface from the wafer center to the outermost periphery. If ZDD is positive, the surface has displaced in the warp direction, and if ZDD is negative, the surface has displaced in the warp direction.

[0058] Fig. 9A and Fig. 9B are graphs illustrating measurement results of ZDD of the front surface and the back surface of wafer samples.

[0059] As in Fig. 9A, ZDD on the front surface of the wafer is the same and substantially unchanged in Comparative Example, Example 1, and Example 2. As shown in Fig. 9B, ZDD is smallest on the back surface of the wafer in the comparative example and increases from example 1 to example 2.

[0060] Next, after forming a 2.75 µm thin silicon epitaxial layer on the front surface of the silicon wafers W of Comparative Example and Example 1, the flatness of the back surface of the silicon epitaxial wafer was measured.

[0061] Fig. 10A and Fig. 10B are graphs showing the height profile of the back surface of epitaxial wafers EW, where the horizontal axis represents the distance from the wafer center in the radial direction (mm) and the vertical axis represents the height of the reference plane (nm). Fig. 10A shows the flatness of the wafer of the comparative example, and Fig. 10B the flatness of the wafer of Example 1. Line A in Fig. 10A and Fig. 10B shows the height profile of the back surface of the epitaxial wafer EW before epitaxial growth, line B shows the height profile of the back surface of the epitaxial wafer EW after epitaxial growth, and line C shows the silicon accumulation amount profile of the back surface of the epitaxial wafer EW.

[0062] As in Fig. 10A and Fig. 10B, in the height profile A of the back surface of the epitaxial wafer EW before epitaxial growth, the edge drop of the first embodiment ( Fig. 10B) larger than in the comparison example ( Fig. 10A), while in the height profile B of the back surface of the epitaxial wafer EW after epitaxial growth, the accumulation of the epitaxial layer on the back and the edge drop compensate each other, so that the flatness in the first embodiment ( Fig. 10B) larger than in the comparison example ( Fig.10A). This confirms that controlling the double-side polishing conditions such that the edge drop on the back surface of the silicon wafer is matched to the back epitaxial layer before forming the epitaxial layer enables high flatness of the back surface of the silicon epitaxial wafer. [List of reference symbols] 1 double-sided polishing device 2 upper lapping plate 3 lower lapping plate 4 polishing cloths 5 polishing cloths 6 Sun gear 7 ring gear 10 carriers for double-sided polishing 10a holding hole (wafer holding hole) 10b Outer peripheral teeth of the carrier 11 Main support body 11a Opening of the main carrier body 11b Outer peripheral teeth of the carrier main body (outer peripheral teeth of the carrier) 12 plastic inserters 12a inner opening of the plastic inserter 12c chamfering section 30 Epitaxial growth device 31 Chamber 31a upper room 32 cover element 33 Susceptor 34 Preheating ring 35 Bearing shaft 36 Gas inlet opening 37 Baffle 38 Planarization element 39 Gas outlet opening 40 upper lamp 41 lower lamp C CB bottom corner of the retaining hole C CF top corner of the retaining hole C WB bottom corner of the wafer C WF top corner of the wafer Ea silicon epitaxial layer Eb backside silicon layer EW silicon epitaxial wafer (epitaxial wafer) h1 Height dimension of the chamfer section h2 Width dimension of the chamfer section S B Back surface of the wafer S F Front surface of the wafer In Silicon wafer (Substrate material)

Claims

[1] A method for polishing both sides of a wafer simultaneously by inserting a wafer into a holding hole of a double-side polishing carrier arranged between an upper lapping plate and a lower lapping plate, each of which has a polishing cloth attached thereto, and rotating the upper lapping plate and the lower lapping plate in a state where the wafer and the double-side polishing carrier are sandwiched between the upper lapping plate and the lower lapping plate, a chamfered portion is formed at least at one of an upper corner and a lower corner of the holding hole of the double-side polishing carrier, and simultaneously polishing both sides of the wafer such that an edge drop is formed on the back surface of the wafer facing the side on which the chamfered portion is formed on the double-side polishing carrier.is larger than an edge drop on the front surface of the wafer. [2] The method for both-side polishing a wafer according to claim 1, wherein the height dimension of the chamfer portion of the both-side polishing carrier is preferably half the thickness of the carrier or less. [3] The method for both-side polishing a wafer according to claim 2, wherein a width dimension of the chamfer portion of the both-side polishing carrier is equal to the height dimension of the chamfer portion. [4] The method for both-side polishing a wafer according to claim 3, wherein the height dimension and the width dimension of the chamfer portion of the both-side polishing carrier are both 0.2 mm or more and 0.4 mm or less. [5] A method for polishing both sides of a wafer according to any one of claims 1 to 4, wherein the carrier for polishing both sides comprises a carrier main body made of metal having a circular opening larger than the diameter of the wafer, and an annular plastic inserter arranged along the inner circumference of the opening of the carrier main body, the holding hole being the inner opening of the plastic inserter, and the chamfering portion being formed on the plastic inserter. [6] The method for both-side polishing a wafer according to any one of claims 1 to 4, wherein the carrier for both-side polishing is a carrier main body made of plastic having a circular opening, the opening of the carrier main body is the holding hole, and the chamfer portion is formed at the opening. [7] Method for producing an epitaxial wafer, characterized bythat a first epitaxial layer is formed on the entire front surface of a wafer polished in the method for polishing both sides of a wafer according to any one of claims 1 to 6, and a second epitaxial layer is formed on parts of the outer peripheral portion of the back surface of the wafer. [8] A method of manufacturing an epitaxial wafer according to claim 7, wherein the second epitaxial layer has a thickness distribution that compensates for the edge drop on the back surface of the wafer. [9] A method of manufacturing an epitaxial wafer according to claim 7 or 8, wherein the wafer is a silicon wafer and the first and second epitaxial layers are silicon epitaxial layers. [10] An epitaxial wafer comprising a wafer whose back edge drop is larger than its front edge drop, a first epitaxial layer formed on the entire front surface of the wafer, and a second epitaxial layer formed on parts of the outer peripheral portion of the back surface of the wafer, wherein the flatness of the outer peripheral portion of the wafer where the second epitaxial layer is formed is higher than the flatness of the outer peripheral portion of the wafer where the second epitaxial layer is not formed. [11] The epitaxial wafer of claim 10, wherein the second epitaxial layer has a thickness distribution that compensates for the edge drop on the back surface of the wafer. [12] The epitaxial wafer of claim 10 or 11, wherein the wafer is a silicon wafer and the first and second epitaxial layers are silicon epitaxial layers.

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