SEMICONDUCTOR DEVICE

Abstract

Semiconductor device comprising: - a semiconductor substrate (1) which has a front and a back side that are opposite each other; - a first metal layer (2) which is formed on the front side of the semiconductor substrate (1); - a second metal layer (3) for soldering, which is formed on the first metal layer (2); - a third metal layer (5) which is formed on the back side of the semiconductor substrate (1); and - a fourth metal layer (6) for soldering, which is formed on the third metal layer (5), wherein: - the second metal layer (3) has a greater thickness than the fourth metal layer (6), - the first and third metal layers (2, 5) are not divided into a pattern, - the second metal layer (3) is divided into a pattern and has a plurality of metal layers which are electrically connected to each other via the first metal layer (2), - the fourth metal layer (6) is divided into a pattern and has a plurality of metal layers which are electrically connected to each other via the third metal layer (5), and - the number of subdivided parts of the second metal layer (3) is greater than the number of subdivided parts of the fourth metal layer (6).

Description

Area

[0001] The present invention relates to a semiconductor device in which metal layers for soldering are formed on both a front and a back side of a substrate. background

[0002] MOSFETs, IGBTs, or diodes with high voltage withstand capability are used as power semiconductor devices. Desirable requirements for a power semiconductor device include advantageous electrical properties such as low power loss, high damage tolerance, and small size, as well as low cost. Grinding semiconductor substrates to reduce thickness is a current trend in an attempt to achieve both advantageous electrical properties and a reduction in the chip unit price. A common design for a power semiconductor has traditionally involved forming a metal layer on one of the back electrodes of a semiconductor substrate to react with a solder for soldering, while a metal wire connection for both electrodes was implemented on the front side.However, it is increasingly the case that metal layers for soldering are formed on both the front and back sides of a substrate, and that soldering is carried out on both sides, with the aim of achieving low power loss and size reduction.

[0003] Publication JP 2013 - 194 291 A discloses a semiconductor device and a method for its fabrication, for example in connection with an IGBT, in which warping or deformation due to the effects of thermal stress or the like is suppressed, particularly when an electrically conductive metal layer is formed, which is provided on the front and back of a wafer and is intended to exhibit particularly good wetting properties. Furthermore, no crystalline structure should be present in a coating layer corresponding to a change in temperature or voltage, and no cracks or the like should be caused in a coating due to the formation of grain boundary voids.To solve this, an amorphous electroless Ni coating layer and an electroless Au coating layer are formed on a first main electrode, which is provided on a first main surface of a semiconductor substrate, and on a second main electrode, which is provided on a second main surface.

[0004] The publication JP S64 - 20 752 U relates to a thin-film solar cell in which a large number of slot-like notches are provided on the back electrode of the thin-film solar cell using the silicon substrate.

[0005] US patent 2015 / 0155608A1 discloses an electrode structure for preventing cracking in a metal electrode due to heating during the manufacturing process when stacking an insulating resin and the metal electrode with different coefficients of thermal expansion. An electrode for a semiconductor circuit, stacked on an insulating resin substrate, has an electrode structure consisting of a main electrode with a slot created by cutting out a portion of the main electrode to prevent cracking during the manufacturing process due to the different coefficients of thermal expansion with the substrate, and an auxiliary electrode that covers the slot in the main electrode. Instead of a slot, a bridge is formed at the point where the slot in the main electrode and the slot in the auxiliary electrode overlap, thus avoiding an area without an electrode.

[0006] The publication LIN, CS [et al.]: Structural Evolution and Internal Stress of Nickel-Phosphorous Electrodeposits. In: Journal of The Electrochemical Society, Vol. 152, 2005, C370 - C375, describes properties of nickel-phosphorus or Ni-P electrodeposits that are best related to their phosphorus content and microstructure. The microstructural evolution and mechanical properties of the deposits, which are produced from nickel sulfamate baths with 0 to 40 g / dm³, are investigated. 3Phosphoric acid (H3PO3) was used to deposit the nickel. The experimental results show that coarse nickel grains were significantly refined by the incorporation of phosphorus into the deposit. For example, with increasing phosphorus content from 0 to 14 wt%, the structure of the deposit changed stepwise from a coarse columnar structure to a mixture of columns and lamellae, then to a pronounced lamellar structure, and finally to a homogeneous, amorphous matrix with dispersed nanograins. Parallel to this structural evolution, the deposit showed a significant change in hardness and internal stress. These properties and the relationships between microstructure and deposit are discussed with regard to lattice defects in the grains and proton discharges during electroplating. Summary Technical Problem

[0007] When the thickness or material of metal layers differs between the front and back sides of a semiconductor substrate, distortion of the substrate has been a common problem, causing cracks or voids in the solder and adversely affecting assembly. The trend of grinding semiconductor substrates to make them thinner has exacerbated this problem, making distortion more pronounced. A method has been disclosed in which the metal layers formed on both sides are heat-treated to crystallize for soldering, thus counteracting the stress applied from both sides and the resulting distortion (see, for example, JP 2015-53455A4). However, this method requires a heat treatment process after the metal layers have formed on the front side.Another problem is a deterioration in the assembly capability, as the metal layers oxidize and impair solder wettability during assembly.

[0008] The present invention was implemented to solve the problem described above, and it is an object of the invention to realize a semiconductor device that improves assembly capability without causing oxidation of the metal layers for soldering. Solution to the problem

[0009] The problem underlying the invention is solved according to the invention in a semiconductor device by the features of claim 1 and alternatively in a semiconductor device by the features of claim 3. Advantageous embodiments are the subject of the respective dependent claims.

[0010] A semiconductor device according to one aspect of the present invention comprises: a semiconductor substrate having a front and a back side opposite each other; a first metal layer formed on the front side of the semiconductor substrate; a second metal layer for soldering formed on the first metal layer; a third metal layer formed on the back side of the semiconductor substrate; and a fourth metal layer for soldering formed on the third metal layer, wherein the second metal layer has a greater thickness than the fourth metal layer, wherein the first and third metal layers are not divided into a pattern, and the second metal layer is divided into a pattern and has a plurality of metal layers electrically connected to each other via the first metal layer.The fourth metal layer is divided into a pattern and has multiple metal layers that are electrically connected to each other via the third metal layer. The number of subdivided parts of the second metal layer is greater than the number of subdivided parts of the fourth metal layer. Advantageous effects of the invention

[0011] In the present invention, the second metal layer is divided into a pattern, while the first, third, and fourth metal layers are not divided into a pattern. The stress generated when the thick second metal layer expands or contracts due to a temperature change is therefore absorbed by the gaps in the pattern. This reduces the stress on the semiconductor substrate and minimizes distortion of the semiconductor substrate. Consequently, assembly properties can be improved. Brief description of the characters Fig. Figure 1 is a cross-sectional view illustrating a semiconductor device according to embodiment 1 of the present invention. Fig. Figure 2 is a cross-sectional view illustrating a semiconductor device according to the comparison example. Fig. Figure 3 is a cross-sectional view illustrating a semiconductor device according to embodiment 2 of the present invention. Fig. Figure 4 is a cross-sectional view illustrating a semiconductor device according to embodiment 3 of the present invention. Description of the embodiments

[0012] A semiconductor device according to the embodiments of the present invention is described with reference to the figures. The same components are identified by the same reference numerals, and their repeated description is omitted. Design 1

[0013] Fig. Figure 1 is a cross-sectional view illustrating a semiconductor device according to embodiment 1 of the present invention. A semiconductor substrate 1 has a front and a back side, which are opposite each other. A first metal layer 2 is formed on the front side of the semiconductor substrate 1 such that it is in direct contact with the front side of the semiconductor substrate 1 and is electrically connected to it. The first metal layer 2 is, for example, an emitter electrode of an IGBT or an anode electrode of a diode. The second metal layer 3 for soldering is formed on the first metal layer 2. A metal layer 4 is formed on the second metal layer 3 to prevent oxidation of the second metal layer 3.

[0014] A third metal layer 5 is formed on the back side of the semiconductor substrate 1 such that it is in direct contact with the back side of the semiconductor substrate 1 and electrically connected to it. The third metal layer 5 is, for example, a collector electrode of an IGBT or a cathode electrode of a diode. A fourth metal layer 6 for soldering is formed on the third metal layer 5. A metal layer 7 is formed on the fourth metal layer 6 to prevent oxidation of the fourth metal layer 6.

[0015] The second metal layer 3 has a greater thickness than the fourth metal layer 6. The second and fourth metal layers 3 and 6, intended for soldering, contain the least nickel and have a higher solder wettability than the first and third metal layers 2 and 5. The first, third, and fourth metal layers 2, 5, and 6 are uniformly distributed on the front or back of the semiconductor substrate 1 and are not divided into a pattern. The second metal layer 3 is divided into a pattern and has multiple metal layers electrically connected to each other via the first metal layer 2.

[0016] Next, the effects of this embodiment will be described in comparison to a comparative example. Fig. Figure 2 is a cross-sectional view illustrating a semiconductor device according to the comparative example. The second and fourth metal layers 3 and 6 expand as the temperature increases and contract as the temperature decreases. In the comparative example, the thick second metal layer 3 on the front side is uniformly distributed across the front of the semiconductor substrate 1 and is not divided into a pattern. Therefore, the expansion and contraction due to temperature changes occur more strongly in the thick second metal layer 3 on the front side than in the fourth metal layer 6 on the back side.This results in a difference between the stress introduced by the second metal layer 3 on the front side of the semiconductor substrate 1 and the stress introduced by the fourth metal layer 6 on the back side of the semiconductor substrate 1, which results in a warping of the semiconductor substrate 1.

[0017] In contrast to other embodiments, the first, third, and fourth metal layers 2, 5, and 6 are not divided into a pattern, while the second metal layer 3 is divided into a pattern. The stress generated when the thick second metal layer 3 expands or contracts due to temperature changes is therefore mitigated by the gaps in the pattern. This reduces the stress on the semiconductor substrate 1 and minimizes distortion. Since there is no need to crystallize the second and fourth metal layers 3 and 6 by means of heat treatment to mitigate stress, solder wettability is not impaired by oxidation. Consequently, assembly properties can be improved. Design 2

[0018] Fig. Figure 3 is a cross-sectional view illustrating a semiconductor device according to embodiment 2 of the present invention. In contrast to embodiment 1, the second and fourth metal layers 3 and 6 are both divided into a pattern. Specifically, the second metal layer 3 is divided into a pattern and has a plurality of metal layers electrically connected to each other via the first metal layer 2. The fourth metal layer 6 is also divided into a pattern and has a plurality of metal layers electrically connected to each other via the third metal layer 5.

[0019] The number of subdivided parts A of the second metal layer 3 is greater than the number of subdivided parts B of the fourth metal layer 6 (A > B). The stress generated on the front side is absorbed more easily than the stress generated on the back side. Therefore, the difference between these stresses experienced by the semiconductor substrate 1 can be reduced, and thus warping of the semiconductor substrate 1 can be minimized. Consequently, assembly capability can be improved. embodiment 3

[0020] Fig.Figure 4 is a cross-sectional view illustrating a semiconductor device according to embodiment 3 of the present invention. In contrast to embodiment 1, the second metal layer 3 is formed uniformly on the front face of the semiconductor substrate 1 and is not divided into a pattern. The second and fourth metal layers 3 and 6 are formed by electroless coating with amorphous nickel comprising phosphorus.

[0021] Nickel is commonly used as a soldering metal. Electroless plating is a known method for forming a thick nickel layer. Electroless plating employs a mechanism by which metal is deposited using a reducing agent. It is known to use hypophosphoric acid as the reducing agent. In electroless plating using hypophosphoric acid to form a nickel layer, the nickel forms an alloy with the phosphorus in the hypophosphoric acid and is deposited in an amorphous state.

[0022] As mentioned above, the second and fourth metal layers 3 and 6 expand and contract with temperature changes. The property parameter that characterizes the degree of expansion due to temperature is the coefficient of linear thermal expansion. It is known that the coefficient of linear thermal expansion of a nickel-phosphorus alloy varies according to the concentration of phosphorus in the nickel. The higher the phosphorus concentration, the lower the coefficient of linear thermal expansion.

[0023] In this embodiment, the second metal layer 3 has a higher phosphorus concentration α than the phosphorus concentration β of the fourth metal layer 6 (α > β). Therefore, the extent of expansion and contraction per unit volume of the second metal layer 3 on the front side due to temperature changes is less than in the fourth metal layer 6 on the back side. Compared to the case where the phosphorus concentration is identical for both sides, the difference in stress experienced by the semiconductor substrate 1 during temperature changes is reduced, thus minimizing distortion of the semiconductor substrate 1. Consequently, assembly properties can be improved.

[0024] While a silicon (Si) substrate can generally be used as the semiconductor substrate 1 in embodiments 1 to 3, the substrate is not limited to silicon. Silicon carbide (SiC) or gallium nitride (GaN) substrates, which are harder than silicon substrates, can be used to reduce warping of the semiconductor substrate 1. Power semiconductor devices using a SiC or GaN substrate have high dielectric strength and allowable current density, thus enabling size reduction. By using such smaller devices, a semiconductor module incorporating this device can be made smaller. Furthermore, the device has greater heat resistance, making it possible to reduce the size of cooling fins on a heat sink and to replace water-cooled components with air-cooled parts, thereby further reducing the size of the semiconductor module.Furthermore, the high efficiency of the device with low power loss can improve the efficiency of the semiconductor module. Reference symbol list 1 Semiconductor substrate 2 first metal layer 3 second metal layer 5 third metal layer 6 fourth metal layer

Claims

Semiconductor device comprising: - a semiconductor substrate (1) having a front and a back side opposite each other; - a first metal layer (2) formed on the front side of the semiconductor substrate (1); - a second metal layer (3) for soldering formed on the first metal layer (2); - a third metal layer (5) formed on the back side of the semiconductor substrate (1);and- a fourth metal layer (6) for soldering, which is formed on the third metal layer (5), wherein:- the second metal layer (3) has a greater thickness than the fourth metal layer (6),- the first and third metal layers (2, 5) are not divided into a pattern,- the second metal layer (3) is divided into a pattern and has a plurality of metal layers which are electrically connected to each other via the first metal layer (2),- the fourth metal layer (6) is divided into a pattern and has a plurality of metal layers which are electrically connected to each other via the third metal layer (5), and- the number of divided parts of the second metal layer (3) is greater than the number of divided parts of the fourth metal layer (6).; Semiconductor device according to claim 1, wherein the second and fourth metal layers (3, 6) contain nickel. Semiconductor device comprising: - a semiconductor substrate (1) having a front and a back side opposite each other; - a first metal layer (2) formed on the front side of the semiconductor substrate (1); - a second metal layer (3) for soldering formed on the first metal layer (2); - a third metal layer (5) formed on the back side of the semiconductor substrate (1); and - a fourth metal layer (6) for soldering formed on the third metal layer (5), wherein: - the second metal layer (3) has a greater thickness than the fourth metal layer (6), - the second and fourth metal layers (3, 6) are made of amorphous nickel containing phosphorus, and - the second metal layer (3) has a higher phosphorus concentration than the fourth metal layer (6). Semiconductor device according to one of the preceding claims, wherein the second and fourth metal layers (3, 6) are not crystallized. Semiconductor device according to one of the preceding claims, wherein the semiconductor substrate (1) is a SiC substrate or a GaN substrate.

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