SEMICONDUCTOR DEVICE

Abstract

Semiconductor device (100, 200, 300) comprising: a semiconductor substrate (10); a first region (16) of a first conductivity type formed on the side of a front surface of the semiconductor substrate (10); a drift region (18) of a second conductivity type formed closer to a back surface of the semiconductor substrate (10) than the first region (16); a buffer region (20) of a second conductivity type formed closer to the back surface of the semiconductor substrate (10) than the drift region (18) and having a plurality of peaks (26) of an impurity density distribution which are higher than an impurity density of the drift region (18);and a lifetime reducer (28) arranged on the rear surface of the semiconductor substrate (10) and reducing a carrier lifetime, wherein a peak of a density distribution of the lifetime reducer (28) is located between a peak of the plurality of peaks (26) of the defect density in the buffer region (20) that is closest to a front surface of the semiconductor substrate (10) and a rear surface side of the buffer region (20), and wherein the peak of the density distribution of the lifetime reducer (28) is located within the buffer region (20) and at a position that does not overlap any of the plurality of peaks (26) of the defect density in the buffer region (20).

Description

BACKGROUND1. TECHNICAL FIELDThe present invention relates to a semiconductor device.2. Prior ArtA structure of a conventional power semiconductor element provided with a field stop layer is known (for example, see Please Patent Document 1). n-type impurities such as protons are implanted into the field stop layer.Patent Document 1: Description of U.S. Pat. No. 7,842,590 B2US 2012 / 0 267 681 A1 discloses a semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided on one main surface of the first semiconductor layer and having an impurity density greater than that of the first semiconductor layer; a third semiconductor layer of a first conductivity type provided on the other main surface of the first semiconductor layer and having an impurity density greater than that of the first semiconductor layer; and a first conductivity type wide buffer region provided in the first semiconductor layer and having an impurity density larger than that of the first semiconductor layer, and in which a local maximum value of an impurity density distribution is smaller than the impurity density of the second semiconductor layer and the third semiconductor layer, wherein the total amount of the net doping concentration of the wide buffer region is equal to or more than 4.8×10 11atoms / cm2and equal to or less than 1.0×10 12atoms / cm2, and wherein the resistivity ρ satisfies 0 (Ωcm) of the first semiconductor layer 0.12 V 0 ≦ ρ 0 ≦ 0.25 V 0 with respect to a rated voltage V 0 (V).The document JP 2015-211 149 A discloses a semiconductor device comprising a semiconductor substrate having an IGBT region and a diode region. In an n-type impurity density distribution in a direction from a surface to a back surface of the semiconductor substrate, a local minimum value is formed at a boundary between a cathode region and a buffer region, and a local maximum value is formed in the buffer region; and at least in the buffer region or the cathode region, a crystal defect region in which a crystal defect is distributed at a higher concentration than in the periphery is formed; and a peak value of a concentration of a crystal defect in a concentration distribution of a crystal defect in a direction from the surface to the back surface is formed in a region closer to the back surface than a position having an n-type impurity density that is half of the local maximum value of the n-type impurity density.US 2017 / 0 069 625 A1 discloses a semiconductor device comprising: a semiconductor substrate comprising an IGBT region and a diode region, an emitter electrode provided on a front side of the semiconductor substrate in the IGBT region; an anode electrode provided on the front side of the semiconductor substrate in the diode region; and a back electrode provided on a back side of the semiconductor substrate, wherein the IGBT region comprises: an n-type emitter region contacting the emitter electrode; a p-type body region contacting the emitter electrode; an n-type IGBT drift region separated from the emitter region by the body region; a p-type collector region separated from the body region by the IGBT drift region and in contact with the back electrode; a gate insulating film in contact with the body region; and a gate electrode facing the body region by the gate insulating film, the diode region comprising: a p-type anode region and in contact with the anode electrode; an n-type diode drift region adjoining the anode region at a back surface and connected to the IGBT drift region; an n-type buffer zone region adjoining the diode drift zone at the back surface; and an n-type cathode region adjoining the buffer zone region at the back surface and in contact with the back electrode,US 2015 / 0364 613 A1 discloses a semiconductor device comprising: a substrate having a surface and another surface opposite to the one surface; a first semiconductor region of a first conductivity type formed in the substrate; a second semiconductor region of a second conductivity type, the second semiconductor region being selectively provided in a first surface layer of the substrate comprising the one surface; a first electrode in contact with the second semiconductor region to form a transition between the second semiconductor region and the first electrode; a third semiconductor region of the first conductivity type provided in a second surface layer comprising the other surface of the substrate, the third semiconductor region having a higher impurity density than the first semiconductor region; a fourth semiconductor region of the second conductivity type provided in the substrate at a position lower than the third semiconductor region from the other surface; and a second electrode in contact with the third semiconductor region, wherein an end portion of the fourth semiconductor region is disposed at a position that is at least a diffusion length of a minority carrier toward an inside of an end portion of the junction between the second semiconductor region and the first electrode.US 2015 / 0 311 279 A1 discloses a semiconductor device in which a lifetime of carriers is locally controlled, comprising: a semiconductor substrate of a first conductivity type having defects, the defects having free bonds generated by breaking interatomic bonds of atoms constituting the semiconductor substrate; and a high hydrogen concentration region having hydrogen atoms formed on a back surface of the semiconductor substrate and having a higher hydrogen concentration than the front surface of the semiconductor substrate, wherein fewer defects are present in the high hydrogen concentration region than in a region of the semiconductor substrate other than the high hydrogen concentration region, and a carrier lifetime is longer than that on the front surface of the semiconductor substrate.US 2013 / 0 075 783 A1 discloses a semiconductor device comprising: a semiconductor substrate comprising: an n-type drift layer, a p-type base layer on an upper surface side of the drift layer, and a high-impurity n-layer on a lower surface side of the drift layer, wherein the high-impurity n-layer contains hydrogen ion donors as dopants and has a higher density of n-type impurities than the drift layer, wherein a lifetime control region containing crystal defects as lifetime killers is formed in the high-impurity n-layer and a part of the drift layer, a position of the donor peak, where a hydrogen ion donor density in the high impurity n-layer is highest in a depth direction of the semiconductor substrate, abuts or is identical to a position of the defect peak where a crystal defect density is highest in the lifetime control region in the depth direction of the semiconductor substrate, and the crystal defect density in the position of the defect peak of the lifetime control region is 1×1012atoms / cm3or more.When n-type impurities such as protons are implanted into a semiconductor substrate and the semiconductor substrate is subjected to heat treatment, the impurities such as protons eliminate defects and the like in the semiconductor substrate, and the lifetime of carriers is recovered. However, when the carrier lifetime on the back surface side of the semiconductor substrate becomes too long, the tail current at the time of the reverse recovery operation increases and the reverse recovery loss increases.General DisclosureAn aspect of the present invention provides a semiconductor device including a semiconductor substrate. A first region of a first conductivity type may be formed on a front surface side of the semiconductor substrate. On the semiconductor substrate, a drift region of a second conductivity type may be formed closer to a back surface of the semiconductor substrate than the first region. On the semiconductor substrate, a buffer region of a second conductivity type may be formed, which is formed closer to the back surface of the semiconductor substrate than the drift region. The buffer region may have one or more peaks of an impurity density higher than an impurity density in the drift region. On the semiconductor substrate, a lifetime killer may be formed which is disposed on the back surface side of the semiconductor substrate and shortens a carrier lifetime. A peak of a density of the lifetime killer may be disposed between a peak closest to a front surface of the semiconductor substrate from the peaks of the impurity density in the buffer region and the back surface of the semiconductor substrate.Further, on the semiconductor substrate, a second region of the first conductivity type may be formed between a peak closest to the back surface of the semiconductor substrate among the peaks of the impurity density in the buffer region and the back surface of the semiconductor substrate. The peak of the density of the lifetime killer may be disposed closer to a front surface of the semiconductor substrate than the peak of the impurity density in the second region.The distribution of impurity density in the buffer region may have a plurality of peaks. The peak of the density of the lifetime killer may be disposed closer to the back surface of the semiconductor substrate than a peak closest to the back surface of the semiconductor substrate among the peaks of the impurity density in the buffer region.A distance between the lifetime killer density peak and the impurity density peak in the second region may be larger than a distance between the lifetime killer density peak and the peak closest to the back surface of the semiconductor substrate among the impurity density peaks in the buffer region.The peak of the density of the lifetime killer may be located between any two peaks of the impurity density in the buffer region.A peak of a density of the lifetime killer may be disposed at a position that does not overlap any of the peaks of the impurity density in the buffer region.The peak of the density of the lifetime killer may be higher than a peak closest to the back surface of the semiconductor substrate among the peaks of the impurity density in the buffer region. The density peak of the lifetime killer may be lower than the concentration peak in the second region.Protons may be implanted into the buffer region. The lifetime killer may be helium.A full width at half maximum of a density distribution of the lifetime killer in a depth direction of the semiconductor substrate may be equal to or greater than 5 μm. The buffer region may have two peaks of impurity density sandwiching the peak of density of the lifetime killer, and a full width at half maximum of a density distribution of the lifetime killer may be equal to or greater than 70% of an interval between the two peaks.The semiconductor substrate may have a transistor part in which a transistor is formed and a diode part in which a diode is formed. The second regions may be discretely provided in the diode part. On a plane parallel to the back surface of the semiconductor substrate, a distance D between a boundary between the transistor part and the diode part and the second region may be larger than an interval between the second regions.The distance D may be greater than a thickness of the semiconductor substrate. The distance D may be greater than a width of the second region.The summary does not necessarily describe all necessary features of the embodiments of the present invention. The present invention may also be a sub-combination of the features described above.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1 is a figure showing a cross section of a semiconductor device 100 according to an embodiment. FIG. 2 is a figure showing an example of impurity density distribution in a cathode region 24, an intermediate region 22, an FS region 20, and a drift region 18. FIG. 3 is an enlarged figure showing an impurity density distribution in a part near the intermediate region 22 and a fourth peak 26- 4. FIG. 4 is a figure showing a positional relationship between the peak of the density of a lifetime killer 28 and a peak 26 in the FS region 20. FIG. 5 is a figure showing a measurement result of the leakage current of the semiconductor device 100. FIG. 6 is a figure showing time waveforms of a reverse voltage Vr and a reverse current Ir at the time of the reverse recovery operation of the semiconductor device 100. FIG. 7 is a figure showing an example of a manufacturing process of the semiconductor device 100. FIG. 8 is a sectional view showing another example of a configuration of the semiconductor device 100. FIG. 9 is a figure showing a cross section of a semiconductor device 200 according to another embodiment. FIG. 10 is a figure showing a cross section of a semiconductor device 300 according to another embodiment. FIG. 11 is a figure showing another example of a cross section of the semiconductor device 300. FIG. 12 is a figure showing an example of arrangement of the intermediate regions 22 on a plane parallel to the back surface of the semiconductor device 300 shown in FIG. 11. FIG. 13 is a figure showing another example of the density distribution of the lifetime killer 28 in the depth direction.DESCRIPTION OF EXEMPLARY EMBODIMENTSHereinafter, a (some) embodiment(s) of the present invention will be described.FIG. 1 is a figure showing a cross section of a semiconductor device 100 according to an embodiment. The semiconductor device 100 is a vertical semiconductor device in which electrodes are formed on the front surface and the back surface of a semiconductor substrate 10 and current flows in the depth direction of the semiconductor substrate 10. When a front surface and a back surface are simply mentioned in the present description, this refers to the front surface and the back surface of the semiconductor substrate 10. The diode may operate as a free wheeling diode (FWD) provided in parallel with a switching element such as an IGBT.The semiconductor device 100 includes the semiconductor substrate 10, an anode electrode 12, and a cathode electrode 14. the anode electrode 12 is provided in contact with the front surface of the semiconductor substrate 10. The cathode electrode is provided in contact with the back surface of the semiconductor substrate 10. The anode electrode 12 and the cathode electrode 14 are formed of, for example, metal materials containing aluminum.The semiconductor substrate 10 is formed of a semiconductor material such as silicon or a compound semiconductor. The semiconductor substrate 10 is doped with a predetermined impurity density. Unless expressly stated otherwise, the impurities in the present specification refer to a dopant having an n- or p-type conductivity when doped into a semiconductor material. The semiconductor substrate 10 in the present example has the n-type conductivity type. The n-type is an example of a second conductivity type. Further, the p-type is an example of a first conductivity type. However, the first conductivity type and the second conductivity type may be opposite conductivity types, respectively.The semiconductor substrate 10 has an anode region 16, a drift region 18, a buffer region (FS region 20), an intermediate region 22, and a cathode region 24. the anode region 16 is an example of a first region and the intermediate region 22 is an example of a second region. The buffer region may function as a field stop layer suppressing the spread of a depletion layer.The drift region 18 has the same conductivity type as the semiconductor substrate 10.The anode region 16 is formed on the front surface side of the drift region 18 and is in electrical connection with the anode electrode 12. The anode region 16 is doped with impurities of a different conductivity type than the drift region 18. In the present example, the anode region 16 corresponds to the p-type.The FS region 20 is formed on the back surface side of the drift region 18. The FS region 20 has the same conductivity type as the drift region 18 and, in addition, a higher impurity density than in the drift region 18 is implanted therein. In the present example, the FS region 20 corresponds to the n-type. Further, the impurities implanted in the FS region 20 are referred to as first impurities. The first impurities are, for example, hydrogen or phosphorus.Hydrogen is bound in a semiconductor material at vacancies (V) and oxygen (O) in the form of a cluster and forms a defect complex (VOH defects). Since these VOH defects become a donor, the VOH defects become an n-type dopant (impurities). Hydrogen may be introduced into the semiconductor material by implanting hydrogen ions such as protons or deutrons. Oxygen may be included in a semiconductor material during its manufacture or may be selectively introduced into a semiconductor region during manufacture of the semiconductor device. The semiconductor material may be manufactured by a floating zone (FZ) process, a Czochralski (CZ) process, an applied magnetic field Czochralski (MCZ) process, or the like. For example, when a CZ process or an MCZ process is applied, a dopant consisting of VOH defects can be formed appropriately because the density of oxygen in a semiconductor material becomes equal to or higher than 1×10 17 / cm 3 and equal to or lower than 1×10 18 / cm 3.Vacancies may be included in a semiconductor material during its manufacture or may be selectively introduced into a semiconductor region during manufacture of the semiconductor device. By providing the FS region 20 with a high density, it is possible to prevent a depletion layer extending from an interface of the anode region 16 from reaching the intermediate region 22 or the cathode region 24. The vacancies may be introduced, for example, by ion implantation using protons, an electron beam, helium, or the like.The density distribution of the first impurities in the depth direction of the semiconductor substrate 10 has one or more peaks 26 in the FS region 20. The density of the impurities at the respective peaks 26 is higher than the impurity density in the drift region 18.The intermediate region 22 is formed on the back surface side of the FS region 20. The intermediate region 22 is locally formed on a plane parallel to the back surface of the semiconductor substrate 10 in the present example. The intermediate region 22 has the same conductivity type as the anode region 16. Further, the impurities implanted in the intermediate region 22 are referred to as second impurities. The second impurities are, for example, boron. A region that is on the back surface side of the FS region 20 and in which the intermediate region 22 is not formed has the same conductivity type as the drift region 18.The cathode region 24 is formed on the back surface side of the intermediate region 22. The cathode region 24 has the same conductivity type as the FS region 20, and the impurity density in the cathode region 24 is higher than the respective impurity densities of the FS region 20 and the intermediate region 22 in the present example. Further, the impurities implanted in the cathode region 24 are referred to as third impurities. The third impurity is phosphorus, for example. The cathode region 24 is electrically connected to the cathode electrode 14.There is known a phenomenon in which when a diode is turned on during reverse recovery at a low current which is only about 1 / 10 of the rated current, carriers on the cathode side are decreased and a current or voltage waveform greatly oscillates. In the semiconductor device 100 according to the present example, when a depletion layer spreads from the anode side at the time of reverse recovery and depletion of the carriers on the cathode side is imminent, a high electric field is applied to the pn junction between the intermediate layer 22 and the cathode region 24, and the junction experiences avalanche breakdown. Thereby, holes are implanted into the drift region 18 from the cathode side, and the carrier density of the drift region 18 on the cathode side can be increased. As a result, the oscillation of the voltage / current due to the decrease in the carriers can be suppressed.Further, when impurities such as protons are implanted into the FS region 20 and the semiconductor substrate 10 is then subjected to a heat treatment, the impurities such as protons are dispersed and remove defects. Thereby, the lifetime of a region in which the impurities such as protons are distributed is recovered. Thereby, the reverse recovery operation of the semiconductor device 100 can be made a soft recovery operation.On the other hand, when the carrier life on the cathode side becomes too long, the tail current increases at the time of the reverse recovery operation. As tail current increases, reverse recovery loss increases. To cope with this, the semiconductor device 100 according to the present example has a lifetime killer 28 disposed on the back surface side of the semiconductor substrate 10 and shortening the carrier lifetime. The lifetime killer 28 is helium, for example.The density distribution peak of the lifetime killer 28 in the depth direction is located between the first peak 26- 1 closest to the front surface among the peaks 26 in the FS region 20 and the back surface of the semiconductor substrate 10 (a plane in contact with the cathode electrode 14 in the present example). With such a configuration, it is possible to reduce the carrier lifetime of a region contributing to the tail current to reduce the tail current.FIG. 2 is a figure showing an example of the impurity density distribution in the cathode region 24, the intermediate region 22, the FS region 20, and the drift region 18. Furthermore, the density distribution of the lifetime killer 28 is also shown in FIG. 2. The impurity density distribution in the cathode region 24, the intermediate region 22, the FS region 20, and the drift region 18 shows the net impurity density (net impurity density) obtained by integrating the densities of the respective impurities except for the lifetime killer 28. As mentioned above, the impurity density peak of the lifetime killer 28 is disposed between the first peak 26- 1 closest to the front surface (i.e., closest to the drift region 18) among the impurity density peaks 26 in the FS region 20 and the back surface of the semiconductor substrate 10. The peak density of the first peak 26- 1 closest to the front surface may be higher than the peak density of the second peak 26- 2 adjacent thereto on the back surface side.When the semiconductor substrate 10 has the intermediate region 22, the peak of the impurity concentration of the lifetime killer 28 is disposed closer to the front surface of the semiconductor substrate 10 than a peak 23 of the impurity concentration in the intermediate region 22. Thereby, it is possible to suppress the disappearance of carriers in the intermediate region 22 by the implantation of the lifetime killer 28.Further, when a plurality of peaks 26 are present in the FS region 20, the peak of the impurity density of the lifetime killer 28 may be located between any two peaks 26 among the plurality of peaks 26. The impurity density peak of the lifetime killer 28 may be located between the first peak 26- 1 closest to the front surface and the second peak 26- 2 subsequent thereto, may be located between the fourth peak 26- 4 closest to the rear surface and the fourth peak 26- 3 subsequent thereto, or may be located between two peaks 26 not located closest to the front surface or the rear surface.Further, the impurity density peak of the lifetime killer 28 may be disposed closer to the back surface than the fourth peak 26- 4 that is closest to the back surface among the impurity density peaks 26 in the FS region 20. By disposing the impurity concentration peak of the lifetime killer 28 closer to the back surface than the fourth peak 26- 4, the peak of the lifetime killer 28 can be disposed in a region that does not reach the depletion layer extending from the anode side. Accordingly, an increase in the leakage current caused by implanting the lifetime killer 28 can be suppressed.FIG. 3 is an enlarged figure showing an impurity density distribution in the part near the intermediate region 22 and the fourth peak 26- 4. In the present example, the peak of the density of the lifetime killer 28 is located between the peak 23 of the impurity density in the intermediate region 22 and the fourth peak 26- 4. In the present example, it is assumed that the depth position of the peak of the impurity density of the intermediate region 22 is P 1, the depth position of the fourth peak 26- 4 is P 2, and the depth position of the density peak of the lifetime killer 28 is P 3. The positions of the respective peaks are positions at which the density has its maximum value.The distance (P 3-P 1) between the density peak of the lifetime killer 28 and the impurity density peak 23 in the intermediate region 22 is preferably larger than the distance (P 2-P 3) between the density peak of the lifetime killer 28 and the fourth peak 26- 4 that is in the FS region 20 and is closest to the back surface. That is, the density peak of the lifetime killer 28 is located between the peak 23 and the fourth peak 26- 4, and preferably, is located closer to the fourth peak 26- 4.This makes it possible to suppress the disappearance of carriers in the intermediate region 22 caused by the implantation of the lifetime killer 28. The pitch (P 3-P 1) may be twice the pitch (P 2-P 3) or more or three times the pitch (P 2-P 3) or more.Further, a peak value D 3 of the density of the lifetime killer 28 may be lower than a peak value D 1 of the density in the intermediate region 22, thereby achieving the vibration suppression function of the intermediate region 22, even if carriers in the intermediate region 22 partially disappear due to the implantation of the lifetime killer 28. The peak value D 3 of the density of the lifetime killer 28 may be 80% of the peak value D 1 or less or 50% of the peak value D 1 or less.Further, the peak value D 3 of the density of the lifetime killer 28 may be higher than the peak value D 2 of the fourth peak 26- 4 closest to the back surface among the peaks 26 of the impurity density in the FS region 20. Thereby, even when the carrier lifetime is recovered due to protons or the like, excessive carriers on the back surface side at the time of the barrier recovery operation can be sufficiently reduced. The peak value D 3 of the density of the lifetime killer 28 may be twice the peak value D 2 or more, five times the peak value D 2 or more, or ten times the peak value D 2 or more.FIG. 4 is a figure showing a positional relationship between the peak of the density of the lifetime killer 28 and a peak 26 in the FS region 20. The density peak of the lifetime killer 28 is preferably disposed at a position where it does not overlap any of the impurity density peaks 26 in the FS region 20. Thereby, it is possible to suppress defects generated by the lifetime killer 28 being excessively recovered due to protons or the like implanted in the FS region 20.The phrase that "density peaks do not overlap each other" refers to a distance X between the peaks being equal to or greater than a predetermined value. As an example, the distance X may be equal to or greater than a half width at a half maximum Y / 2 of the density distribution of the lifetime killer 28, equal to or greater than a full width at a half maximum Y thereof, or twice the full width at the half maximum Y or more.Likewise, the peak of the density of the lifetime killer 28 preferably does not overlap the peak 23 of the impurity density of the intermediate region 22, thereby making it possible to suppress the disappearance of carriers in the intermediate region 22 by the lifetime killer 28.Further, the lifetime killer 28 may be implanted at a plurality of positions in the depth direction. As an example, density peaks of the lifetime killer 28 may be respectively formed between the peak 23 of the intermediate region 22 and the fourth peak 26- 4 in the FS region 20 and between any two peaks 26 in the FS region 20. The values of the plurality of density peaks of the lifetime killer 28 may decrease as the distance from the cathode side increases.FIG. 5 is a figure showing a measurement result of the leakage current of the semiconductor device 100. In the semiconductor device 100 according to the present example, as shown in FIG. 3, the lifetime killer 28 is disposed between the peak 23 of the intermediate region 22 and the fourth peak 26- 4 that is in the FS region 20 and is closest to the cathode. In FIG. 5, the horizontal axis indicates the reverse bias voltage Vr, and the vertical axis indicates the leakage current Ir.Further, in FIG. 5, an example in which the lifetime killer 28 is implanted is indicated with a solid line, and an example in which the lifetime killer 28 is not implanted is indicated with a broken line. As shown in FIG. 5, even when the lifetime killer 28 is implanted, the leakage current does not increase.FIG. 6 is a figure showing time waveforms of the reverse voltage Vr and the reverse current Ir at the time of the reverse recovery operation of the semiconductor device 100. In FIG. 5, an example in which the lifetime killer 28 is implanted is indicated with a solid line, and an example in which the lifetime killer 28 is not implanted is indicated with a broken line.It is known that, as shown in FIG. 6, the tail current in the reverse current Ir decreases by implanting the lifetime killer 28. Thereby, a loss at the time of the lock recovery operation can be reduced. Also, at the time of the reverse recovery operation, no substantial oscillations are generated at voltage / current.FIG. 7 is a figure showing an example of a manufacturing process of the semiconductor device 100. First, in a front structure forming step S 700, the front surface side structure of the semiconductor device 100 is formed. In the example shown in FIG. 1, the anode electrode 12 and the anode region 16 are formed. Further, in S 700, after forming the front surface side structure, the back surface side of the semiconductor substrate 10 is polished to adjust the thickness of the semiconductor substrate 10 according to a predetermined withstand voltage.Subsequently, in a cathode region forming step S 702, impurities are implanted from the back surface side of the semiconductor substrate 10 to form the cathode region 24. As an example, in S 702, the impurities are phosphorus, the dose amount is 1×10 15 / cm 2 and the acceleration voltage is 40 keV.Subsequently, in an intermediate region forming step S 704, impurities are locally implanted from the back surface side of the semiconductor substrate 10 to form the intermediate region 22. As an example, in S 704, the impurities are boron, the dose amount is 1×10 13 / cm 2 and the acceleration voltage is 240 keV. The dose amount of boron may be equal to or greater than 3×10 12 / cm 2 and equal to or less than 3×10 13 / cm 2. Subsequently, in a laser annealing step S 706, a region in which the impurities have been implanted from the back surface side of the semiconductor substrate 10 is annealed.Subsequently, in a proton implantation step S 708, protons are implanted from the back surface side of the semiconductor substrate 10 to form the FS region 20. When four peaks 26 are formed in the FS region 20 as shown in FIG. 2, protons are implanted four times at different acceleration voltages.As an example, the dose amount of protons and the acceleration voltage corresponding to the fourth peak 26- 4 are 3.0×10 14 / cm 2 and respectively. 400 keV, the dose amount of protons and the acceleration voltage corresponding to the third peak 26-3 are 1.0×10 13 / cm 2 and, respectively. 820 keV, the dose amount of protons and the acceleration voltage corresponding to the second peak 26-2 are 7.0×10 12 / cm 2 and 820 keV, respectively. 1100 keV, and the dose amount of protons and the acceleration voltage corresponding to the first peak 26- 1 are 1.0×10 13 / cm 2 and. 1450 keV.Subsequently, in a first furnace annealing step S 710 the semiconductor substrate 10 is annealed in an annealing furnace, for example in a nitrogen atmosphere. As an example, the annealing temperature is 370° and the annealing time is 5 hours. Subsequently, in a helium implantation step S 712, helium is implanted from the back surface side of the semiconductor substrate 10 to form the lifetime killer 28. As an example, in S 712, He 2+ is implanted at the dose amount of 2×10 12 / cm 2 and at the acceleration energy of 700 keV.Subsequently, in an electron beam irradiation step S 710, the back surface side of the semiconductor substrate 10 is irradiated with electron beams. As an example, the amount of electron beam irradiation is 160 kGy. Subsequently, in a second furnace annealing step S 716, the semiconductor substrate 10 is annealed in an annealing furnace, for example in a nitrogen atmosphere. As an example, the annealing temperature is 360° and the annealing time is 1 hour.Then, in a back surface electrode forming step S 718, the cathode electrode 14 is formed. The cathode electrode 14 may be formed by sputtering. Further, the cathode electrode 14 may be a laminated electrode formed by stacking aluminum layers, titanium layers, nickel layers, and the like. The semiconductor device 100 may be manufactured in steps corresponding to the above-explained steps.FIG. 8 is a sectional view showing another example of a configuration of the semiconductor device 100. The semiconductor device 100 according to the present example is different from the semiconductor device 100 shown in FIG. 1 in the position of the intermediate region 22.The intermediate region 22 in the present example is formed at the same depth position as the cathode region 24. In this case, in addition to being formed between any one of the peaks 26 of the FS region 20 and the density peak of the intermediate region 22, the lifetime killer 28 is also formed between any one of the peaks 26 of the FS region 20 and the density peak of the cathode region 24.The positions of the lifetime killer 28 formed over the intermediate region 22 and the lifetime killer 28 formed over the cathode region 24 may be equal to each other in the depth direction. Even with such a configuration, the tail current at the time of the reverse recovery operation can be reduced, and an increase in the leakage current can be suppressed.FIG. 9 is a figure showing a cross section of a semiconductor device 200 according to another embodiment. The semiconductor device 200 is an IGBT (Insulated Gate Bipolar Transistor). The semiconductor device 200 includes the semiconductor substrate 10, an emitter electrode 112, and a collector electrode 130.The emitter electrode and 12 are provided in contact with the front surface of the semiconductor substrate 10. The collector electrode 130 is provided in contact with the back surface of the semiconductor substrate 10. The emitter electrode 112 and the collector electrode 130 are formed of metal materials containing aluminum, for example.A gate pattern 120 is formed on the front surface side of the semiconductor substrate 10. The gate structure 120 corresponds to the trench type in the present example, but the gate structure 120 also corresponds to the planar type. The gate structure 120 includes a gate insulating film 122 and a gate electrode 124.The gate insulating film 122 is formed so as to cover the periphery of the gate electrode 124. The gate insulating film 122 according to the present example is formed so as to cover the inner wall of a gate trench formed on the front surface of the semiconductor substrate 10. The gate electrode 124 is formed at a position opposing a base region 118 where a channel is formed. The gate electrode 124 according to the present example is polysilicon formed to be covered by the gate insulating film 122 within the gate trench. The gate electrode 124 according to the present example faces the base region 118 along the depth direction of the semiconductor substrate 10.An interlayer dielectric film 114 covering the gate pattern 120 is formed on the front surface of the semiconductor substrate 10. Thereby, the emitter electrode 112 and the gate structure 120 are insulated.An n+ emitter region 116 and a p-type base region 118 are formed on the front surface side of the semiconductor substrate 10. The base set 118 is an example of a first region. The gate structure 120 according to the present example is formed penetrating the base region 118. The emitter region 116 is formed in a region adjoining the gate structure 120. At the front surface of the semiconductor substrate 10, the emitter region 116 and the base region 118 are in contact with the emitter electrode 112.An n-type drift region 126 is formed on the back surface side of the base region 118. The FS region 20 is formed on the back surface side of the drift region 126. A p+ collector region 128 is formed on the back surface side of the FS region 20. The collector region 128 is an example of a second region.Also in the present example, the density peak of the lifetime killer 28 is located between the first peak 26- 1 closest to the front surface of the semiconductor substrate 10 among the peaks 26 of the impurity density in the FS region 20 and the back surface of the semiconductor substrate 10. The density peak of the lifetime killer 28 is preferably located between the fourth peak 26- 4 closest to the back surface of the semiconductor substrate 10 among the peaks 26 of the impurity density in the FS region 20 and the density peak of the collector region 128.FIG. 10 is a figure showing a cross section of a semiconductor device 300 according to another embodiment. The semiconductor device 300 is a reverse-conduction IGBT (RC-IGBT) in which an IGBT and a diode for reverse recovery are formed on the same substrate. The semiconductor device 300 includes the semiconductor substrate 10, the emitter electrode 112, and the collector electrode 130.On the back surface side of the semiconductor substrate 10 according to the present example, the p+ collector region 128 is formed in the transistor part 70 which is a region acting as an IGBT, and the n+ cathode region 24 is formed in the diode part 80 which is a region acting as a diode. An emitter region 116 may not be present, but a p+ contact region 115 may be formed on the front surface of the base region 118 in a mesa portion 150 which is among the mesa portions 150 of the transistor portion 70 (trench-sandwiched regions of the semiconductor substrate) and connects to a trench portion 120 which is at or near a position which appears imaginary on the front surface when the position at which the cathode region 24 contacts the collector region 128 is projected imaginaryly onto the front surface.The structure of the transistor part 70 is similar to that of the semiconductor device 200 shown in FIG. 9. However, in the present example, a plurality of gate structures 120 are formed in the transistor part 70. The gate electrode(s) 124 of at least one of the plurality of gate structures 120 is / are electrically connected to the gate terminal. Further, the gate electrode(s) 124 of at least one of the plurality of gate structures 120 may be electrically connected to the emitter electrode 112 and act as a dummy trench. By providing a dummy trench, an injection enhancement (IE) effect can be achieved.The structure of a region acting as a diode is similar to that of the semiconductor device 100 shown in FIG. 1 or 8. The base region 118 shown in FIG. 10 acts as an anode region of the diode.Further, the intermediate region 22 is omitted in FIG. 10. The intermediate region 22 may be locally formed above the cathode region 24 shown in FIG. 10, similar to the semiconductor device 100 shown in FIG. 1. Further, in the semiconductor substrate 10 shown in FIG. 10, the front surface side of the diode part 80 has one or more dummy trench structures 140. The dummy trench structures 140 have a similar structure to the gate structures 120. However, the gate electrode in a dummy trench structure 140 is electrically connected to the emitter electrode 112.The density peak of a lifetime killer 28 in a region to function as the diode is provided at a similar position as in the semiconductor device 100 shown in FIG. 1 or 8. Further, the density peak of the lifetime killer 28 is provided in the transistor part 70 at a similar position as in the semiconductor device 200 shown in FIG. 9. The lifetime killer 28 may be formed in the transistor part 70 and the diode part 80 at the same depth position.FIG. 11 is a figure showing another example of a cross section of the semiconductor device 300. The semiconductor device 300 according to the present example has the intermediate regions 22, except for the intermediate regions 22, the structure may be the same as that of the semiconductor device 300 shown in FIG. 10.In the present example, a region in the semiconductor substrate 10 to act as a transistor such as an IGBT is assumed to be the transistor part 70, and a region thereof to act as a diode such as an FWD is assumed to be the diode part 80. The emitter region 116 is formed on the front surface of the transistor part 70 and the collector region 128 is formed on the rear surface thereof. The emitter region 116 is not formed on the front surface of the diode part 80, but the base region 118 is formed therein, and the cathode region 24 is formed on the rear surface thereof. The boundary between the collector region 128 and the cathode region 24 is assumed to be the boundary between the transistor part 70 and the diode part 80.The emitter region 116 may not be present, but a p+ contact region 115 may be formed on the front surface of the base region 118 in a mesa portion 150 that is among the mesa portions 150 of the transistor portion 70 (trench-sandwiched regions of the semiconductor substrate) and connects to a trench portion 120 that is at or near a position that appears imaginary on the front surface when the position at which the cathode region 24 contacts the collector region 128 is projected imaginaryly onto the front surface.The intermediate regions 22 are provided for the diode part 80. The intermediate regions 22 may be formed on the cathode region 24 as shown in FIG. 1, or may be formed at the same depth positions as the cathode region 24 shown in FIG. 8.The gate structures 120 have trench structures, and the dummy trench structures are formed in a direction perpendicular to the cross section shown in FIG. 11. The direction in which the gate structures 120 and the dummy trench structures 140 extend is assumed to be the trench length direction (Y axis direction in FIG. 11 ), and the direction orthogonal to the trench length direction on the front surface of the semiconductor substrate 10 is assumed to be the trench width direction (X axis direction in FIG. 11 ).The distance that is between the boundary between the transistor part 70 and the diode part 80 and the intermediate region 22 closest to the transistor part 70 and is in a plane parallel to the back surface of the semiconductor substrate 10 along the trench lateral direction (X-axis direction) is assumed to be D. That is, the distance between the collector region 128 and the intermediate region 22 in the X-axis direction is assumed to be D.Further, a plurality of intermediate regions 22 are discretely formed on a plane parallel to the back surface of the semiconductor substrate 10. The interval between the intermediate regions 22 in the trench width direction (X-axis direction) is assumed to be L 1, and the width of the intermediate regions 22 is assumed to be L 2. The interval L 1 and the width L 2 of the intermediate regions 22 used may be the average values or the maximum values of the plurality of intermediate regions 22. Further, the thickness of the semiconductor substrate 10 in the depth direction (Z-axis direction in FIG. 11 ) orthogonal to both the trench longitudinal direction and the trench lateral direction is assumed to be W.The distance D between the collector region 128 and the intermediate region 22 is larger than the interval L 1 between the intermediate regions 22, that is, in an end portion of the diode portion 80 connected to the transistor portion 70, the density of the intermediate regions 22 is low compared with other regions. The end portion of the diode part 80 may refer to one or more trench parts sandwiching one or more mesa parts 150 in the trench lateral direction from a position that appears imaginary on the front surface when the position at which the cathode region 24 is in contact with the collector region 128 is projected imaginary on the front surface, as an example. Near the boundary between the transistor part 70 and the diode part 80, the collector region 128 may act similarly to the intermediate regions 22 at the time of reverse recovery. Due to this, in the end portion of the diode portion 80, the oscillation of voltage and current at the time of reverse recovery can be suppressed even without the intermediate regions 22 being provided. The boundary between the transistor part 70 and the diode part 80 may refer to a position at which the cathode region 24 is in contact with the collector region 128, for example.Since no intermediate regions 22 are provided in the end portion of the diode portion 80, the total area of the intermediate regions 22 in the XY plane can be reduced. Due to this, the operation of the diode part 80 can be stabilized, and the forward voltage of the diode part 80 can be reduced.Further, the distance D between the collector region 128 and the intermediate region 22 may be larger than the width L 2 of the intermediate region 22. Further, the distance D between the collector region 128 and the intermediate region 22 may be larger than the thickness W of the semiconductor substrate 10. When the distance D is further increased, characteristics such as the forward voltage of the diode part 80 can be further improved.FIG. 12 is a figure showing an example of arrangement of the intermediate regions 22 on a plane parallel to the back surface of the semiconductor device 300 shown in FIG. 11. In FIG. 12, the positions of the intermediate regions 22, the gate structures 120, the dummy trench structures 140, the cathode region 24, the gate connection part 160, and the dummy connection part 170 are shown to overlap each other. On the back surface side of the semiconductor substrate 10, in a region in which the cathode region 24 is not formed, the collector region 128 is formed.Although the gate structures 120 and the dummy trench structures 140 according to the present example have a U-shape, the shapes of the gate structure 120 and the dummy trench structures 140 are not limited thereto. The gate structures 120 and the dummy trench structures 140 each have linear parts formed extending in the Y-axis direction. A region sandwiched between the linear parts of the gate structures 120 or the dummy trench structures 140 is referred to as a mesa part 150.The gate connection part 160 is a gate runner connected to a gate electrode 124 of a gate structure 120. The dummy connection part 170 is a dummy runner connected to an electrode within a dummy trench structure 140. The gate connection part 160 and the dummy connection part 170 according to the present example are formed of polysilicon or the like. The gate connection part 160 and the dummy connection part 170 are formed above the front surface of the semiconductor substrate 10. An insulating film such as the interlayer dielectric film 114 is formed between the gate connection part 160 and the dummy connection part 170 and the semiconductor substrate 10. The gate connection part 160 and the dummy connection part 170 pass through contact holes formed in the interlayer dielectric film 114 and contact the front surface of the semiconductor substrate 10. The gate connection part 160 may be connected to a gate pad formed of a metal material. The dummy connection part 170 may be connected to the emitter electrode 112.As mentioned above, the gate structures 120 are formed on the front surface side of the transistor part 70, and the collector region 128 is formed on the back surface side. In the transistor part 70, one or more linear parts of the dummy trench structures 140 and one or more linear parts of the gate structures 120 may be formed alternately in the X-axis direction.The dummy trench structures 140 are formed on the front surface side of the diode part 80, and the cathode region 24 and the intermediate regions 22 are formed on the back surface side. The distance D between an end part of the cathode region 24 in the X-axis direction and the intermediate region 22 may be larger than the width L 3 of the mesa part 150. That is, in an end portion of the diode portion 80 in the X-axis direction under at least one mesa portion 150, intermediate regions 22 are not necessarily formed. In an end portion of the diode portion 80 in the X-axis direction, intermediate regions 22 are not necessarily formed among a plurality of mesa portions 150.Further, in the Y-axis direction, the distance between an end part of the cathode region 24 (a part contacting the collector region 128) and the intermediate region 22 is assumed to be DY. The distance DY may be larger than the interval L 4 between intermediate regions 22 in the Y-axis direction, larger than the width L 5 between intermediate regions 22 in the Y-axis direction, or larger than the thickness W of the semiconductor substrate 10.FIG. 13 is a figure showing another example of the density distribution of the lifetime killer 28 in the depth direction. In the present example, a position P 6 of the peak of the lifetime killer 28 is between positions P 4 and P 5 of the two peaks 26- a, 26- bin the FS region 20. As mentioned above, by disposing the peak position of the lifetime killer 28 and the peak position in the FS region 20 separately from each other, extinction between the lifetime killer 28 and protons or the like in the FS region 20 is suppressed.The density distribution of the lifetime killer 28 according to the present example has a relatively wide distribution. Since the lifetime killer 28 has a wide density distribution, the semiconductor device 100 can be caused to perform a soft recovery operation. Further, even if the implantation position of the lifetime killer 28 varies, the influence of the variation can be reduced. As an example, the full width at half maximum FWHM of the density distribution of lifetime killer 28 is equal to or greater than 5 μm. The full width at half maximum FWHM may be equal to or greater than 7 μm or equal to or greater than 9 μm.Further, the full width at the half maximum FWHM of the density distribution of the lifetime killer 28 may be equal to or greater than 70% of the interval (P 4-P 5) of the two peaks 26- aand 26- bten sandwiching the density peak of the lifetime killer 28. The full width at half maximum FWHM may be equal to or greater than 80% or 100% of the interval (P 4-P 5) of peak 26 of FS region 20.Further, the lifetime killer 28 may be distributed to reach a position where it overlaps the two peaks 26- aand 26- bof the FS region 20. As an example, at each of the position P 4 and the position P 5, the density of the lifetime killer 28 may be equal to or greater than 1% or 10% of the peak density of the lifetime killer 28.The operations, operations, steps, and steps of each process executed by an apparatus, a system, a program, and a method shown in the claims, embodiments, or diagrams may be executed in any order as long as the order is not indicated by "before", "before", or the like and as long as the product from a previous process is not used in a subsequent process. Although the process flow in the claims, embodiments, or diagrams is described using terms such as "first" or "subsequently", this does not necessarily mean that the process needs to be performed in this order.Explanation of Reference Numerals10: Semiconductor substrate; 12: anode electrode; 14: cathode electrode; 16: anode region; 18: drift region; 20: FS region; 22: intermediate region; 23: peak; 24: cathode region; 26: peak; 28: lifetime killer; 70: transistor part; 80: diode part; 100: semiconductor device; 112: emitter electrode; 114: interlayer dielectric film; 115: contact region; 116: emitter region; 118: base region; 120: gate structure; 122: gate insulating film; 124: gate electrode; 126: drift region; 128: collector region; 130: collector electrode; 140: dummy trench structure; 150: mesa part; 160: gate connection part; 170: dummy connection part; 200: semiconductor device; 300: semiconductor device

Claims

A semiconductor device (100, 200, 300) comprising: a semiconductor substrate (10); a first region (16) of a first conductivity type formed on a front surface side of the semiconductor substrate (10); a drift region (18) of a second conductivity type formed closer to a rear surface of the semiconductor substrate (10) than the first region (16); a buffer region (20) of a second conductivity type formed closer to the rear surface of the semiconductor substrate (10) than the drift region (18) and having a plurality of peaks (26) of an impurity density distribution higher than an impurity density of the drift region (18); and a lifetime killer (28) disposed on the back surface side of the semiconductor substrate (10) and shortening a carrier lifetime, wherein a density distribution peak of the lifetime killer (28) is disposed between a peak closest to a front surface of the semiconductor substrate (10) among the plurality of impurity density peaks (26) in the buffer region (20) and a back surface side of the buffer region (20), and wherein the density distribution peak of the lifetime killer (28) is disposed within the buffer region (20) and at a position not overlapping any of the plurality of impurity density peaks (26) in the buffer region (20).The semiconductor device (100, 200, 300) according to claim 1, wherein the density peak of the lifetime killer (28) is disposed closer to the back surface of the semiconductor substrate (10) than a peak disposed closest to the back surface of the semiconductor substrate (10) among the impurity density peaks (26) in the buffer region (20).The semiconductor device (100, 200, 300) according to claim 1 or 2, further including a second region of the first conductivity type formed between a peak closest to the back surface of the semiconductor substrate (10) among the peaks (26) of impurity density in the buffer region (20) and the back surface of the semiconductor substrate (10), wherein the peak of density of the lifetime killer (28) is disposed at a position not overlapping a peak of impurity density in the second region (22).The semiconductor device (100, 200, 300) according to claim 3, wherein the peak of the density of the lifetime killer (28) is disposed closer to the front surface of the semiconductor substrate (10) than the peak of the impurity density in the second region.The semiconductor device (100, 200, 300) according to claim 4, wherein a distance between the peak of the density of the lifetime killer (28) and the peak of the impurity density in the second region is larger than a distance between the peak of the density of the lifetime killer (28) and the peak closest to the back surface of the semiconductor substrate (10) from the peaks (26) of the impurity density in the buffer region (20).The semiconductor device (100, 200, 300) according to claim 4, further including a cathode region (24) of the second conductivity type formed at the same depth position as the second region (22), wherein the lifetime killer (28) is also formed above the cathode region (24).The semiconductor device (100, 200, 300) according to claim 1, wherein the density peak of the lifetime killer (28) is located between any two peaks (26) of the impurity density in the buffer region (20).The semiconductor device (100, 200, 300) according to claim 1, wherein a density distribution of the lifetime killer (28) in a depth direction of the semiconductor substrate (10) has a plurality of peaks.The semiconductor device (100, 200, 300) according to any one of claims 1 to 8, wherein the peak of the density of the lifetime killer (28) is higher than a peak closest to the back surface of the semiconductor substrate (10) among the peaks (26) of the impurity density in the buffer region (20).The semiconductor device (100, 200, 300) according to any one of claims 3 to 6, wherein the density peak of the lifetime killer (28) is lower than the density peak in the second region.The semiconductor device (100, 200, 300) according to any one of claims 1 to 10, wherein protons are implanted into the buffer region (20), and the lifetime killer (28) is helium.The semiconductor device (100, 200, 300) according to any one of claims 1 to 11, wherein a full width at half maximum of a density distribution of the lifetime killer (28) in a depth direction of the semiconductor substrate (10) is equal to or greater than 5 μm.The semiconductor device (100, 200, 300) according to claim 7, wherein the buffer region (20) has two peaks (26) of impurity density sandwiching the peak of density of the lifetime killer (28), and a full width at half maximum of density distribution of the lifetime killer (28) is equal to or greater than 70% of an interval between the two peaks (26).The semiconductor device (100, 200, 300) according to any one of claims 3 to 6, wherein the semiconductor substrate (10) has a transistor part (70) in which a transistor is formed and a diode part (80) in which a diode is formed, the second regions (22) are discretely provided in the diode part, and on a plane parallel to the back surface of the semiconductor substrate (10), a distance D between a boundary between the transistor part (70) and the diode part (80) and the second region (22) is larger than an interval between the second regions (22).A semiconductor device (100, 200, 300) comprising: a semiconductor substrate (10) having a front side and a back side; a first region of a first conductivity type formed on a front side of the semiconductor substrate (10); a drift region (18) of a second conductivity type formed closer to the back side of the semiconductor substrate (10) than the first region (16); a buffer region (20) of the second conductivity type formed closer to the back side of the semiconductor substrate (10) than the drift region (18), wherein the buffer region (20) has a plurality of peaks (26) of an impurity density distribution higher than an impurity density of the drift region (18); a second region (22) of the first conductivity type or the second conductivity type formed on a back side of the semiconductor substrate (10) and adjacent to the buffer region (20); a lifetime killer (28) disposed on the back surface of the semiconductor substrate (10), wherein the lifetime killer (28) shortens a carrier lifetime, wherein a peak of a density distribution of the lifetime killer (28) is disposed between a peak of the plurality of peaks (26) of the impurity density distribution in the buffer region (20) closest to the front surface of the semiconductor substrate (10) and a back surface side of the buffer region (20), the peak of the density distribution of the lifetime killer (28) is within the buffer region (20), and a distance between a peak of the plurality of peaks (26) of the impurity density in the buffer region (20) adjoining the peak of the density distribution of the lifetime killer (28) at the front surface of the semiconductor substrate (10), and the peak of the density distribution of the lifetime killer (28) is equal to or larger than half the width at half maximum of the density distribution of the peak of the lifetime killer (28).The semiconductor device (100, 200, 300) according to claim 15, wherein the density distribution peak of the lifetime killer (28) is disposed at a position not overlapping with one or more of the plurality of impurity density distribution peaks (26) in the buffer region (20).The semiconductor device (100, 200, 300) according to claim 15, wherein the density distribution peak of the lifetime killer (28) is located between any two peaks (26) of the impurity density in the buffer region (20).The semiconductor device (100, 200, 300) according to claim 17, wherein the distance between the peak (26) of the plurality of peaks (26) of the impurity density distribution in the buffer region (20) adjacent to the peak of the density distribution of the lifetime killer (28) at the front side of the semiconductor substrate (10) and the peak of the density distribution of the lifetime killer (28) is equal to or greater than the full width at half maximum of the density distribution of the peak of the lifetime killer (28).The semiconductor device (100, 200, 300) according to claim 15, wherein the density peak of the lifetime killer (28) is disposed closer to the back surface of the semiconductor substrate (10) than a peak among the impurity density peaks (26) in the buffer region (20) closest to the back surface of the semiconductor substrate (10).The semiconductor device (100, 200, 300) according to claim 15, wherein the density distribution of the lifetime killer (28) in the depth direction of the semiconductor substrate (10) has a plurality of peaks including the density distribution peak of the lifetime killer (28).The semiconductor device (100, 200, 300) according to claim 15, wherein the density peak of the lifetime killer (28) is higher than one of the plurality of impurity density peaks (26) in the buffer region (20) closest to the back surface of the semiconductor substrate (10).The semiconductor device (100, 200, 300) of claim 15, wherein protons are implanted into the buffer region (20) and the lifetime killer (28) is helium.The semiconductor device (100, 200, 300) according to claim 15, wherein a full width at half maximum (FWHM) of the density distribution of the lifetime killer (28) in a depth direction of the semiconductor substrate (10) is equal to or greater than 5 μm.The semiconductor device (100, 200, 300) according to claim 17, wherein the plurality of peaks (26) of the impurity density in the buffer region (20) include two peaks (26) embedding the peak of the density of the lifetime killer (28), and a full width at half maximum (FWHM) of the density of the lifetime killer (28) is equal to or greater than 70% of an interval between the two peaks (26).The semiconductor device (100, 200, 300) according to claim 15, wherein the second region is formed of a third region of the first conductivity type and a fourth region of the second conductivity type adjacent to the third region.The semiconductor device (100, 200, 300) according to claim 15, wherein the semiconductor substrate (10) includes a transistor part (70) in which a transistor is formed and a diode part (80) in which a diode is formed, and the second region in the transistor part (70) has the first conductivity type and the second region in the diode part (80) has at least the first conductivity type.The semiconductor device (100, 200, 300) according to claim 26, wherein the second region in the transistor part (70) is formed of a third region of the first conductivity type and a fourth region of the second conductivity type adjacent to the third region.The semiconductor device (100, 200, 300) according to claim 25, wherein the fourth region is a cathode region (24) formed at the same depth position as the second region (22).The semiconductor device (100, 200, 300) according to claim 26, wherein the second region in the transistor part (70) is a p-type collector region (128).

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