Semiconductor device and power converter device

Abstract

Semiconductor device that features the following: - a semiconductor substrate (1); - a semiconductor layer (2) of a first conductivity type arranged on a first main surface of the semiconductor substrate; - a first semiconductor region (3) of the first conductivity type, which is selectively formed in an upper layer region of the semiconductor layer; - a second semiconductor region (4) of a second conductivity type, which is formed in the upper layer region of the semiconductor layer by contacting the first semiconductor region; - a third semiconductor region (5) of the second conductivity type, which is in contact with a base surface of the first and second semiconductor regions; - Trenches (6) passing through the first and third semiconductor regions in the thickness direction and reaching an inner side of the semiconductor layer; - a gate insulating layer (9) covering an inner surface of each of the trenches; - a gate electrode (10) embedded in each of the trenches, which is covered with the gate insulating layer; - a trench soil protection layer (7) of the second conductivity type, designed to touch each soil of the respective trench; - a depletion suppression layer (8, 81) of the first conductivity type, placed between adjacent trench soil protection layers; - an intermediate insulating layer (16) covering the uppermost areas of the trenches and the first semiconductor region around the trenches and having a contact hole (CH) over the first and second semiconductor region; - a first main electrode (11) covering the intermediate insulating layer and embedded in the contact hole; and - a second main electrode (12) arranged on a second main surface of the semiconductor substrate, - wherein the depletion suppression layer (8, 81) has an intermediate point which is horizontally equidistant to the adjacent trench soil protection layers (7), - wherein the depletion suppression layer (8, 81) is so large that it does not touch any of the third semiconductor regions, the trenches and the trench bottom protection layers (7), - wherein the depletion suppression layer (8, 81) is designed to be at the same depth and thickness as the trench bottom protection layer (7), and - wherein the impurity concentration of the depletion suppression layer (8, 81) is specified as higher than the impurity concentration of the semiconductor layer.

Description

TECHNICAL AREA

[0001] The present invention relates to a semiconductor device, in particular to a semiconductor device with a trench gate. STATE OF THE ART

[0002] In power electronics devices, a switching component, referred to as an insulated gate semiconductor device, such as an IGBT (Insulated Gate Bipolar Transistor) and a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), is commonly used to control the power supply to a load, such as an electric motor.

[0003] An example of such a semiconductor device with an insulated gate is a trench-gate MOSFET, in which a gate electrode is embedded in a semiconductor layer. In a trench-gate MOSFET, the formation of trenches in the semiconductor layer and the use of the side faces as channel areas make it possible to increase the channel width density and improve the device's performance.

[0004] As a next-generation semiconductor device capable of achieving high breakdown voltage and low loss, a semiconductor device with a wide bandgap semiconductor, such as silicon carbide (SiC), has attracted attention, and the use of trench-gate type MOSFETs has also been promoted.

[0005] When using silicon carbide as a semiconductor material, its high dielectric breakdown voltage makes it possible to achieve a semiconductor device with a high breakdown voltage. However, since a high voltage is applied during the OFF state, a strong electric field is applied to the gate insulating layer, increasing the likelihood of failure. In particular, with trench-gate designs, the bottom of the trench is located close to the substrate, and the electric field is easily concentrated at this point. Therefore, there is a risk of reduced reliability of the gate insulating layer.

[0006] As a method for reducing the electric field at the bottom of the trench, a configuration was proposed, as shown in Patent Document 1, in which the bottom of the trench is covered with an impurity layer of a conductivity opposite to that of a drift layer to form a protective layer. Patent Document 1 shows a configuration in which a trench gate is formed in an n-type drift layer and a p-type protective layer is formed such that it is in contact with the bottom surface of the n-type drift layer. The bottom of the trench can be protected from the electric field by applying a high bias voltage between a drain electrode and the source electrode, and the field intensity of the gate insulating layer formed at the bottom of the trench can be kept low.

[0007] This method of forming the protective layer on the bottom of the trench makes it possible to protect the trench bottom and improve reliability. A JFET (Junction Field Effect Transistor) region is formed between the p-type protective layers on the bottoms of the adjacent trenches. When the MOSFET is switched on, a drain current flows through the JFET region sandwiched between the p-type protective layers. However, because a depletion layer extending from the protective layer into the drift layer also spreads to some extent when the MOSFET is switched on, one current path narrows and the ON resistance of the switching device increases.

[0008] Therefore, as shown in patent document 2, a configuration has been proposed in which an n-type impurity layer is formed to come into contact with a side surface of a p-type protective layer to form a depletion suppression layer to suppress depletion.

[0009] The formation of the n-type impurity layer makes it possible to suppress the extension of the depletion layer from the protective layer and to widen the current path. However, this also increases the field intensity at the bottom of the trench, and the field intensity of the gate insulating layer cannot be kept low. In particular, one corner of the trench bottom is not covered by the p-type protective layer, so a field strength reduction effect is not to be expected.

[0010] Another example of a configuration to maintain the ON resistance (ensuring the current path) while simultaneously reducing the JFET resistance is to increase the cell spacing (the distance between the trench gates) of the MOSFET, thereby decreasing the number of trenches per unit area. This reduces the channel width density serving as the current path, leading to an increase in the ON resistance. Furthermore, as the distance between the shielding layers increases, the field intensity at the bottom of the trench and at the base of a body region also increases, resulting in a decrease in the breakdown voltage of the device and a deterioration in the reliability of the gate insulation layer. STATE OF THE ART Patent document 1: WO 2015 / 072 052 A1 Patent document 2: JP 2005 - 236 267 A BRIEF DESCRIPTION OF THE INVENTION Problems to be solved with the invention

[0011] As described above, in a trench-gate MOSFET, the electric field tends to concentrate at the bottom of the trench when a high voltage is applied in the OFF state. Therefore, as with the trench-gate MOSFETs described in patent documents 1 and 2, a configuration has been proposed in which a protective layer with a conductivity opposite to that of the drift layer is formed at the bottom of the trench.

[0012] In such a configuration, the problem arises due to the depletion layer extending from the protective layer: the current path of the drain current between the adjacent protective layers narrows, and the ON resistance of the switching component increases.

[0013] As shown in patent document 2, if a high-concentration depletion suppression layer of the same conductivity type as the drift layer is formed on the side surface of the protective layer, the extent of the depletion layer can be suppressed, and the current path widens to allow for a reduction in the increase in the ON resistance. However, because the depletion suppression layer, with a higher concentration than the drift layer, is in contact with the gate insulating layer at the bottom of the trench, the field intensity at the bottom of the trench increases.

[0014] In this way, when the configuration for relaxing the electric field applied to the gate insulating layer is achieved by placing the protective layer at the bottom of the trench, the current path narrows because the depletion layer extends from the protective layer into the drift layer, causing an increase in the JFET resistance, but in solving this problem, the field strength at the bottom of the trench increases.

[0015] The present invention was designed to solve the problem described above, and it is an object of the present invention to provide a semiconductor device that improves the trade-off between reducing the concentration of the electric field at the bottom of a trench and reducing the ON resistance. Means of solving the problems

[0016] The present invention solves the problem with a semiconductor device according to independent claims 1, 2, 5 and a power converter device according to independent claim 11. Advantageous further developments are specified in dependent claims 3, 4 and 6 to 10. Effect of the invention

[0017] The present invention makes it possible to improve the trade-off between reducing the concentration of the electric field at the bottom of the trench and reducing the ON resistance. Furthermore, the breakdown voltage can be maintained without increasing the field strength at the bottom of the third semiconductor region, which is a body region. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 is a sectional view showing a configuration of a cell of a MOSFET in a first embodiment according to the present invention; Fig. Figure 2 is a view showing a depletion layer that forms when the MOSFET is switched on in the first embodiment according to the present invention; Fig. Figure 3 shows a depletion layer that forms when the MOSFET is turned on if no depletion suppression layer is present; Fig. Figure 4 is a graphic showing simulation results of the MOSFET of the first embodiment according to the present invention and of a conventional MOSFET; Fig. Figure 5 is a graphic showing simulation results of the MOSFET of the first embodiment according to the present invention and of the conventional MOSFET; Fig. Figure 6 is a sectional view to illustrate a manufacturing step of the MOSFET in the first embodiment according to the present invention; Fig. Figure 7 is a sectional view to illustrate a manufacturing step of the MOSFET in the first embodiment according to the present invention; Fig. Figure 8 is a sectional view to illustrate a manufacturing step of the MOSFET in the first embodiment according to the present invention; Fig. Figure 9 is a sectional view to illustrate a manufacturing step of the MOSFET in the first embodiment according to the present invention; Fig. Figure 10 is a sectional view to illustrate a manufacturing step of the MOSFET in the first embodiment according to the present invention; Fig. Figure 11 is a sectional view to illustrate a manufacturing step of the MOSFET in the first embodiment according to the present invention; Fig. Figure 12 is a sectional view to illustrate a manufacturing step of the MOSFET in the first embodiment according to the present invention; Fig. Figure 13 is a sectional view to illustrate a manufacturing step of the MOSFET in the first embodiment according to the present invention; Fig. Figure 14 is a view showing an example of a planar pattern of a cell of the MOSFET in the first embodiment according to the present invention; Fig. Figure 15 is a view showing an example of the planar pattern of the cell of the MOSFET in the first embodiment according to the present invention; Fig. Figure 16 is a view showing an example of the planar pattern of the cell of the MOSFET in the first embodiment according to the present invention; Fig. Figure 17 is a top view showing a configuration of a potential fixing area of ​​a trench bottom protection layer and a source electrode; Fig. Figure 18 is a sectional view showing the configuration of the potential fixing area of ​​the trench bottom protection layer and the source electrode; Fig. Figure 19 is a sectional view to illustrate one step in the formation of the potential fixation area; Fig. Figure 20 is a cross-sectional view to illustrate the formation process of the potential fixation area; Fig. Figure 21 is a sectional view to illustrate the formation process of the potential fixation area; Fig. Figure 22 is a sectional view showing a configuration of a cell of a MOSFET in a first modification of the first embodiment according to the present invention; Fig. Figure 23 is a sectional view showing a configuration of a cell of a MOSFET in a second modification of the first embodiment according to the present invention; Fig. Figure 24 is a sectional view showing a configuration of a cell of a MOSFET in a third modification of the first embodiment according to the present invention; Fig. Figure 25 is a sectional view showing a configuration of a cell of a MOSFET in a fourth modification of the first embodiment according to the present invention; Fig. Figure 26 is a sectional view showing a configuration of a cell of a MOSFET in a second embodiment according to the present invention; Fig. Figure 27 is a view showing the relation between a side wall of a trench and a crystal plane; Fig. Figure 28 is a view showing an example of a planar pattern of the cell of the MOSFET in the second embodiment according to the present invention; Fig. Figure 29 is a view showing an example of the planar pattern of the cell of the MOSFET in the second embodiment according to the present invention; Fig. Figure 30 is a view showing an example of the planar pattern of the cell of the MOSFET in the second embodiment according to the present invention; Fig. Figure 31 is a sectional view showing a configuration of a cell of a MOSFET in a third embodiment according to the present invention; Fig. Figure 32 is a view showing an example of a planar pattern of a cell of a MOSFET in a modification of the third embodiment according to the present invention; Fig. Figure 33 is a sectional view showing a configuration of a potential fixing area of ​​a trench bottom protection layer and a source electrode; Fig. Figure 34 is a sectional view showing the configuration of the potential-fixing area of ​​the trench bottom protection layer and the source electrode; and Fig. Figure 35 is a block diagram showing a configuration of an energy converter system in a fifth embodiment according to the present invention. DESCRIPTION OF THE FORM(S) Introduction

[0018] Embodiments according to the present invention are described below. Furthermore, the sizes of each individual element in the drawings described below may differ from the actual size to facilitate understanding. This also applies to each drawing.

[0019] In the past, the term "MOS" was used for the interconnect structures of metal-oxide semiconductors. It is believed to have been adopted from the acronym for metal-oxide semiconductor. However, in the case of field-effect transistors with a MOS structure (hereinafter simply referred to as "MOS transistor"), the materials for the gate insulating layer and the gate electrode have been improved due to recent integration and improvements in manufacturing processes, among other things.

[0020] For example, in MOS transistors, polycrystalline silicon has been used instead of metal as the material for the gate electrode, primarily due to the self-aligning formation of the source and drain. From the perspective of improving electrical properties, a material with a high dielectric constant is used for the gate insulating layer, and this material is not necessarily limited to an oxide.

[0021] Therefore, the term "MOS" is not necessarily used only with the restriction of the laminated or layered structure of metal-oxide semiconductors. Such a restriction is not assumed in the present description. That is to say, from a general technical perspective, "MOS" here not only has a meaning as an abbreviation from its etymology, but also signifies a layered structure of a conductor-insulator semiconductor.

[0022] In the following description, an n-type is generally defined as the “first conductivity type” and a p-type as the “second conductivity type” in relation to a conductivity type of impurities, although of course the reverse definition can also be used. Design 1: Summary of Configuration

[0023] Fig. Figure 1 is a sectional view that schematically represents a partial configuration of a field-effect transistor (SiC-MOSFET) 100 with a MOS structure formed on a SiC substrate. Fig. Figure 1 shows the minimal unit structure of the MOS, referred to as the "cell", surrounded by dashed lines, and the actual SiC-MOSFET 100 has a multitude of cells.

[0024] As in Fig. Figure 1 shows the SiC MOSFET 100 on a SiC substrate 1 with n-type (first conductivity type) impurities in a relatively high concentration in the range of 1 × 10 18 up to 1 × 10 21 cm -3 educated.

[0025] A drift layer 2 (semiconductor layer) is formed on the main surface of the SiC substrate 1, containing n-type impurities in a relatively low concentration in the range of 1 × 10 14 up to 1 × 10 17 cm -3contains. Drift layer 2, for example, is formed by epitaxial growth.

[0026] In an upper layer region of drift layer 2, there is a source region 3 (first semiconductor region) with n-type impurities (donor impurities) of approximately 1 × 10 19 cm -3 and a body contact area 4 (second semiconductor area) with p-type (second conductivity type) impurities (acceptor impurities) of about 1 × 10 20 cm -3 arranged in a sandwich-like fashion towards source area 3.

[0027] A body region 5 (third semiconductor region) with p-impurities in a relatively low concentration in the range of 1 × 10 14 cm -3 up to 1 × 10 18 cm -3 is designed in such a way that it is in contact with the ground surfaces of the source area 3 and the body contact area 4.

[0028] Two trenches 6, which penetrate the source region 3 and the body region 5 in the thickness direction and extend into the interior of the drift layer 2, are designed to enclose the body contact region 4. A gate insulating layer 9 is designed to cover the inner surface of the trench 6, and a gate electrode 10 is embedded in the trench 6 covered by the gate insulating layer 9.

[0029] The upper ends or top surfaces of the trench 6 and the source region 3 surrounding the trench 6 are covered with an intermediate insulating layer 16. A contact hole CH, reaching the source region 3 and the body contact region 4, is formed in the intermediate insulating layer 16. Although the gate electrode 10 is covered by the intermediate insulating layer 16, a gate voltage is applied via an opening in the intermediate insulating layer 16, which is formed in a region not shown here.

[0030] A source electrode 11 (first main electrode) is configured to cover the intermediate insulating layer 16 and fill the contact hole CH, and a drain electrode 12 (second main electrode) is formed on the main surface of the SiC substrate 1 on the side opposite the side on which the source electrode 11 is formed.

[0031] In drift layer 2, a trench bottom protection layer 7, approximately the same width as trench 6, is formed in such a way that it is in contact with the bottom surface of trench 6. The trench bottom protection layer 7 contains phosphorus impurities in a relatively high concentration in the range of 1 × 10⁻⁶ 17 up to 1 × 10 19 cm -3 , and their thickness is specified in the range of 0.1 µm to 2.0 µm.

[0032] Then, in the drift layer 2 between the adjacent trench soil protection layers 7, an n-type depletion suppression layer 8 with a contamination concentration higher than that of the drift layer 2 is formed such that it includes an intermediate point that is equidistant in the horizontal direction (parallel to the main surface of the substrate) to the two adjacent trench soil protection layers 7.

[0033] The depletion suppression layer 8 is designed with such a size that it does not touch the body area 5, the trenches 6, or the trench bottom protection layers 7. The depletion suppression layer 8 is in Fig. 1 designed so that its horizontal center coincides with the horizontal center between the trench bottom protection layers 7, i.e. the depletion suppression layer 8 is equidistant from both trench bottom protection layers 7.

[0034] If the depletion suppression layer 8 contains n-type impurities at a higher concentration than the drift layer 2, it becomes possible to suppress the extent of the depletion layer within the depletion suppression layer 8 and prevent an overlap of the depletion layers extending from the two trenches 6. The application of the depletion suppression layer 8 leads to a slight increase in the electric field at the bottom of the trench 6, so that the impurity concentration in the depletion suppression layer 8 is set higher than the concentration required to prevent an overlap of the depletion layers extending from the two adjacent trench bottom protection layers 7 during the ON state of the MOSFET.

[0035] It is set such that an increase in the electric field at the bottom of trench 6 to, for example, 30% or less at the time a high bias voltage is applied during the OFF state of the MOSFET is suppressed. It is therefore set, for example, in the range of 1 × 10 16 up to 1 × 10 18 cm -3 or in the range of 2 to 100 times higher than specified in drift layer 2.

[0036] The width of the depletion suppression layer 8 is specified in the range of 5% to 50% of the cell pitch of the MOSFET (a distance between the centers of the trench gates), so that the bottom of the trench 6 is not exposed to a high electric field when the high bias voltage is applied. To suppress horizontal expansion of the depletion layer from the trench bottom protection layer 7 when the MOSFET is switched on, and to maintain the breakdown voltage by sufficient expansion of the depletion layer in the drift layer 2 when the MOSFET is switched off, the depletion suppression layer 8 is preferably designed to be at the same depth as the trench bottom protection layer 7 and is specified to have a thickness in the range of 0.1 to 2 µm, which corresponds to the thickness of the trench bottom protection layer 7.

[0037] In Fig. 2 Depletion layers DL are indicated by dashed lines, which are created when the MOSFET is switched on; the extent of the depletion layers of the two adjacent trench soil protection layers 7 is suppressed. Fig. Figure 3 shows, using dashed lines, the depletion layers DL that form when the MOSFET is switched on, in a case where the depletion suppression layer 8 is not formed and the depletion layers DL extend from the trench bottom protection layers 7 to the central region between the trench gates. Due to the influence of the depletion layers DL, a JFET region formed between the adjacent trench bottom protection layers 7 narrows, and an ON current path narrows, increasing the JFET resistance.

[0038] On the other hand, as in Fig. 2 shown, then, if the depletion suppression layer 8 is formed with a contaminant concentration higher than the contaminant concentration of the drift layer 2 between the trench bottom protection layers 7, the extent of the depletion layer DL is reduced, and the EIN current path widens, which reduces the JFET resistance.

[0039] Furthermore, widening the EIN current path prevents the increase in JFET resistance from having an effect even when the cell spacing is narrowed, compared to the conventional case. This makes it possible to suppress a reduction in channel width density caused by widening the cell spacing, thus avoiding an increase in JFET resistance and suppressing an increase in EIN resistance. Additionally, the distance between the trench bottom protection layers 7 decreases due to the reduced cell spacing, which reduces the field intensity at the bottom of the trench 6, thereby improving the breakdown voltage and reliability of the gate insulation layer 9.

[0040] This allows for a higher reduction effect of the EIN resistance. Although the width of the depletion layer increases with increasing temperature, the rise in the JFET resistance can be suppressed by the depletion suppression layer 8, which also improves the temperature characteristics of the EIN resistance.

[0041] The Fig. 4 and Fig. Figure 5 shows simulation results for a conventional configuration in which an n-type impurity layer is formed in contact with the side face of a p-type protective layer, as is the case with a configuration of the SiC-MOSFET 100 in Fig. 1 is shown.

[0042] Fig. Figure 4 is a diagram showing the characteristic curve of the field intensity (arbitrarily chosen unit) of the gate insulating layer in relation to a change in the drain voltage (arbitrarily chosen unit) during the OFF state of the MOSFET; Fig. Figure 5 is a graph showing the characteristic curve of a drain current (arbitrarily chosen unit) in relation to a change in the drain voltage (arbitrarily chosen unit) during the OFF state of the MOSFET; in each of the Fig. 4 and Fig. 5. The characteristic curve of the conventional configuration is represented by a dashed line, and the characteristic curve of the configuration according to Fig. 1 is indicated by a solid line.

[0043] From the Fig. 4 and Fig. 5 shows that when configuring according to Fig. 1, in which the depletion suppression layer 8 is formed at a location remote from the trench 6 and the trench bottom protection layer 7, the field intensity at the bottom of the trench is reduced, and the field intensity of the gate insulating layer and the drain current during the OFF state of the MOSFET are reduced compared to the conventional configuration. This leads to an improvement in the breakdown voltage and the reliability of the gate insulating layer 9.

[0044] Furthermore, with the depletion suppression layer 8 also being located away from the body region 5, the field intensity at the bottom of the body region 5 does not increase during the off-state, which improves the reliability of the gate insulating layer 9 without a decrease in the breakdown voltage.

[0045] As described above, the application of the depletion suppression layer 8 reduces the width of the depletion layer, which extends horizontally from the trench bottom protection layer 7 into the drift layer 2 when the device is switched on, and widens the ON current path in the JFET area, making it possible to reduce the JFET resistance generated between the trench bottom protection layers 7 and to reduce the ON resistance of the MOSFET.

[0046] Furthermore, by removing the depletion suppression layer 8 from the body area 5, the trench 6 and the trench bottom protection layer 7, it is possible to improve the breakdown voltage and reduce the field strength of the gate insulation layer 9 compared to the conventional structure in which the depletion suppression layer and the trench bottom protection layer are located next to each other.

[0047] Furthermore, it is possible to reduce cell division, increase channel width density, and relax the electric field at the bottom of the trench. These effects improve the reduction of the ON resistance, the reliability of the gate insulating layer, and the breakdown voltage, thus improving the compromise between the ON and OFF characteristics of the device. Manufacturing process

[0048] With reference to the Fig. Figures 6 to 13, which sequentially depict sectional views, are followed by a description of a manufacturing process for the SiC MOSFET 100. The materials mentioned as examples in the following description can be substituted for other materials with equivalent functions.

[0049] First, in the Fig. In step 6, a SiC substrate 1 with n-type impurities in the range of 1 × 10 is shown. 18 up to 1 × 10 21 cm -3The substrate is prepared, and on a major surface of the SiC substrate 1, an n-type silicon carbide layer is formed by epitaxial growth to create the drift layer 2. The impurity concentration of the drift layer 2 is in the range of 1 × 10⁻⁶ 14 up to 1 × 10 17 cm -3 It should be noted that the thickness of the SiC substrate 1 is between 50 µm and 400 µm and the thickness of the drift layer 2 is between 5 µm and 150 µm.

[0050] Next, in the Fig. In step 7, body region 5 is formed in the upper layer of drift layer 2, and source region 3 and body contact region 4 are selectively formed in the upper layer of body region 5. Body region 5, source region 3, and body contact region 4 can be formed by ion implantation or epitaxial growth, and the order of formation is not restricted. For example, after body region 5 is formed by ion implantation or epitaxial growth, source region 3 is selectively formed by ion implantation of n-type impurities in the upper layer of body region 5, and then body contact region 4 is selectively formed by ion implantation of p-type impurities in a portion of source region 3.

[0051] It should be noted that the contamination concentration of body area 5 is in the range of 1 × 10 14 up to 1 × 10 18 cm -3and whose thickness is specified in the range of 0.2 µm to 1.0 µm. The concentration and thickness do not need to be uniform. Furthermore, the impurity concentration of source area 3 is set to approximately 1 × 10 19 cm -3 specified, the thickness to 0.2 to 0.5 µm, the contamination concentration of the body contact area 4 to approximately 1 × 10 20 cm -3 , the thickness to approximately the same as that of the source area 3.

[0052] Next, in the Fig. In step 8, a resist mask RM1 with a pattern in which an opening is formed above a region where the depletion suppression layer 8 is to be formed is created on the SiC substrate 1 in a state where the source region 3 and the like are formed by photolithography. The ion implantation of n-type impurities is carried out from above the resist mask RM1 to form the depletion suppression layer 8 in the drift layer 2. It should be noted that this ion implantation can be carried out before or after the formation of the source region 3, the body contact region 4, and the body region 5, as long as the drift layer 2 is formed.

[0053] Alternatively, ion implantation can be performed during the formation of drift layer 2 to form depletion-suppression layer 8. That is, when the epitaxial growth of drift layer 2 is underway and its thickness exceeds the position of the top surface of depletion-suppression layer 8, ion implantation of n-type impurities is selectively performed to form depletion-suppression layer 8. Subsequently, epitaxial growth of drift layer 2 is restarted to achieve a configuration in which depletion-suppression layer 8 is embedded within drift layer 2.

[0054] When this method is applied, the implantation depth at the time of ion implantation can be reduced to allow implantation at a low accelerating voltage. This makes it possible to suppress excessive diffusion, the generation of crystal defects, and similar issues caused by high-energy ion implantation. As a result, the need for high-accelerating voltage ion implantation is eliminated, and there is also the advantage of reducing the equipment costs associated with ion implantation.

[0055] When the above procedure is applied, heat treatment (tempering) can be carried out after ion implantation to repair damage, such as a crystal defect caused by ion implantation, or an oxide layer can be formed on the surface of the drift layer 2 after ion implantation (sacrificial oxidation), and the oxide layer can then be removed by etching to eliminate the damage on the surface of the drift layer 2 along with the oxide layer, and after that the epitaxial growth can be carried out again to bring the drift layer 2 to a predetermined height.

[0056] After removing the resist mask RM1, the following occurs in the Fig. In step 9, a silicon oxide layer is formed on the SiC substrate 1, and a resist mask with a pattern containing an opening above the area where the trench 6 is to be formed is created on the silicon oxide layer using photolithography. The silicon oxide layer is then structured by an etching process using the resist mask as the etching mask to obtain an etching mask EM1 with an opening above the area where the trench 6 is to be formed. Using the etching mask EM1, trenches 6, which penetrate the source area 3 and the body area 5 in the thickness direction, are formed by reactive ion etching. The depth of the trench 6 is equal to or greater than the depth of the body area 5 and is specified to a depth of 1.0 to 6.0 µm.

[0057] Next, in the Fig. In step 10, using the etching mask EM1 as an implantation mask, p-type contaminants are implanted as ions into the drift layer 2 below the bottom surface of trench 6 to form the trench bottom protection layer 7. The concentration of the p-type contaminants in the trench bottom protection layer 7 is in the range of 1 x 10 17 up to 1 x 10 19 cm -3 and the thickness is specified in the range of 0.1 to 2.0 µm.

[0058] Instead of ion implantation, the trench floor protective layer 7 can be formed in trench 6 by epitaxial growth into the depth after the formation of trench 6, by the thickness of the trench floor protective layer 7 (0.1 to 2.0 µm). It should be noted that the concentration and thickness of the trench floor protective layer 7 may be uneven.

[0059] After removing the etching mask EM1, tempering is performed using a heat treatment unit (tempering unit) to activate the impurities implanted as ions in the previous steps. This tempering is carried out in an inert gas atmosphere such as argon (Ar) gas or in a vacuum at a temperature in the range of 1300 °C to 1900 °C for 30 seconds to one hour.

[0060] Next, in the Fig. In the step shown in Figure 11, after the formation of an insulating layer 20, e.g., made of silicon oxide, to at least cover the inner surface of the groove 6, a conductive layer 21, e.g., made of conductive polysilicon, is formed on the insulating layer 20 and the conductive layer 21 is embedded in the groove 6. Then, the conductive layer 21 and the insulating layer 20 are etched with a pattern such that only the gate insulating layer 9 and the gate electrode 10 remain in the groove 6.

[0061] Here, the thickness of the insulating layer 20 at the bottom of the trench 6 can be greater than the thickness of the insulating layer 20 in the lateral area of ​​the surface of the trench 6. Although the thickness of the in Fig. Since the gate insulating layer 9 shown in Figure 1 is the same for both the side surface area and the bottom, only the side surface area actually contributes to the operation of the MOSFET like the gate insulating layer, and the bottom does not contribute to the operation as a MOSFET.

[0062] Furthermore, as described above, the electric field tends to concentrate on the bottom of the trench 6, and dielectric breakdown is likely to occur. Therefore, by selectively thickening the lower gate insulating layer in addition to applying the trench bottom protective layer 7, it is possible to further reduce the influence of the electric field acting on the gate insulating layer 9.

[0063] Next, in the Fig. In step 12, an insulating layer 22, for example made of silicon dioxide, is formed to cover the SiC substrate 1, and it covers the gate insulating layer 9 and the gate electrode 10 in the trench 6, which are exposed on the surface of the source region 3. Using photolithography, a resist mask RM2 is formed with a pattern in which an opening is formed over the source region 3 and the body contact region 4, and the uppermost areas of the trench 6 and the source region 3 around the trench 6 are covered.

[0064] Using the resist mask RM2 as an etching mask, the insulating layer 22 is then patterned by etching to form the intermediate insulating layer 16 with a contact hole CH that reaches the source area 3 and the body contact area 4 and covers the uppermost areas of the trenches 6 and the source area 3 around the trench 6, as shown in Fig. 13 shown.

[0065] Next, the source electrode 11 is formed, which covers the intermediate insulating layer 16 and fills the contact hole CH. To ensure that the source electrode 11 is in ohmic contact with the source area 3 and the body contact area 4, a metal layer is first formed on the entire surface of the drift layer 2, including the inside of the contact hole CH, by sputtering or a similar process. This metal layer contains, for example, nickel (Ni) as the main component and is reacted with silicon carbide by heat treatment at 600 °C to 1100 °C to form a nickel silicide layer (not shown) as an ohmic electrode. The unreacted metal layer on the intermediate insulating layer 16 is then removed by wet plating. A further heat treatment can be performed after removing the metal layer from the intermediate insulating layer 16.

[0066] In this case, the ohmic contact with an even lower contact resistance is formed by carrying out the heat treatment at a higher temperature than in the previous heat treatment. Then, by sputtering or the like, a metal layer of an Al (aluminum) alloy or the like is formed to cover the silicide layer and the intermediate insulating layer 16, so that the source electrode 11 is formed on the intermediate insulating layer 16 and the contact hole CH.

[0067] As a result, the source electrode 11 is electrically connected via the nickel silicide layer as an ohmic electrode to the source area 3 and the body contact area 4, so that the source electrode 11 essentially comes into ohmic contact with the source area 3 and the body contact area 4 in order to enable a reduction of the contact resistance.

[0068] Finally, a metal layer made of an Al alloy is formed by sputtering or the like on the main surface of the SiC substrate 1 on the side opposite the side on which the source electrode 11 is formed, in order to form the drain electrode 12 and connect the SiC MOSFET 100 to the Fig. to obtain the cell structure shown in 1.

[0069] Here it shows Fig. 14 an example of the planar cell pattern of the SiC-MOSFET 100. Fig. Figure 14 shows a cell of a planar pattern in which the trenches 6 are strip-shaped, and a cross-section along line AA according to Fig. 14 in the direction of the arrow corresponds to the section view according to Fig. 1. In Fig. For the sake of simplicity, the configuration above the source area 3 and the body contact area 4 has been omitted, and the body area 5, the gate insulating layer 9 and the gate electrode 10 in the trench 6 are seen from above, but for clarity the depletion suppression layer 8 is indicated as being surrounded by a dashed line.

[0070] As in Fig. As shown in Figure 14, the depletion suppression layer 8 is formed along the extension direction of the trench 6, but has a length that does not correspond to the length of the trench 6 and is configured to be subdivided into a predetermined length.

[0071] Fig. Figure 15 is a view showing another example of the planar cell pattern of the SiC-MOSFET 100 and depicts a cell with a planar pattern in which the trenches 6 have a grid shape. When the trench 6 has a grid shape, the shape in the top view of the cell enclosed by the trench 6 is a quadrilateral / square, but is not limited to a quadrilateral. The shape in the top view of the cell enclosed by the trench 6 can be a rectangle or a polygon, or each corner can have a curvature. Furthermore, the trenches 6 can be shaped so that quadrilateral / square cells are arranged in a zigzag pattern.

[0072] Fig. Figure 16 shows another example of a planar cell pattern of the cells of the SiC MOSFET 100. In the planar pattern, where the trenches 6 are formed in strip form, the quadrilateral depletion suppression layers 8 are discontinuously formed along the extension direction of the trenches 6. Such an arrangement is called an island configuration.

[0073] Although in the Fig. Not shown in Figures 14 to 16, the trench floor protection layer 7 has the same length as the length of the trench 6 in the direction of extension of the trench 6, and the source areas 3 and the body contact areas 4 are formed in strip or island form according to the shape of the trenches 6.

[0074] The depletion suppression layer 8 is to be formed only in the central area between the trench soil protection layers 7 (not shown) horizontally equidistant from the trench soil protection layer 7 around the depletion suppression layer 8, and the depletion suppression layers 8 are to be formed in strip form according to Fig. 14 or in island form according to Fig. 15 and Fig. 16. It should be noted that the shape in the top view of the impoverishment suppression layer 8 is not limited to the square or the rectangle, but can be a polygon or have each corner with a curvature.

[0075] Furthermore, it is desirable that the trench bottom protection layer 7 be connected to the source electrode 11 and the potential fixed (grounded). A configuration of a connection section (potential fixing area) between the trench bottom protection layer 7 and the source electrode 11 is described with reference to the Fig. 17 and Fig. 18 described.

[0076] Fig. Figure 17 is a top view showing the configuration of the potential fixing area and Fig. 18 is a section view showing a section configuration along line BB in Fig. 17 shows. Fig. Figure 17 illustrates a configuration in which the impoverishment suppression layers 8 are arranged in the island shape in a planar pattern, in which the trenches 6 are formed in strip form and the shape in plan view is configured such that from a multitude of body areas 5 defined in the strip form by the trenches 6, one body area 5 is divided by a trench 60 in the middle and this is a potential fixing area 17.

[0077] That means, in potential fixation area 17, as in Fig. Figure 18 shows the trench 60, with a width greater than that of the trench 6, configured to extend between the cells, and the trench bottom protective layer 7, with a width approximately equal to the width of the trench 60, configured to touch the bottom surface of the trench 60. The side surface of the trench 60 is covered by the gate insulating layer 9 and by the gate electrode 10 via the gate insulating layer 9.

[0078] The inner surface of the trench 60 is covered with the intermediate insulating layer 16, including the gate electrode 10. A contact hole CH1 is formed at the bottom of the trench 60, penetrating the intermediate insulating layer 16 and reaching the trench bottom protective layer 7. The source electrode 11 is configured to embed the interior of the trench 60 with its inner surface covered by the intermediate insulating layer 16 and is electrically connected to the trench bottom protective layer 7 via the contact hole CH1, so that the potential of the trench bottom protective layer 7 can be linked to the source potential.

[0079] Next, the steps for forming the potential fixation area 17 will be described with reference to the Fig. described in sections 19 to 21. It should be noted that the Fig. Sectional views 19 to 21 show the steps involved in forming the potential-fixation area as described above, with reference to the Fig. The manufacturing steps described in points 11 to 13 show the same components as those mentioned above, with reference to the Fig. Components described in sections 11 to 13 are identified by the same reference symbols, and repetitions of descriptions are omitted.

[0080] After the formation of trenches 6 and 60 by the with reference to the Fig. 6 to Fig. The 10 steps described are explained in the Fig. In step 19, the insulating layer 20 is formed so that it covers the inner surfaces of the trenches 6 and 60, and the conductive layer 21 is formed on the insulating layer 20 to embed the conductive layer 21 in the trench 6 and to cover the inner surface of the trench 60 with the conductive layer 21. Afterwards, the conductive layer 21 and the insulating layer 20 are patterned and back-etched so that the gate insulating layer 9 and the gate electrode 10 remain only in the trenches 6 and 60.

[0081] Here, the conductive layer 21 formed on the side surface of the trench 60 is much thicker than the conductive layer 21 formed in a flat area, such as the bottom surface of the trench, because a conductive layer deposited horizontally from the side surface and a conductive layer deposited vertically from the bottom overlap. By controlling the etching time, the conductive layer 21 in the flat area is therefore removed, and the gate electrode 10 can be formed on the side surface of the trench 60, leaving the conductive layer 21 in place.

[0082] Next, in the Fig. In step 20, the insulating layer 22 is formed such that it covers the SiC substrate 1 and the gate insulating layer 9 and the gate electrode 10 in the trench 6, which are exposed on the surface of the source area 3 and cover the side surface of the gate electrode 10 together with the inner surface of the trench 60. A resist mask RM2 is formed using photolithography, in which an opening is formed above the source area 3 and the body contact area 4, and in the central area on the bottom surface of the trench 60.

[0083] The insulating layer 22 is then provided with a pattern by the resist mask RM2 as an etching mask through the etching process to form the intermediate insulating layer 16 with a contact hole CH that reaches the source area 3 and the body contact area 4 and with a contact hole CH1 that reaches the trench bottom protection layer 7 in the central area on the bottom surface of the trench 60, as shown in Fig. 21 shown.

[0084] After that, the in Fig. The potential-fixing region 17 shown in Figure 18 is obtained by forming the source electrode 11, which covers the intermediate insulating layer 16 and embeds the inner surfaces of the contact holes CH and CH1, and the potential of the trench bottom protective layer 7 is bound to the source potential, so that the field intensity of the gate insulating layer 9 at the bottom of the trench can be kept low. Although in Fig. 17 where only one potential fixation area 17 is shown, the potentials of the trench floor protection layers 7 on the bottoms of the two trenches 6 are determined by a potential fixation area when the trenches 6 are formed in a strip shape, so that a potential fixation area is formed for every two remaining trenches 6.

[0085] During the formation of the source electrode 11, as described above, a nickel silicide layer is first formed on the bottom surface of the contact hole CH as an ohmic electrode. This also applies to the contact hole CH1. The source electrode 11 is electrically connected to the trench bottom protective layer 7 via a silicide layer as an ohmic electrode, and the source electrode 11 is essentially in ohmic contact with the trench bottom protective layer 7 in order to reduce the contact resistance. First modification

[0086] Next, a configuration of a SiC MOSFET 100A according to a first modification of the first embodiment with reference to Fig. 22 described. In Fig. 22 will be the same components as those of the one with reference to Fig. The SiC-MOSFET 100 described in section 1 is designated with the same reference numerals, omitting any repetition of the description.

[0087] As in Fig. As shown in Figure 22, the SiC MOSFET 100A has a contamination area 15 which is located in the drift layer 2 below the body area 5 such that it is in contact with the bottom surface of the body area 5. The contamination area 15 contains n-type impurities at a high concentration in the range of 5 to 100 times that of the drift layer 2, in particular n-type impurities with a concentration in the range of 1 × 10 16 up to 1 × 10 18 cm -3 The thickness of the contamination zone 15 is specified in the range of 0.1 to 2 µm.

[0088] The JFET resistance is formed between the body area 5 and the trench bottom protection layer 7, but the formation of this contamination area 15 suppresses the extension of the depletion layer from the body area 5 to the drift layer 2 and widens the current path, allowing a reduction in the JFET resistance. Second modification

[0089] Fig. Figure 23 is a sectional view showing a configuration of a SiC MOSFET 100B according to a second modification of the first embodiment. Fig. 23 will use the same components as those of the one with reference to Fig. The SiC-MOSFET 100 described in section 1 is designated with the same reference numerals, omitting any repetitions of the description.

[0090] As in Fig. As shown in Figure 23, the SiC MOSFET 100B has a contamination area 151 formed in the drift layer 2 beneath the body area 5 to make contact with the bottom surface of the body area 5. The contamination area 151 does not cover the entire bottom surface of the body area 5 and is configured such that it does not cover the central area of ​​the bottom surface of the body area 5. The contamination concentration and thickness are identical to those of the contamination area 15 of the SiC MOSFET 100A.

[0091] The reason for not including the contamination area 151 in the central area of ​​the bottom surface of the body region 5 is that the central area does not become a current path, so that even if the depletion layer expands, the current path does not narrow easily, so that the resistance hardly increases, and furthermore, the breakdown voltage can be increased by the depletion layer, which extends from the p-type body region 5 to the n-type drift layer 2, in order to suppress the electric field applied to the gate insulating layer 9. Third modification

[0092] Fig. Figure 24 is a sectional view showing a configuration of a SiC MOSFET 100C according to a third modification of the first embodiment. Fig. 24 will have the same components as those of the one with reference to Fig. The SiC-MOSFET 100 described in section 1 is designated with the same reference numerals, omitting any repetitions of the description.

[0093] As in Fig. As shown in Figure 24, in the SiC-MOSFET 100C, a depletion suppression layer 8A formed in the drift layer 2 between the adjacent trench soil protection layers 7 is not uniform, but uneven with respect to the impurity concentration, i.e. with a concentration distribution.

[0094] That is, the in Fig. The depletion suppression layer 8A shown in Figure 24 has the highest impurity concentration in the horizontal direction in a central region 81, and the impurity concentration is lower on the left and right sides of the central region 81 than in the central region 81. To obtain such an impurity concentration distribution, ions are implanted obliquely or ions with a wider dispersion angle are implanted so that an implantation layer with a laterally (horizontally) uneven concentration can be formed.

[0095] By constructing the depletion suppression layer 8A with a contaminant concentration distribution, as described, where the highest contaminant concentration is in the central region 81, the extent of the depletion layer, which extends horizontally from the trench bottom protection layer 7, can be reliably suppressed in the area where the depletion layer extends furthest, thus improving the trade-off between the breakdown stress and the EIN resistance. It should be noted that the depletion suppression layer 8A can have a multi-layered structure with varying concentrations in the horizontal direction. Fourth modification

[0096] Fig. Figure 25 is a sectional view showing a configuration of a SiC MOSFET 100D according to a fourth modification of the first embodiment. Fig. 25 will have the same components as those of the one with reference to Fig. The SiC-MOSFET 100 described in section 1 is designated with the same reference numerals, omitting any repetitions of the description.

[0097] As in Fig. As shown in Figure 25, in the SiC-MOSFET 100D, a depletion suppression layer 8B formed in the drift layer 2 between the adjacent trench soil protection layers 7 is not uniform, but uneven with respect to the impurity concentration, i.e. with a concentration distribution.

[0098] That is, the in Fig. The depletion suppression layer 8B shown in Figure 25 has the highest impurity concentration in a central region 82 in the vertical direction (a direction perpendicular to the main surface of the substrate), and the impurity concentration is lower in the top and bottom of the central region 82 than in the central region 82. To obtain such an impurity concentration distribution, the acceleration energy at the time of ion implantation is set so that it lies on an implantation peak in the central region 82, so that an implantation layer with a longitudinally (vertically) non-uniform concentration can be formed.

[0099] By constructing the depletion suppression layer 8B as a contamination layer with a non-uniform contamination concentration distribution, as described, the extent of the depletion layer, which extends horizontally from the trench bottom protection layer 7, can be reliably suppressed in an area where the depletion layer extends furthest, and the contamination concentration is lower in an area closer to the bottom of the trench 6, thus enabling a reduction in the field strength exerted on the trench 6.

[0100] The depletion suppression layer 8B can have a multilayer structure with varying concentrations in the vertical direction. Within depletion suppression layer 8B, one of the impurity concentrations at the top and bottom of the central region 82 can be lower than the other. If the impurity concentration is sufficiently high, at least in the central region 82, it is possible to suppress the extent of the depletion layer within depletion suppression layer 8. Design 2

[0101] Fig. Figure 26 is a sectional view that schematically represents a partial configuration of a SiC MOSFET 200 formed on the SiC substrate. Fig. 26 will be the same components as those of the one with reference to Fig. The SiC-MOSFET 100 described in section 1 is designated with the same reference numerals, omitting any repetitions of the description.

[0102] As in Fig. As shown in Figure 26, the depletion suppression layer 8 formed in the drift layer 2 between the adjacent trench soil protection layers 7 has an intermediate point that is horizontally equidistant from the adjacent trench soil protection layer 7. The depletion suppression layer 8 is formed at such a position that the distance d1 to a side wall 61 of one of the trenches 6 differs from the distance d2 to a side wall 62 of the other of the trenches 6. That is, the depletion suppression layer 8 is formed such that it is offset in the direction of one of the trenches 6.

[0103] It should be noted that the horizontal position of the depletion suppression layer 8 between the adjacent trench soil protection layers 7 is determined by the position of the opening of the resist mask RM1 in the area referred to in Fig. The step described in point 8 is determined and can therefore be easily moved by changing the position of the opening of the resist mask RM1.

[0104] In this way, by adjusting the distance between the side wall of the trench 6 and the depletion suppression layer 8 in a specific direction, which differs from the distance in the other direction, it is possible, in addition to the effect of the first embodiment, to reduce current fluctuations during the ON state, depending on the difference in the crystal plane due to the influence of an offset angle of the substrate. This is done with reference to Fig. 27 describes the relationship between the side wall of trench 6 and the crystal plane. As in Fig. Figure 27 shows the main area of ​​the SiC substrate 1, if the SiC substrate 1 is a 4H-SiC substrate, with a <0001> The c-axis is inclined from a normal direction N to a <11-20> direction by an angle θ. This angle θ is called the offset angle, and due to the influence of the offset angle, the side wall 61 of the trench 6 and the side wall 62 have different plane orientations. More precisely, the side wall 61 of the trench 6 is a surface with a (11-20) plane inclined by the offset angle in a (0001) plane direction, and the side wall 62 of the trench 6 is a surface with the (11-20) plane inclined by the offset angle in a (000-1) plane direction.

[0105] In such a configuration, the electron mobility of the MOSFET channel formed on each sidewall surface is different, and the current density during the ON state differs between sidewall 61 and sidewall 62. If we assume here that sidewall 61 has a crystal plane with high electron mobility (a crystal plane with a first electron mobility), then sidewall 62 has a crystal plane with low electron mobility (a crystal plane with a second electron mobility).

[0106] By increasing the distance d1 compared to the distance d2, the width of the depletion layer between the vicinity of the side wall 61 and the depletion suppression layer 8 becomes greater than the width of the depletion layer between the vicinity of the side wall 62 and the depletion suppression layer 8, and the flow path becomes narrower. That is, the width of the flow path changes due to the expansion of the depletion layer, corresponding to the distance between the side wall of the trench 6 and the depletion suppression layer 8.

[0107] By changing the distance to the depletion suppression layer 8 according to the plane orientation of the side wall of the trench 6, the current density can be adjusted for each plane orientation of the side wall of the trench 6 to reduce the influence of current fluctuations. This reduces the current fluctuations in the device, which improves the reliability of the device.

[0108] Although it is assumed here that the side wall 61 is the surface inclined about the offset angle in the (0001) plane direction and the distance d1 between the side wall 61 and the depletion suppression layer 8 is greater than the distance d2, the present invention is not limited to this and the distance d2 between the side wall 62 inclined in the (000-1) plane direction and the depletion suppression layer 8 can be made greater than the distance d1.

[0109] Fig. Figure 28 shows a cell with a planar pattern in which the trenches 6 are strip-shaped, and a cross-section along line CC according to Fig. 28 in the direction of the arrow corresponds to the section view according to Fig. 26. As in Fig. As shown in Figure 28, the position of the depletion suppression layer 8 is specified such that, of the two parallel trenches with the depletion suppression layer 8 in between, the distance between the side wall 61 of one trench 6 and the depletion suppression layer 8 is greater than the distance between the side wall 62 of the other trench 6 and the depletion suppression layer 8.

[0110] Fig. Figure 29 shows a cell with a planar pattern in which the trenches 6 have a grid shape. As in Fig. As shown in Figure 29, in the grid configuration of the trenches 6, the shape in the top view of the cell surrounded by the trenches 6 is a quadrilateral, and the shape in the top view of the depletion suppression layer 8 is also a quadrilateral similar to the cell. In this case, the position of the depletion suppression layer 8 is predetermined such that, of the two trenches provided with the intervening depletion suppression layer 8, the distance between the side wall 61 of one trench 6 and the depletion suppression layer 8 is greater than the distance between the side wall 62 of the other trench 6 and the depletion suppression layer 8.

[0111] In the case of the planar pattern, in which the trenches 6 are formed in lattice form, the cell is surrounded by four trenches 6, but the plane orientation of the crystal plane differs for each side wall of the trench 6 due to the difference in the plane orientation of the substrate crystal, and the electron mobility differs for each side wall surface, so the current varies.

[0112] To reduce power fluctuations, as described in Fig. As shown in Figure 30, by arranging the depletion suppression layer 8 at a location near a corner of the cell, the respective distances between the side wall of the trench 6 and the depletion suppression layer 8 can be varied in two or more different directions. In the configuration according to Fig. 30 The distances between the four side walls of the impoverishment suppression layer 8 and the side walls of the four opposite trenches 6 are different.

[0113] However, even in this case, the position of the depletion suppression layer 8 must be specified such that it has an intermediate point that is horizontally equidistant from the adjacent trench soil protection layer 7. It should be noted that the shape of the depletion suppression layer 8 in plan view is not limited to a square or a rectangle, but can be a polygon or have each corner with a curvature. embodiment 3

[0114] Fig. Figure 31 is a sectional view that schematically represents a partial configuration of a SiC MOSFET 300 formed on the SiC substrate. Fig. 31 will use the same components as those of the one with reference to Fig. The SiC-MOSFET 100 described in section 1 is designated with the same reference numerals, omitting any repetitions of the description.

[0115] As in Fig. As shown in Figure 31, the SiC-MOSFET 300 is configured such that the depletion suppression layer 8 formed in the drift layer 2 between the adjacent trench soil protection layers 7 has a breakdown stress resistance layer 19 with p-impregnations in the horizontal central area.

[0116] With such a configuration, the breakdown voltage retention layer 19 can be caused to also share the electric field acting on the trench bottom protection layer 7 during the OFF state, and it is possible to reduce the field intensity both at the bottom of the body area 5 and at the bottom of the trench 6 and to maintain the breakdown voltage.

[0117] This means that if the breakdown voltage resistance layer 19 is not provided, the electric field is applied to the trench bottom protection layer 7 during the OFF state. If the area of ​​the trench bottom protection layer 7 is large, the concentration of the electric field hardly occurs, but because the area of ​​the trench bottom protection layer 7 is defined by the bottom area of ​​the trench 6, the trench bottom protection layer 7 is narrow and the concentration of the electric field occurs easily.

[0118] By installing the breakdown voltage resistance layer 19 between the trenches 6, the electric field, which only acts on the trench bottom protection layer 7, also acts on the breakdown voltage resistance layer 19, thus reducing the concentration of the electric field at the bottom of the trench. The installation of the breakdown voltage resistance layer 19 can also reduce the concentration of the electric field on the underside of the body section 5.

[0119] The thickness of the breakdown stress-resistance layer 19 can be less or greater than that of the depletion suppression layer 8. If the thickness of the breakdown stress-resistance layer 19 is less than that of the depletion suppression layer 8, it can be configured so that the depletion suppression layer 8 covers either the top or bottom surface of the breakdown stress-resistance layer 19, thus eliminating any level difference between the two layers. Alternatively, it can be configured so that the breakdown stress-resistance layer 19 is surrounded by the depletion suppression layer 8.

[0120] If the thickness of the breakdown stress resistance layer 19 is equal to or greater than the thickness of the depletion suppression layer 8, the thickness of the breakdown stress resistance layer 19 can be a thickness associated with the upper body region 5.

[0121] The width of the breakthrough stress resistance layer 19 is preferably equal to or less than the width of the trench bottom protection layer 7.

[0122] After the formation of the depletion suppression layer 8 using the resist mask RM1 in the reference to Fig. In step 8 described, the breakdown stress resistance layer 19 can be formed by using a resist mask with an opening for the formation of the breakdown stress resistance layer 19 for ion implantation of p-type impurities into the central region of the depletion suppression layer 8, the impurity concentration of which is in the range of 1 × 10 16 up to 1 × 10 19 cm -3 lies. modification

[0123] Next, a configuration of a SiC MOSFET 300A according to a modification of the third embodiment with reference to Fig. 32 described. Fig. Figure 32 is a view showing a planar pattern of the cell of the SiC-MOSFET 300A and illustrating such a configuration that in the planar pattern in which the trenches 6 are formed in strip form, the quadrilateral depletion suppression layers 8 are formed in strip form along the extension direction of the trenches 6.

[0124] The shape in plan view is configured such that, from a multitude of body areas 5 defined in the strip shape by the trenches 6, one body area 5 is divided by the trench 60 in the middle, which corresponds to a similar configuration to that of the one with reference to Fig. 18 described potential fixation area 17.

[0125] As in Fig. As shown in Figure 32, the breakdown stress resistance layers 19 are formed in strip form along the depletion suppression layer 8 in the central area in the width direction of the strip-shaped depletion suppression layer 8, and the depletion suppression layers 8 and the breakdown stress resistance layer 19 extend without being subdivided into other areas than an area in which the potential fixing area 17 is formed.

[0126] In the area where the body area 5 is divided by the trench 60 in the middle, it is configured such that the depletion suppression layer 8 is divided in front of the trench 60, while the breakthrough stress resistance layer 19 extends to the lower part of the side surface of the trench 60 and is connected to the side surface of the trench bottom protection layer 7 on the bottom of the trench 60. In other words, the configuration is such that the trench bottom protection layer 7, formed on the bottom of the trench 60 and extending between the cells, is connected to the breakthrough stress resistance layer 19.

[0127] With such a configuration, the breakdown voltage retention layer 19 is electrically connected to the source electrode 11 via the trench bottom protection layer 7, and the breakdown voltage retention layer 19 has the same potential as the trench bottom protection layer 7, so that when the MOSFET is switched off, the electric field near the bottom of the trench can be more uniform and the concentration of the electric field for maintaining the breakdown voltage can be relaxed.

[0128] Furthermore, the breakdown voltage resistance layer 19 is electrically connected to the source electrode 11 via the trench bottom protection layer 7 in order to increase the response speed of the charges, so that a reduction in switching losses can be expected by improving the switching speed.

[0129] Fig. 33 is a section view showing a cross-sectional configuration along line DD in Fig. 32 shows, and Fig. 34 is a section view showing a cross-sectional configuration along line EE in Fig. 32 shows. As in Fig. As shown in Figure 33, the configuration is such that the breakdown stress resistance layer 19 is formed in strip form in the horizontal central area of ​​each of the depletion suppression layers 8.

[0130] The thickness of the breakthrough stress resistance layer 19 can be smaller or thicker than that of the depletion suppression layer 8, but is preferably about the same as or smaller than the thickness of the trench bottom protection layer 7.

[0131] It should be noted that the expression "A and B are electrically connected" used in the above description means that a current flows bidirectionally between component A and component B. Furthermore, the equal thickness and depth do not refer to a case where they are perfectly identical, but also include a case where they differ by a range of -20% to +20%. Other application examples

[0132] In the first to third embodiments described above, examples are shown in which the present invention is applied to the MOSFET, wherein the drift layer 2 and the SiC substrate 1 (which has a buffer layer) have the same conductivity type, but the present invention also applies to an IGBT with the drift layer 2 and the SiC substrate 1 having different conductivity types.

[0133] For example, with regard to the in Fig. The configuration shown in Figure 1 is a configuration in which the SiC substrate 1 is a p-type with respect to the n-type drift layer 2, a configuration of an IGBT. In this case, the source region 3 and the source electrode 11 of the MOSFET correspond to an emitter region and an emitter electrode of the IGBT, respectively, and the drain electrode 12 of the MOSFET corresponds to a collector electrode.

[0134] The present invention also applies to a freestanding substrate consisting only of the drift layer 2 (epitutional growth layer) by removing the SiC substrate 1 mechanically, chemically, or by other methods. It should be noted that the freestanding substrate consisting only of the epitaxial growth layer can also be referred to as a "SiC substrate." A MOSFET is obtained by forming a source region, a source electrode, and the like on one major surface of the freestanding substrate and a drain electrode on the other major surface, while an IGBT is obtained by forming an emitter region, an emitter electrode, and the like on one major surface of the freestanding substrate and a collector region and a collector electrode on the other major surface.The first to third embodiments show examples in which the present invention is applied to a silicon carbide semiconductor, but the present invention is also applicable to other wide-bandgap semiconductors such as gallium nitride (GaN), diamond (C), and the like. Even when a silicon carbide-containing semiconductor is used as the semiconductor material, the electric field at the bottom of the trench can be relaxed, and the reliability of the gate insulating layer and the breakdown voltage can be improved. Design 4

[0135] In the present embodiment, the semiconductor devices according to the first to third embodiments described above are used in a power converter device. Although the present invention is not limited to a specific power converter device, a case in which the present invention is used in a three-phase inverter will be referred to below as the fourth embodiment.

[0136] Fig. Figure 35 is a block diagram showing a configuration of a power converter system in which the power converter device is used according to the present embodiment.

[0137] The in Fig. Figure 35 shows a power converter system comprising a power supply 500, a power converter device 600, and a load 700. The power supply 500 is a DC power supply and provides the power converter device 600 with direct current. The power supply 500 can be of various types and may, for example, consist of a DC system, a solar battery, a storage battery, a rectifier circuit, or an AC / DC converter connected to an AC system. Furthermore, the power supply 500 can consist of a DC / DC converter that converts the DC voltage supplied by the DC system into a predetermined electrical power.

[0138] The power converter device 600 is a three-phase inverter connected between the power supply 500 and the load 700. It converts the DC voltage supplied by the power supply 500 into AC voltage and delivers the AC voltage to the load 700. As shown in Fig. As shown in Figure 35, the power converter device 600 comprises: a main converter circuit 601 for converting direct current into alternating current and for outputting the alternating current power, a driver circuit 602 for outputting a driver signal for controlling each switching element of the main converter circuit 601, and a control circuit 603 for outputting a control signal to the driver circuit 602 for controlling the driver circuit 602.

[0139] The Last 700 is a three-phase motor driven by the 600 power converter using alternating current. It should be noted that the Last 700 is not limited to a specific application but can be an electric motor installed in various electrical devices, such as hybrid vehicles, electric vehicles, rail vehicles, elevators, or as an electric motor for air conditioning systems.

[0140] The following describes the details of a power converter device 600. The main converter circuit 601 comprises a switching element and a freewheeling diode (not shown). By switching the switching element, the main converter circuit 601 converts the direct current supplied by the power supply 500 into alternating current and delivers the alternating current to the load 700. Although there are various specific circuit configurations of the main converter circuit 601, according to the present embodiment, the main converter circuit 601 is a two-stage, three-phase full-bridge circuit and can have six switching elements and six freewheeling diodes connected antiparallel to the respective switching elements.

[0141] For each switching element of the main converter circuit 601, the semiconductor device is used according to one of the first to third embodiments described above. The six switching elements are connected in series to form the upper and lower branches, and each upper and lower branch forms one phase (U-phase, V-phase, W-phase) of the full bridge circuit. The output terminals of the upper and lower branches, namely three output terminals of the main converter circuit 601, are connected to the load 700.

[0142] The driver circuit 602 generates a driver signal to drive the switching element of the main converter circuit 601 and supplies the driver signal to a control electrode of the switching element of the main converter circuit 601. In particular, according to a control signal from a control circuit 603 described later, a driver signal is fed to the control electrode of each switching element to bring the switching element into the ON state and a driver signal is fed to bring the switching element into the OFF state.

[0143] When the switching element is held in the ON state, the driver signal is a voltage signal (turn-on signal) equal to or higher than a threshold voltage of the switching element, and when the switching element is held in the OFF state, the drive signal is a voltage signal (turn-off signal) equal to or lower than the threshold voltage of the switching element.

[0144] The control circuit 603 controls the switching element of the main converter circuit 601 so that the desired power is supplied to the load 700. In particular, the time (on-time) during which each switching element of the main converter circuit 601 should be in the ON state is calculated from the electrical energy to be supplied to the load 700. For example, it is possible to control the main converter circuit 601 via PWM control, which modulates the on-time of the switching element according to a voltage to be output.

[0145] A control command (control signal) is then issued to the driver circuit 602 such that an ON signal is issued to the switching element to enter the ON state at the appropriate time, and an OFF signal is issued to the switching element to enter the OFF state at the appropriate time. Based on this control signal, the driver circuit 602 outputs an ON signal or an OFF signal as a driver signal to the control electrode of each switching element.

[0146] In the power converter device according to the present embodiment, the semiconductor device according to one of the first to third embodiments is used as a switching element of the main converter circuit 601, so that it is possible to improve the trade-off between reducing the concentration of the electric field at the bottom of the trench and reducing the ON resistance. Furthermore, the breakdown voltage can be maintained without increasing the field strength at the bottom of the third semiconductor region, which is a body region.

[0147] The present embodiment describes an example in which the present invention is applied to a dual-level three-phase inverter, but the present invention is not limited thereto and can also be applied to various other power converter devices. Although the power converter device in the present embodiment is a dual-level power converter device, it can also be a three-level or a multi-level power converter device.

[0148] If the power supply is to be provided to a single-phase load, the present invention can also be applied to a single-phase inverter. If a DC load or the like is to be powered, the present invention can also be used for a DC / DC converter or an AC / DC converter.

[0149] Furthermore, the power converter device to which the present invention has been applied is not limited to the case where the load described above is an electric motor, but can, for example, be used as a power supply for a spark erosion machine, a laser processing machine, an induction heating cooking appliance or a contactless power system, and can also be used as a power conditioner for a photovoltaic system, an energy storage system or the like.

Claims

[1] Semiconductor device comprising: - a semiconductor substrate (1); - a semiconductor layer (2) of a first conductivity type arranged on a first main surface of the semiconductor substrate; - a first semiconductor region (3) of the first conductivity type, which is selectively formed in an upper layer region of the semiconductor layer; - a second semiconductor region (4) of a second conductivity type, which is formed in the upper layer region of the semiconductor layer by contacting the first semiconductor region; - a third semiconductor region (5) of the second conductivity type, which is in contact with a base surface of the first and second semiconductor regions; - Trenches (6) passing through the first and third semiconductor regions in the thickness direction and reaching an inner side of the semiconductor layer; - a gate insulating layer (9) covering an inner surface of each of the trenches; - a gate electrode (10) embedded in each of the trenches, which is covered with the gate insulating layer; - a trench soil protection layer (7) of the second conductivity type, designed to touch each soil of the respective trench; - a depletion suppression layer (8, 81) of the first conductivity type, placed between adjacent trench soil protection layers; - an intermediate insulating layer (16) covering the uppermost areas of the trenches and the first semiconductor region around the trenches and having a contact hole (CH) over the first and second semiconductor region; - a first main electrode (11) covering the intermediate insulating layer and embedded in the contact hole; and - a second main electrode (12) arranged on a second main surface of the semiconductor substrate, - wherein the depletion suppression layer (8, 81) has an intermediate point which is horizontally equidistant to the adjacent trench soil protection layers (7), - wherein the depletion suppression layer (8, 81) is so large that it does not touch any of the third semiconductor regions, the trenches and the trench bottom protection layers (7), - wherein the depletion suppression layer (8, 81) is designed to be at the same depth and thickness as the trench bottom protection layer (7), and - wherein the impurity concentration of the depletion suppression layer (8, 81) is specified as higher than the impurity concentration of the semiconductor layer. [2] Semiconductor device comprising the following: - a semiconductor substrate (1); - a semiconductor layer (2) of a first conductivity type arranged on a first main surface of the semiconductor substrate; - a first semiconductor region (3) of the first conductivity type, which is selectively formed in an upper layer region of the semiconductor layer; - a second semiconductor region (4) of a second conductivity type, which is formed in the upper layer region of the semiconductor layer by contacting the first semiconductor region; - a third semiconductor region (5) of the second conductivity type, which is in contact with a base surface of the first and second semiconductor regions; - a contamination area (15, 151) of the first conductivity type, which is configured to be in contact with a bottom surface of the third semiconductor area; - Trenches (6) passing through the first and third semiconductor regions in the thickness direction and reaching an inner side of the semiconductor layer; - a gate insulating layer (9) covering an inner surface of each of the trenches; - a gate electrode (10) embedded in each of the grooves covered with the gate insulating layer; - a trench soil protection layer (7) of the second conductivity type, designed to touch soil of the respective trench; - a depletion suppression layer (8, 81) of the first conductivity type, which is placed between adjacent trench soil protection layers (7); - an intermediate insulating layer (16) covering the uppermost areas of the trenches and the first semiconductor region around the trenches and having a contact hole (CH) over the first and second semiconductor region; - a first main electrode (11) covering the intermediate insulating layer and embedded in the contact hole; and - a second main electrode (12) arranged on a second main surface of the semiconductor substrate, - wherein the depletion suppression layer (8, 81) has an intermediate point which is horizontally equidistant to the adjacent trench bottom protection layers, - wherein the depletion suppression layer (8, 81) is large enough that it does not touch any of the third semiconductor regions, the trenches and the trench bottom protective layers, wherein the impurity concentration of the depletion suppression layer (8, 81) is specified as higher than the impurity concentration of the semiconductor layer, and wherein the contamination area is formed at a location outside the depletion suppression layer (8, 81). [3] Semiconductor device according to claim 2, wherein the contamination area is formed in a region, excluding a horizontal central region of the bottom surface of the third semiconductor region between the trench bottom protective layers (7). [4] Semiconductor device according to one of claims 1 to 3, wherein the trench bottom protective layer (7) is electrically connected to the first main electrode (11). [5] Semiconductor device comprising the following: - a semiconductor substrate (1); - a semiconductor layer (2) of a first conductivity type arranged on a first main surface of the semiconductor substrate; - a first semiconductor region (3) of the first conductivity type, which is selectively formed in an upper layer region of the semiconductor layer; - a second semiconductor region (4) of a second conductivity type, which is formed in the upper layer region of the semiconductor layer by contacting the first semiconductor region; - a third semiconductor region (5) of the second conductivity type, which is in contact with a base surface of the first and second semiconductor regions; - Trenches (6) passing through the first and third semiconductor regions in the thickness direction and reaching an inner side of the semiconductor layer; - a gate insulating layer (9) covering an inner surface of each of the trenches; - a gate electrode (10) embedded in each of the grooves covered with the gate insulating layer (9); - a trench soil protection layer (7) of the second conductivity type, designed to be in contact with soil from the respective trench; - a depletion suppression layer (8, 81) of the first conductivity type, formed between adjacent trench soil protection layers (7); - an intermediate insulating layer (16) covering the uppermost areas of the trenches and the first semiconductor region around the trenches and having a contact hole (CH) over the first and second semiconductor region; - a first main electrode (11) covering the intermediate insulating layer (16) and embedded in the contact hole; and - a second main electrode (12) arranged on a second main surface of the semiconductor substrate, - wherein the depletion suppression layer (8, 81) has an intermediate point which is horizontally equidistant to the adjacent trench soil protection layers (7), - wherein the depletion suppression layer (8, 81) is so large that it does not touch any of the third semiconductor regions, the trenches and the trench bottom protection layers (7), - wherein the horizontal position of the depletion suppression layer (8, 81) is specified such that the horizontal distance to a side wall of the trench varies according to a plane orientation of a crystal plane of the side wall of the trench, and - wherein the impurity concentration of the depletion suppression layer (8, 81) is specified as higher than the impurity concentration of the semiconductor layer. [6] Semiconductor device according to claim 5, wherein the position of the depletion suppression layer (8, 81) is specified such that a horizontal distance to a first side wall (61) consisting of a crystal plane with a first electron mobility is greater than a horizontal distance to a second side wall (62) consisting of a crystal plane with a second electron mobility that is lower than the first electron mobility. [7] Semiconductor device according to any one of claims 1 to 6, wherein the depletion suppression layer (81) comprises a breakdown voltage withstand layer (19) of the second conductivity type. [8] Semiconductor device according to claim 7, wherein the breakdown voltage resistance layer (19) is connected to the trench bottom protection layer. [9] Semiconductor device according to one of claims 7 or 8, wherein the breakdown voltage suppression layer (19) is formed in the horizontal central region of the depletion suppression layer. [10] Semiconductor device according to one of claims 1 to 9, wherein the first main electrode (11) is designed such that it comes into ohmic contact with the first and second semiconductor regions via the contact hole. [11] Power converter device comprising the following: - a main converter circuit comprising a semiconductor device according to one of claims 1 to 10 and converting the supplied electrical energy into the output converted electrical energy; - a driver circuit that outputs a driver signal to the semiconductor device to drive the semiconductor device; and - a control circuit that outputs a control signal to the driver circuit for controlling the driver circuit.

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