Semiconductor devices and methods for their manufacture

Abstract

Semiconductor device (1) comprising: a semiconductor layer (11) of a first conductivity type having a front (2), a back (3) opposite the front (2), and an end face (7); a circuit element formed on a front section of the semiconductor layer (11); a first electrode (6) connected to the semiconductor layer (11) on the back (3) of the semiconductor layer (11); a relaxation region (14) for an electric field reaching the back (3) from the front (2) of the semiconductor layer (11) in a circumferential region (12) that includes an active region (13) in which the circuit element is formed, wherein the relaxation region (14) for the electric field is either a high-resistance region with a higher resistance than the semiconductor layer (11) or an impurity region of a second conductivity type;and a surface termination structure (33) formed on a more inner side than the relaxation region (14) for the electric field in the circumferential region (12) of the semiconductor layer (11), wherein the first electrode (6) is in contact with the relaxation region (14) for the electric field and forms a Schottky contact with a part of the semiconductor layer (11), and wherein a MIS transistor structure (22), which serves as a circuit element, is formed on the front side section of the semiconductor layer (11).

Description

Technical FieldThe present invention relates to semiconductor devices and methods of manufacturing the same, and more particularly to a reverse blocking semiconductor device in which a Schottky contact is formed on a back surface of a semiconductor layer.BackgroundA bidirectional switch using a MOSFET or an IGBT is already known. The bidirectional switch is used, for example, in a matrix converter circuit or in a neutral point terminal.For example, Patent Literature 1 discloses a reverse blocking IGBT as a device used as a bidirectional switch, and the reverse blocking IGBT includes a drift layer made of an n-type semiconductor substrate, a p-type base region formed on a surface side of the drift layer, an n-type emitter region of a surface layer of the p-type base region, a gate oxide film on a surface of the p-type base region interposed between the n-type emitter region and a surface of the drift layer, a gate electrode on the gate oxide film, a terminal region with an FLR formed on the outer periphery of an active region of the drift layer, a p-type collector layer formed on the other surface side of the drift layer, and an isolation region, which is disposed on the outer periphery of the FLR and which adjoins the p-type collector layer while passing through the drift layer from the one surface side of the drift layer.Moreover, for example, Patent Literature 2 discloses a reverse blocking MOSFET unlike a reverse blocking device including IGBTs, and the reverse blocking MOSFET is composed of an n -- type drift layer of SiC, a p +- type substrate formed on a main surface side of the n -- type drift layer, a plurality of back side trenches that pass through the p +- type substrate and reach the n -- type drift layer, and a titanium electrode that makes Schottky contact with the n -- type drift layer in a lower portion of each of the back side trenches.Citation ListPatent LiteraturePatent Literature 1: JP 2016-004 930 APatent Literature 2: JP 2012-174831 APatent Literature 3: U.S. Pat. No. 9,018,633 B2Patent Literature 4: US 2014 / 0 361 312 A1Patent Literature 5: US 2012 / 0 211 768 A1Patent Literature 6: US 2014 / 0 001 487 A1Patent Literature 7: US 2011 / 0 121 440 A1Patent Literature 8: JP 2009-123 914 APatent Literature 9: US 2007 / 0 272 979 A1Patent Literature 10: US 2006 / 0 249 797 A1Patent Literature 11: US 2011 / 0 215 435 A1Patent Literature 12: US 2005 / 0 029 568 A1SUMMARY OF THE INVENTIONTechnical ProblemAs described above, various inventions have been proposed as a reverse blocking device. In consideration of these circumstances, the present invention proposes a reverse blocking semiconductor device having a simple configuration capable of increasing a yield in the manufacturing process and ensuring a reverse voltage by using a Schottky contact, and a method of manufacturing the reverse blocking semiconductor device.Solution of the ProblemThis object is achieved by semiconductor devices according to the independent claims and by the corresponding methods for their production. Further embodiments are shown in the dependent claims.Therefore, it is possible to block an electric current flowing through the inside of the semiconductor layer in the thickness direction by a Schottky barrier of a Schottky contact between the semiconductor layer and the first electrode when a reverse voltage is applied to the circuit element (for example, an MIS transistor structure). In addition, a relaxation region for the electric field is formed around the circuit element. Consequently, even if a barrier layer spreads toward the end face (chip end face) of the semiconductor layer upon application of a reverse voltage, it is possible to stop the barrier layer over the electric field relaxation region and prevent the barrier layer from reaching the end face. This makes it possible to relieve the electric field strength in the vicinity of the end face of the semiconductor layer. Therefore, even if a defective region is present at the end surface of the semiconductor layer by dicing (dicing), it is possible to prevent a leakage current from flowing in the defective region by forming electron-hole pairs. Based on this, it is possible that a semiconductor device according to the present invention can ensure excellent blocking voltage, and thus it is possible to use it excellently as a reverse blocking MISFET for bidirectional switches.According to the manufacturing methods, an electric field relaxation region is formed in a stable state in which the semiconductor layer is mounted on the substrate. In other words, it is not necessary to form an electric field relaxation region in a thin wafer state after removing the base substrate, and it is possible to prevent a wafer from breaking into pieces by a handling error, for example. Moreover, it is possible to restrict a step performed after removing the base substrate and thinning the wafer to the step of forming the first electrode, thereby making it possible to reduce the number of handling times for handling the thinned wafer and reduce the possibility of a handling error. Based on this, it is possible to reduce the probability of occurrence of defective articles, thereby improving the yield in the manufacturing process.Moreover, when the circuit element is formed on the front surface portion of the semiconductor layer, it is possible to form an electric field relaxation region by processing from the front surface side of the semiconductor layer in parallel with this production. Thereby, it is possible to reduce limiting factors (temperature, chemical compounds, devices, etc.) that influence each element of the circuit element, as compared with the case where the electric field relaxation region is produced after the circuit element. Based on this, it is possible to improve the efficiency of the manufacturing process.The semiconductor layer may be made of SiC, and the electric field relaxation region may be a high resistance region having a crystal defect concentration of 1×10 14 cm -3 to 1×10 22 cm -3.The semiconductor layer may be SiC, and the electric field relaxation region may be an impurity region of a second conductivity type having an impurity concentration of 1×10 18 cm -3 to 1×10 22 cm -3.The electric field relaxation region may be formed inward away from the end surface of the semiconductor layer so that the electric field relaxation region surrounds the active region.The semiconductor layer may include a first peripheral impurity region of a first conductivity type between the electric field relaxation region and the end surface of the semiconductor layer, wherein the first electrode may be in contact with the peripheral impurity region of the semiconductor layer, and wherein the semiconductor device may further include an auxiliary electrode that is in contact with the peripheral impurity region on the front side of the semiconductor layer and that is electrically connected to the first electrode.According to this configuration, the electric potential of the peripheral impurity region is set to the same electric potential from the front side to the back side of the semiconductor layer. This makes it possible to bring about a state in which an electric field does not easily form in the peripheral impurity region, and thereby makes it possible to further relax the electric field strength in the vicinity of the end surface of the semiconductor layer.The auxiliary electrode may bridge a boundary portion between the electric field relaxation region and the peripheral impurity region, and may be in contact with both the electric field relaxation region and the peripheral impurity region.The electric field relaxation region may reach the end surface of the semiconductor layer.The first electrode may be in contact with the electric field relaxation region at the back side of the semiconductor layer, and the semiconductor device may further include an auxiliary electrode that is in contact with the electric field relaxation region at the front side of the semiconductor layer and that is electrically connected to the first electrode.According to this configuration, the electric potential of the electric field relaxation region can be fixed to the same electric potential from the front side to the back side of the semiconductor layer. This makes it possible to bring about a state in which the electric field does not easily form in the electric field relaxation region, and thereby makes it possible to further relax the electric field strength in the vicinity of the end faces of the semiconductor layer.The peripheral portion of the semiconductor layer may include a flat portion with which the front surface of the semiconductor layer is planar, and the electric field relaxation portion may reach the back surface from the front surface of the semiconductor layer of the flat portion.The semiconductor device may further include a concave portion formed from the front side in the peripheral area of the semiconductor layer, and the electric field relaxation area may be formed along an inner surface of the concave portion, and a lower portion of the electric field relaxation area is exposed at the back side of the semiconductor layer.The semiconductor device may further include a second electric field relaxation region formed on a back surface portion of the semiconductor layer and being either a high resistance region having a higher resistance than the semiconductor layer or an impurity region of a second conductivity type.According to this configuration, it is possible to expand the electric field of the Schottky interface between the semiconductor layer and the first electrode. Consequently, it is possible to reduce a back leakage current even when a metal having a comparatively small work function is used as the first electrode, and thus a small "on" resistance can be ensured by using this metal.The second electric field relaxation region may be exposed on the back side of the semiconductor layer, and the first electrode may be in contact with the second electric field relaxation region on the back side of the semiconductor layer.A plurality of second electric field relaxation regions may be formed in a discrete or matrix-like manner when the semiconductor layer is viewed from the back side.A plurality of second electric field relaxation regions may be arranged in a stripe shape or the second electric field relaxation region may be formed in a lattice pattern when the semiconductor layer is viewed from the back side.The semiconductor device may include a second electrode formed on the semiconductor layer and electrically connected to a source or an emitter of the MIS transistor structure.A semiconductor package may include a semiconductor device including a lead frame on which the semiconductor device is mounted and a sealing resin sealing the semiconductor device and at least a part of the lead frame.A power source conversion device may use the semiconductor device as a bidirectional switching device, and for example, may employ the bidirectional switching device as a switching circuit for a matrix converter circuit from the polyphase input to the polyphase output.Forming the electric field relaxation region may include forming the high resistance region by radiating a first substance including at least protons, helium ions, and / or electron beams from a front surface side of the semiconductor layer after forming the semiconductor layer.Forming the electric field relaxation region may include forming the second conductivity type impurity region by implanting second conductivity type impurity ions from a front side side side of the semiconductor layer after forming the semiconductor layer.Forming the semiconductor layer may include forming the semiconductor layer according to a multistage epitaxial method in which a first conductivity type layer is epitaxially grown a plurality of times repeatedly, and forming the electric field relaxation region may include forming a second conductivity type region by implanting impurity ions of the second conductivity type into a predetermined part of the first conductivity type layers when each of the first conductivity type layers is grown, and forming the second conductivity type impurity region may be performed by sequentially stacking the second conductivity type regions together in conjunction with growth of the first conductivity type layer.Forming the semiconductor layer may include forming the semiconductor layer according to a multistage epitaxial method in which a first conductivity type layer is epitaxially grown a plurality of times repeatedly, and forming the electric field relaxation region may include forming a region of a first substance including at least protons, helium ions, and / or electron beams, irradiated on a predetermined part of the first conductivity type layer when each of the first conductivity type layers is grown, and forming the high resistance region may be performed by sequentially stacking the regions of the first substance together in conjunction with growth of the first conductivity type layer.Forming the electric field relaxation region may include forming a through hole that reaches the substrate from the front side of the semiconductor layer after the semiconductor layer is formed, and forming the second conductivity type impurity region by backfilling the through hole with a second conductivity type semiconductor layer by epitaxial growth.Forming the electric field relaxation region may include forming a concave portion from the front side of the semiconductor layer after forming the semiconductor layer, and forming the second conductivity type impurity region extending along an inner surface of the concave portion and having the lower portion reaching the substrate by implanting second conductivity type impurity ions into the inner surface of the concave portion.Forming the electric field relaxation region may include forming a concave portion from the front side of the semiconductor layer after forming the semiconductor layer, and forming the high resistance region extending along an inner surface of the concave portion and having the lower portion reaching the substrate by radiating a first substance including at least protons, helium ions, and / or electron beams onto the inner surface of the concave portion.Furthermore, filling the concave portion with a conductive material may be part of the manufacturing method.Forming the semiconductor layer may include forming a first semiconductor layer on the substrate and forming a second semiconductor layer on the first semiconductor layer, wherein the manufacturing method of semiconductor device further includes forming a second electric field relaxation region on the first semiconductor layer before forming the second semiconductor layer, wherein the second relaxation region is either a high resistance region having a higher resistance than the semiconductor layer or an impurity region of the second conductivity type.Removing the substrate may include removing portions of the semiconductor layer in addition to the substrate until the second electric field relaxation region is exposed from the back side of the semiconductor layer.The end face may be formed so as to make it possible to front the rear surface side of the semiconductor layer by etching. It is possible to form the electric field relaxation region into the end surface by ion implantation or the like as described above, and therefore it is possible to more easily form the electric field relaxation region with lower energy than in a case where the electric field relaxation region ranging from the front side to the back side of the semiconductor layer is formed by ion implantation or the like.In a semiconductor device, the semiconductor layer may have an upper end face end that is an end edge of the end face on a side of the front side, and a lower end face end that is an end edge of the end face on a side of the back side and that is disposed at a position more inside than the upper end face end in a cross-sectional view, and a phantom linear line segment connecting the upper end face end and the lower end face end to each other is inclined at an angle greater than 90° with respect to the back side of the semiconductor layer.In a semiconductor device, the electric field may be formed along at least a part of the end face in a cross-sectional view having a substantially constant thickness.Forming the groove may include forming the groove by performing etchings from the back side to a center in the thickness direction of the semiconductor layer, wherein the semiconductor device manufacturing method further includes a step of cutting the semiconductor layer after forming the first electrode along a cutting line extending along the groove.Brief Description of the Drawings[FIG. 1] FIG. 1 is a schematic plan view of a semiconductor device according to a preferred embodiment of the present invention.[FIG. 2 ] FIG. 2 is a schematic bottom view of the semiconductor device according to a preferred embodiment of the present invention.[FIG. 3] FIG. 3 is a cross-sectional view obtained when the semiconductor device is cut along the line III-III of FIG. 1.[FIG. 4] FIG. 4 is a view showing a planar pattern of an electric field relaxation region of FIG. 3.[FIG. 5A] FIG. 5A is a view illustrating a part of a manufacturing process of the semiconductor device of FIG. 3.[FIG. 5B ] FIG. 5B shows a step following the step of FIG. 5A.[FIG. 5C ] FIG. 5C shows a step following the step of FIG. 5B.[FIG. 5D ] FIG. 5D shows a step following the step of FIG. 5C.[FIG. 5E ] FIG. 5E shows a step following the step of FIG. 5D.[FIG. 5F ] FIG. 5F shows a step following the step of FIG. 5E.[FIG. 6A ] FIG. 6A is a view illustrating a part of another manufacturing process of the semiconductor device of FIG. 3.[FIG. 6B ] FIG. 6B shows a step following the step of FIG. 6A.[FIG. 6C ] FIG. 6C shows a step following the step of FIG. 6B.[FIG. 6D ] FIG. 6D shows a step following the step of FIG. 6C.[FIG. 7 ] FIG. 7 is a schematic cross-sectional view of a semiconductor device according to another preferred embodiment of the present invention.[FIG. 8] FIG. 8 is a schematic cross-sectional view of a semiconductor device according to another preferred embodiment of the present invention.[FIG. 9A] FIG. 9A is a view illustrating a part of another manufacturing process of the semiconductor device of FIG. 8.[FIG. 9B ] FIG. 9B shows a step following the step of FIG. 9A.[FIG. 10] FIG. 10 is a schematic cross-sectional view of a semiconductor device according to another preferred embodiment of the present invention.[FIG. 11 ] FIG. 11 is a view showing a planar pattern of an electric field relaxation region of FIG. 10.[FIG. 12] FIG. 12 is a schematic cross-sectional view of a semiconductor device according to another preferred embodiment of the present invention.[FIG. 13 ] FIG. 13 is a view showing a planar pattern of both an electric field relaxation region and a second drain electrode of FIG. 12.[FIG. 14] FIG. 14 is a schematic cross-sectional view of a semiconductor device according to another preferred embodiment of the present invention.[FIG. 15] FIG. 15 is a schematic cross-sectional view of a semiconductor device according to another preferred embodiment of the present invention.[FIG. 16A] FIG. 16A is a view illustrating a part of a manufacturing process of the semiconductor device of FIG. 15.[FIG. 16B ] FIG. 16B shows a step following the step of FIG. 16A.[FIG. 16C ] FIG. 16C shows a step following the step of FIG. 16B.[FIG. 16D ] FIG. 16D shows a step following the step of FIG. 16C.[FIG. 16E ] FIG. 16E shows a step following the step of FIG. 16D.[FIG. 17] FIG. 17 is a schematic cross-sectional view of a semiconductor device according to another preferred embodiment of the present invention.[FIG. 18] FIG. 18 is a schematic cross-sectional view of a semiconductor device according to another preferred embodiment of the present invention.[FIG. 19] FIG. 19 is a schematic cross-sectional view of a semiconductor device according to another preferred embodiment of the present invention.[FIG. 20 ] FIG. 20 is a view showing a basic pattern of a second electric field relaxation region of FIG. 19.[FIG. 21] FIG. 21 is a view showing a basic pattern of the second electric field relaxation region of FIG. 19.[FIG. 22] FIG. 22 is a view showing a basic pattern of the second electric field relaxation region of FIG. 19.[FIG. 23A] FIG. 23A is a view illustrating a part of a manufacturing process of the semiconductor device of FIG. 19.[FIG. 23B ] FIG. 23B shows a step following the step of FIG. 23A.[FIG. 23C ] FIG. 23C shows a step following the step of FIG. 23B.[FIG. 23D] FIG. 23D shows a step following the step of FIG. 23C.[FIG. 23E ] FIG. 23E is a step following the step of FIG. 23D.[FIG. 23F] FIG. 23F shows a step following the step of FIG. 23E.[FIG. 23G ] FIG. 23G shows a step following the step of FIG. 23F.[FIG. 23H] FIG. 23H shows a step following the step of FIG. 23G.[FIG. 24] FIG. 24 is a schematic cross-sectional view of a semiconductor device according to another preferred embodiment of the present invention.[FIG. 25] FIG. 25 is a view describing an effect caused by a structure of the semiconductor device of FIG. 24.[FIG. 26A] FIG. 26A is a view describing a variation of the end face shape of the semiconductor layer.[FIG. 26B ] FIG. 26B is a view describing a variation of the end face shape of the semiconductor layer.[FIG. 26C ] FIG. 26C is a view describing a variation of the end face shape of the semiconductor layer.[FIG. 27A] FIG. 27A is a view describing a positional relationship between an electric field relaxation region and a drain electrode in the semiconductor device of FIG. 24.[FIG. 27B ] FIG. 27B is a view describing a positional relationship between an electric field relaxation region and a drain electrode in the semiconductor device of FIG. 24.[FIG. 27C ] FIG. 27C is a view describing a positional relationship between an electric field relaxation region and a drain electrode in the semiconductor device of FIG. 24.[FIG. 27D] FIG. 27D is a view describing a positional relationship between an electric field relaxation region and a drain electrode in the semiconductor device of FIG. 24.[FIG. 27E] FIG. 27E is a view describing a positional relationship between an electric field relaxation region and a drain electrode in the semiconductor device of FIG. 24.[FIG. 28A] FIG. 28A is a view illustrating a part of a manufacturing process of the semiconductor device of FIG. 24.[FIG. 28B ] FIG. 28B shows a step corresponding to the step Figure 28A follows.[FIG. 28C ] FIG. 28C shows a step corresponding to the step Figure 28B follows.[FIG. 28D ] FIG. 28D shows a step corresponding to the step Figure 28C follows.[FIG. 28E ] FIG. 28E shows a step corresponding to the step Figure 28D follows.[FIG. 28F ] FIG. 28F shows a step subsequent to the step Figure 28E follows.[FIG. 28G ] FIG. 28G shows a step corresponding to the step Figure 28F follows.[FIG. 28H ] FIG. 28H shows a step corresponding to the step Figure 28G follows.[FIG. 28I ] FIG. 28I shows a step corresponding to the step Figure 28H follows.[FIG. 28J] FIG. 28J shows a step corresponding to the step Figure 28I follows.[FIG. 28K ] FIG. 28K shows a step corresponding to the step FIG. 28J follows.[FIG. 28L ] FIG. 28L shows a step corresponding to the step Fig. 28K follows.[FIG. 29A] FIG. 29A is a view illustrating a part of another manufacturing process of the semiconductor device of FIG. 24.[FIG. 29B ] FIG. 29B shows a step corresponding to the step Figure 29A follows.[FIG. 29C ] FIG. 29C shows a step subsequent to the step Fig. 29B follows.[FIG. 29D ] FIG. 29D shows a step corresponding to the step Figure 29C follows.[FIG. 29E ] FIG. 29E shows a step corresponding to the step Fig. 29D follows.[FIG. 30] FIG. 30 is a schematic perspective view of a semiconductor package according to a preferred embodiment of the present invention.[FIG. 31 ] FIG. 31 is a view for detecting an electric field relaxation effect caused by an electric field relaxation region.[FIG. 32] FIG. 32 is a view for detecting an electric field relaxation effect caused by an electric field relaxation region.[FIG. 33] FIG. 33 is a circuit diagram of a matrix converter circuit in which a semiconductor device according to a preferred embodiment of the present invention is integrated as a bidirectional switch.[FIG. 34] FIG. 34 is a cross-sectional view showing another shape of the semiconductor device.DESCRIPTION OF THE EMBODIMENTSPreferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.FIGS. 1 and 2 are a top and bottom view, respectively, of the semiconductor device 1 according to a preferred embodiment of the present invention.The semiconductor device 1 has a source electrode 4 serving as an example of a second electrode of the present invention, and a gate pad 5 on its front surface 2 and a drain electrode 6 serving as an example of a first electrode of the present invention on its back surface 3.The source electrode 4 is formed substantially in a quadrangular shape over substantially the entire surface of the front side 2, and has a peripheral edge 9 that is inward away from the end surface 7 of the semiconductor device 1. The peripheral edge 9 is provided with a surface termination structure such as a snap ring, which will be explained below. As a result, a semiconductor region 8 is exposed on the front side 2 of the semiconductor device 1 around the source electrode 4. In the present preferred embodiment, the semiconductor region 8 surrounds the source electrode 4. the gate pad 5 is placed in a corner of the source electrode 4 separately from the source electrode 4 and connected to a gate electrode 26 of each MIS transistor structure 22 which will be described later.The drain electrode 6 is formed in a quadrangular shape over the entire surface of the back surface 3 and has a peripheral edge 10 that coincides with the end surface 7 of the semiconductor device 1 (i.e., which is an extension of the end surface 7). Note that, although an electric field relaxation region 14 forms on the semiconductor device 1 as described later, it is not illustrated in FIG. 1 and FIG. 2.FIG. 3 is a cross-sectional view obtained when the semiconductor device is cut along the line III-III of FIG. 1. FIG. 4 is a view showing a planar pattern of the electric field relaxation region 14 of FIG. 3.The semiconductor device 1 includes a semiconductor layer 11 of n -- type SiC. The semiconductor layer 11 has a front surface 2 which is a Si plane of the SiC, a back surface 3 which is disposed on the opposite side to the front surface 2 and which is a C plane of the SiC, and an end surface 7 which extends in a direction intersecting the front surface 2 (i.e., which extends in a perpendicular direction in FIG. 3 ). The front side 2 may be a plane other than the Si plane of the SiC, and the back side 3 may be a plane other than the C plane of the SiC.The semiconductor layer 11 has a thickness of 5 μm to 300 μm depending on the desired blocking voltage. In addition, the semiconductor layer 11 as a whole has a substantially uniform impurity concentration, for example, an impurity concentration of 1×10 14 cm -3 to 1×10 17 cm -3. The phrase "the semiconductor layer 11 has a substantially uniform impurity concentration" as mentioned herein means that the semiconductor layer 11 does not have an n-type part having a comparatively high impurity concentration (for example, an n +- type part) in its back portion (for example, in a region at a predetermined distance from the back 3 in the thickness direction).The semiconductor layer 11 has an outer peripheral portion 12 which is an example of a peripheral portion in the sense of the present invention and which is disposed at the peripheral edge portion (i.e., a part in the vicinity of the end face 7) and has an active portion 13 surrounded by the outer peripheral portion 12.In the active region 13, a plurality of MIS transistor structures 22 are formed at a front side portion of the semiconductor layer 11. The MIS transistor structure 22 has a p-type body region 23, an n +- type source region 24, a gate insulating film 25, a gate electrode 26, and a p +- type body terminal region 27.More specifically, a plurality of p-type body regions 23 are formed at the front side portion of the semiconductor layer 11. Each p-type body region 23 constitutes a minimum unit (unit cell) through which an electric current flows in the active region 13. The n +- type source region 24 is formed in an inner region of each p type body region 23 so as to be exposed at the front side 2 of the semiconductor layer 11. In the p-type body region 23, a region outside the n + type source region 24 (i.e., a region surrounding the n +- type source region 24) defines a channel region 28. the gate electrode 26 bridges adjacent unit cells and coats the channel region 28 with a gate insulating film 25 therebetween. the p +- type body terminal region 27 passes through the n +- type source region 24 and is electrically connected to the p-type body region 23.Each element of the MIS transistor structure 22 will now be described. The impurity concentration of the p-type body region 23 is, for example, 1×10 16 cm -3 to 1×10 19 cm -3 and the impurity concentration of the n +- type source region 24 is, for example, 1×10 19 cm -3 to 1×10 21 cm -3 and the impurity concentration of the p +- type body terminal region 27 is, for example, 1×1019cm-3to 1×1021cm-3. The gate insulating film 25 is made of, for example, silicon oxide (SiO 2) and its thickness is 20 nm to 100 nm. The gate electrode 26 is made of polysilicon, for example.An n -- type region on the back side 3 with respect to the MIS transistor structure 22 in the semiconductor layer 11 constitutes an n -- type drift region 29 and is exposed to the back side 3 of the semiconductor layer 11.On the front side 2 of the semiconductor layer 11, an intermediate insulation layer 30 bridging over the active region 13 and the outer peripheral region 12 is formed. The interlayer insulating film 30 is made of, for example, silicon oxide (SiO 2) and its thickness is 0.5 μm to 3.0 μm. The interlayer insulating film 30 has a contact hole 31 formed to expose the n +- type source region 24 and the p +- type body terminal region 27 of each unit cell.The source electrode 4 is formed on the interlayer insulating layer 30. The source electrode 4 enters each contact hole 31 and makes ohmic contact with the n +- type source region 24 and the p +- type body terminal region 27. The source electrode 4 has an overlap portion 32 that extends from the active region 13 to the outer peripheral region 12 and that extends on the intermediate insulating layer 30 on the outer peripheral region 12.At the front surface portion of the semiconductor layer 11 in the outer peripheral region 12, a surface termination structure 33 is formed. The surface termination structure 33 may include a plurality of parts including at least a part lying on a peripheral edge portion of the source electrode 4 (i.e., a peripheral edge) of a connection with the semiconductor layer 11). In FIG. 3, an innermost reduced surface field (RESURF) layer 34 and a plurality of guard ring layers 35 surrounding the resurf layer 34 are included. The "resurf" layer 34 is formed so as to bridge an inner side and an outer side of an opening 36 of the interlayer insulating layer 30 and is in contact with the peripheral edge portion of the source electrode 4 inside the opening 36. The plurality of guard ring layers 35 are mutually spaced. Although the resurf layer 34 and the guard ring layer 35 are formed by the p-type impurity region, these layers may be formed by a high-resistance region. If so, the resurf layer 34 and the guard ring layer 35 may have a crystal defect concentration of 1×10 14 cm -3 to 1×10 22 cm -3.In the outer peripheral region 12, an electric field relaxation region 14 is formed outside the surface termination structure 33. The electric field relaxation region 14 is a high resistance region having a larger resistance than the semiconductor layer 11 (the n -- type drift region 29) or a p-type semiconductor region. For example, when the electric field relaxation region 14 is a high-resistivity region, this high-resistivity region has a crystal defect concentration of 1×10 14 cm -3 to 1×10 22 cm -3. In contrast, when the electric field relaxation region 14 is a p-type semiconductor region, an impurity concentration of the p-type semiconductor region is 1×10 18 cm -3 to 1×10 22 cm -3. If the impurity concentration falls within this range, then it is possible to easily maintain the entire p-type semiconductor region at the same electric potential.The electric field relaxation region 14 is a fixed region ranging from the front side 2 to the back side 3 of the semiconductor layer 11. In the present preferred embodiment, the electric field relaxation region 14 is formed such that an inner surface 15 closer to the active region 13 and an outer surface 16 opposite thereto are perpendicular to the front side 2 and the back side 3 in the cross-sectional view illustrated in FIG. 3. This allows the width W 1 of the electric field relaxation region 14 to be substantially constant from the front side 2 to the back side 3 of the semiconductor layer 11.In addition, in the present preferred embodiment, the electric field relaxation region 14 is formed inward away from the end surface 7 of the semiconductor layer 11, and thereby an n -- type peripheral region 17 which is an example of a peripheral impurity region and which is a part of the semiconductor layer 11 is formed outside the electric field relaxation region 14 (i.e., between the electric field relaxation region 14 and the end surface 7 of the semiconductor layer 11). In the present preferred embodiment, the electric field relaxation region 14 is formed in a ring shape in plan view, so that, as shown in FIG. 4, a closed space is created by enclosing the n -- type drift region 29, and a ring-shaped region reaching to the end face 7 is formed outside the electric field relaxation region 14 as the n -- type peripheral region 17.The drain electrode 6 is formed on the back surface 3 of the semiconductor layer 11. The drain electrode 6 is formed on the entire back surface 3 of the semiconductor layer 11 as an integrally molded member. Thereby, the drain electrode 6 comes into contact with the n -- type drift region 29, the electric field relaxation region 14, and the n -- type peripheral region 17 on the back surface 3 of the semiconductor layer 11. Specifically, it is preferable to allow a layer (for example, a Ti layer) in contact with the n -- type drift region 29 in the drain electrode 6 to form a Schottky contact with the n -- type drift region 29. In the present preferred embodiment, the drain electrode 6 is also in contact with the n -- type peripheral region 17 and forms a Schottky contact with the n -- type peripheral region 17.Next, a method of manufacturing the semiconductor device 1 will be described with reference to FIGS. 5A to 5F.To manufacture the semiconductor device 1, a semiconductor layer 11 having a lower concentration than the base substrate 18 is first formed by epitaxial growth on the base substrate 18 (wafer) of n +- type SiC (whose impurity concentration is, for example, 1×10 18 cm -3 to 1×10 20 cm -3 ), as illustrated in FIG. 5A. The thickness of the base substrate 18 may be, for example, 250 μm to 450 μm.Subsequently, an impurity region of the MIS transistor structure 22, the surface termination structure 33, and the electric field relaxation region 14 is formed as illustrated in FIGS. 5B and 5C.In detail, it is individually described whether the electric field relaxation region 14 is a p-type semiconductor region or a high-resistance region.When the electric field relaxation region 14 is a p-type semiconductor region, first, impurity ions are selectively implanted from the front side 2 of the semiconductor layer 11 into regions in which impurity regions of the MIS transistor structure 22 (specifically, the p-type body region 23, the n +- type source region 24, and the p +- type body terminal region 27) and the surface termination structure 33 (specifically, the "resurf" layer 34 and the guard ring layer 35) are to be formed.Thereafter, p-type impurity ions (for example, B ions or Al ions) are selectively implanted from the front side 2 of the semiconductor layer 11 into the regions where the electric field relaxation region 14 is to be formed. At this time, the electric field relaxation region 14 needs to be formed to pass through a region from the front side 2 of the semiconductor layer 11 to the back side 3 and to the base substrate 18, and thus p-type impurity ions are implanted at an implantation energy of, for example, 1 MeV to 10 MeV.After the implantation, each of the impurity ions for forming the impurity regions of the MIS transistor structure 22, the surface termination structure 33, and the electric field relaxation region 14 is simultaneously activated by an annealing treatment (for example, 1500° C. to 1800° C.), and these regions are formed.On the other hand, when the electric field relaxation region 14 is a high-resistance region, first, impurity ions are selectively implanted from the front side 2 of the semiconductor layer 11 into regions in which impurity regions of the MIS transistor structure 22 (specifically, the p-type body region 23, the n +- type source region 24, and the p +- type body terminal region 27) and the surface termination structure 33 (specifically, the resurf layer 34 and the guard ring layer 35) are to be formed.After the implantation, each of the impurity ions to form the impurity regions of the MIS transistor structure 22 and the surface termination structure 33 is activated by an annealing treatment (for example, 1500° C. to 1800° C.), and these regions are formed.Thereafter, a mask (not shown here) is selectively formed on the semiconductor layer 11, and substances such as protons, helium ions, electron beams, all of which are an example of a first substance in the sense of the present invention and each have a comparatively low mass, are radiated through the mask onto the front side 2 of the semiconductor layer 11. After the irradiation, an annealing treatment (for example, 300° C. to 1200° C.) is performed, whereby a crystal defect generated by the radiation particles is formed as an electric field relaxation region 14 (high-resistance region). The annealing treatment of 300° C. to 1200° C. can be omitted.Although there is a case where an annealing treatment is performed after implantation of p-type impurity ions or after emission of protons or the like, when the electric field relaxation region 14 is a p-type semiconductor region or a high resistance region, an element that is weak to a high temperature (for example, a metal such as the source electrode 4) is not yet formed on both the front side 2 of the semiconductor layer 11 and the back side 3 in this annealing treatment, so that it is possible to perform an annealing treatment at a comparatively high temperature. This makes it possible to efficiently generate the electric field relaxation region 14.Subsequently, the gate insulating film 25 and the gate electrode 26, which are the remaining elements of the MIS transistor structure 22, are formed as illustrated in FIG. 5D. Thereafter, the interlayer insulating layer 30 and the source electrode 4 are formed.Thereafter, the entire back surface 3 of the semiconductor layer 11 is exposed by removing the base substrate 18 as illustrated in FIG. 5E. This step may be completed, for example, by polishing (e.g., CMP) after the base substrate 18 is substantially completely removed from the back side 3 by a grinding operation. In the polishing step, the semiconductor layer 11 exposed after completion of the grinding process may be further thinned. Specifically, the base substrate 18 having a thickness of 350 μm may be removed by grinding the back surface, and then the semiconductor layer 11 having a thickness of 50 μm may be polished so that the semiconductor layer 11 becomes 40 μm thick. Performing the final polishing step makes it possible to smooth a surface state of the back surface 3 of the exposed semiconductor layer 11, and thus it is possible for the drain electrode 6 to produce an excellent Schottky contact.Thereafter, the drain electrode 6 (for example, Ti / Al) is formed on the entire back surface 3 of the semiconductor layer 11 by, for example, a "sputtering" method as shown in FIG. 5F. Thereafter, the semiconductor layer 11 is cut into pieces along a cut line preset at a predetermined position. Thereby, semiconductor devices 1 each of which is one of a plurality of pieces are obtained.According to the above method, the electric field relaxation region 14 is formed in a stable state in which the semiconductor layer 11 is fixed on the base substrate 18 as illustrated in FIG. 5C. In other words, it is not necessary to form the electric field relaxation region 14 in a thin wafer state (for example, FIG. 5E ) after removing the base substrate 18, and it is possible to prevent the wafer from breaking into pieces due to, for example, a handling error. Moreover, it is also possible to restrict a step performed after removing the base substrate 18 and thinning the wafer to the step of forming the drain electrode 6 shown in FIG. 5F, and thus reduce the number of handling times in handling the thinned wafer and reduce a probability of handling errors. Thereby, it is possible to reduce the probability of occurrence of defective articles and thus improve the yield in the manufacturing process.In addition, when the MIS transistor structure 22 is formed at the front side portion of the semiconductor layer 11 as illustrated in FIG. 5C, it is possible to form the electric field relaxation region 14 by processing (ion implantation, proton radiation, etc.) from the front side 2 of the semiconductor layer 11 in parallel with the production thereof. Therefore, it is possible to place restrictions on factors (temperature, chemical compound to be used, devices, etc.) that affect each element of the MIS transistor structure 22 that are smaller than the case where the electric field relaxation region 14 is formed after the formation of the MIS transistor structure 22.Thereby, it is possible to improve the efficiency of the manufacturing process.In addition, with the semiconductor device 1 obtained above, it is possible to block an electric current flowing through the inside of the semiconductor layer 11 in the thickness direction by the Schottky barrier of the Schottky contact between the semiconductor layer 11 and the drain electrode 6 when a reverse voltage is applied to the MIS transistor structure 22. In addition, the electric field relaxation region 14 is formed around the MIS transistor structure 22. Therefore, even if a barrier layer spreads toward the end face 7 (chip end face) of the semiconductor layer 11 upon application of a reverse voltage, it is possible to stop the barrier layer via the electric field relaxation region 14 and prevent the barrier layer from reaching the end face 7. This makes it possible to reduce the electric field strength in the vicinity of the end surface 7 of the semiconductor layer 11. Therefore, even if a defective region is present at the end surface 7 of the semiconductor layer 11 due to dicing, it is possible to prevent a leakage current from flowing through the formation of electron-hole pairs in the defective region. This allows the semiconductor device 1 to provide an excellent reverse voltage, and thus allows the semiconductor device 1 to be used as a reverse blocking MISFET for bidirectional switches.FIGS. 6A to 6D respectively show parts of another manufacturing process of the semiconductor device 1. when the electric field relaxation region 14 is a p-type impurity region, it is possible to manufacture the electric field relaxation region 14 by performing the steps of FIGS. 6A to 6D instead of the above-mentioned steps of FIGS. 5A to 5C.For example, the semiconductor layer 11 having a lower concentration than the base substrate 18 is first formed by epitaxial growth on the base substrate 18 (wafer) of n +- type SiC (whose impurity concentration is, for example, 1×10 18 cm -3 to 1×10 20 cm -3 ), as shown in FIG. 6A.Subsequently, a mask (not illustrated here) selectively having an opening in a region where the electric field relaxation region 14 is to be formed is formed on the semiconductor layer 11, and the semiconductor layer 11 is selectively etched from the front side 2 through the mask. This etching process is continuously performed until it passes through the semiconductor layer 11 and reaches the base substrate 18. As a result, a through hole 19 is formed in the semiconductor layer 11, which meets the base substrate 18 from the front side 2, as illustrated in FIG. 6B.Thereafter, the p-type SiC is epitaxially grown in the through hole 19 while introducing p-type impurity ions, as shown in FIG. 6C. Accordingly, the through hole 19 is backfilled with p-type SiC, thereby forming the electric field relaxation region 14 comprised of these p-type SiC.Thereafter, an impurity region of the MIS transistor structure 22 and the surface termination structure 33 is formed in which impurity ions are selectively implanted from the front side 2 of the semiconductor layer 11 as illustrated in FIG. 6D. Specifically, the p-type body region 23, the n +- type source region 24, the p +- type body terminal region 27, the resurf layer 34, and the guard ring layer 35 are formed.Thereafter, the steps of FIGS. 5D to 5F are performed, and as a result, the aforementioned semiconductor device 1 (note that the electric field relaxation region 14 here is a p-type impurity region) is obtained.Next, another embodiment of the semiconductor device 1 according to a preferred embodiment will be described with reference to the drawings.In FIG. 3, the electric field relaxation region 14 was formed such that the inner surface 15 and the outer surface 16 are perpendicular to the front side 2 and the back side 3, and its width W 1 was substantially constant from the front side 2 to the back side 3 of the semiconductor layer 11. However, as illustrated in FIG. 7, the electric field relaxation region 14 may be formed such that the inner surface 15 and the outer surface 16 are inclined with respect to the front side 2 and the rear side 3, and thereby may have a conical shape in which the width W 1 gradually becomes narrower in cross section from the rear side 3 toward the front side 2.In addition, the electric field relaxation region 14 shown in FIG. 3 was formed by ion implantation, proton irradiation or the like, or the filling of the through hole 19 so that the inner surface 15 and the outer surface 16 were formed to be substantially flat in cross section. However, as illustrated in FIG. 8, the inner surface 15 and the outer surface 16 of the electric field relaxation region 14 may be concavo-convex surfaces which regularly wave in the thickness direction of the semiconductor layer 11. A method of forming this configuration may be described with reference to FIGS. 9A and 9B.For example, the semiconductor layer 11 is first formed by a multistage epitaxial process in which an n -- type layer 20 is repeatedly epitaxially grown on the base substrate 18 as shown in FIG. 9A. In this step, when each n -- type layer 20 is grown, p-type impurity ions or protons or the like are implanted in a predetermined part of the n -- type layer 20. Thereafter, a p-type impurity region or a high resistance region of protons or the like is sequentially stacked in association with the fact that the n -- type layers 20 are stacked together to achieve a multilayer structure. Thereby, p-type impurity regions or high-resistance regions of the adjacent n -- type layers 20 are mutually arranged, and the electric field relaxation region 14 having the inner surface 15 and the outer surface 16 as concavo-convex surfaces is formed. When the electric field relaxation region 14 (high resistance region) is formed by using the multistage epitaxial method, the formation of the electric field relaxation region 14 reaching the back surface 3 from the front surface 2 of the semiconductor layer 11 by once radiation is omitted as described above, and it is only necessary that the protons or the like fully spread in the thickness direction of each comparatively thin n -- type layer 20 in the single implantation step. Therefore, it is possible to form the electric field relaxation region 14 also by implanting boron (B) or argon (Ar) without being limited to light chemical elements such as protons. When boron is implanted, it depends on an annealing temperature whether the electric field relaxation region 14 becomes a high impedance region or a p-type region. For example, the electric field relaxation region 14 does not become a p-type region in annealing treatment of As impla and 1200° C. or less, and the electric field relaxation region 14 functions as a high resistance region. On the other hand, when the annealing treatment is performed at 1200° C. or more, boron atoms are activated and the electric field relaxation region 14 can function as a p-type region. In order to increase the activation rate as a p-type, the annealing treatment needs to be performed at an even higher temperature (1500° C. or more).Thereafter, an impurity region of the MIS transistor structure 22 and the surface termination structure 33 is formed by selectively implanting impurity ions from the front side 2 of the semiconductor layer 11 as illustrated in FIG. 9B. Specifically, the p-type body region 23, the n +- type source region 24, the p +- type body terminal region 27, the resurf layer 34, and the guard ring layer 35 are formed.Subsequently, the steps of FIGS. 5D to 5F are performed, and thereby the aforementioned semiconductor device 1 (note that the electric field relaxation region 14 here is a p-type impurity region) is obtained.Although the electric field relaxation region 14 has been formed inward away from the end surface 7 of the semiconductor layer 11 as shown in FIG. 3, the electric field relaxation region 14 may be formed to reach the end surface 7 of the semiconductor layer 11 as shown in FIGS. 10 and 11. Thereby, the outer surface 16 of the electric field relaxation portion 14 becomes a surface coincident with the end surface 7 of the semiconductor layer 11.In addition, the semiconductor device 1 may include a second drain electrode 37, as illustrated in FIGS. 12 and 13, which is an example of an auxiliary electrode within the meaning of the present invention and which is formed on the front side 2 of the semiconductor layer 11 so as to be equal in electric potential to the drain electrode 6.Specifically, in the semiconductor device 1 of FIGS. 12 and 13, in the intermediate insulating layer 30, a contact hole 38 through which the n -- type peripheral region 17 and the electric field relaxation region 14 are exposed in one end of the semiconductor layer 11 is formed. The contact hole 38 has an annular inner peripheral edge 39 surrounding the n -- type drift region 29 as shown in FIG. 13. Although the contact hole 38 is formed up to the end face 7 of the semiconductor layer 11 such that the intermediate insulation layer 30 is not formed in the vicinity of the end face 7 of the semiconductor layer 11 in FIG..12 And remaining in FIG. 13, the contact hole 38 may have an outer peripheral edge positioned inwardly at a distance from the end face 7 such that a portion of the intermediate insulation layer 30 remains near the end face 7.The second drain electrode 37 enters the contact hole 38 and bridges a boundary between the n -- type peripheral region 17 and the electric field relaxation region 14 in the contact hole 38 and is adjacent to the two regions 14 and 17. In addition, when the electric field relaxation region 14 is formed up to the end surface 7 of the semiconductor layer 11 as described with reference to FIG. 10, the second drain electrode 37 may be in contact with only the electric field relaxation region 14 in the contact hole 38 as illustrated in FIG. 14.The second drain electrode 37 is electrically connected to the drain electrode 6, not shown in FIGS. 12 to 14 (see FIG. 38 regarding a connection mode between the drain electrode 6 and the second drain electrode 37). Accordingly, the electric potentials of the n -- type peripheral region 17 (FIG. 12 ) and the electric field relaxation region 14 (FIG. 14 ) are at the same electric potential from the front side 2 of the semiconductor layer 11 with which the second drain electrode 37 is in contact to the back side 3 with which the drain electrode 6 is in contact. Thereby, it is possible to bring about a state in which an electric field does not easily form in the n -- type peripheral region 17 (FIG. 12 ) and the electric field relaxation region 14 (FIG. 14 ), and thus it is possible to further reduce an electric field strength in the vicinity of the end surface 7 of the semiconductor layer 11.Moreover, in the aforementioned FIGS. 1 to 14, each electric field relaxation region 14 has been formed to reach the back surface 3 from a flat part of the front surface 2 of the semiconductor layer 11 (i.e., a part in which a concave portion such as a trench is not intentionally formed and in which the state of the epitaxially grown front surface 2 is maintained). However, the electric field relaxation region 14 may be formed with a structure illustrated in FIG. 15.In particular, in the outer peripheral region 12 of the semiconductor layer 11, a trench 40 is formed from the front side 2 of the semiconductor layer 11 outside the surface termination structure 33, which is an example of a concave portion in the sense of the present invention and which has a lower portion at the rear-side portion of the semiconductor layer 11. The trench 40 is formed annularly so as to enclose the n -- type drift region 29, not shown, in the same manner as the electric field relaxation region 14 of FIG. 4.In addition, the electric field relaxation region 14 is entirely formed of a side portion and a lower portion of the trench 40 along the inner surface of the trench 40, and the lower portion is exposed at the back surface 3 of the semiconductor layer 11. In other words, the electric field relaxation region 14 formed on the side portion of the trench 40 at the opening end of the trench 40 is exposed to the front side 2, and the electric field relaxation region 14 formed below the lower portion of the trench 40 is exposed to the back side 3. Accordingly, the electric field relaxation region 14 is formed so as to penetrate the semiconductor layer 11 from the front side 2 to the back side 3 as a whole.The interlayer insulating layer 30 is formed along the inner surface of the trench 40 and forms a fixed cavity 41 inside the trench 40.A method of forming this configuration may be described with reference to FIGS. 16A to 16E.For example, the semiconductor layer 11 lower in concentration than the base substrate 18 is first formed by epitaxial growth on the base substrate 18 (wafer) of n +- type SiC whose impurity concentration is, for example, 1×10 18 cm -3 to 1×10 20 cm -3 as illustrated in FIG. 16A.Thereafter, an impurity region of the MIS transistor structure 22 and the surface termination structure 33 is formed in which impurity ions are selectively implanted from the front side 2 of the semiconductor layer 11 as illustrated in FIG. 16B. Specifically, the p-type body region 23, the n +- type source region 24, the p +- type body terminal region 27, the resurf layer 34, and the guard ring layer 35 are formed.Thereafter, a mask (not shown) selectively having an opening in a region where the electric field relaxation region 14 is to be formed is formed on the semiconductor layer 11, and the semiconductor layer 11 is selectively etched from the front side 2 through the mask. Thereby, the trench 40 is formed in the semiconductor layer 11 as illustrated in FIG. 16C.Thereafter, p-type impurity ions are selectively implanted into the inner surface of the trench 40 and then an annealing treatment is performed, or alternatively, substances such as protons are implanted for high-resistance regions as illustrated in FIG. 16D. Accordingly, the electric field relaxation region 14 is formed along the inner surface of the trench 40. Also, in this step, the depth of the region where the electric field relaxation region 14 is to be formed is reduced by forming the trench 40 as in a case where the multistage epitaxial method as described above is applied, and therefore it is possible to form the electric field relaxation region 14 also by implanting boron (B) or argon (Ar) without being limited to light chemical elements such as protons.Thereafter, the gate insulating film 25 and the gate electrode 26 which are the remaining elements of the MIS transistor structures 22 are formed as illustrated in FIG. 16E. Subsequently, the interlayer insulating layer 30 and the source electrode 4 are formed.Thereafter, the steps of FIGS. 5E and 5F are performed, thereby obtaining the aforementioned semiconductor device 1 (note that the electric field relaxation region 14 here is a p-type impurity region).In addition, in the semiconductor device 1 of FIG. 15, a conductive material 45 may be embedded in the cavity 41 as illustrated in FIGS. 16 and 17. When the conductive material 45 is embedded in the cavity 41, the inner interlayer insulating layer 30 in the trench 40 is removed, and the conductive material 45 is in contact with the electric field relaxation region 14 in the inner surface of the trench 40.The conductive material 45 is metal (for example, W), polysilicon, or the like. When the conductive material 45 is metal, the conductive material 45 may be used as an embedded electrode as well as the aforementioned second drain electrode 37 (see FIGS. 12 and 14 ), as illustrated in FIG. 17. In other words, the conductive material 45 is electrically connected to the drain electrode 6, and thereby the electric potential of the electric field relaxation region 14 is fixed to the same electric potential from the inner surface of the trench 40 in contact with the conductive material 45 to the back surface 3 in contact with the drain electrode 6. Thereby, it is possible to bring about a state in which an electric field does not easily form in the electric field relaxation region 14, and thereby it is possible to relax an electric field strength in the vicinity of the end surface 7 of the semiconductor layer 11. On the other hand, when the conductive material 45 is polysilicon, the second drain electrode 37 may be formed to come into contact with the conductive material 45 as shown in FIG. 18.In addition, the semiconductor device 1 may have a second electric field relaxation region 42 at a bottom surface portion of the semiconductor layer 11 as shown in FIGS. 19 to 22.The second electric field relaxation region 42 is formed to be exposed to a Schottky interface (back surface 3) of the drain electrode 6 in the semiconductor layer 11, and the drain electrode 6 is in contact with the second electric field relaxation region 42 to which it is exposed. The second electric field relaxation region 42 is, in the same manner as the electric field relaxation region 14, a high resistance region having a higher resistance than the semiconductor layer 11 (n -- type drift region 29) or a p-type semiconductor region. For example, when the second electric field relaxation region 42 is a high-resistance region, this high-resistance region has a crystal defect concentration of 1×10 14 cm -3 to 1×10 22 cm -3. On the other hand, when the second electric field relaxation region 42 is a p-type semiconductor region, this p-type semiconductor region has an impurity concentration of 1×10 16 cm -3 to 1×10 19 cm -3.The formation of the second electric field relaxation region 42 makes it possible to relax the electric field of the Schottky interface between the semiconductor layer 11 and the drain electrode 6. Accordingly, it is possible to reduce a back leakage current even when a metal having a comparatively small work function is used as the drain electrode 6, and thus the use of this metal ensures a low "on" resistance.In a bottom view in which the semiconductor layer 11 is viewed from the back 3, the pattern of the second electric field relaxation region 42 (base pattern) may be a matrix pattern as illustrated in FIG. 20, a lattice pattern as illustrated in FIG. 21, or a stripe pattern as illustrated in FIG. 22. The FIGURE shows the FIGURE.20 Patterns illustrated to FIG. 22 are merely examples of patterns of the second electric field relaxation region 42, and for example, other patterns (staggered patterns or the like) in which a plurality of second electric field relaxation regions 42 are regularly discretely arranged, or a pattern in which a single second electric field relaxation region 42 is arranged below the MIS transistor structure 22 are applicable. Although the second electric field relaxation region 42 spans the electric field relaxation region 14 and is formed on the entire back surface 3 of the semiconductor layer 11 in FIGS. 20 to 22, the second electric field relaxation region 42 may be formed only in a region surrounded by the electric field relaxation region 14.A method of forming the second electric field relaxation region 42 can be described with reference to FIGS. 23A to 23H.For example, an n -- type first semiconductor layer 43 lower in concentration than the base substrate 18 may be formed first by epitaxial growth on the base substrate 18 (wafer) of n +- type SiC (the impurity concentration of which is, for example, 1×10 18 cm -3 to 1×10 20 cm -3) as shown in FIG. 23A. The thickness of the first semiconductor layer 43 is, for example, 0.5 μm to 5 μm.Thereafter, the second electric field relaxation region 42 is formed on the first semiconductor layer 43 as illustrated in FIG. 23B. The second electric field relaxation region 42 may be formed according to the same formation method as the aforementioned electric field relaxation region 14.In other words, p-type impurity ions are selectively implanted into the front surface of the first semiconductor layer 43, and then the first semiconductor layer 43 is subjected to an annealing treatment (for example, 1500° C. to 1800° C.), or alternatively, boron or the like is selectively irradiated onto the front surface of the first semiconductor layer 43, and the first semiconductor layer 43 then undergoes an annealing treatment (for example, 300° C. to 1200° C.). In either case, the annealing treatment may be performed in a later step (for example, simultaneously with a step in which the impurity region of the MIS transistor structure 22 is activated), or when the second electric field relaxation region 42 is a high impedance region, the annealing treatment is performed or omitted only if necessary.Accordingly, in both cases, the second electric field relaxation region 42 which is a p-type impurity region or a high-resistance region is formed. At this time, although in FIG. 23B, the second electric field relaxation region 42 is formed at the front side portion of the first semiconductor layer 43 so as not to pass through the first semiconductor layer 43, each of the second electric field relaxation regions 42 may pass through the first semiconductor layer 43 and reach the base substrate 18, for example. Although there is a case where annealing treatment is performed even in the formation of the second electric field relaxation region 42 after implanting p-type impurity ions or after radiating boron or the like, an element weak to a high temperature has not yet been formed on both the base substrate 18 and the first semiconductor layer 43 in the execution of the annealing treatment, so that it is possible to perform the annealing treatment at a comparatively high temperature.Thereafter, a second n -- type semiconductor layer 44 is formed by further epitaxial growth on the first semiconductor layer 43 as shown in FIG. 23C. The thickness of the second semiconductor layer 44 is, for example, 5 μm to 300 μm. Accordingly, the semiconductor layer 11 consisting of the first semiconductor layer 43 and the second semiconductor layer 44 is formed. The second electric field relaxation region 42 formed at the front side portion of the first semiconductor layer 43 is in a state embedded in the lower portion of the semiconductor layer 11.Thereafter, an impurity region of the MIS transistor structure 22 and the surface termination structure 33 is formed by selectively implanting impurity ions from the front side 2 of the semiconductor layer 11 as illustrated in FIG. 23D. Specifically, the p-type body region 23, the n +- type source region 24, the p +- type body terminal region 27, the resurf layer 34, and the guard ring layer 35 are formed.Thereafter, in the semiconductor layer 11, the electric field relaxation region 14 is formed as illustrated in FIG. 23E. The electric field relaxation region 14 is formed by the same method as described in FIG. 5C.Thereafter, the gate insulating film 25 and the gate electrode 26 which are the remaining elements of the MIS transistor structure 22 are formed as shown in FIG. 23F. Thereafter, the interlayer insulating layer 30 and the source electrode 4 are formed.Thereafter, the entire back surface 3 of the semiconductor layer 11 is exposed by removing the base substrate 18 as illustrated in FIG. 23G. Although this step is continued until the second electric field relaxation region 42 is exposed at the back surface 3, this step may be stopped before the second electric field relaxation region 42 appears on the exposed surface (a base surface). Thereby, it is possible to obtain a configuration in which the second electric field relaxation region 42 is embedded without being exposed from the back surface 3 of the semiconductor layer 11.Thereafter, the drain electrode 6 (for example, Ti / Al) is entirely formed on the back surface 3 of the semiconductor layer 11 by, for example, a "sputtering" method as shown in FIG. 23H. Thereafter, the semiconductor layer 11 is cut into pieces along a cut line extending at a predetermined position. This results in semiconductor devices 1, each of which is one of a plurality of pieces.FIG. 24 is a schematic cross-sectional view of a semiconductor device 1 according to another preferred embodiment of the present invention.In the semiconductor device 1 illustrated in FIG. 24, the end surface 7 of the semiconductor layer 11 includes a part facing the back side 3 of the semiconductor layer 11 in the thickness direction. In FIG. 24, the linearly illustrated planar end face 7 is inclined at an angle greater than 90° (internal angle θ between end face 7 and the rear side 3>90°) to the rear side 3 of the semiconductor layer 11 in a cross-sectional view, such that the entire planar end face 7 in the thickness direction faces the rear side 3 of the semiconductor layer 11. In other words, the normal direction n of a part of the end face 7 (for example, point P in the end face 7) is not parallel to the back surface 3 of the semiconductor layer 11, but is inclined in a direction approaching the back surface 3.The electric field relaxation region 14 is formed at least on the end surface 7 of the semiconductor layer 11 and exposed at the end surface 7.The drain electrode 6 is formed on the entire surface of the back surface 3 of the semiconductor layer 11 and further on the end surface 7. The drain electrode 6 is in contact with the electric field relaxation region 14 at the end surface 7 of the semiconductor layer 11.According to the present configuration, it is possible to form the drain electrode 6 on the entire surface of the back surface 3, so that simple "die" bonding is possible when it is joined to a frame 46 (for example, an island portion of a lead frame) by a joining material 47 (for example, solder) as illustrated in FIG. 25. In addition, the end face 7 of the semiconductor layer 11 is covered with the drain electrode 6 continuously extending from the back surface 3, so that even if an excessive joining material 47 runs along the end face 7 of the semiconductor layer 11, this excessive joining material 47 only comes into contact with the drain electrode 6, thus presenting no specific problem.Next, the shape of the end surface 7 of the semiconductor layer 11 in the present preferred embodiment will be described with reference to FIGS. 26A to 26C. In FIGS. 26A to 26C, among the configurations illustrated in FIG. 24, only the configuration required for describing the shape of the end surface 7 is illustrated, and the other configurations are omitted.First, the semiconductor layer 11 has an upper end face end 48 that is an end edge on the front side 2 of the end face 7, and a lower end face end 49 that is an end edge on the back side 3 of the end face 7 in a cross-sectional view that is the same in FIGS. 26A to 26C. The lower end face end 49 is disposed at a position more inward than the upper end face end 48.As just described, the end surface 7 connects the lower end surface end 49 disposed in a relatively inner position and the upper end surface end 48 disposed in a relatively outer position, and thereby the end surface 7 includes a part facing the back side of the semiconductor layer 11 in the thickness direction as described above.In other words, in the present preferred embodiment, a phantom linear line segment 50 by which the upper end face 48 and the lower end face 49 are connected to each other is to be inclined only at an angle exceeding 90° to the back surface 3 of the semiconductor layer 11, as illustrated in FIGS. 26A to 26C. In this case, the end face 7 may be a planar face (which is identical in configuration to that of FIG. 24 ) coincident with the phantom line segment 50 as illustrated in FIG. 26A in a cross-sectional view, or the end face 7 may be a convex face bulging outward with respect to the phantom line segment 50 as illustrated in FIG. 26B, or the end face 7 may be a concave face bulging inward with respect to the phantom line segment 50 as illustrated in FIG. 26C.Moreover, it is permissible to use a shape (perpendicular shape) in which a part facing the back side 3 of the semiconductor layer 11 in the thickness direction extends from the lower end face end 49 to a center in the thickness direction of the semiconductor layer 11 and a part from there to the upper end face end 48 does not face the back side 3 as described later (as described with reference to FIGS. 29A to 29E ).Next, a positional relationship between the electric field relaxation region 14 and the drain electrode 6 in the present preferred embodiment will be described with reference to FIGS. 27A to 27E. In FIGS. 27A to 27E, only the configuration necessary to describe a positional relationship between the electric field relaxation region 14 and the drain electrode 6 between the configuration illustrated in FIG. 24 is illustrated, and the other configurations are omitted.First, the electric field relaxation region 14 may be formed to extend from the back surface 3 of the semiconductor layer 11 to the front surface 2, as illustrated in FIG. 27A. More specifically, the electric field relaxation region 14 integrally includes a main portion 51 formed along the end face 7 and having an inner surface 15 at a position substantially constant in thickness to the end face 7, and a lower surface side portion 52 drawn inward from a lower end of the main portion 51 (an end on the back side 3 of the semiconductor layer 11). The undersurface-side portion 52 has an inner surface 15 at a position having a substantially constant thickness toward the back surface 3. When expressed differently, the width of the electric field relaxation region 14 may be defined by the thickness of the electric field relaxation region 14 in the cross-sectional view or as the depth from the back 3 and the end face 7. In addition, the relaxation region of the electric field 14 is exposed at the rear side 3 and at the end face 7. The drain electrode 6 is formed from the back surface 3 of the semiconductor layer 11 to the front surface 2, and has the peripheral edge 10 at a position of the front surface 2 of the semiconductor layer 11. According to this configuration, it is possible to omit a patterning step of the drain electrode 6 and simplify the manufacturing process in a manufacturing process illustrated in FIGS. 28A to 28L.Thus, as illustrated in FIG. 27B, the electric field relaxation region 14 has a main portion 51 formed from the back surface 3 of the semiconductor layer 11 to a thickness direction center portion of the end surface 7, and an n -- type region 54 that is a part of the n -- type drift region 29 may be interposed between the front surface 2 and an upper end 53 of the electric field relaxation region 14. In this case, it is preferable that the drain electrode 6 is also formed away from the front side 2 of the semiconductor layer 11 like the electric field relaxation region 14, and the peripheral edge 10 of the drain electrode 6 is disposed on the back side 3 in the thickness direction with respect to the end 53 of the electric field relaxation region 14 in FIG. 27B. This prevents the drain electrode 6 and the n -- type region 54 from coming into contact with each other at the end surface 7 of the semiconductor layer 11.Thus, in a configuration in which the main portion 51 is formed from the back side 3 to the front side 2 in the same manner as in FIG. 27A, the electric field relaxation region 14 may additionally and integrally include a surface side portion 55 that is drawn inward from the upper end of the main portion 51 (an end on the front side 2 of the semiconductor layer 11) as illustrated in FIG. 27C. According to this configuration, a part of the electric field relaxation region 14 is configured to extend from the peripheral edge 10 of the drain electrode 6, so that it is possible to further improve a blocking voltage.Thus, in a case where the electric field relaxation region 14 has the configuration of FIG. 27A, the peripheral edge 10 of the drain electrode 6 in the thickness direction may be disposed on the back side 3 with respect to the end 53 of the electric field relaxation region 14 (the front side 2 of the semiconductor layer 11) of FIG. 27D. According to this configuration, a part of the electric field relaxation region 14 is configured to extend from the peripheral edge 10 of the drain electrode 6, and therefore it is possible to further improve a blocking voltage.Thus, the electric field relaxation region 14 is selectively formed as the main portion 51 only on the end surface 7 of the semiconductor layer 11 as illustrated in FIG. 27E, and does not necessarily need to be formed on the back surface 3. Specifically, the electric field relaxation region 14 is formed from the front side 2 of the semiconductor layer 11 to a thickness direction center portion of the end surface 7, and an n -- type region 57 that is a part of the n -- type drift region 29 may be interposed between the back side 3 and the lower end 56 of the electric field relaxation region 14. In this case, the drain electrode 6 may be in contact with the electric field relaxation region 14 at the end surface 7 and may form a Schottky contact with the n -- type region 57 by contact with the n type region 57. It is possible to further reduce a leakage current when the barrier height of the Schottky contact at the end surface 7 is higher than the barrier height of the Schottky contact at the back surface 3.Next, a method of manufacturing the semiconductor device 1 according to the present preferred embodiment will be described with reference to FIGS. 28A to 28L. In FIGS. 28A to 28L, among the configuration illustrated in FIG. 24, only the configuration of a characterizing part of the manufacturing process of the present preferred embodiment is illustrated, and the other configurations are omitted. In FIGS. 28A to 28L, the same reference numeral is given for a component identical to that of FIGS. 5A to 5F.First, the semiconductor layer 11 is formed on the base substrate 18 (wafer) by epitaxial growth as illustrated in FIG. 28A. Thereafter, the MIS transistor structure 22 (not shown) is formed at a front side portion of the semiconductor layer 11 and a surface metal 58. The surface metal 58 may include the source electrode 4 of FIG. 24, a gate pad connected to the gate electrode 26, and the like.Thereafter, adhesion to the front surface of the semiconductor layer 11 may be allowed to occur to a support substrate 60 by an adhesive member 59 (adhesive, adhesive tape, etc.) as illustrated in FIG. 28B.Thereafter, the back surface 3 of the semiconductor layer 11 is exposed by grinding the base substrate 18 from the back surface side, as illustrated in FIG. 28C.Thereafter, a mask 61 having an opening is selectively formed on the back surface 3 of the semiconductor layer 11 as shown in FIG. 28D. For example, a metal foil, an insulating foil, a resist, etc. may be used as the mask 61.Thereafter, the semiconductor layer 11 is selectively etched from the back side 3 through the mask 61 as shown in FIG. 28E. More specifically, an etchant is added to the semiconductor layer 11, and thereby the semiconductor layer 11 is etched from the back side 3. For example, dry etching with a fluorine-containing gas such as SF 6, can be used as the etching process. In addition, the etching process may be performed from the back surface 3 of the semiconductor layer 11 to the front surface 2 or from the back surface 3 to a center in the thickness direction of the semiconductor layer 11. By the etching process, a groove 62 surrounded by the end surface 7 facing the back side 3 in the thickness direction of the semiconductor layer 11 is formed. Thereafter, the mask 61 used for the etching is removed.Thereafter, a mask 63 having an opening is selectively formed on the back surface 3 of the semiconductor layer 11 as shown in FIG. 28F. For example, a metal foil, an insulating foil, a resist, etc. may be used as the mask 63. Thereafter, from the back surface 3 of the semiconductor layer 11, substances of comparatively small mass such as p-type impurity ions, protons, helium ions, electron beams are implanted via the mask 63. Accordingly, along the end face 7, the electric field relaxation region 14 is formed with a substantially constant width. At this time, using the mask 63 having a width W 2 narrower than a width W 1 between grooves 62 connecting each other enables a part of the back surface 3 of the semiconductor layer 11 to be exposed and thus ions or the like to be introduced into the exposed part. Thereby, it is possible to form the undersurface side portion 52 of the electric field relaxation region 14 (see FIG. 27A and the like). Thereafter, if necessary, laser annealing is performed to restore crystal damage that the semiconductor layer 11 has obtained due to the etching process or the ion implantation process as illustrated in FIG. 28G.Thereafter, the drain electrode 6 is formed so as to integrally cover the back surface 3 and the end surface 7 of the semiconductor layer 11 by, for example, a sputtering method as shown in FIG. 28H.Thereafter, a dicing tape 64 (Engl.) is allowed to adhere to the back side 3 of the semiconductor layer 11, i.e., to adhere to the drain electrode 6, as shown in FIG. 28I.Thereafter, the support substrate 60 is removed from the front side 2 of the semiconductor layer 11 together with the adhesive member 59 as illustrated in FIG. 28J.Thereafter, the semiconductor layer 11 is cut along a cut line 65 set along the groove 62, for example, as shown in FIG. 28K. This dicing step is not necessary when an etching step is performed from the back side 3 to the front side 2 of the semiconductor layer 11 as shown in FIG. 28E.Thereafter, the dicing tape 64 is removed, and thereby semiconductor devices 1 each of which is one of a plurality of pieces is included, as illustrated in FIG. 28L.According to the aforementioned method, the end surface 7 is formed to face the back side 3 of the semiconductor layer 11 by etching. It is possible to form the electric field relaxation region 14 also by ion implantation into the end surface 7 as described above, and therefore it is possible to easily form the electric field relaxation region 14 with lower energy than in the case where the electric field relaxation region 14 ranging from the front side 2 to the back side 3 of the semiconductor layer 11 is formed by ion implantation as in the aforementioned preferred embodiment. Moreover, it is possible to make the steps simpler than in a case where the electric field relaxation region 14 is formed by backfilling the through hole 19 illustrated in FIGS. 6A to 6D.Although FIGS. 28A to 28L show the case where the etching of the semiconductor layer 11 is performed from the back surface 3 to the front surface 2, these steps may be changed to steps of FIGS. 29A to 29E.Specifically, etching of the semiconductor layer 11 at the center in the thickness direction of the semiconductor layer 11 from the back surface 3 may be stopped as illustrated in FIG. 29B after the back surface 3 of the semiconductor layer 11 is exposed by the back surface grinding step of FIG. 29A.Thereafter, a step of forming the electric field relaxation region 14 (FIG. 29C ) and a step of forming the drain electrode 6 (FIG. 29D ) are performed, and then a "dicing" step is performed as illustrated in FIG. 29E. In this case, a portion not yet etched in the semiconductor layer 11 is exposed as the end face 66 perpendicular to the front side 2, as shown in FIG. 29E. Therefore, a top on the front side 2 is exposed at the end face 7 of the semiconductor layer 11 as the perpendicular end face 66. The perpendicular end surface 66 may be formed by the dicing step and is not formed yet when ions are implanted to form the electric field relaxation region 14 and when the drain electrode 6 is formed. Therefore, neither the electric field relaxation region 14 nor the drain electrode 6 is formed on the perpendicular end surface 66, and an n -- type region 67 that is part of the n -- type drift region 29 is exposed.FIG. 30 is a schematic perspective view of a semiconductor package 71 according to a preferred embodiment of the present invention. In FIG. 30, the same reference numeral is assigned to a component that is the same as a corresponding component of FIGS. 1 to 23, and a description of this component is omitted. In addition, for the sake of convenience, the inside of the resin package 74 is shown in phantom in FIG. 30.The semiconductor package 71 includes a semiconductor chip 72, a substrate terminal 73, and the resin package 74.The semiconductor chip 72 can be formed in the same manner as a semiconductor device 1 according to FIGS. 1 to 23.The substrate terminal 73 is a plate (a metal substrate) made of a metallic material such as Cu, and includes a drain terminal 77, a source terminal 78, and a gate terminal 79.The drain terminal 77 includes an island portion 80 that is quadrangular in plan view and a linear terminal portion 81 extending from one side of the island portion 80. The source terminal 78 and the gate terminal 79 are each formed in the shape of a line parallel to the terminal portion 81 of the drain terminal 77, and are disposed on the right side and on the left side of the drawing sheet, respectively, to wedge the central drain terminal 77 (the terminal portion 81) placed therebetween from both sides in the width direction.The island portion 80 serves to support the semiconductor chip 72 and has a larger area than the semiconductor chip 72. Accordingly, the island portion 80 has an outer peripheral portion 88 that is a part outside the semiconductor chip 72 and surrounds the semiconductor chip 72 in the mounted state of the semiconductor chip 72.The drain electrode (the drain electrode 6 of FIG. 3 ) of the semiconductor chip 72 is electrically connected to the island portion 80 by die bonding. On the other hand, the source electrode 4 and the gate pad 5 of the semiconductor chip 72 are electrically connected to the source terminal 78 and the gate terminal 79 via bonding wires 85 and 86, respectively. When the semiconductor chip 72 additionally includes the second drain electrode 37 illustrated in FIGS. 12 and 14, the second drain electrode 37 is connected to the drain electrode 6 via a bonding wire 82 and the drain terminal 77 (the island portion 80). This makes it possible to equalize the electric potential of the drain electrode 6 and the second drain electrode 37 with each other.Next, the effects obtained by the aforementioned electric field relaxation region 14 will be described with reference to FIGS. 31 and 32.FIGS. 31 and 32 are views (simulations) showing an electric field distribution when a reverse voltage is applied to the front-side electrode and the back-side electrode disposed on the front side and the back side of the semiconductor layer 11. FIG. 31 is an example in which the electric field relaxation region 14 is not included in the outer peripheral region, whereas FIG. 32 is an example in which the electric field relaxation region 14 (high-resistance region) is included in the outer peripheral region.When the electric field relaxation region 14 is not included, as shown in FIG. 31, a high intensity electric field (a region where a distance between the potential lines is narrow) is distributed to the end surface 7 of the semiconductor layer 11. Thus, when a defective region is present in the end surface 7 of the semiconductor layer 11 due to dicing, there is a concern that a leakage current may be generated by generation of electron-hole pairs in the defective region when a reverse voltage is applied.On the other hand, when the electric field relaxation region 14 is included as illustrated in FIG. 32, a high intensity electric field is intercepted by the electric field relaxation region 14 (high resistance region) and the high intensity electric field is prevented from forming on the end surface 7 of the semiconductor layer 11. Thus, even if a defective region is present in the end surface 7 of the semiconductor layer 11 due to dicing, it is possible to prevent a leakage current from flowing in the defective region due to the formation of electron-hole pairs.Although the preferred embodiments of the present invention have been described above, the present invention can be practiced otherwise than as otherwise described above.For example, the above semiconductor device 1 may be integrated into a matrix converter circuit 100 illustrated in FIG. 33 as a bidirectional switch. Specifically, the matrix converter circuit 100 includes a three-phase input section 103, a three-phase output section 104, a main circuit section 105, and a filter circuit 106. The semiconductor device 1 is inserted as a bidirectional switch 101 into each switch section 107 of the main circuit section 105. The bidirectional switch 101 may be configured by a combination of two transistors (semiconductor devices 1) 102A and 102B and two diodes 108A and 108B.In addition, for example, the aforementioned semiconductor device 1 may include a protective film 68 formed at least in the outer peripheral region 12 of the semiconductor layer 11 and with which a region from the peripheral edge portion of the source electrode 4 to the end surface 7 of the semiconductor layer 11 is covered as illustrated in FIG. 34. The terminal of the protective film 68 may not be the end surface 7 of the semiconductor layer 11. For example, polyimide may be used as the protective film 68. With respect to the protective film 68, only a case where it is used in the mode of FIG. 3 has been shown, and of course, the protective film 68 may be used in the modes of FIGS. 7, 8, 10, 12, 14, 15, 17, 18, 19 and 24.Although only a case where the MIS transistor structure is formed on the front side portion of the semiconductor layer has been illustrated in the above-mentioned preferred embodiments, it is also conceivable to form an electric field relaxation region on an element such as a JFET element or a diode element in which the MIS transistor structure is not formed according to a preferred embodiment of the present invention. Moreover, although only a case where a sub-surface electrode is a Schottky contact has been shown, it is conceivable to configure the sub-surface electrode as an ohmic contact.Although only a case where the semiconductor layer 11 is made of SiC has been shown in the above preferred embodiments, the material of the semiconductor layer 11 may be another material called a wide band gap type such as GaN, or the semiconductor layer 11 may be Si. In addition, when the semiconductor device of the preferred embodiments of the present invention is used as a bidirectional switch of a power supply device, it is easily possible to obtain a power supply device in which the reliability of the reverse voltage is improved and in which a power loss in the on state is low.Moreover, design changes can be made that are within the scope of the subject matter recited in the claims.List of reference characters1 Semiconductor device 2 Front side (of the semiconductor layer) 3 Back side (of the semiconductor layer) 4 Source electrode 6 Drain electrode 7 End surface (of the semiconductor layer) 11 Semiconductor layer 12 Outer peripheral region 13 Active region 14 Electric field relaxation region 17 N -- peripheral type region 18 Base substrates 19 Through hole 20 N -- type layer 21 P-type region 22 MIS transistor structure 23 P-type body region 24 N +- type source region 25 Gate insulating film 26 Gate electrode 29 N -- type drift region 33 Surface termination structure 37 Second drain electrode 40 Trench 42 Second relaxation region for electrical field relaxation an electric field 43 First semiconductor layer 44 Second semiconductor layer 45 Conductive material 71 Semiconductor package 73 Semiconductor chip 73 Substrate terminal 74 Resin package

Claims

A semiconductor device (1) comprising: a semiconductor layer (11) of a first conductivity type having a front side (2), a back side (3) opposite to the front side (2), and an end surface (7); a circuit element formed at a front side portion of the semiconductor layer (11); a first electrode (6) connected to the semiconductor layer (11) on the back side (3) of the semiconductor layer (11); an electric field relaxation region (14) reaching the back side (3) from the front side (2) of the semiconductor layer (11) in a peripheral region (12) including an active region (13) in which the circuit element is formed, wherein the electric field relaxation region (14) is either a high resistance region having higher resistance than the semiconductor layer (11) or an impurity region of a second conductivity type; and a surface termination structure (33) formed on a more inner side than the electric field relaxation region (14) in the peripheral region (12) of the semiconductor layer (11), wherein the first electrode (6) is in contact with the electric field relaxation region (14) and forms a Schottky contact with a part of the semiconductor layer (11), and wherein an MIS transistor structure (22) serving as a circuit element is formed on the front side portion of the semiconductor layer (11).The semiconductor device (1) according to claim 1, wherein the semiconductor layer (11) is SiC, and the electric field relaxation region (14) is a high resistance region having a crystal defect concentration of 1×10 14 cm -3 to 1×10 22 cm -3.The semiconductor device (1) according to claim 1, wherein the semiconductor layer (11) is SiC, and the electric field relaxation region (14) is a second conductivity type impurity region having an impurity concentration of 1×10 18 cm -3 to 1×10 22 cm -3.The semiconductor device (1) according to any one of claims 1 to 3, wherein the electric field relaxation region (14) is formed inward away from the end surface (7) of the semiconductor layer (11) such that the electric field relaxation region (14) surrounds the active region (13).The semiconductor device (1) according to claim 4, wherein the semiconductor layer (11) includes a first peripheral impurity region (17) of a first conductivity type between the electric field relaxation region (14) and the end face (7) of the semiconductor layer (11), wherein the first electrode (6) on the back side is in contact with the peripheral impurity region of the semiconductor layer (11), and wherein the semiconductor device (1) further comprises an auxiliary electrode (37) that is in contact with the peripheral impurity region (17) on the front side (2) of the semiconductor layer and that is electrically connected to the first electrode (6).The semiconductor device (1) according to claim 5, wherein the auxiliary electrode (37) bridges a boundary portion between the electric field relaxation region (14) and the peripheral impurity region (17) and is in contact with both the electric field relaxation region (14) and the peripheral impurity region (17).The semiconductor device (1) according to any one of claims 1 to 3, wherein the electric field relaxation region (14) reaches the end surface (7) of the semiconductor layer (11).The semiconductor device (1) according to claim 7, wherein the first electrode is in contact with the electric field relaxation region (14) at the back side (3) of the semiconductor layer (11), the semiconductor device (1) further comprising an auxiliary electrode (37) which is in contact with the electric field relaxation region (14) at the front side (2) of the semiconductor layer (11) and which is electrically connected to the first electrode (6).The semiconductor device (1) according to any one of claims 1 to 8, wherein the peripheral region (12) of the semiconductor layer (11) includes a flat portion planar with the front side (2) of the semiconductor layer (11), and wherein the electric field relaxation region (14) reaches the back side (3) from the front side (2) of the semiconductor layer (11) of the flat portion.The semiconductor device (1) according to any one of claims 1 to 8, further comprising a concave portion (40) formed from the front surface (2) in the peripheral region (12) of the semiconductor layer (11), wherein the electric field relaxation region (14) is formed along an inner surface of the concave portion (40) and has a lower portion exposed at the back surface (3) of the semiconductor layer (11).The semiconductor device (1) according to any one of claims 1 to 10, further comprising a second electric field relaxation region (42) formed at a back surface portion of the semiconductor layer (11) and being either a high resistance region higher in resistance than the semiconductor layer (11) or an impurity region of a second conductivity type.The semiconductor device (1) according to claim 11, wherein the second electric field relaxation region (42) is exposed on the back side of the semiconductor layer (11), and wherein the first electrode (6) is in contact with the second electric field relaxation region (42) on the back side (3) of the semiconductor layer (11).The semiconductor device (1) according to claim 11 or 12, wherein a plurality of second electric field relaxation regions (42) are discretely and matrix-shaped when the semiconductor layer (11) is viewed from the back side (3).The semiconductor device (1) according to claim 11 or 12, wherein a plurality of second electric field relaxation regions (42) are arranged in a stripe shape or the second electric field relaxation region (42) is formed as a lattice pattern when the semiconductor layer (11) is viewed laterally from the back side (3) side.The semiconductor device (1) according to any one of claims 1 to 8, further comprising a second electrode (4) formed on the semiconductor layer (11) and electrically connected to a source or emitter of the MIS transistor structure (22).A semiconductor package, comprising: the semiconductor device (1) according to any one of claims 1 to 15; a lead frame (46) on which the semiconductor device is mounted; and a sealing resin (74) sealing the semiconductor device (1) and at least a part of the lead frame (46).A power source conversion device in which the semiconductor device (1) according to any one of claims 1 to 8 is used as the bidirectional switching device (101).The power source conversion device according to claim 17, wherein the bidirectional switching device (101) is used as a switching circuit of a matrix converter circuit (100) from a polyphase input to a polyphase output.A manufacturing method of a semiconductor device (1) comprising: forming a semiconductor layer (11) of a first conductivity type on a substrate; forming a circuit element on a front side portion of a side opposite to the substrate of the semiconductor layer (11); forming an electric field relaxation region (14) which is either a high resistance region higher in resistance than the semiconductor layer (11) or an impurity region of a second conductivity type to reach a back side (3) on a side opposite to the front side (2) of the semiconductor layer (11) from the front side (2) of the semiconductor layer (11) in a peripheral region (12) surrounding an active region (13) in which the circuit element is formed; forming a surface termination structure (33) formed on a more inner side than the electric field relaxation region (14) in the peripheral region (12) of the semiconductor layer (11); exposing the back side (3) of the semiconductor layer (11) by removing the substrate; and forming a first electrode (6) connected to the semiconductor layer (11) on the back side (3) of the semiconductor layer (11), wherein the first electrode (6) is in contact with the electric field relaxation region (14) and forms a Schottky contact with a part of the semiconductor layer (11), and wherein an MIS transistor structure (22) serving as a circuit element is formed on the front side portion of the semiconductor layer (11).A manufacturing method of a semiconductor device (1) comprising: forming a semiconductor layer (11) of a first conductivity type on a substrate; forming a circuit element on a front side portion of a side opposite to the substrate of the semiconductor layer (11); forming an electric field relaxation region (14), which is a high resistance region having higher resistance than the semiconductor layer (11), to reach a back side (3) on a side opposite to the front side (2) of the semiconductor layer (11) from the front side (2) of the semiconductor layer (11) in a peripheral region (12) surrounding an active region (13) in which the circuit element is formed; exposing the back side (3) of the semiconductor layer (11) by removing the substrate; and forming a first electrode (6) connected to the semiconductor layer (11) on the back surface (3) of the semiconductor layer (11), wherein forming the electric field relaxation region (14) includes forming the high resistance region by radiating a first substance including protons, helium ions, and / or electron beams from a front surface (2) side of the semiconductor layer (11) after forming the semiconductor layer (11).The manufacturing method according to claim 19, wherein the relaxation region (14) is the second conductivity type impurity region, and forming the electric field relaxation region (14) includes forming the second conductivity type impurity region by implanting second conductivity type impurity ions from a front side (2) side of the semiconductor layer (11) after forming the semiconductor layer (11).The manufacturing method according to claim 19, wherein the relaxation region (14) is the second conductivity type impurity region, and forming the semiconductor layer (11) includes forming the semiconductor layer (11) by a multistage epitaxial method in which a first conductivity type layer (20) is epitaxially grown a plurality of times repeatedly, and wherein forming the electric field relaxation region (14) includes forming a second conductivity type region by implanting second conductivity type impurity ions into a predetermined part of the first conductivity type layers (20) when each of the first conductivity type layers (20) is grown, and forming the second conductivity type impurity region is performed by sequentially stacking the second conductivity type regions together in conjunction with growth of the first conductivity type layer (20).A manufacturing method of a semiconductor device (1) comprising: forming a semiconductor layer (11) of a first conductivity type on a substrate; forming a circuit element on a front side portion of a side opposite to the substrate of the semiconductor layer (11); forming an electric field relaxation region (14), which is a high resistance region having higher resistance than the semiconductor layer (11), to reach a back side (3) on a side opposite to the front side (2) of the semiconductor layer (11) from the front side (2) of the semiconductor layer (11) in a peripheral region (12) surrounding an active region (13) in which the circuit element is formed; exposing the back side (3) of the semiconductor layer (11) by removing the substrate; and forming a first electrode (6), which is connected to the semiconductor layer (11) on the back surface (3) of the semiconductor layer (11), wherein forming the semiconductor layer (11) includes forming the semiconductor layer (11) according to a multistage epitaxial method in which a first conductivity type layer (20) is epitaxially grown a plurality of times repeatedly, and wherein forming the electric field relaxation region (14) includes forming a first substance region by radiating a first substance including protons, helium ions, and / or electron beams onto a predetermined part of the first conductivity type layer (20) when each of the first conductivity type layers (20) is grown, and forming the high resistance region is performed by sequentially stacking the first substance regions together in conjunction with growth of the first conductivity type layer (20).The manufacturing method according to claim 19, wherein the relaxation region (14) is the second conductivity type impurity region, and forming the electric field relaxation region (14) includes: forming a through hole (19) that reaches the substrate from the front side (2) of the semiconductor layer (11) after the semiconductor layer (11) is formed; and forming the second conductivity type impurity region by backfilling the through hole (19) with a second conductivity type semiconductor layer by epitaxial growth.The manufacturing method according to claim 19, wherein the relaxation region (14) is the second conductivity type impurity region, and forming the electric field relaxation region (14) includes: forming a concave portion (40) from the front side of the semiconductor layer (11) after forming the semiconductor layer (11); and forming the second conductivity type impurity region extending along an inner surface of the concave portion (40) and having the lower portion reaching the substrate by implanting second conductivity type impurity ions into the inner surface of the concave portion (40).A manufacturing method of a semiconductor device (1) comprising: forming a semiconductor layer (11) of a first conductivity type on a substrate; forming a circuit element on a front side portion of a side opposite to the substrate of the semiconductor layer (11); forming an electric field relaxation region (14), which is a high resistance region having higher resistance than the semiconductor layer (11), to reach a back side (3) on a side opposite to the front side (2) of the semiconductor layer (11) from the front side (2) of the semiconductor layer (11) in a peripheral region (12) surrounding an active region (13) in which the circuit element is formed; exposing the back side (3) of the semiconductor layer (11) by removing the substrate; and forming a first electrode (6) connected to the semiconductor layer (11) on the back surface (3) of the semiconductor layer (11), wherein forming the electric field relaxation region (14) includes: forming a concave portion (40) from the front surface (2) of the semiconductor layer (11) after forming the semiconductor layer (11); and forming the high resistance region extending along an inner surface of the concave portion (40) and having the lower portion thereof reaching the substrate by radiating a first substance including protons, helium ions, and / or electron beams onto the inner surface of the concave portion (40).The manufacturing method according to claim 25 or 26, further comprising filling the concave portion (40) with a conductive material (45).A manufacturing method for a semiconductor device (1) comprising: forming a semiconductor layer (11) of a first conductivity type on a substrate; forming a circuit element on a front side portion of a side opposite to the substrate of the semiconductor layer (11); forming an electric field relaxation region (14) which is either a high resistance region higher in resistance than the semiconductor layer (11) or an impurity region of a second conductivity type to reach a back side (3) on a side opposite to the front side (2) of the semiconductor layer (11) from the front side (2) of the semiconductor layer (11) in a peripheral region (12) surrounding an active region (13) in which the circuit element is formed; exposing the back side (3) of the semiconductor layer (11) by removing the substrate; and forming a first electrode (6) connected to the semiconductor layer (11) on the back side (3) of the semiconductor layer (11), wherein forming the semiconductor layer (21) includes forming a first semiconductor layer (43) on the substrate and forming a second semiconductor layer (44) on the first semiconductor layer (11), wherein the manufacturing method further comprises forming a second electric field relaxation region (42) on the first semiconductor layer (43) before forming the second semiconductor layer (44), wherein the second relaxation region (42) is either a high resistance region higher than the semiconductor layer (11) or an impurity region of the second conductivity type.The manufacturing method according to claim 28, wherein the removing the substrate includes removing a part of the semiconductor layer in addition to the removing the substrate until the second electric field relaxation region (42) is exposed from the back surface (3) of the semiconductor layer (11).The semiconductor device (1) according to claim 1, wherein the end surface (7) of the semiconductor layer (11) is formed such that the end surface (7) includes a part facing a side of the back surface (3) in a thickness direction of the semiconductor layer (11), wherein the electric field relaxation region (14) is formed at least along the end surface (7).The semiconductor device (1) according to claim 30, wherein the semiconductor layer (11) has an upper end face end (48) which is an end edge of the end face (7) on a side of the front side (2) and a lower end face end (49) which is an end edge of the end face (7) on a side of the back side (3) and which is disposed at a position more inside than the upper end face end (48) in a cross-sectional view, and wherein a phantom linear line segment (50) which connects the upper end face end (48) and the lower end face end (49) to each other is inclined at an angle greater than 90° with respect to the back side (3) of the semiconductor layer (11).The semiconductor device (1) according to claim 30 or 31, wherein the electric field relaxation region (14) is formed along at least a part of the end face (7) in a cross-sectional view having a substantially constant width.The manufacturing method according to claim 19, further comprising: forming a groove (62) surrounded by an end face (7) facing a side of the back side (3) in a thickness direction of the semiconductor layer (11) by selectively etching the semiconductor layer (11) from the side of the back side (3); forming an electric field relaxation region (14) along the end face (7) either by implanting impurity ions of the second conductivity type or by radiating a first substance including protons, helium ions and / or electron beams onto the end face (7) of the groove (62).The manufacturing method according to claim 33, wherein forming the groove (62) includes forming the groove (62) by performing etchings from the back surface (3) to a center in the thickness direction of the semiconductor layer (11), the manufacturing method including cutting the semiconductor layer (11) along a cut line running along the groove (62) after forming the first electrode (6).

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