Semiconductor device, image pickup device and method for manufacturing a semiconductor device

Abstract

Semiconductor device (1, 2) comprising: a multilayer wiring layer (300) in which insulation layers (100) and diffusion prevention layers (200) are alternately laminated and a wiring layer (300) is provided inside; a through-hole (510) provided to penetrate at least one or more insulation layers (100) from a surface of the multilayer wiring layer (300) and having an inner side covered with a protective side wall (520); a gap (530) provided in at least one or more insulation layers (100) immediately below the through-hole (510); and a pair of substrates (600, 620) sandwiching the multilayer wiring layer (300) in a lamination direction, wherein one substrate (620) is bonded to the multilayer wiring layer (300).

Description

Technical FieldThe present invention relates to a semiconductor device, an image pickup device, and a method of manufacturing a semiconductor device.Prior ArtIn recent years, with miniaturization of semiconductor devices, signal delay due to wiring has attracted attention as a factor that reduces an operation speed of a semiconductor device. In particular, because an area of section of the wiring decreases due to miniaturization of the semiconductor device and a wiring resistance increases, a delay increases in proportion to a product between the wiring resistance and the wiring capacitance (also referred to as RC delay).In order to reduce such signal delay due to wiring, forming an interlayer film between wirings to have a lower dielectric constant has been considered. However, no interlayer film material realizing a sufficiently low dielectric constant has been found yet.Accordingly, reducing the dielectric constant between wirings by removing the material between the wirings and providing a hollow layer (also referred to as an air gap) having a specific dielectric constant 1 between the wirings has been further considered.For example, Patent Literature 1 listed below discloses providing a structure that does not damage the wirings when removing insulating layers between wirings to form an air gap structure.Patent Literature 2, for example, discloses an integrated electronic circuit including insulating layers stacked on top of each other and metal elements distributed within these insulating layers.Patent Literature 3, for example, discloses a method of manufacturing a semiconductor device.Patent Literature 4, for example, discloses a method of manufacturing a semiconductor device having an air gap multi-layered connection wiring structure.Patent Literature 5, for example, discloses a method of providing a first layer of a semiconductor structure having at least one air gap between conductive lines formed in the first layer.Patent Literature 6, for example, discloses a method of manufacturing an integrated circuit.Patent Literature 7, for example, discloses a method of manufacturing a microelectronic chip including a passive device, for example, an inductor, overlying an air gap.List of the cited patentsPatent Literature 1: JP 2006-19401 APatent Literature 2: US 2008 / 0 179 750 A1Patent Literature 3: US 2010 / 0 055 893 A1Patent Literature 4: US 2009 / 0 065 946 A1Patent Literature 5: US 2012 / 0 126 413 A1Patent Literature 6: US 2005 / 0 167 841 A1Patent Literature 7: US 2008 / 0 173 976 A1Summary of the InventionTechnical ProblemHowever, since a thin film having low mechanical strength protrudes into a space in which the air gap is formed according to the technology disclosed in Patent Literature 1, there is a possibility that the protruding thin film collapses. In addition, because a mechanical strength of an entire semiconductor device is deteriorated due to the air gap, if intervals between the wirings are wide according to the technology disclosed in Patent Literature 1, there is a possibility that the reliability of the semiconductor device is deteriorated.Accordingly, the present disclosure proposes a novel and improved semiconductor device, an image pickup device, and a method of manufacturing the semiconductor device capable of reducing a wiring capacitance by using gaps and maintaining a mechanical strength and reliability.Solution of the ProblemAccording to a first aspect, the present invention provides a semiconductor device according to independent claim 1. According to a second aspect, the present invention provides an image pickup apparatus according to independent claim 11. According to a third aspect, the present invention provides a method of manufacturing a semiconductor device according to independent claim 14. Further aspects of the invention are set out in the dependent claims, the drawings and the following description.According to the present disclosure, there is provided a semiconductor device including: a multilayer wiring layer in which insulation layers and diffusion preventing layers are alternately laminated and a wiring layer is provided inside; a through hole provided so as to penetrate at least one or more insulation layers from a surface of the multilayer wiring layer and having an inner side covered with a protection side wall; and a gap provided in at least one or more insulation layers immediately below the through hole.In addition, according to the present disclosure, there is provided an image pickup device including: a multilayer wiring layer in which insulation layers and diffusion preventing layers are alternately laminated and a wiring layer is provided inside; a through hole provided so as to penetrate at least one or more insulation layers from a surface of the multilayer wiring layer and having an inner side covered with a protective side wall; and a gap provided in at least one or more insulation layers immediately below the through hole.Furthermore, according to the present disclosure, there is provided a method of manufacturing a semiconductor device, including: a step of forming a multilayer wiring layer in which insulation layers and diffusion preventing layers are alternately laminated and a wiring layer is provided inside; a step of forming a through hole such that the through hole passes through at least one or more insulation layers from a surface of the multilayer wiring layer; a step of forming a protective side wall inside the through hole; and a step of forming a gap by etching at least one or more insulation layers immediately below the through hole.According to the present disclosure, it is possible to form gaps in insulation layers that are the second and subsequent layers from a surface of the multilayer wiring layer that constitutes a semiconductor device. Accordingly, because it is possible to provide a cavity having a specific dielectric constant 1 between wirings while maintaining the mechanical strength of the semiconductor layer, it is possible to reduce a wiring capacity of the semiconductor device.Advantageous Effects of the InventionAccording to the present disclosure, it is possible to reduce wiring capacitance through the gaps and maintain mechanical strength and reliability of the semiconductor device.Note that the above-described effects are not necessarily limitative. With or instead of the above effect(s), any of the effects described in this specification or other effects that can be obtained from this specification can be obtained.Brief Description of the Drawings[FIG. 1 ] FIG. 1 is a sectional view of a semiconductor device according to a first embodiment of the present disclosure in a lamination direction.[FIG. 2 ] FIG. 2 is a sectional view illustrating a configuration in which a protection layer is formed in a surface within a gap in the semiconductor device illustrated in FIG. 1.[FIG. 3] FIG. 3 is a planar diagram of the semiconductor device according to the embodiment in a plan view in the lamination direction.[FIG. 4] FIG. 4 is a sectional view illustrating a step of a method of manufacturing the semiconductor device according to the embodiment.[FIG. 5 ] FIG. 5 is a sectional view illustrating a step of a method of manufacturing the semiconductor device according to the embodiment.[FIG. 6 ] FIG. 6 is a sectional view illustrating a step of a method of manufacturing the semiconductor device according to the embodiment.[FIG. 7 ] FIG. 7 is a sectional view illustrating a step of a method of manufacturing the semiconductor device according to the embodiment.[FIG. 8] FIG. 8 is a sectional view illustrating a step of a method of manufacturing the semiconductor device according to the embodiment.[FIG. 9] FIG. 9 is a sectional view illustrating a step of a method of manufacturing the semiconductor device according to the embodiment.[FIG. 10] FIG. 10 is a sectional view illustrating a step of a method of manufacturing the semiconductor device according to the embodiment.[FIG. 11 ] FIG. 11 is a sectional view illustrating a semiconductor device according to a first modification example in a lamination direction.[FIG. 12] FIG. 12 is a sectional view illustrating a semiconductor device according to a second modification example in a lamination direction.[FIG. 13 ] FIG. 13 is a sectional view illustrating a semiconductor device according to a third modification example in a lamination direction.[FIG. 14] FIG. 14 is a sectional view illustrating a semiconductor device according to a second embodiment of the present disclosure in a lamination direction.[FIG. 15] FIG. 15 is a sectional view illustrating a step of a method of manufacturing the semiconductor device according to the embodiment.[FIG. 16] FIG. 16 is a sectional view illustrating a step of a method of manufacturing the semiconductor device according to the embodiment.[FIG. 17] FIG. 17 is a sectional view illustrating a step of a method of manufacturing the semiconductor device according to the embodiment.[FIG. 18] FIG. 18 is a sectional view illustrating a step of a method of manufacturing the semiconductor device according to the embodiment.[FIG. 19] FIG. 19 is a sectional view illustrating a step of a method of manufacturing the semiconductor device according to the embodiment.[FIG. 20] FIG. 20 is a sectional view illustrating a step of a method of manufacturing the semiconductor device according to the embodiment.[FIG. 21] FIG. 21 is a sectional view illustrating a step of a method of manufacturing the semiconductor device according to the embodiment.DESCRIPTION OF THE EMBODIMENTSHereinafter, (one) preferred embodiment(s) of the present disclosure will be described in detail with reference to the attached drawings. Note that, in this specification and the appended drawings, structural elements having substantially the same function and structure are denoted by the same reference numerals, and repeated explanation of these structural elements is omitted.Note that the description is given in the following order.1 First Embodiment 1.1 Sectional structure of Semiconductor Device 1.2 Planar structure of Semiconductor Device 1.3 Method of Manufacturing Semiconductor Device 1.4 Modification Examples 2 Second Embodiment 2.1 Sectional structure of Semiconductor Device 2.2 Method of Manufacturing Semiconductor Device 3 Conclusion<1 First Embodiment>(1.1. Sectional Structure of Semiconductor Device)First, a sectional structure of a semiconductor device according to a first embodiment of the present disclosure will be described with reference to FIG. 1. FIG. 1 is a sectional view of a semiconductor device 1 according to the embodiment in a lamination direction. Note that FIG. 1 illustrates a part of the cut surface of the semiconductor device 1 according to the embodiment, and it goes without saying that the semiconductor device 1 also extends in an in-plane direction in a range not illustrated in the drawingAs illustrated in FIG. 1, the semiconductor device 1 includes a substrate 600 and a multilayer wiring layer in which first to fifth insulation layers 110, 120, 130, 140, and 150 and first to fifth diffusion prevention layers 210, 220, 230, 240, and 250 are alternately laminated. In addition, the substrate 600 is provided with a semiconductor element (not illustrated), and the second to fifth insulating layers 120, 130, 140, and 150 are provided with first to fourth wiring layers 310, 320, 330, and 340, respectively. Note that the semiconductor element is caused to have continuity with the first wiring layer 310 via a contact plug 610, and the first to fourth wiring layers 310, 320, 330, and 340 are caused to have continuity with each other via first to third through-vias 410, 420, and 430.In the following description, the first to fifth insulation layers 110, 120, 130, 140, and 150 are also collectively referred to as insulation layers 100, while the first to fifth diffusion prevention layers 210, 220, 230, 240, and 250 are also collectively referred to as diffusion prevention layers 200. In addition, the first to fourth wiring layers 310, 320, 330, and 340 are also collectively referred to as wiring layers 300, while the first to third through vias 410, 420, and 430 are also collectively referred to as through vias 400.That is, the semiconductor device 1 includes the multilayer wiring layer in which the insulation layers 100 including the wiring layers 300 and the through vias 400 and the diffusion preventing layers 200 are alternately laminated.Note that, although FIG. 1 illustrates that the semiconductor device 1 has a five-layer structure configuration in which the first to fifth insulation layers 110, 120, 130, 140, and 150 and the first to fifth diffusion prevention layers 210, 220, 230, 240, and 250 are alternately laminated, the technology according to the present disclosure is not limited to such an illustrative example. For example, the semiconductor device 1 may include a multilayer wiring layer including three or four layers, or may include a multilayer wiring layer including six or more layers.The insulating layers 100 are main layer forming materials that electrically insulate the wiring layers 300 from each other and form the semiconductor device 1. The insulation layers 100 include an insulation material that can be relatively easily etched (more specifically, can be etched more easily than the diffusion layers 200 described later), and may include an insulation material such as SiO x, for example.The diffusion preventing layers 200 are provided so as to sandwich the respective insulating layers 100, suppress diffusion of metal atoms constituting the wiring layers 300, and serve as stoppers when parts in the upper layers are processed. Specifically, the diffusion preventing layers 200 include an insulating material having a higher etch resistance (for example, an etch resistance with respect to fluorine compounds) than the insulating layers 100, and may include an insulating material such as, for example, SiN x, SiCN, SiON, or SiC.The wiring layer 300 provides currents or voltages between the respective elements provided in the semiconductor device 1. The wiring layers 300 include a conductive metal material, and may include, for example, copper (Cu), tungsten (W), aluminum (Al), or an alloy containing these metals. In addition, barrier metal layers using a metal having a high barrier property may be formed on the surfaces of the wiring layers 300, although they are not illustrated in the drawings. The barrier metal layer may include a metal such as, for example, tantalum (Ta), titanium (Ti), ruthenium (Ru), cobalt (Co), or manganese (Mn), or nitrides or oxides of these metals.The through vias 400 electrically connect the wiring layers 300 provided in different insulation layers 100. Specifically, the first through via 410 connects the first wiring layer 310 to the second wiring layer 320, the second through via 420 connects the second wiring layer 320 to the third wiring layer 330, and the third through via 430 connects the third wiring layer 330 to the fourth wiring layer 340. The through vias 400 include a conductive metal material similar to the wiring layers 300 and may include, for example, copper (Cu), tungsten (W), aluminum (Al), or an alloy including these materials. In addition, barrier metal layers may be formed on the surfaces of the through vias 400 similar to the wiring layers 300.The substrate 600 is a substrate including various semiconductors, and may be a substrate including polycrystalline, monocrystalline, or amorphous silicon (Si). In addition, the substrate 600 is provided with a semiconductor element that realizes functions of the semiconductor device 1. Since the semiconductor element is provided on the substrate 600, a logic circuit or the like including, for example, a storage element, a color sensor, or a transistor can be exemplified.The contact plug 610 electrically connects an electrode or a wiring of the semiconductor element or the like provided on the substrate 600 to the first wiring layer 310. The contact plug 610 may include a metal material similar to that of the through vias 400, and may include, for example, copper (Cu), tungsten (W), aluminum (Al), or an alloy including these metals.In addition, the semiconductor device 1 is provided with a through hole 510 that penetrates the five diffusion layers 250, the fifth insulation layer 150, and the fourth diffusion preventing layer 240 and has an inner side covered with a protection side wall 520 as illustrated in FIG. 1. The through hole 510 causes a gap 530 provided at the third insulating layer 130 and the fourth insulating layer 140 to communicate with an external space.Note that a sealing layer that blocks an opening of the through hole 510 may be provided on the fifth diffusion preventing layer 250, although not illustrated in FIG. 1. The sealing layer includes any insulation material such as, for example, SiO x, SiN x, SiCN, SiON, or SiC, and prevents moisture and the like from entering the through hole 510 or the gap 530.The through hole 510 is provided to penetrate the insulation layer 100 provided on any surface of the semiconductor device 1 and the diffusion preventing layers 200 sandwiching the insulation layer 100. Specifically, the through hole 510 is provided so as to penetrate through the fifth insulation layer 150, and the fourth diffusion preventing layer 240 and the fifth diffusion preventing layer 250 sandwiching the fifth insulation layer 150 therebetween. The shape of the opening of the through hole 510 may be, for example, a substantially quadrangular shape having a side of at least 50 nm to 300 nm, or may be a circular shape having a diameter of 50 nm to 300 nm.The protection side wall 520 is provided inside the through hole 510 to protect a side surface of the fifth insulation layer 150 exposed due to the through hole 510. The protection sidewall 520 includes an insulating material having a higher etch resistance (for example, an etch resistance with respect to fluorine compounds) than, for example, those of the insulating layers 100, and may include an insulating material such as, for example, SiN x, SiCN, SiON, SiOC, or SiC.The protection side wall 520 functions to protect the fifth insulation layer 150 so that the fifth insulation layer 150 is not etched when the gap 530 is formed. Specifically, the gap 530 is formed by introducing an etching solution via the through hole 510 and performing wet etching on the third insulating layer 130 and the fourth insulating layer 140. At this time, the protective side wall 520 prevents the fifth insulation layer 150 from being wet-etched by the etching solution. Therefore, it is possible to form the gap 530 in the insulation layer 100 provided inside the second and subsequent layers in the multilayer wiring layer in the semiconductor device 1 by using the through hole 510 with the inside covered with the protection side wall 520. Note that the protection side wall 520 may be, for example, a thin film of 5 nm to 30 nm.The gap 530 is provided in the second and subsequent insulation layers 100 in the multilayer wiring layer (i.e., in the inside of the multilayer wiring layer) of the semiconductor device 1, and spaces in the wiring layers 300 are formed as voids having a specific dielectric constant of 1. In this way, the gap 530 can reduce a wiring capacitance in the wiring layers 300. Specifically, the gap 530 is provided at the third insulating layer 130 and the fourth insulating layer 140, and can reduce the wiring capacitance by providing the space between the third wiring layer 330 and the second wiring layer 320 as a cavity.Note that the gap 530 is not provided in the insulation layer 100 on the surface of the multilayer wiring layer in the semiconductor device 1. Specifically, the gap 530 is not provided in the first insulation layer 110 and the fifth insulation layer 150 on the surface of the multilayer wiring layer. In this way, it is possible to maintain an entire mechanical strength even though the gap 530 is formed in the semiconductor device 1.The gap 530 may be formed by introducing an etching solution via the through hole 510 and performing etching on the third insulating layer 130 and the fourth insulating layer 140 by using a wet etching method.At this time, a region where the gap 530 is formed is limited to a region surrounded by the diffusion preventing layers 200 in the lamination direction of the multilayer wiring layer. This is because etching through the diffusion preventing layers 200 is difficult to advance due to higher etching resistance thereof than those of the insulating layers 100. Therefore, if sufficient etching is performed, the gap 530 causes the second diffusion preventing layer 220 and the fourth diffusion preventing layer 240 provided above and below the third insulating layer 130 and the fourth insulating layer 140 to be exposed.In addition, the region where the gap 530 is formed is controlled by a length of time during which etching is performed in the in-plane direction of the multilayer wiring layer. That is, the gap 530 is formed in a region isotropically extending from a part immediately below the through hole 510 into which the etching solution has been introduced, while the width of the region is controlled by an etching time.Note that the through vias 400 or the wiring layers 300 are not etched under conditions where the insulation layers 100 are etched. Therefore, if the through vias 400 or the wiring layers 300 are present in the region where the gap 530 is formed, the through vias 400 or the wiring layers 300 remain directly within the gap 530. In addition, if the insulation layers 100 are spatially divided by the through vias 400 or the wiring layers 300, the etching solution does not enter an opposite-side space divided by the through vias 400 or the wiring layers 300. In this case, the region where the gap 530 is formed is limited by the through vias 400 or the wiring layers 300.If the gap 530 is provided in a plurality of insulation layers 100, a part of the diffusion preventing layers 200 between the plurality of insulation layers 100 is removed before forming an opening. Specifically, the gap 530 is provided in the third insulating layer 130 and the fourth insulating layer 140, and a part of the third diffusion preventing layer 230 in the vicinity of the through hole 510 is removed before forming an opening. In this way, because the etching solution can spread from the fourth insulating layer 140 to the third insulating layer 130 when the etching for forming the gap 530 is performed, it is possible to form the gap 530 over multiple layers, namely, the third insulating layer 130 and the fourth insulating layer 140.In addition, at this time, an opening is formed in the diffusion preventing layers 200, so that a region protruding to the gap 530 and not formed above the wiring layer 300 is not formed. In this way, it is possible to prevent the diffusion preventing layers 200 protruding into the gap 530 from collapsing after the gap 530 is formed.Note that, although FIG. 1 illustrates a case where only one through hole 510 is formed, the technology according to the present disclosure is not limited to the aforementioned illustrative example. For example, a plurality of through holes 510 may be formed. In such a case, the plurality of through holes 510 may form the same gap 530, or may each form a separate gap 530.In addition, the protective layer 540 may be formed on the surface exposed by the gap 530, as illustrated in FIG. 2. FIG. 2 is a sectional view illustrating a configuration in which the protection layer 540 is formed on the inner surface of the gap 530 in the semiconductor device 1 illustrated in FIG. 1.As illustrated in FIG. 2, the protection layer 540 may be formed on each of the surfaces of the insulation layers 100, the diffusion preventing layers 200, the wiring layers 300, and the through vias 400 exposed through the gap 530.The protection layer 540 includes, for example, any insulation material, and may include an insulation material such as, for example, SiO x, SiN x, SiCN, SiON, SiOC, or SiC. In addition, the film thickness of the protective layer 540 may be, for example, 2 nm to 50 nm. The protection layer 540 may improve the reliability of the wirings by preventing electromigration or time-dependent dielectric breakdown (TDDB) in the wiring layers 300 and the through vias 400. Such a protective layer 540 may be formed by introducing a raw material gas into the gap 530 via the through hole 510, and performing, for example, an atomic layer deposition (ALD) method.According to the semiconductor device 1 described above, it is possible to form a cavity between the wiring layers 300 through the gap 530, thereby reducing the wiring capacitance. Therefore, it is possible to realize high operation speed and low power consumption by suppressing delay in wirings according to the semiconductor device 1.In addition, because the gap 530 is not provided in the insulation layers 100 (i.e., the first insulation layer 110 and the fifth insulation layer 150) provided on the surface of the multilayer wiring layer in the semiconductor device 1, it is possible to maintain a mechanical strength of the entire semiconductor device 1. Further, because the diffusion preventing layers 200 protruding into the gap 530 are not formed in the semiconductor device 1, it is possible to prevent the diffusion preventing layers 200 from collapsing with low mechanical strength.(1.2. Planar Arrangement of Semiconductor Device)Next, an example of planar arrangement of the respective configurations in the semiconductor device 1 according to the embodiment will be described with reference to FIG. 3. FIG. 3 is a planar diagram illustrating the semiconductor device 1 according to the embodiment in a plan view in the lamination direction.Note that only the planar arrangement of the second to fourth wiring layers 320, 330, and 340, the through hole 510, and an opening 231 formed in the third diffusion preventing layer 230 is illustrated, and illustration of the other configurations is omitted. In addition, the planar arrangement illustrated in FIG. 3 is only an example, and the planar arrangement of the respective configurations of the semiconductor device 1 according to the embodiment is not limited thereto.Because the second to fourth wiring layers 320, 330, and 340 are formed in different insulation layers 100, respectively, as illustrated in FIG. 3, partial regions thereof are formed in overlapping fashions, respectively. In addition, the first through via 410 and the second through via 420 may be formed, for example, in the partial regions where the second to fourth wiring layers 320, 330, and 340 overlap each other.The through hole 510 is formed in a region where the through hole 510 does not overlap with the third wiring layer 330 and the fourth wiring layer 340, so that the third wiring layer 330 and the fourth wiring layer 340 are not disturbed. The shape of the opening of the through hole 510 may be, for example, a substantially quadrangular shape having a side of at least 50 nm to 300 nm. In addition, one through hole 510 may be provided for one gap 530, or a plurality of through holes 510 may be provided for one gap 530. Further, the through hole 510 may be provided in an area for which it is desirable to reduce the wiring capacitance.The gap 530 is formed in a region where the second to fourth wiring layers 320, 330, and 340 are not formed, although not illustrated in the drawing.The opening 231 formed in the third diffusion preventing layer 230 is formed in a region that prevents the region in which the second wiring layer 320 is formed from being formed. This is to prevent the second wiring layer 320 from collapsing by forming the opening 231 because the third diffusion preventing layer 230 is formed on the second wiring layer 320. In addition, the opening 231 may be formed in a region including a region in which the through hole 510 is formed, or may be formed in a region not including the region in which the through hole 510 is formed. Note that the shape of the opening 231 formed in the third diffusion preventing layer 230 may be an arbitrary polygonal shape having a side of 50 nm to 500 nm.(1.3. Method of Manufacturing Semiconductor Device)Next, a method of manufacturing the semiconductor device 1 according to the embodiment will be described with reference to FIGS. 4 to 10. FIGS. 4 to 10 are sectional views illustrating steps of the method for manufacturing the semiconductor device 1 according to the embodiment.First, the first insulation layer 110, the first diffusion preventing layer 210, the second insulation layer 120, the second diffusion preventing layer 220, the third insulation layer 130, and the third diffusion preventing layer 230 are sequentially laminated on the substrate 600 provided with the semiconductor element and the like by a CVD method, as illustrated in FIG. 4. In addition, the contact plug 610, the first wiring layer 310, the second wiring layer 320, and the first through via 410 are formed in each of the insulation layers 100.Specifically, the first insulation layer 110 is formed on the substrate 600 including silicon (Si) or the like first. Next, the first wiring layer 310 may be formed by using a damascene method in which the first diffusion preventing layer 210 and the second insulating layer 120 are formed on the first insulating layer 110, the first diffusion preventing layer 210 and the second insulating layer 120 are then removed in a predetermined region by etching, and the etched part is re-buried with copper (Cu) or the like. In addition, the second wiring layer 320 and the first through via 410 may be formed by a similar method.Note that the first to third insulation layers 110, 120, and 130 may include SiO x or the like, which can be easily etched with hydrofluoric acid, and the first to third diffusion preventing layers 210, 220, and 230 may include SiC or the like having high etching resistance with respect to hydrofluoric acid.Next, a part of the third diffusion preventing layer 230 is removed using a photolithography method as illustrated in FIG. 5. At this time, the region from which the third diffusion preventing layer 230 has been removed functions as an opening for introducing the etching solution into the second insulating layer 120 in a step of etching the second insulating layer 120 and the third insulating layer 130 in a later stage.Next, the fourth insulation layer 140, the fourth diffusion preventing layer 240, the fifth insulation layer 150, and the fifth diffusion preventing layer 250 are sequentially laminated on the third diffusion preventing layer 230 by a CVD method, as illustrated in FIG. 6. In addition, the third wiring layer 330, the fourth wiring layer 340, the second through via 420, and the third through via 430 are formed on each of the insulation layers 100.Specifically, it is possible to form the third wiring layer 330 by using the damascene method in which the fourth insulation layer 140 is formed on the third diffusion preventing layer 230, the fourth insulation layer 140 in a predetermined region is then removed by etching, and the etched part is buried with copper (Cu) or the like. In addition, it is possible to form the fourth wiring layer 340, the second through via 420, and the third through via 430 by a similar method. Note that the fourth and fifth insulation layers 140 and 150 may include SiO x or the like, which can be easily etched with hydrofluoric acid, and the fourth and fifth diffusion preventing layers 240 and 250 may include SiC or the like having high etching resistance with respect to hydrofluoric acid.Next, the through hole 510 is formed by forming a barrier layer 511 on the fifth diffusion preventing layer 250 and removing the fifth insulation layer 150, the fourth diffusion preventing layer 240, and the fifth diffusion preventing layer 250 in a partial region by using etching or the like, as illustrated in FIG. 7. The barrier layer 511 functions to protect the fifth diffusion preventing layer 250, and may include, for example, SiO 2 of about 100 nm. In addition, the region where the through hole 510 is formed is, for example, a region where the third wiring layer 330 and the fourth wiring layer 340 are not formed, and the shape of the opening of the through hole 510 may be a square shape of 50 nm to 300 nm. It is noted that a plurality of through holes 510 may be provided.Next, a protective film 521 is formed on the barrier layer 511 and inside the through hole 510 by using an ALD method, as illustrated in FIG. 8. The protective film 521 may be formed to have a film thickness of 5 nm to 30 nm with SiC or the like having high etching resistance with respect to hydrofluoric acid, for example. Here, because the protective film 521 is formed by using the ALD method, the protective film 521 is uniformly (conformally) formed on the barrier layer 511 and inside the through hole 510.Next, the protective film 521 is removed while causing the protective side wall 520 to remain within the through hole 510 by etching back the entire surface of the protective film 521, thereby causing the barrier layer 511 and the fourth insulation layer 140 to be exposed, as illustrated in FIG. 9. Such etching back of the entire surface can be realized by performing etching with significantly high perpendicular anisotropy. At this time, it is possible to prevent the fifth diffusion preventing layer 250 from being damaged by etching back the entire surface because the barrier layer 511 is provided on the fifth diffusion preventing layer 250.Next, the gap 530 is formed by introducing a dilute hydrofluoric acid into the second insulating layer 120 and the third insulating layer 130 via the through hole 510, and performing wet etching thereon, as illustrated in FIG. 10. Note that the barrier layer 511 is removed by the wet etching using the diluted hydrofluoric acid at this time.At this time, since the protection side wall 520 and the second to fourth diffusion preventing layers 220, 230, and 240 include SiC or the like having high etching resistance with respect to hydrofluoric acid, the etching hardly penetrates through the protection side wall 520 and the second to fourth diffusion preventing layers 220, 230, and 240. In addition, the etching hardly penetrates through the second wiring layer 320, the third wiring layer 330, the first through via 410, and the second through via 420, because the second wiring layer 320, the third wiring layer 330, the first through via 410, and the second through via 420 include a metal material such as copper (Cu) and have high resistance to hydrofluoric acid. Therefore, the region where the gap 530 is formed is controlled in the lamination direction of the semiconductor device 1 depending on a region sandwiched between the second diffusion preventing layer 220 and the fourth diffusion preventing layer 240, and is controlled in the in-plane direction of the semiconductor device 1 depending on a time during which wet etching is performed.In this way, it is possible to etch only the second insulating layer 120 and the third insulating layer 130 by the wet etching using the dilute hydrofluoric acid, thereby forming the gap 530. Note that the third diffusion preventing layer 230 is formed in a region having an end corresponding to a region where the second wiring layer 320 is formed and does not protrude into the gap 530, it is possible to prevent the third diffusion preventing layer 230 from collapsing.It is possible to manufacture the semiconductor device 1 according to the embodiment by the aforementioned process. Note that a sealing layer that includes an insulating material and blocks the opening of the through hole 510 may be provided on the fifth diffusion preventing layer 250 to prevent moisture and the like from entering the gap 530.In the aforementioned manufacturing method, hydrofluoric acid is used for etching, SiO x is used as a material that can be easily etched with respect to hydrofluoric acid for the insulation layers 100, and SiC is used as a material having high etching resistance with respect to hydrofluoric acid for the diffusion preventing layer 200. However, the technology according to the present disclosure is not limited to the aforementioned illustrative example. An arbitrary combination may be employed as a combination of materials used for the insulation layers 100 and the diffusion preventing layer 200 as long as it is possible to guarantee a sufficient etching selection ratio. In addition, it is possible to appropriately select the etching solution used for the etching according to the insulation layers 100 and the diffusion preventing layers 200.(1.4. Modification Examples)Here, modification examples of the semiconductor device 1 according to the embodiment will be described with reference to FIGS. 11 to 13. FIG. 11 is a sectional view illustrating a semiconductor device 1A according to a first modification example of the embodiment along the lamination direction, FIG. 12 is a sectional view illustrating a semiconductor device 1B according to a second modification example of the embodiment along the lamination direction, and FIG. 13 is a sectional view illustrating a semiconductor device 1C according to a first modification example of the embodiment along the lamination direction. Note that, of course, FIGS. 11 to 13 illustrate parts of the cut surfaces of the semiconductor devices, and the semiconductor devices also extend in the in-plane direction in regions not illustrated in the drawings.(First Modification Example)First, the semiconductor device 1A according to the first modification example of the embodiment will be described with reference to FIG. 11.As illustrated in FIG. 11, the semiconductor device 1A includes a multilayer wiring layer in which six insulation layers 100 and six diffusion preventing layers 200 are alternately laminated, and is different from the semiconductor device 1 as illustrated in FIG. 1 in that a gap 530A is formed in the fifth insulation layer 150. Here, a sixth insulation layer 160 may include a material similar to that of the first to fifth insulation layers 110, 120, 130, 140, and 150, and the sixth diffusion prevention layer 260 may include a material similar to that of the first to fifth diffusion prevention layers 210, 220, 230, 240, and 250. In addition, here, because the other configurations are as described above with reference to FIG. 1, a description thereof is omitted.As illustrated in the semiconductor device 1A according to the first modification example, a gap 530A may be formed only in an insulating layer 100 (that is, the fifth insulating layer 150). At this time, because an opening is not formed in the fourth diffusion preventing layer 240 provided below the fifth insulating layer 150 by etching, the etching solution does not penetrate into the fourth insulating layer 140, and the gap 530A is not formed in the fourth insulating layer 140. In the semiconductor device 1A according to the first modification example, a space in which the gap 530A is formed is reduced, it is possible to improve a mechanical strength of the entire semiconductor device 1A.In addition, the semiconductor device 1A according to the first modification example may include a multilayer wiring layer in which six insulation layers 100 and six diffusion preventing layers 200 are alternately laminated, or may include a multilayer wiring layer in which seven or more insulation layers 100 and seven or more diffusion preventing layers 200 are alternately laminated.(Second Modification Example)Next, a semiconductor device 1B according to a second modification example of the embodiment will be described with reference to FIG. 12.As illustrated in FIG. 12, the semiconductor device 1B is different from the semiconductor device 1 as illustrated in FIG. 1 in that a through hole 510B is formed to penetrate the fourth and fifth insulating layers 140 and 150 and the third to fifth diffusion preventing layers 230, 240, and 250 Therefore, the gap 530 is formed in the second insulating layer 120 and the third insulating layer 130 in the semiconductor device 1B. Note that, because the respective configurations in the semiconductor device 1B are as described above with reference to FIG. 1, a description thereof is omitted here.As illustrated in the semiconductor device 1B according to the second modification example, the through hole 501B may be provided to penetrate the plurality of insulation layers 100 (i.e., the fourth insulation layer 140 and the fifth insulation layer 150). At this time, because the opening is formed in the second diffusion preventing layer 220 and the etching solution for forming the gap 530 penetrates the second insulating layer 120 from the third insulating layer 130, the gap 530 is formed in the second insulating layer 120 and the third insulating layer 130. Because the gap 530 in the third and subsequent layers is formed from the surface of the multilayer wiring layer in the semiconductor device 1B according to the second modification example, it is possible to improve a mechanical strength of the entire semiconductor device 1B.In addition, the through hole 510B may be provided to further penetrate three or more insulation layers 100 in the semiconductor device 1B according to the second modification example. However, because it becomes more difficult to form the through hole 510B as the aspect ratio increases, the number of the insulation layers 100 penetrating the through hole 510B may be, for example, four or less.(Third Modification Example)Next, a semiconductor device 1C according to a third modification example of the embodiment will be described with reference to FIG. 13.As illustrated in FIG. 13, the semiconductor device 1C is different from the semiconductor device 1 illustrated in FIG. 1 in that a gap 530C is formed in the second to fourth insulation layers 120, 130, and 140. Note that, because the respective configurations in the semiconductor device 1C are as described above with reference to FIG. 1, a description thereof is omitted here.As illustrated in the semiconductor device 1B according to the second modification example, the gap 530C may be further formed over the three or more insulating layers 100 other than the insulating layers 100 on the surface of the multilayer wiring layer (i.e., the first insulating layer 100 and the fifth insulating layer 150) constituting the semiconductor device 1C. At this time, because an opening is formed in the second diffusion preventing layer 220 and the third diffusion preventing layer 230 by etching, the etching solution enters the second insulating layer 120 and the third insulating layer 130, and the gap 530C is formed from the second insulating layer 120 to the fourth insulating layer 140. In the semiconductor device 1C according to the third modification example, it is possible to form the gap 530C in more insulation layers 100, thereby further suppressing signal delay and further reducing power consumption by further reducing wiring capacitance between the wirings.In addition, the gap 530C may be further provided in a plurality of insulation layers 100 in the semiconductor device 1C according to the third modification example. However, because a likelihood that a mechanical strength of the entire semiconductor device 1C is deteriorated increases with an increase in a space in which the gap 530C is formed, the number of the insulation layers 100 in which the gap 530C is formed may be, for example, 5 or less.<2 Second Embodiment>(2.1. Sectional Structure of Semiconductor Device)Next, a sectional structure of a semiconductor device according to a second embodiment of the present disclosure will be described with reference to FIG. 14. FIG. 14 is a sectional view of a semiconductor device 2 according to the embodiment in a lamination direction. Note that FIG. 14 illustrates a part of the sectional surface of the semiconductor device 2, and it goes without saying that the semiconductor device 2 also extends in an in-plane direction in a range not illustrated in the drawingAs illustrated in FIG. 14, the multilayer wiring layer in which the insulation layers 100 and the diffusion preventing layers 200 are alternately laminated is sandwiched between a pair of substrates 600 and 620 in the semiconductor device 2, and the first through hole 510 is provided so as to penetrate the first substrate 600 and the first insulation layer 110. Note that the semiconductor device 2 illustrated in FIG. 14 is obtained by vertically inverting the semiconductor device 1 illustrated in FIG. 1.Here, a sixth insulation layer 160 and a seventh insulation layer 170 may include a material similar to that of the first to fifth insulation layers 110, 120, 130, 140, and 150, and the sixth diffusion prevention layer 260 may include a material similar to that of the first to fifth diffusion prevention layers 210, 220, 230, 240, and 250. In addition, here, because the other configurations are as described above with reference to FIG. 1, a description thereof is omitted.In the semiconductor device 2 according to the embodiment, it is possible to improve a mechanical strength of the entire semiconductor device 2 by sandwiching the multilayer wiring layer in which the insulation layers 100 and the diffusion preventing layers 200 are alternately laminated between the pair of substrates 600 and 620.A substrate made of any material may be used as the substrate 620, as long as it is possible to bond the substrate 620 to the multilayer wiring layer in which the insulation layers 100 and the diffusion preventing layers 200 are alternately laminated. The substrate 620 may be a substrate including, for example, glass such as quartz, a resin such as polyimide or polyester, or a semiconductor of silicon (Si), or the like.In addition, the thickness of the substrate 600 having the semiconductor element (not illustrated) formed thereon may be reduced by using chemical mechanical polishing (CMP) or the like. If the semiconductor element provided on the substrate 600 is a color sensor, such a semiconductor device 2 may be used as, for example, a back surface irradiation type image pickup device.As illustrated in the semiconductor device 2 according to the embodiment, the through hole 510 may be provided in the insulation layer 100 on any of the surfaces of the multilayer wiring layer in which the insulation layers 100 and the diffusion preventing layers 200 are alternately laminated. That is, the through hole 510 may be provided in the first insulation layer 110 or may be provided in the seventh insulation layer 170. It is also possible to provide the gap 530 inside the multilayer wiring layer, similarly to the first embodiment, in the semiconductor device 2 via the through hole 510 in such a case.(2.2. Method of Manufacturing Semiconductor Device)Next, a method of manufacturing the semiconductor device 2 according to the embodiment will be described with reference to FIGS. 15 to 21. FIGS. 15 to 21 are sectional views illustrating steps of the method for manufacturing the semiconductor device 2 according to the embodiment.First, the first insulation layer 110, the first diffusion preventing layer 210, and the second diffusion preventing layer 220 are sequentially laminated on the substrate 600 having the semiconductor element and the like provided thereon by the CVD method, as illustrated in FIG. 15. In addition, the contact plug 610 is formed on the first insulation layer 110, and the first wiring layer 310 is formed on the second insulation layer 120.Specifically, the first insulation layer 110 is formed on the substrate 600 including silicon (Si) or the like first. Next, the first wiring layer 310 may be formed by using a damascene method in which the first diffusion preventing layer 210 and the second insulating layer 120 are formed on the first insulating layer 110, the first diffusion preventing layer 210 and the second insulating layer 120 in a predetermined region are then removed by etching, and the etched part is re-buried with copper (Cu) or the like.Note that the first and second insulation layers 110 and 120 may include SiO x or the like, which can be easily etched with hydrofluoric acid, and the first and second diffusion preventing layers 210 and 220 may include SiC or the like having high etching resistance with respect to hydrofluoric acid.Next, a part of the second diffusion preventing layer 220 is removed using a photolithography method as illustrated in FIG. 16. At this time, the region from which the second diffusion preventing layer 220 has been removed functions as an opening for introducing the etching solution into the third insulating layer 130 in a step of etching the second insulating layer 120 and the third insulating layer 130 in a later stage.Next, the third insulating layer 130, the third diffusion preventing layer 230, the fourth insulating layer 140, the fourth diffusion preventing layer 240, the fifth insulating layer 150, and the fifth diffusion preventing layer 250 are sequentially laminated on the second diffusion preventing layer 220 by a CVD method, as illustrated in FIG. 17. In addition, the second wiring layer 320, the third wiring layer 330, the fourth wiring layer 340, the first through via 410, the second through via 420, and the third through via 430 are formed on each of the insulation layers 100.Specifically, it is possible to form the second wiring layer 320 by using the damascene method in which the third insulation layer 130 is formed on the second diffusion preventing layer 220, the third insulation layer 130 in a predetermined region is then removed by etching, and the etched part is buried with copper (Cu) or the like. In addition, it is possible to form the third wiring layer 330, the fourth wiring layer 340, the first through via 410, the second through via 420, and the third through via 430 by a similar method. Note that the third to fifth insulation layers 130, 140, and 150 may include SiO x or the like, which can be easily etched with hydrofluoric acid, and the third to fifth diffusion preventing layers 230, 240, and 250 may include SiC or the like having high etching resistance with respect to hydrofluoric acid.Next, the sixth insulation layer 160, the sixth diffusion preventing layer 260, and the seventh insulation layer 170 are laminated on the fifth diffusion preventing layer 250 by the CVD method, and then the substrate 620 is bonded to the surface of the seventh insulation layer 170, as illustrated in FIG. 18. In addition, the thickness of the substrate 600 may be reduced by CMP or the like after the substrate 620 is bonded to the multilayer wiring layer.The sixth and seventh insulation layers 160 and 170 may include SiO x or the like, which can be easily etched with hydrofluoric acid, and the sixth diffusion preventing layer 260 may include SiC or the like having high etching resistance with respect to hydrofluoric acid. In addition, the substrate 620 may be a silicon (Si) substrate.Next, the through hole 510 may be formed by removing the first insulation layer 110, the first diffusion preventing layer 210, and the substrate 600 in a partial region by using etching or the like, as illustrated in FIG. 19. In addition, the protective film 521 is formed on the substrate 600 and inside the through hole 510. The shape of the opening of the through hole 510 may be, for example, a square shape having a side of 50 nm to 300 nm, and a plurality of through holes 510 may be provided. The protective film 521 can be formed to have a film thickness of 5 nm to 30 nm, for example, by using SiC or the like having high etching resistance with respect to hydrofluoric acid. Here, because the protective film 521 is formed by using the ALD method, the protective film 521 is uniformly (conformally) formed on the substrate 600 and inside the through hole 510.Next, the substrate 600 and the second insulating layer 120 are exposed by removing the protective film 521 while causing the protective side wall 520 to remain within the through hole 510 by etching back the entire surface of the protective film 521 as illustrated in FIG. 20. Such etching back of the entire surface can be realized by performing, for example, etching with high perpendicular anisotropy.Next, the gap 530 is formed by introducing a dilute hydrofluoric acid into the second insulating layer 120 and the third insulating layer 130 via the through hole 510, and performing wet observation as illustrated in FIG. 21.At this time, since the protection side wall 520 and the first to third diffusion preventing layers 210, 220, and 230 include SiC or the like having high etching resistance with respect to hydrofluoric acid, the etching hardly penetrates through the protection side wall 520 and the first to third diffusion preventing layers 210, 220, and 230. In addition, since the first wiring layer 310, the second wiring layer 320, and the first through via 410 include a metal material such as copper (Cu) and have high etch resistance with respect to hydrofluoric acid, the etch hardly penetrates through the first wiring layer 310, the second wiring layer 320, and the first through via 410. Therefore, the region where the gap 530 is formed is controlled in the lamination direction of the semiconductor device 2 depending on a region sandwiched between the first diffusion preventing layer 210 and the third diffusion preventing layer 230, and is controlled in the in-plane direction of the semiconductor device 2 depending on a time during which wet etching is performed.It is possible to manufacture the semiconductor device 2 according to the embodiment by the aforementioned process. Note that a sealing layer that includes an insulating material and blocks the opening of the through hole 510 may be provided on the substrate 600 to prevent moisture and the like from entering the gap 530.In the method of manufacturing the semiconductor device 2 according to the embodiment, the gap 530 is formed inside the semiconductor device 2 after the thickness of the substrate 600 is reduced by the CMP. Accordingly, it is possible to suppress occurrence of cracking or the like in the CMP process because the gap 530 is formed in the semiconductor device 2 after the CMP process in which a mechanical stress is applied.<3 Conclusion>As described above, it is possible to provide a void between the wiring layers 300 through the gap 530 provided inside, and thereby reduce a wiring capacitance according to the semiconductor device of the embodiment of the present disclosure. In this way, it is possible to suppress delay in the wirings and thereby realize high operation speed and lower power consumption according to the semiconductor device.In addition, because the gap 530 is not provided in the insulation layers 100 provided on the surface of the multilayer wiring layer in the semiconductor device, it is possible to maintain a mechanical strength of the entire semiconductor device. Further, because the diffusion preventing layers 200 protruding into the gap 530 are not formed in the semiconductor device, it is possible to prevent the diffusion preventing layers 200 from collapsing with low mechanical strength.According to the semiconductor device of the embodiment of the present disclosure, it is possible to use the semiconductor device in, for example, a memory device, a logic circuit, or an image pickup device by changing semiconductor elements to be mounted thereon. In particular, it is possible to use the semiconductor device 2 according to the second embodiment of the present disclosure as a back surface irradiation type image pickup device by mounting a color sensor as a semiconductor element.Further, the effects described in this specification are merely illustrative or exemplary effects and are not limiting. That is, the technology according to the present disclosure can achieve other effects with or instead of the above effects, which will be apparent to a person skilled in the art from the description of this specification.In addition, the present technology may also be configured as described below. (1) A semiconductor device including:a multilayer wiring layer in which insulation layers and diffusion preventing layers are alternately laminated and a wiring layer is provided inside;a through hole provided to penetrate at least one or more insulation layers from a surface of the multilayer wiring layer and having an inner side covered with a protection sidewall; anda gap provided in at least one or more insulation layers immediately below the through hole.(2) The semiconductor device according to (1), wherein at least a part of the wiring layer is provided within the gap. (3) The semiconductor device according to (1) or (2), wherein the gap is provided over a plurality of the insulation layers. (4) The semiconductor device according to (3), wherein an opening is provided in a partial region in the diffusion preventing layer between the plurality of insulation layers provided with the gap. (5) The semiconductor device according to (4), wherein the opening provided in the diffusion preventing layer is provided in a region that is not in contact with the wiring layer. (6) The semiconductor device according to any one of (1) to (5), wherein the through hole is provided so as to penetrate a plurality of the insulation layers from a surface of the multilayer wiring layer. (7) The semiconductor device according to any one of (1) to (6), wherein a surface of the wiring layer exposed by the gap is covered with a protective layer. (8) The semiconductor device according to any one of (1) to (7), wherein the gap is provided in a region including a region immediately below the through hole in a plan view from a lamination direction of the multilayer wiring layer. (9) The semiconductor device according to any one of (1) to (8), wherein the gap causes the diffusion preventing layers laminated on an upper surface and a lower surface of the insulation layer provided with the gap to be exposed. (10) The semiconductor device according to any one of (1) to (9), wherein the diffusion preventing layers and the protective side wall include materials having higher etch resistance with respect to a fluorine compound than the insulating layers. (11) An image pickup device including:a multilayer wiring layer in which insulation layers and diffusion preventing layers are alternately laminated and a wiring layer is provided inside;a through hole provided to penetrate at least one or more insulation layers from a surface of the multilayer wiring layer and having an inner side covered with a protection sidewall; anda gap provided in at least one or more insulation layers immediately below the through hole.(12) The image pickup device according to (11), further comprising:a pair of substrates sandwiching the multilayer wiring layer in a lamination direction,wherein the through hole is provided to further penetrate one of the substrates.(13) The image pickup device according to (11) or (12), wherein the multilayer wiring layer includes a color sensor inside, and the surface on the side on which the through hole is provided is a surface on a side on which the color sensor is provided in the multilayer wiring layer. (14) A method of manufacturing a semiconductor device, comprising:a step of forming a multilayer wiring layer in which insulation layers and diffusion preventing layers are alternately laminated and a wiring layer is provided inside;a step of forming a through hole such that the through hole passes through at least one or more insulation layers from a surface of the multilayer wiring layer;a step of forming a protective side wall inside the through hole; anda step of forming a gap by etching at least one or more insulation layers immediately below the through hole.(15) The method for manufacturing a semiconductor device according to (15), wherein the gap is formed by performing wet etching on the insulation layer.List of reference characters1, 2 Semiconductor device 100 Insulation layer 110 First insulation layer 120 Second insulation layer 130 Third insulation layer 140 Fourth insulation layer 150 Fifth insulation layer 200 Diffusion prevention layer 210 First diffusion prevention layer 220 Second diffusion prevention layer 230 Third diffusion prevention layer 240 Fourth diffusion prevention layer 250 Fifth diffusion prevention layer 300 Wiring layer 310 First wiring layer 320 Second wiring layer 330 Third wiring layer 340 Fourth wiring layer 400 Through via 410 First through via 420 Second through via 430 Third through via 510 Through hole 520 Protection side wall 530 Gap 540 Protection layer 610 Contact plugs 600, 620 Substrate

Claims

A semiconductor device (1, 2) comprising: a multilayer wiring layer (300) in which insulation layers (100) and diffusion preventing layers (200) are alternately laminated and a wiring layer (300) is provided inside; a through hole (510) provided so as to penetrate at least one or more insulation layers (100) from a surface of the multilayer wiring layer (300) and having an inner side covered with a protective side wall (520); a gap (530) provided in at least one or more insulation layers (100) immediately below the through hole (510); and a pair of substrates (600, 620) sandwiching the multilayer wiring layer (300) in a lamination direction, wherein a substrate (620) is bonded to the multilayer wiring layer (300).The semiconductor device (1, 2) according to claim 1, wherein at least a part of the wiring layer (300) is provided inside the gap (530).The semiconductor device (1, 2) according to claim 1, wherein the gap (530) extends across a plurality of the insulation layers (100).The semiconductor device (1, 2) according to claim 3, wherein an opening is provided in a partial region in the diffusion preventing layer (200) between the plurality of insulation layers (100) provided with the gap (530).The semiconductor device (1, 2) according to claim 4, wherein the opening provided in the diffusion preventing layer (200) is provided in an area that is not in contact with the wiring layer (300).The semiconductor device (1, 2) according to claim 1, wherein the through hole (510) is provided to penetrate a plurality of the insulation layers (100) from a surface of the multilayer wiring layer (300).The semiconductor device (1, 2) according to claim 1, wherein a surface of the wiring layer (300) exposed by the gap (530) is covered with a protection layer (540).The semiconductor device (1, 2) according to claim 1, wherein the gap (530) is provided in a region including a region immediately below the through hole (510) in a plan view from a lamination direction of the multilayer wiring layer (300).The semiconductor device (1, 2) according to claim 1, wherein the gap (530) causes the diffusion preventing layers (200) laminated on an upper surface and a lower surface of the insulation layer (100) provided with the gap (530) to be exposed.The semiconductor device (1, 2) according to claim 1, wherein the diffusion preventing layers (200) and the protection side wall (520) include materials having higher etch resistance with respect to a fluorine compound than the insulating layers (100).An image pickup device comprising: a multilayer wiring layer (300) in which insulation layers (100) and diffusion preventing layers (200) are alternately laminated and a wiring layer (300) is provided inside; a through hole (510) provided so as to penetrate at least one or more insulation layers (100) from a surface of the multilayer wiring layer (300) and having an inner side covered with a protective side wall (520); a gap (530) provided in at least one or more insulation layers (100) immediately below the through hole (510); and a pair of substrates (600, 620) sandwiching the multilayer wiring layer (300) in a lamination direction, wherein a substrate (620) is bonded to the multilayer wiring layer (300).The image pickup device according to claim 11, wherein the through hole (510) is provided to further penetrate one of the substrates (600, 620).The image pickup device according to claim 11, wherein the multilayer wiring layer (300) includes a color sensor inside, and the surface on the side on which the through hole (510) is provided is a surface on a side on which the color sensor is provided in the multilayer wiring layer (300).A method for manufacturing a semiconductor device (1, 2), comprising: a step of forming a multilayer wiring layer (300) on a first substrate (600) in which insulation layers (100) and diffusion preventing layers (200) are alternately laminated and a wiring layer (300) is provided inside; a step of forming a through hole (510) such that the through hole (510) passes through at least one or more insulation layers (100) from a surface of the multilayer wiring layer (300); a step of forming a protective side wall (520) inside the through hole (510); a step of forming a gap (530) by etching at least one or more insulation layers (100) immediately below the through hole (510); and a step of bonding a second substrate (620) to the multilayer wiring layer (300) so that the multilayer wiring layer (300) is sandwiched between the pair of substrates (600, 620).The method for manufacturing a semiconductor device (1, 2) according to claim 14, wherein the gap (530) is formed by performing wet etching on the insulation layer (100).

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