METHOD AND SYSTEMS FOR AVERAGE INLINE TESTING OF COMPONENTS AND FOR LATENT RELIABILITY OF DEFECT DETECTION

Abstract

A typical inline testing procedure for components includes: Performing inline inspection and inline metrology with an inline inspection tool (502) on a variety of wafers (506) at a variety of critical steps during wafer production; Aggregating the test results obtained from inline inspection and inline metrology, using one or more processors (504) to obtain a plurality of aggregated test results for the plurality of wafers (506); Identify, with the one or more processors (504), one or more statistical outliers among the multitude of wafers (506), at least partially based on the multitude of aggregated test results obtained from the multitude of wafers (506), and on a correlation of a reliability test of one or more components formed from one or more wafers (506) from a multitude of previously manufactured wafers (506), and aggregated test results obtained for the multitude of previously manufactured wafers (506); and Selective sorting, based on a selected risk tolerance level, with the one or more processors (504), a portion of the one or more statistical outliers of the multitude of wafers (506) from a supply chain for a downstream manufacturing process, if the one or more statistical outliers are in an operational component; and Reporting the selectively rejected part of the one or more statistical outliers of the multitude of wafers (506) for marking.

Description

CROSS-REFERENCE TO RELATED REGISTRATIONS

[0001] The present application claims priority under 35 USC § 119 (e) over provisional US patent application serial number 62 / 475,749, filed on March 23, 2017. TECHNICAL AREA

[0002] The description refers generally to the field of process control and in particular to the inspection and metrology of semiconductor devices. BACKGROUND

[0003] Thin polished plates, such as silicon wafers and the like, are a very important component of modern technology. A wafer, for example, is a thin disc of semiconductor material used in the manufacture of integrated circuits and other electronic components. Other examples of thin polished plates include substrates for magnetic disks, gauge blocks, and the like. While the technique described here primarily refers to wafers, it is clear that the technique is also applicable to other types of polished plates. The terms "wafer" and "thin polished plate" can be used interchangeably in this description.

[0004] During the manufacturing of a semiconductor device, a wafer undergoes hundreds of processing steps to create a functional sample. Throughout these steps, inspection and metrology procedures are performed to ensure the process is under control and that a working product results at the end of the manufacturing cycle. Inspection tools can detect unintended defects in the sample formation, while metrology tools can measure the physical parameters of the films and samples in relation to their intended dimensions. While some defects and flaws detected by metrology may be significant enough to clearly indicate device failure, smaller deviations may have an unclear effect. Some of these devices may later lead to earlier reliability failures after exposure to their operating environment.Risk-averse users of semiconductor devices, such as those in automotive, military, aerospace, and medical applications, demand failure rates in the parts-per-billion (ppb) range, which is significantly lower than current standards. Detecting and controlling these defects with latent reliability is key to meeting these industry requirements. This necessitates the provision of methods and systems for detecting defects with latent reliability.

[0005] US Patent 2016 / 0314578A1 concerns methods and systems for identifying outliers in multiple instances of a structure of interest. This involves capturing images of instances of the structure of interest at different positions within a die. These positions are at least partially aperiodic within the die.

[0006] US Standard 2009 / 0299679A1 pertains to the in-process testing of semiconductor chips to identify and reject potentially defective chips. The decision to reject chips includes the costs of further testing. Evaluation criteria for the chips are dynamically updated.

[0007] US 2015 / 0221076A1 concerns the classification of defects on a wafer. The classification is based, at least in part, on attributes assigned to a defect based on a reference image corresponding to the defect. SUMMARY

[0008] The present description relates to an average inline testing procedure for parts. The procedure may include: performing inline inspection and inline metrology on a multitude of wafers at a multitude of critical steps in wafer manufacturing; aggregating the inspection results of the inline inspection and inline metrology using one or more processors to obtain a multitude of aggregated test results for the multitude of wafers; identifying one or more statistical outliers among the multitude of wafers, based at least in part on the multitude of aggregated test results for the multitude of wafers; and removing the one or more statistical outliers from a supply chain for a downstream manufacturing process, or separating the one or more statistical outliers for further evaluation, testing, or repurposing.

[0009] Another embodiment of the present invention is an inspection system. The system can comprise one or more inspection tools configured to perform inline inspection and inline metrology on a plurality of wafers at a plurality of critical steps in wafer manufacturing. The system can also comprise one or more processors that are communicatively connected to one or more inspection tools.The one or more processors can further be configured to: aggregate the inspection results obtained from one or more inspection tools to obtain a multitude of aggregated inspection results for the multitude of wafers; identify one or more statistical outliers among the multitude of wafers, based at least in part on the multitude of aggregated inspection results obtained from the multitude of wafers; and filter out the one or more statistical outliers from a supply chain for a downstream manufacturing process, or to exclude the one or more statistical outliers for further evaluation, testing, or repurposing.

[0010] Another embodiment of the present description relates to an inspection system. The system may comprise one or more inspection tools configured to perform inline inspection and inline metrology on a multitude of wafers at a multitude of critical steps in wafer fabrication. The system may also comprise one or more processors communicatively connected to one or more inspection tools. The one or more processors may be configured to facilitate inline average testing of the component across the multitude of wafers.The one or more processors can further be configured to: generate a control boundary to define a risk tolerance for a downstream manufacturing process that uses the multitude of wafers; aggregate inspection results obtained from the one or more inspection tools to obtain a multitude of aggregated inspection results for the multitude of wafers; identify one or more statistical outliers that have not complied with the control boundary for the downstream manufacturing process, which is based at least in part on the multitude of aggregated inspection results obtained from a multitude of wafers; and remove one or more statistical outliers from a downstream manufacturing supply chain, or remove one or more statistical outliers for further evaluation, testing, or repurposing.

[0011] It is understood that both the preceding general description and the following detailed description are exemplary and merely explanatory, not necessarily limiting, to the present description. The accompanying drawings, which are included in the description and form part of it, illustrate the subject matter of the description. Together, the description and the drawings serve to explain the principles of the revelation. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The numerous advantages of the revelation are better understood by experts in this field with reference to the accompanying figures, in which: Fig. 1 is a representation of a stacked defect card representing test results obtained from an inline defect inspection tool configured in accordance with an embodiment of the present disclosure; Fig. 2 is a representation of a defect histogram created by DIEs on a plurality of wafers that have undergone the same inline inspection plan in accordance with an embodiment of the present disclosure; Fig. 3 another representation of the defect histogram and an exemplary output of an inline inspection defect analysis configured according to an embodiment of the present disclosure; Fig. 4 is a flowchart representing an embodiment of an average inline test (I-PAT) method configured according to an embodiment of the present disclosure; and Fig. 5 is a block diagram representing an inspection system configured in accordance with embodiments of the present disclosure. DETAILED DESCRIPTION

[0013] The disclosed subject matter, illustrated in the accompanying drawings, will now be described in detail. The invention is defined by the claims.

[0014] Embodiments of the present disclosure are directed to methods and systems for average inline testing and the detection of the latent reliability of defects. Latent reliability defects refer to defects that are present in a component from the time of manufacture and have passed initial quality tests, but lead to premature failure when activated in their operating environment. For example, wafers can be manufactured and used to produce various types of electronic semiconductor components. These electronic semiconductor components can then be used in the field for various purposes (for example, they can be installed in automobiles or other types of vehicles, aircraft, military, medical, or other devices requiring high reliability and low field failure rates) and operated in various environments.Some of these electronic semiconductor components may fail prematurely at a specific point in the future, thus causing reliability issues. Methods and systems configured in accordance with this disclosure are designed to detect latent reliability defects in order to identify at-risk wafers / DIEs for further testing or exclusion from the supply chain, thereby reducing the number of DIEs that may fail prematurely in the field.

[0015] Methods and systems configured in accordance with this disclosure can utilize average inline testing (I-PAT) to provide latent reliability defect detection. Average part testing (PAT) is a statistically based method for excluding components with abnormal characteristics (outliers) from semiconductor components delivered according to established guidelines (e.g., the automotive industry may have established guidelines according to the Automotive Electronics Council). The test limits used in PAT can be based on the electrical test results for that specific component with its unique design and processing. Each component design and its associated processing can exhibit a distribution of test results for each test requirement, and this data can be used as the basis for determining the PAT limits.

[0016] Reliability studies have shown that semiconductor devices with abnormal electrical properties tend to have a higher proportion of long-term quality and reliability issues. Specifically, devices that initially passed all manufacturing tests but could be considered outliers within the same population or batch compared to other devices are much more likely to fail in the field. Product Approval Testing (PAT) methods can therefore proactively identify these outliers for further testing, estimation, or exclusion from production shipments. However, it should be noted that existing PATs rely on electrical parametric data from probers and testers, which generally allow for achieving a manufacturing-grade reliability level of one part per million (PPM) in defect control, but struggle with detecting latent defects.The new requirement from the automotive industry is one part per billion (PPB), which represents levels of control that existing PATs cannot provide.

[0017] Average inline defect inspection (I-PAT) extends the PAT methodology by incorporating inspection results provided by inline defect inspection tools (such as broadband plasma, laser scanning, macro, backside inspection, and the like). Studies have shown that for a well-designed product and a mature semiconductor manufacturing process, the majority of defects that can cause latent reliability failures can be detected by inline defect inspection tools. The complication is that there are thousands of these defects on each wafer, while only a very small fraction of them result in potential reliability issues. Thus, relying solely on inline defect inspection tools can lead to the identification of too many defects (e.g., some defects can be found in almost every die), which in turn leads to a very low production yield (e.g.,(the scrapping of almost every die on the wafer, since defects occur in almost every die).

[0018] It is therefore intended that, in accordance with some embodiments of the present disclosure, I-PAT is configured such that data / results from a combination of inline defect inspection tools, metrology tools (such as overlay, film thickness, critical dimension and the like), defect analysis or management tools relating to yield, final test data, electrical start-up data and / or various other types of statistical data can be considered to find correlations that can be used to understand which inline defects have a statistically higher probability of forming defects with latent reliability.Similar to existing parametric methodologies, it can be shown that dies exhibiting higher metrological defects or variability outside the normal population distribution have a higher rate of premature failure, even if they have passed final electrical tests. The supplier can use this information to selectively subject these dies to further evaluation, testing, or repurposing, or to selectively exclude these dies from a supply chain for a downstream manufacturing process (such as in the automotive industry or similar risk-averse applications).

[0019] It is now generally referred to as... Fig. 1 and Fig. 2. Referenced. Fig. Figure 1 shows a stacked defect map 100, representing inspection results obtained from an inline defect inspection tool. The stacked defect map 100 can represent an aggregated inspection obtained from a large number of layers. Fig. Figure 2 is a defect histogram 200 that can be generated from all DIEs on a large number (a population) of wafers that have undergone the same inline inspection plan. It is assumed that statistical outliers can then be identified. These outliers can be separated from production shipments for further inspection, repurposing, or rejection because they are more likely to fail in the field.

[0020] As in Fig. As shown in 2, the following can be found in Fig. The y-axis of example histogram 200, shown in Figure 2, represents the number of stacked defects or some modifications thereof, based on probability, defect size, critical defect index, and / or other types of defect measurement. The dashed vertical line 202 can represent a control limit, which stands for a certain tolerance level of risk defined for a particular product. For example, an electronic semiconductor component used in a disposable, non-safety-critical component may have a relatively higher tolerance level for risk, so the control limit 202 is positioned more towards the right side of histogram 200 to tolerate a higher reliability risk (and thus scrap fewer potentially good dies). On the other hand, an electronic semiconductor component used in a non-disposable and safety-critical component (such as a radio frequency identification system) may have a higher tolerance level for risk.(e.g., an automobile) have a relatively lower tolerance level for risk, so the control limit 202 is positioned more towards the left side of the histogram 200 to achieve a more aggressive weeding out of potential reliability defects (thus scrapping more potentially good DIEs).

[0021] It is intended that the control limit 202 can be static. However, the control limit 202 can also be configured to be set dynamically in some embodiments. For example, the control limit 202 can be configured as a dynamic limit for the permissible quantity of high-risk anomalies per die, where the control limit 202 can be set for a different population of wafers, a batch of wafers, or a multitude of batches of wafers. It is also considered that the number of stacked defects, or some modifications thereof, could be used to set the control limit 202, merely as an example, which is not to be understood as restrictive.It is intended that the criteria used for the control limit 202 and the identification of a risk DIE may include, but are not limited to, the stacked number of layer defects from the inspection with one or more inspection sources, the number of individual critical layer defects from the inspection, the population of defect size per DIE, the population of defect type per DIE (such as either by re-examination or derived from image attributes), the collection of defects by attributes (such as size, polarity, or other attributes derived during the inspection), and / or known or suspected hotspots.

[0022] Additional criteria used to determine the Control Limit 202 may include the number of defects, defect size, defect type, or the rejection rate within a specific range (defect density) or within a definable, sensitive "area of ​​vigilance" that is known or believed to be critical with respect to performance, reliability, and longevity. Metrology data from targets or DIEs relating to overlay measurements, critical dimensions and / or optical critical dimensions, shape measurements, layer thicknesses or layer composition, wafer flatness or wafer topography, resistivity, or localized stress information may also be considered when establishing the Control Limit 202.

[0023] It is intended that DIEs that violate one or more of the aforementioned control limits 202 will be considered a de facto “risk” (simply because the population is outside the normal distribution) and can be identified and / or excluded from shipment of production, as they are more likely to fail in the field. However, it should be noted that this approach has some limitations. For example, it requires a large (but manageable) scope of inspection to be effective. Generally, the more inspection is performed, the greater the likelihood of identifying defects with latent reliability. However, in certain situations, a large portion of this data (e.g., specific steps, defect types, defect sizes, or similar) may be of little value in this regard.Additionally, a statistical approach can inevitably lead to a certain degree to an alpha risk (the risk of weeding out good DIEs, also known as "overkill") and a beta risk (the risk of failing to weed out bad DIEs, also known as "underkill").

[0024] Both underkill and overkill are costly and should be minimized where possible. In some implementations, it may be possible to optimize the inspection load and increase confidence in exclusion or quarantine parameters by applying data processing algorithms to correlate inline inspection data with quality control data from launch reliability testing, field returns, or a combination thereof. The purpose of such data processing algorithms is to identify these inspection steps, defect types, defect sizes, and / or metrology parameters to provide the most actionable data for effectively checking for statistical outliers.It is considered that this approach can help eliminate test steps with low correlation and improve the overall correlation, which in turn reduces overkill or underkill.

[0025] Fig. Figure 3 is a representation of an exemplary implementation of I-PAT, configured in accordance with the procedure described above. As in Fig. As shown in Figure 3, a stacked defect map of a wafer, collected from several critical process steps (e.g., 10), can be analyzed against a probability histogram of 300 latent defects. As previously described, a probability of latent defects for each DIE on the wafer can be calculated based on the number of stacked defects, taking into account size, coarse classification by bin, location of defects, area of ​​consideration, weighting of layer steps, and / or other types of defect measurement. It should be noted that some of these DIEs may be identified as statistical outliers (such as those resulting from a comparison against a defined control limit 302, such as the mean of three standard deviations or the like). These statistical outliers can be identified in an output file (such as...).a wafer card file containing data indicating the location of these DIEs) or are physically marked as defective or otherwise sorted out for evaluation, repurposing or disposal from the supply chain, helping to reduce the number of wafers / DIEs that fail prematurely in the field.

[0026] Fig. Figure 4 is a flowchart illustrating an embodiment of a method 400 for average inline testing (I-PAT) configured in accordance with the present disclosure. As shown in Fig. As shown in Figure 4, a wafer manufacturer can select the identification of the starting material that will ultimately undergo the initial reliability test (Step 402). The wafer manufacturer can also choose whether to perform inspection and metrology on all wafers at each critical step (such as 100% inspection and metrology) during the manufacturing process (Step 404). It is considered that inspection recipes can be used to detect all possible defects. In some embodiments, raw defect data can be collected and recorded for subsequent analysis using one or more databases or data storage devices.

[0027] After processing and final testing, all DIEs undergo a reliability test (sometimes referred to as initial burn-in, a procedure in which system components are tested before being put into operation) to identify reliability failures (Step 406). Additionally and / or alternatively, a physical failure analysis and a hit-back analysis can be performed for all reliability failures (such as those actually encountered in returned units from the field) to correlate reliability failures with inline failure data (Step 408). The resulting correlations can then be used in Step 410 to identify the most critical layers, defect types, defect locations, size limits, sensitivity requirements, and / or inspection tools.The information obtained in step 410 can be used to establish an implementation strategy (step 412) for high-volume manufacturing (HVM). It is considered that such a strategy will still require non-discretionary inspection (such as 100% inspection and metrology, as continued in step 404), but it can be performed on a reduced set of shifts.

[0028] The information obtained in step 410 can also be used in step 414 to help plot the alpha / beta curves, enabling the wafer manufacturer to determine whether (and / or how) the previously described control limit(s) need to be adjusted. The wafer manufacturer is intended to be able to repeat steps 402 to 414 on a continuous basis to refine the inspection strategy for maximum correlation at minimum cost. It is also intended that, as the cumulative data volume grows, data processing algorithms can be used to further improve the overall correlation and, consequently, the inspection accuracy.

[0029] As can be seen from the above, the Average Inline Testing (I-PAT) Procedure 400, as described above, represents an integration of inline inspection and average component testing. The I-PAT Procedure 400, configured in this way, offers a higher level of control for latent reliability defects compared to existing inspection techniques. It is considered that the I-PAT Procedure 400 can leverage all the advantages of many inline inspection and inline metrology attributes to identify latent defects that might otherwise leave the manufacturing facility / site. Furthermore, the I-PAT Procedure 400 is flexible in that it allows semiconductor manufacturers (and component manufacturers) to adjust the level of control to achieve the desired balance between implementation costs and reducing the latent reliability of defects.

[0030] In Fig.Figure 5 shows a block diagram of an inspection system 500 configured in accordance with embodiments of the present disclosure shown. The inspection system 500 can comprise one or more inline defect inspection tools 502 communicatively coupled to one or more computer processors 504. The inline defect inspection tool(s) 502 can be configured to inspect a plurality of layers on a plurality of wafers 506 using different inline inspection techniques. The inline defect inspection can be performed by applying certain defect detection algorithms and / or methods to the images obtained from the wafers. The defect detection algorithm and / or method can use any suitable algorithm and / or method known from the prior art.For example, the 504 processors can quantify some of the detected features and compare them to a threshold. Any output with values ​​above the threshold can be identified as a potential defect, while any output with values ​​below the threshold cannot be identified as a potential defect. In another example, the 504 processors can be configured to send the obtained results to a 508 storage medium, with or without performing error detection on the output.

[0031] The 504 processors can also be configured to receive inspection results from the 502 inline defect inspection tool and aggregate these results to obtain a multitude of aggregated results for the multitude of wafers. The 504 processors can then be used to assist in determining one or more control limits, which can be used to help identify the dies that are effectively considered "at-risk" and to identify them for further evaluation or to exclude these dies from being shipped from production because they are more likely to fail in the field. The 504 processors can also be configured to receive quality control data from 510 tools used in the initial (burn-in) reliability test and / or from 512 returned wafers from the field.The 504 processors can process the data received from the 510 tools of the initial (burn-in) reliability test and / or 512 field returns, together with the data from the 502 inline inspection tools for defects, to correlate the inline inspection data with the data from the 510 tools of the initial (burn-in) reliability test or the 512 field returns. As mentioned earlier, the purpose of performing this data correlation is to help identify which inspection steps, defect types, defect sizes, and / or metrology parameters are most likely to provide usable data that can be used to effectively filter out statistical outliers.This correlation process is intended to help disqualify / eliminate test steps with low correlation and improve overall correlation, thereby reducing overkill and underkill. In some embodiments where wafers / DIEs with latent reliability issues are identified, these can be reported on one or more indicator devices. Alternatively, wafers / DIEs with latent reliability issues can be identified as defective, physically marked as defective, or otherwise excluded from further evaluation, repurposing, or entry into the supply chain to help reduce the number of wafers / DIEs that fail prematurely in the field.

[0032] It is understood that each of the processor(s) described herein may take various forms, including a personal computer system, image computer, mainframe computer system, workstation, network device, internet device, or other device. In general, the term "computer system" may be broadly defined to include any device that has one or more processors that execute instructions from a storage medium. The computer subsystem(s) or system(s) may also include any suitable processor known in the prior art, such as a parallel processor.Additionally, the computer subsystem(s) or system(s) may include a computer platform with high-speed processing and software, which may be configured as either a standalone or a networked tool.

[0033] If a computer system comprises more than one computer subsystem, the other computer subsystems can be interconnected so that images, data, information, instructions, etc., can be transmitted between them, as further described here. For example, a computer subsystem can be interconnected with an additional computer subsystem(s) by means of any suitable transmission medium, which may include any suitable wired and / or wireless transmission medium known from the prior art. Two or more such computer subsystems can also be effectively interconnected by means of a common computer-readable storage medium.

[0034] It is considered that an additional embodiment of the present invention relates to a non-volatile, computer-readable medium that stores program instructions executable on a computer system to perform a computer-implemented target placement method as described above. The computer-readable medium may be a storage medium such as a magnetic or optical disk, a magnetic tape, or any other suitable non-volatile, computer-readable medium known in the field. The program instructions may be implemented in any number of ways, including procedure-based techniques, component-based techniques, and / or object-oriented techniques.For example, the program instructions can be implemented using ActiveX controls, C++ objects, Java Beans, Microsoft Foundation Classes (“MFC”), SSE (Streaming SIMD Extension) or other technologies or methods, as desired.

[0035] It is also understandable that, although the above examples relate to wafers, the systems and methods described in connection with the present disclosure can also be applied to other types of polished plates according to the present invention without departing from the spirit and scope of the present disclosure. The term wafer, as used in the present disclosure, can include a thin disc of semiconductor material used in the manufacture of integrated circuits and other components, as well as other thin polished plates, such as substrates for magnetic disks, gauge blocks, and the like.

[0036] It is intended that the methods and systems described in this disclosure can be implemented as standalone products or as components of various wafer metrology tools, inspection tools, and / or hotspot detection tools. It is understood that the specific sequence or hierarchy of steps in the disclosed methods are merely examples of exemplary approaches. Based on design preferences, it is natural that the specific sequence or hierarchy of steps in the method can be rearranged while remaining within the scope and spirit of the invention. It should also be understood that the blocks shown separately in the various figures are depicted for illustrative purposes only.It is considered that the blocks shown separately in the various figures could also be implemented as separate (and communicatively coupled) devices and / or processing units, which could also be integrated together without departing from the scope and spirit of the present revelation.

Claims

[1] An average inline test procedure for components includes: Performing inline inspection and inline metrology with an inline inspection tool (502) on a variety of wafers (506) at a variety of critical steps during wafer production; Aggregating the test results obtained from inline inspection and inline metrology, using one or more processors (504) to obtain a plurality of aggregated test results for the plurality of wafers (506); Identify, with the one or more processors (504), one or more statistical outliers among the multitude of wafers (506), at least partially based on the multitude of aggregated test results obtained from the multitude of wafers (506), and on a correlation of a reliability test of one or more components formed from one or more wafers (506) from a multitude of previously manufactured wafers (506), and aggregated test results obtained for the multitude of previously manufactured wafers (506); and Selective sorting, based on a selected risk tolerance level, with the one or more processors (504), a portion of the one or more statistical outliers of the multitude of wafers (506) from a supply chain for a downstream manufacturing process, if the one or more statistical outliers are in an operational component; and Reporting the selectively rejected part of the one or more statistical outliers of the multitude of wafers (506) for marking. [2] Method according to claim 1, wherein the one or more statistical outliers comprise one or more DIEs contained in one or more wafers (506) from the plurality of wafers (506). [3] The method of claim 1, further comprising: Isolating one or more statistically significant and controlled outliers from the supply chain in order to perform further evaluation, testing, or repurposing. [4] Method according to claim 1, wherein the selective sorting based on a selected risk tolerance level of a portion of the one or more statistical outliers of the plurality of wafers (506) from a supply chain for a downstream manufacturing process, when the one or more statistical outliers are located in an operational component, further comprises: a determination of a control limit to define a selected risk tolerance level for the downstream manufacturing process. [5] Method according to claim 4, wherein the control limit is designed such that it is based at least partially on a number of defects in the aggregated test results for the plurality of wafers (506). [6] Method according to claim 4, wherein the provided control limit is at least partially based on: an aggregate defect count per DIE determined on the basis of inline inspection; a single defect count of the critical layer per DIE determined on the basis of inline inspection; a population of defect size per DIE, a population of defect type per DIE, the quantity of defects, the defect size, the reject ratio within a definable range, the overlay measurement, the critical dimension, the optical critical dimension, the shape measurement, the film thicknesses, the flatness of the wafer, the resistivity of the wafer, or the local wafer stress. [7] The method of claim 1, further comprising: Performing a reliability test on the large number of wafers (506) after wafer production; and Correlating the results of the reliability testing of the multitude of wafers (500) and the multitude of aggregated test results of the multitude of wafers (506). [8] The method of claim 7, further comprising: Performing the fault analysis on one or more DIEs that were found in one or more faulty components; and Correlating the results of the failure analysis and the multitude of aggregated test results for the multitude of wafers (506). [9] A system (500) comprises: one or more inspection tools (502) suitable for performing inline inspection and inline metrology on a large number of wafers (506) at a large number of critical steps during wafer production; and one or more processors (504) that are communicatively connected to the one or more inspection tools (502), wherein the one or more processors (504) are configured to enable inline average testing of the component of the plurality of wafers (506) and the one or more processors (504) are further configured to: to aggregate test results from the one or more inspection tools (502) to obtain a plurality of aggregated test results for the plurality of wafers (506); to identify one or more statistical outliers from the multitude of wafers (506), based at least in part on the multitude of aggregated test results for the multitude of wafers (506) and on a correlation of a reliability test of one or more components formed from one or more wafers (506) from a multitude of previously manufactured wafers (506) and aggregated test results obtained for the multitude of previously manufactured wafers (506); and Selective sorting, based on a selected risk tolerance level, of a portion of the one or more statistical outliers of the multitude of wafers (506) from a supply chain for a downstream manufacturing process, if the one or more statistical outliers are located in an operational component; and Reporting the selectively rejected part of the one or more statistical outliers of the multitude of wafers (506) for marking. [10] System (500) according to claim 9, wherein the one or more statistical outliers comprise one or more DIEs contained in one or more wafers (506) from the plurality of wafers (506). [11] System (500) according to claim 9, wherein the one or more processors (504) are further configured to: to isolate one or more statistical outliers from the supply chain in order to use them for further evaluation, testing or repurposing. [12] System (500) according to claim 9, wherein the one or more processors (504) are further configured to: to create a control limit for a risk tolerance level that is defined for the downstream manufacturing process. [13] System (500) according to claim 12, wherein the one or more processors (504) are configured to generate the control boundary which is based at least partially on a number of defects in the aggregated test results for the plurality of wafers (506). [14] System (500) according to claim 12, wherein the one or more processors (504) are configured to generate the control boundary which is at least partially based on: an aggregate defect count per DIE determined on the basis of inline inspection; a single critical layer defect count per DIE determined on the basis of inline inspection; a population of defect size per DIE, a population of defect type per DIE, defect quantity, defect size, reject ratio within a definable range, overlay measurement, critical dimension, optical critical dimension, shape measurement, film thicknesses, wafer flatness, wafer resistivity, or local wafer stress. [15] System (500) according to claim 9, wherein the one or more processors (504) are further configured to: to perform a reliability test of the multitude of wafers (506) after wafer production; and to correlate the results of the reliability testing of the multitude of wafers (506) and the multitude of obtained aggregated test results for the multitude of wafers (506). [16] System (500) according to claim 15, wherein the one or more processors (504) are further configured to: to perform a fault analysis on one or more DIEs that were found in one or more faulty components; and to correlate the results of the error analysis and the multitude of aggregated test results for the multitude of wafers (506). [17] A system (500), comprising: one or more inspection tools (502) suitable for performing inline inspection and inline metrology on a large number of wafers (506) at a large number of critical steps during wafer production; and one or more processors (504) that are communicatively connected to the one or more inspection tools (502), wherein the one or more processors (504) are configured to enable average inline testing of components of the plurality of wafers (506) and the one or more processors (504) are further configured to: to create a control limit for a selected risk tolerance level defined for the downstream manufacturing process that uses the multitude of wafers (506); to aggregate test results from the one or more inspection tools (502) to obtain a plurality of aggregated test results for the plurality of wafers (506); to identify one or more statistical outliers that do not meet the control limit specified for the downstream manufacturing process, at least partially based on the multitude of aggregated test results obtained for the multitude of wafers (506) and on a correlation of a reliability test of one or more components formed from one or more wafers (506) from a multitude of previously manufactured wafers (506) and aggregated test results obtained for the multitude of previously manufactured wafers (506); Selective sorting, based on a selected risk tolerance level, of a portion of the one or more statistical outliers of the multitude of wafers (506) from a supply chain for a downstream manufacturing process, if the one or more statistical outliers are located in an operational component; and Reporting the selectively rejected part of the one or more statistical outliers of the multitude of wafers (506) for marking. [18] System (500) according to claim 17, wherein the one or more processors (504) are further configured to: to isolate one or more statistical outliers from the supply chain in order to use them for further evaluation, testing or repurposing. [19] System (500) according to claim 17, wherein the one or more processors (504) are further configured to: to perform a reliability test of the multitude of wafers (506) after wafer production; and to correlate the results of the reliability testing of the multitude of wafers (506) and the multitude of obtained aggregated test results for the multitude of wafers (506). [20] System (500) according to claim 19, wherein the one or more processors (504) are further configured to: to perform a fault analysis on one or more DIEs that were found in one or more faulty components; and to correlate the results of the failure analysis and the multitude of aggregated test results for the multitude of wafers (506).

Images