Semiconductor device

Abstract

Semiconductor device comprising: a semiconductor layer (2) having a main surface (3) in which trenches are formed, wherein a first trench (12) and a second trench (17, 143) run in the same second direction (Y) and have a gap in plan view; a body region (8) of a first conductivity type, which is formed along side walls of the trenches in a surface layer part of the main surface (3) of the semiconductor layer (2); a contamination region (25) of a second conductivity type, which is formed along the side wall of the first trench (12) in a surface layer part of the body region (8); a gate insulating layer (13) formed on an inner wall of the first trench (12); a gate electrode (14) embedded in the first trench (12) and facing the body region (8) and the contamination region (25), wherein the gate insulating layer (13) is arranged between the gate electrode (14) and the body region (8) and between the gate electrode (14) and the contamination region (25); a trench insulation layer (18, 144) formed on an inner wall of the second trench (17, 143); a trench electrode (19, 145) embedded in the second trench (17, 143) and facing the body region (8), wherein the trench insulating layer (18, 144) is arranged between the trench electrode (19, 145) and the body region (8); and a contact hole (31) formed in a surface layer part of the main surface (3) and extending along a first direction (X) orthogonal to the second direction (Y), wherein a contact electrode (51) is embedded in the contact hole (31), wherein the contact hole (31) has a first cutting region (33) with the gate electrode (14), a second cutting region (34) with the trench electrode (19, 145) and a connecting region (35) that connects the first cutting region (33) and the second cutting region (34) in a region between the first trench (12) and the second trench (17, 143), wherein a bottom wall of the contact hole (31) is formed flush in the first cut region (33), the second cut region (34) and the connection region (35), and wherein the bottom wall of the contact hole (31) is arranged below the main surface (3) of the semiconductor layer (2).

Description

Technical field

[0001] The present invention relates to a semiconductor device. background

[0002] A semiconductor device with an IGBT (Insulated Gate Bipolar Transistor) is shown in patent literature 1. This semiconductor device comprises a semiconductor substrate (semiconductor layer) having a main surface. A trench is formed in the main surface of the semiconductor substrate. A p-shaped body region is formed in a surface layer portion of the main surface of the semiconductor substrate along a side wall of the trench. An n-shaped emitter region (impurity region) is formed in a surface layer portion of the body region along the side wall of the trench.

[0003] A gate insulating layer is formed on the inner wall of the trench. A gate electrode layer is embedded in the trench along with the gate insulating layer. A contact groove, exposing the emitter region, is formed on the main surface of the semiconductor substrate away from the trench. An emitter electrode (contact electrode) is embedded in the contact groove. List of literature on patent literature

[0004] Patent literature 1: JP 2016 - 225 566 A

[0005] The publication US 2015 / 0295071A1 describes a semiconductor device with a trench-gate IGBT and a method for its fabrication. One idea is to improve the IGBT's structure by introducing an embedding insulation layer that isolates the gate electrode system from the emitter electrode. This allows for a reduction in the design space required for contacts in the emitter region, which facilitates device miniaturization. Furthermore, the more compact structure reduces the on-voltage resistance due to a higher hole density in the semiconductor material. Summary of the invention: Technical problem

[0006] In a structure where the gate electrode and the contact electrode are embedded in the surface layer of the semiconductor layer, the contact electrode is formed separately from the gate electrode, so that it does not come into contact with it. The distance between the gate electrode and the contact electrode is set taking into account the dimensional tolerance of the contact electrode. Therefore, it is impossible to make the distance between the gate electrode and the contact electrode smaller than a predetermined value, which is set according to the dimensional tolerance of the contact electrode. This limits the miniaturization of the semiconductor device.

[0007] One object of the present invention is therefore to provide a semiconductor device that is able to reduce a limitation caused by the dimensional tolerance of the contact electrode and that can contribute to further miniaturization. Solution to the problem

[0008] According to one aspect of the present disclosure, a semiconductor device according to claim 1 is provided.

[0009] This semiconductor device makes it possible to reduce the limitations caused by the dimensional tolerance of the contact electrode and to contribute to further miniaturization.

[0010] The above-mentioned or other objects, features and effects of the present invention are clarified by the following description of preferred embodiments with reference to the accompanying drawings. Brief description of the drawings Fig. Figure 1 is a perspective sectional view showing an area of ​​a part of a semiconductor device according to a first preferred embodiment of the present invention. Fig. Figure 2 is a perspective sectional view showing a structure on a main surface of a semiconductor layer made of Fig. 1 was removed. Fig. Figure 3 is a perspective sectional view showing an emitter contact electrode layer made of Fig. 2 was removed. Fig. 4 is a top view showing the semiconductor device of Fig. 3 is shown from the main surface of the semiconductor layer. Fig. 5 is a sectional view, taken along line VV in Fig. 4 was recorded. Fig. 6 is a sectional view along lines VI-VI in Fig. 4. Fig. Figure 7 is a perspective sectional view showing an area of ​​part of a semiconductor device according to a reference example, in which a structure on a major surface of a semiconductor layer has been removed. Fig. Figure 8 is a diagram of a current-voltage characteristic curve obtained through simulations. Fig. Figure 9 is a diagram of a collector peak current obtained through simulations. Fig. 10A is a perspective sectional view illustrating an example of a method for producing the in Fig. 1 semiconductor device shown. Fig. 10B is a perspective section view taken one step after the one from Fig. 10A is displayed. Fig. 10C is a perspective section view, taken one step after the one from Fig. 10B shows. Fig. 10D is a perspective section view, which is one step after the one from Fig. 10C is displayed. Fig. 10E is a perspective section view, taken one step after the one from Fig. 10D shows. Fig. 10F is a perspective section view, taken one step after the one from Fig. 10E is displayed. Fig. 10G is a perspective section view, taken one step after the one from Fig. 10F is shown. Fig. 10H is a perspective section view taken one step after the one from Fig. 10G is displayed. Fig. 10I is a perspective section view, taken one step after the one from Fig. 10H is displayed. Fig. 10J is a perspective sectional view, taken one step after the one by Fig. 10I shows. Fig. 10K is a perspective section view, taken one step after the one by Fig. 10J is shown. Fig. 10L is a perspective sectional view taken one step after the one from Fig. Shows 10K. Fig. 10M is a perspective section view, taken one step after the one from Fig. Shows 10L. Fig. 10N is a perspective section view taken one step after the one from Fig. Shows 10M. Fig. Figure 11 is a perspective sectional view showing an area of ​​part of a semiconductor device according to a second preferred embodiment of the present invention, in which a structure on a main surface of a semiconductor layer has been removed. Fig. Figure 12 is a perspective sectional view showing an area of ​​part of a semiconductor device according to a third preferred embodiment of the present invention, in which a structure on a major surface of a semiconductor layer has been removed. Fig. Figure 13 is a perspective sectional view showing an area of ​​part of a semiconductor device according to a fourth preferred embodiment of the present invention, wherein a structure on a major surface of a semiconductor layer has been removed. Fig. Figure 14 is a perspective sectional view showing an area of ​​part of a semiconductor device according to a fifth preferred embodiment of the present invention, wherein a structure on a major surface of a semiconductor layer has been removed. Fig. Figure 15 is a perspective sectional view showing an area of ​​part of a semiconductor device according to a sixth preferred embodiment of the present invention, wherein a structure on a major surface of a semiconductor layer has been removed. Fig. Figure 16 is a perspective sectional view showing an area of ​​part of a semiconductor device according to a seventh preferred embodiment of the present invention, wherein a structure on a major surface of a semiconductor layer has been removed. Fig. Figure 17 is a perspective sectional view showing an area of ​​part of a semiconductor device according to an eighth preferred embodiment of the present invention, wherein a structure on a major surface of a semiconductor layer has been removed. Fig. Figure 18 is a perspective sectional view showing an area of ​​part of a semiconductor device according to a ninth preferred embodiment of the present invention, wherein a structure on a major surface of a semiconductor layer has been removed. Fig. Figure 19 is a perspective sectional view showing an area of ​​part of a semiconductor device according to a tenth preferred embodiment of the present invention, wherein a structure on a major surface of a semiconductor layer has been removed. Fig. Figure 20 is a perspective sectional view showing an area of ​​part of a semiconductor device according to an eleventh preferred embodiment of the present invention, wherein a structure on a main surface of a semiconductor layer has been removed. Fig. Figure 21 is a perspective sectional view showing an area of ​​part of a semiconductor device according to a twelfth preferred embodiment of the present invention, wherein a structure on a major surface of a semiconductor layer has been removed. Fig. Figure 22 is a perspective sectional view showing an area of ​​part of a semiconductor device according to a fourteenth preferred embodiment of the present invention. Fig. 23 is a perspective sectional view showing the area of ​​the Fig. Figure 22 shows part of the semiconductor device in which a structure has been removed from a major surface of a semiconductor layer. Fig. 24 is a top view of Fig. 23. Fig. 25 is a sectional view along line XXV-XXV in Fig. 24. Fig. Figure 26 is a perspective section view of the area accordingly. Fig. 22, which shows a region of a part of a semiconductor device according to a fourteenth preferred embodiment of the present invention. Fig. 27 is a sectional view of the area which Fig. 25 corresponds to and represents an area of ​​part of the in Fig. The semiconductor device shown in Figure 26 is shown. Fig. 28 is a top view of the area accordingly Fig. 24, which shows a region of a part of a semiconductor device according to a fifteenth preferred embodiment of the present invention. Fig. 29 is a sectional view along line XXIX-XXIX in Fig. 28. Fig. Figure 30 is a cross-sectional view of the area accordingly. Fig. 29, which shows a region of a part of a semiconductor device according to a sixteenth preferred embodiment of the present invention. Fig. Figure 31 is a section view of the area accordingly. Fig. 29, which shows a region of a part of a semiconductor device according to a seventeenth preferred embodiment of the present invention. Fig. Figure 32 is a section view of the area accordingly. Fig. 29, which shows a region of a part of a semiconductor device according to an eighteenth preferred embodiment of the present invention. Fig. Figure 33 is a top view of the part that Fig. 2 corresponds and shows a modification of the semiconductor layer. Fig. Figure 34 is a top view of the part that Fig. 4 corresponds and shows a modification of an embedded gate insulating layer. Fig. Figure 35 is a top view of the part that Fig. 4 corresponds and shows a modification of an emitter contact electrode layer. Description of the exemplary implementations

[0011] Fig. Figure 1 is a perspective sectional view showing an area of ​​a part of a semiconductor device 1 according to a first preferred embodiment of the present invention. Fig. 2 is a perspective sectional view showing a structure on a main surface 3 of a semiconductor layer 2 made of Fig. 1 was removed. Fig. Figure 3 is a perspective sectional view showing an emitter contact electrode layer 51 made of Fig. 2 was removed.

[0012] Fig. 4 is a top view showing the semiconductor device of Fig. 3 is shown from the main surface 3 of the semiconductor layer 2. Fig. 5 is a section view along line VV in Fig. 4. Fig. 6 is a sectional view along line VI-VI in Fig. 4. The structure on the first main surface 3 of the semiconductor layer 2 is also in Fig. 5 and Fig. 6 shown.

[0013] The semiconductor device 1 has a basic form that includes a trench-gate IGBT (Insulated Gate Bipolar Transistor). Fig. 1 to Fig. 6 contains the semiconductor device 1 a n - -like semiconductor layer 2. Semiconductor layer 2 consists of an n - -like silicon single-crystal substrate. The silicon single-crystal substrate is produced using a semiconductor wafer made of an n - -like silicon single crystal formed, which is produced by an FZ (Floating Zone) process.

[0014] Semiconductor layer 2 has a first main surface 3 on one side and a second main surface 4 on the other side. The thickness of semiconductor layer 2 should be not less than 50 µm and not more than 300 µm. The thickness of semiconductor layer 2 should be not less than 50 µm and not more than 100 µm, not less than 100 µm and not more than 150 µm, not less than 150 µm and not more than 200 µm, not less than 200 µm and not more than 250 µm, or not less than 250 µm and not more than 300 µm.

[0015] A p-shaped collector region 5 is formed in a surface layer portion of the second main surface 4. An n-shaped charge storage region 6 is formed in a surface layer portion of the first main surface 3. The charge storage region 6 is formed at a distance on the side of the first main surface 3 relative to the collector region 5.

[0016] In semiconductor layer 2, there is an n in a region between the collector region 5 and the charge storage region 6. - A p-like drift region 7 is formed. The drift region 7 is defined by a region located between the collector region 5 and the charge storage region 6 in the semiconductor layer 2. A p-like body region 8 is formed in a surface layer portion of the charge storage region 6. A plurality of gate-trough electrode structures 10 and a plurality of trench-emitter electrode structures 11 are formed in the surface layer portion of the first main surface 3 with spacings between the electrode structures.

[0017] In Fig. 1 to Fig. Figure 6 shows only a single adjacent trench-gate electrode structure 10 and a single trench-emitter electrode structure 11. The following describes the structure of the semiconductor device 1, focusing on the structure of a single gate-trough electrode structure 10 and a single trench-emitter electrode structure 11.

[0018] The gate-trough electrode structure 10 and the trench-emitter electrode structure 11 are formed at a distance from each other along an arbitrary first direction X. The gate-trough electrode structure 10 and the trench-emitter electrode structure 11 extend in a ribbon-like fashion along a second direction Y, which intersects the first direction X in a top view.

[0019] More precisely, the term "top view" refers to a top view from a normal direction Z to the first principal surface 3 (hereinafter simply referred to as "normal direction Z"). More precisely, the second direction Y is a direction perpendicular to the first direction X. The first direction X and the second direction Y are each also tangential directions to the first principal surface 3.

[0020] The trench spacing P0 between the gate-trough electrode structure 10 and the trench-emitter electrode structure 11 should be not less than 0.1 µm and not less than 0.6 µm. The trench spacing P0 should be not less than 0.1 µm and not more than 0.2 µm, not less than 0.2 µm and not more than 0.3 µm, not less than 0.3 µm and not more than 0.4 µm, not less than 0.4 µm and not more than 0.5 µm, or not less than 0.5 µm and less than 0.6 µm. Preferably, the trench spacing P0 should be not less than 0.2 µm and not more than 0.4 µm (for example, about 0.25 µm).

[0021] The gate-trough electrode structures 10 comprise a gate trench 12 (trench), a gate insulating layer 13, a gate electrode layer 14 (gate electrode), a plurality of gate embedding holes 15, and a plurality of embedded gate insulating layers 16 (embedded insulating layers). The gate trench 12 extends from the first main surface 3 through the body region 8 and the charge storage region 6, reaching the drift region 7.

[0022] The depth of the gate trench 12 should be not less than 2.0 µm and not more than 4.0 µm. The depth of the gate trench 12 should be not less than 2.0 µm and not more than 2.5 µm, not less than 2.5 µm and not more than 3.0 µm, not less than 3.0 µm and not more than 3.5 µm, or not less than 3.5 µm and not more than 4.0 µm. Preferably, the depth of the gate trench 12 is not less than 2.5 µm and not more than 3.5 µm (for example, about 3.0 µm).

[0023] The width of the gate trench 12 in the first direction should be not less than 0.5 µm and not more than 1.5 µm. The width of the gate trench 12 in the first direction should be not less than 0.5 µm and not more than 0.75 µm, not less than 0.75 µm and not more than 1.0 µm, not less than 1.0 µm and not more than 1.25 µm, or not less than 1.25 µm and not more than 1.5 µm. Preferably, the width of the gate trench 12 in the first direction is not less than 0.5 µm and not more than 1.0 µm (for example, about 0.75 µm).

[0024] The gate insulating layer 13 may contain silicon dioxide. The gate insulating layer 13 is formed in film form along an inner wall surface of the gate groove 12. The gate insulating layer 13 defines a recess in the gate groove 12.

[0025] The gate electrode layer 14 can contain electrically conductive polysilicon. The gate electrode layer 14 is controlled by a gate voltage. The gate electrode layer 14 is embedded in the gate groove 12, with the gate insulating layer 13 located between the gate electrode layer 14 and the gate groove 12. More precisely, the gate electrode layer 14 is embedded in a recessed space defined by the gate insulating layer 13 within the gate groove 12. An upper end portion of the gate electrode layer 14 is located on the side of the first principal surface 3 relative to a lower part of the body region 8.

[0026] In the present preferred embodiment, the gate embedding holes 15 are formed in a main surface of the gate electrode layer 14 with spacings between the gate embedding holes 15 along the second direction Y. Therefore, the upper end part of the gate electrode layer 14 has a non-uniform structure including the gate embedding holes 15.

[0027] The spacing between adjacent gate embedding holes 15 should be greater than 0 µm and not more than 10 µm. The spacing between adjacent gate embedding holes 15 is also the width in the second direction Y of a portion located between two adjacent gate embedding holes 15 in the gate electrode layer 14. The spacing between adjacent gate embedding holes 15 should be greater than 0 µm and not more than 2 µm, not less than 2 µm and not more than 4 µm, not less than 4 µm and not more than 6 µm, not less than 6 µm and not more than 8 µm, or not less than 8 µm and not more than 10 µm.

[0028] In the present preferred embodiment, one side wall of each gate embedding hole 15 is defined by the gate insulating layer 13 and by the gate electrode layer 14. A bottom wall of each gate embedding hole 15 is defined by the gate electrode layer 14. The bottom wall of each gate embedding hole 15 is located in a region between the first main surface 3 and the lower part of the body region 8 relative to the normal direction Z.

[0029] In Fig. 6. Each of the gate embedding holes 15 is shaped such that it has a conical form, with a lower surface area smaller than the opening area. The angle θ between the main surface of the gate electrode layer 14 and the side wall of the gate embedding hole 15 in the gate electrode layer 14 can be greater than 90° and not greater than 105° (e.g., approximately 102°).

[0030] The embedded gate insulating layers 16 are each embedded in a surface layer portion of the gate electrode layer 14 within the gate trench 12. More precisely, the embedded gate insulating layers 16 are each embedded in the gate embedding holes 15. Each of the embedded gate insulating layers 16 is exposed by an opening of the gate trench 12.

[0031] The trench-emitter electrode structure 11 comprises an emitter trench 17 (second trench), an emitter insulating layer 18 (inner wall insulating layer), an emitter electrode layer 19 (embedded electrode), an emitter embedding hole 20, and an embedded emitter insulating layer 21 (second embedded insulating layer). The emitter trench 17 extends from the first main surface 3 through the body region 8 and the charge storage region 6, reaching the drift region 7.

[0032] The depth of the emitter trench 17 should be not less than 2.0 µm and not more than 4.0 µm. The depth of the emitter trench 17 should be not less than 2.0 µm and not more than 2.5 µm, not less than 2.5 µm and not more than 3.0 µm, not less than 3.0 µm and not more than 3.5 µm, or not less than 3.5 µm and not more than 4.0 µm. Preferably, the depth of the emitter trench 17 is not less than 2.5 µm and not more than 3.5 µm (for example, about 3.0 µm). Preferably, the depth of the emitter trench 17 is substantially equal to the depth of the gate trench 12.

[0033] The width of the emitter trench 17 in the first direction should be not less than 0.5 µm and not more than 1.5 µm. The width of the gate trench 12 in the first direction should be not less than 0.5 µm and not more than 0.75 µm, not less than 0.75 µm and not more than 1.0 µm, not less than 1.0 µm and not more than 1.25 µm, or not less than 1.25 µm and not more than 1.5 µm. Preferably, the width of the emitter trench 17 in the first direction should be not less than 0.5 µm and not more than 1.0 µm (for example, about 0.75 µm). Preferably, the width of the emitter trench 17 in the first direction is essentially equal to the width of the gate trench 12 in the first direction.

[0034] The emitter insulating layer 18 may contain silicon dioxide. The emitter insulating layer 18 is formed in film form along an inner wall surface of the emitter trench 17. The emitter insulating layer 18 defines a recessed space in the emitter trench 17.

[0035] The emitter electrode layer 19 can contain electrically conductive polysilicon. The emitter electrode layer 19 is controlled by an emitter voltage. The emitter voltage has a lower value than a gate voltage. The emitter voltage can be a reference voltage (e.g., ground voltage).

[0036] The emitter electrode layer 19 is embedded in the emitter trench 17, with the emitter insulating layer 18 located between the emitter electrode layer 19 and the emitter trench 17. More precisely, the emitter electrode layer 19 is embedded in a recessed space defined by the emitter insulating layer 18 in the emitter trench 17.

[0037] In the currently preferred embodiment, the emitter embedding hole 20 is designed such that essentially the entire main surface of the emitter electrode layer 19 is excavated. In other words, the emitter electrode layer 19 is embedded in an intermediate section in the depth direction of the recessed space defined by the emitter insulating layer 18.

[0038] In the currently preferred embodiment, a side wall of the emitter embedding hole 20 is defined by the emitter insulating layer 18. A bottom wall of the emitter embedding hole 20 is defined by the emitter electrode layer 19. The bottom wall of the emitter embedding hole 20 is located in the region between the first principal surface 3 and the lower part of the body region 8 relative to the normal direction Z. In other words, an upper end portion of the emitter electrode layer 19 is located on the side of the first principal surface 3 relative to the lower part of the body region 8. With respect to the normal direction Z, the depth of the emitter embedding hole 20 can be substantially equal to the depth of the gate embedding hole 15.

[0039] The embedded emitter insulating layer 21 is embedded in a surface layer portion of the emitter electrode layer 19 within the emitter trench 17. More precisely, the embedded emitter insulating layer 21 is embedded in the emitter embedding hole 20. Therefore, the embedded emitter insulating layer 21 seals the emitter electrode layer 19. The embedded emitter insulating layer 21 is exposed through an opening in the emitter trench 17.

[0040] A +The emitter region 25 (contamination region) is formed in a region along a side wall of gate trench 12 in a surface layer portion of body region 8. More precisely, emitter region 25 is formed along one side wall and another side wall of gate trench 12 relative to the first direction X. Each emitter region 25 is band-shaped and extends in the second direction Y. Emitter region 25 also borders a side wall of emitter trench 17.

[0041] The emitter region 25, the body region 8, the charge storage region 6, and the drift region 7 are formed in this order from the first main surface 3 towards the side of the second main surface 4 in the region along the side wall of the gate trench 12 in the surface layer portion of the first main surface 3. A channel CH of the IGBT is formed in a region facing the gate electrode layer 14, with the gate insulating layer 13 located between the channel CH and the gate electrode layer 14 in the body region 8.

[0042] In Fig. 3 and Fig. 4. Several first contact holes 31 are formed in the surface layer portion of the first main surface 3. The first contact holes 31 are formed at intervals between each other along the second direction Y. The first contact holes 31 are each formed in a band shape extending along the first direction X. The width in the second direction of each of the first contact holes 31 is smaller than the width of the gate trench 12 in the second direction. The width in the first direction of each of the first contact holes 31 is larger than the width of the gate trench 12 in the first direction.

[0043] More precisely, each of the first contact holes 31 extends through the side wall of the gate trench 12 from an inner region of a corresponding embedded gate insulating layer 16 and is drawn out to the surface layer portion of the first main surface 3. In the present preferred embodiment, each of the first contact holes 31 extends through one side of the side wall and another side of the side wall of the gate trench 12 from the inner region of the embedded gate insulating layer 16 in the first direction X. The width in the second direction of each of the first contact holes 31 is smaller than the width in the second direction of the corresponding embedded gate insulating layer 16.

[0044] Each of the first contact holes 31 further has a drawn-out section 32 extending from the one-sided side wall of the gate trench 12 towards the emitter trench 17. Each of the drawn-out sections 32 penetrates the side wall of the emitter trench 17 from the surface layer portion of the first main surface 3 and reaches the interior of the emitter trench 17. In the present preferred embodiment, each of the drawn-out sections 32 extends through one side of the side wall and another side of the side wall of the emitter trench 17 in the first direction X.

[0045] Each of the first contact holes 31 has a first cutting region 33 that intersects the gate electrode layer 14 in a top view. At the first cutting region 33, a side wall and a bottom wall of the first contact holes 31 are defined by the embedded gate insulating layer 16.

[0046] Each of the first contact holes 31 has a second cut region 34 that intersects the emitter electrode layer 19 in a top view. At the second cut region 34, the side wall and bottom wall of each of the first contact holes 31 are defined by the embedded emitter insulating layer 21.

[0047] Each of the first contact holes 31 has a connecting region 35 through which the first cut region 33 and the second cut region 34 are connected in a plan view in a region between the gate trench 12 and the emitter trench 17. In the connecting region 35, the side wall and the bottom wall of each of the first contact holes 31 are defined by the semiconductor layer 2.

[0048] The side wall of each of the first contact holes 31 is designed to be flush with the first cutting region 33, the second cutting region 34, and the connecting region 35. The bottom wall of each of the first contact holes 31 is designed to be flush with the first cutting region 33, the second cutting region 34, and the connecting region 35.

[0049] The bottom wall of each of the first contact holes 31 is formed in the region between the first main surface 3 and the lower part of body region 8. More precisely, the bottom wall of each of the first contact holes 31 is formed in an area between the lower part of body region 8 and a lower part of emitter region 25.

[0050] The first contact holes 31 are arranged arbitrarily. The first contact holes 31 can be formed at equal intervals along the second direction Y. The first contact holes 31 can be formed at unequal intervals along the second direction Y.

[0051] In body region 8, there is a p + A contact region 36 of a type is formed in a region along the bottom wall of each of the first contact holes 31. The contact region 36 can be formed in a region along the bottom wall and the side wall of each of the first contact holes 31 in body region 8. The contact region 36 is formed in a region that is deeper in the normal direction Z than the emitter region 25 in body region 8.

[0052] Contact region 36 has an exposure area exposed by the bottom wall of the first contact hole 31. The exposure area of ​​contact region 36 is formed in the region between the first main surface 3 and the lower part of body region 8. More precisely, the exposure area of ​​contact region 36 is formed in the region between the lower part of body region 8 and the lower part of emitter region 25. Even more precisely, the exposure area of ​​contact region 36 is formed in an area between an upper surface of the emitter electrode layer 19 and the lower part of emitter region 25.

[0053] An example where the contact region 36 is formed flat on a bottom surface of the first contact hole 31 by a single ion implantation is shown in Fig. 1 to Fig. Figure 3 shows the contact region 36. However, the contact region 36 can be formed deeper by adjusting the number of ion implantations or the energy of the ion implantation.

[0054] With renewed reference to Fig. On the first main surface 3, an insulating intermediate layer 41 (insulating layer) is formed. The insulating intermediate layer 41 covers the gate-trough electrode structure 10 and the trench-emitter electrode structure 11. The insulating intermediate layer 41 covers the embedded gate insulating layer 16 exposed by the gate trench 12 and the embedded emitter insulating layer 21 exposed by the emitter trench 17.

[0055] The insulating interlayer 41 can contain an oxide layer (SiO2 film) or a nitride layer (SiN film). The insulating interlayer 41 can have a layered structure with an oxide film (SiO2 film) and a nitride film (SiN film). The oxide layer (SiO2 layer) can comprise a BPSG (boron-phosphorus-silicon glass) layer containing boron and phosphorus, and / or a PSG (phosphorus-silicon glass) layer containing phosphorus.

[0056] The insulating intermediate layer 41 can have a layered structure comprising a BPSG film and a PSG film stacked in that order from the first principal surface 3. The thickness of the BPSG film should be not less than 2000 Å and not more than 8000 Å (for example, approximately 5000 Å). The thickness of the PSG film should be not less than 2000 Å and not more than 6000 Å (for example, approximately 4000 Å).

[0057] A multitude of second contact holes 42 are formed in the insulating intermediate layer 41. Each of the second contact holes 42 is connected to a corresponding first contact hole 31. In other words, the second contact holes 42 are formed at intervals along the second direction Y and are each formed in a band shape extending along the first direction X.

[0058] The second contact holes 42 extend through the insulating intermediate layer 41, and each of the second contact holes 42 communicates with a corresponding first contact hole 31. Therefore, each of the second contact holes 42 forms an emitter contact hole 31, 42 by a combination of the second contact hole 42 and the corresponding first contact hole 31.

[0059] The width in the second direction of each of the second contact holes 42 can be equal to or greater than the width in the second direction of each of the first contact holes 31. In other words, the width in the second direction of each of the second contact holes 42 can be equal to or greater than the width in the second direction of each of the first contact holes 31. If the width in the second direction of each of the second contact holes 42 exceeds the width in the second direction of each of the first contact holes 31, an inner wall surface of each of the second contact holes 42 can surround an inner wall surface of the corresponding first contact hole 31.

[0060] The second contact holes 42 are arranged arbitrarily and are set in accordance with the arrangement of the first contact holes 31. The second contact holes 42 can be formed at equal intervals from each other along the second direction Y. The second contact holes 42 can be formed at unequal intervals from each other along the second direction Y.

[0061] An emitter main surface electrode layer 43, serving as the first main surface electrode layer, is formed on the insulating intermediate layer 41. The emitter main surface electrode layer 43 enters the second contact hole 42 and the first contact hole 31 (i.e., the emitter contact hole 31, 42) of the insulating intermediate layer 41 from above.

[0062] The emitter main surface electrode layer 43 can have a layered structure with a first electrode layer 44 and a second electrode layer 45, which are stacked on top of each other in that order from the side of the insulating intermediate layer 41. The first electrode layer 44 serves as the ground layer for the second electrode layer 45. The first electrode layer 44 is designed to act as a barrier electrode layer, suppressing diffusion of the second electrode layer 45.

[0063] The first electrode layer 44 is formed in film form along a major surface of the insulating intermediate layer 41. The first electrode layer 44 extends into the interior of the emitter contact hole 31, 42. The first electrode layer 44 is formed in film form within the emitter contact hole 31, 42. The first electrode layer 44 defines a recessed space within the emitter contact hole 31, 42. The first electrode layer 44 is connected to body region 8, emitter region 25, and contact region 36 within the emitter contact hole 31, 42.

[0064] The first electrode layer 44 can have a layered structure with a titanium layer and a titanium nitride layer stacked on top of each other in that order from the side of the first main surface 3. The first electrode layer 44 can have a single-layer structure with either a titanium layer or a titanium nitride layer.

[0065] The second electrode layer 45 is formed in film form on the first electrode layer 44. The second electrode layer 45 extends into the recessed space defined by the first electrode layer 44 in the emitter contact hole 31, 42. The second electrode layer 45 is electrically connected to body region 8, emitter region 25, and contact region 36 via the first electrode layer 44. The second electrode layer 45 may contain a tungsten layer.

[0066] A portion in which the main surface of the insulating intermediate layer 41 is covered by the emitter main surface electrode layer 43 can be formed by a third electrode layer containing a conductive material different from that of the second electrode layer 45. In this case, the third electrode layer is formed on the insulating intermediate layer 41 in such a way that it covers the second electrode layer 45.

[0067] The third electrode layer can contain nickel, palladium, aluminum, copper, an aluminum alloy, and / or a copper alloy. The third electrode layer can contain an Al-Si-Cu (aluminum-silicon-copper) alloy, an Al-Si (aluminum-silicon) alloy, and / or an Al-Cu (aluminum-copper) alloy, each of which is an example of the aluminum alloy. Preferably, the third electrode layer comprises a conductive material containing aluminum as the main element.

[0068] In the present preferred embodiment, a plurality of emitter contact electrode layers 51 (contact electrodes) are formed by parts arranged in the first contact holes 31 in the main emitter surface electrode layer 43. Thus, as in Fig. 1 to Fig. Figure 6 shows a structure formed in which the emitter contact electrode layer 51 is embedded in the surface layer portion of the semiconductor layer 2.

[0069] The emitter contact electrode layers 51 have an arrangement and shape that each correspond to the arrangement and shape of the first contact holes 31. In other words, the emitter contact electrode layers 51 are formed with intervals between them along the second direction Y and are each formed in a band shape extending along the first direction X.

[0070] The width in the second direction of each of the emitter contact electrode layers 51 is smaller than the width in the second direction of the gate trench 12. The width in the first direction of each of the emitter contact electrode layers 51 is larger than the width in the first direction of the gate trench 12.

[0071] Each of the emitter contact electrode layers 51 extends through the side wall of the gate trench 12 from the inner region of a corresponding embedded gate insulating layer 16 and is drawn out to the surface layer portion of the first main surface 3. In the present preferred embodiment, each of the emitter contact electrode layers 51 extends along one side of the side wall and another side of the side wall of the gate trench 12 from the inner region of the embedded gate insulating layer 16 with respect to the first direction X. The width in the second direction of each of the emitter contact electrode layers 51 is smaller than the width in the second direction of the corresponding embedded gate insulating layer 16.

[0072] Each of the emitter contact electrode layers 51 also has a pulled-out section 52 that extends from one side wall of the gate trench 12 toward the emitter trench 17. Each of the pulled-out sections 52 extends through the side wall of the emitter trench 17 from the surface layer portion of the first main surface 3 and reaches the inside of the emitter trench 17. In the present preferred embodiment, each of the pulled-out sections 52 extends through one side of the side wall and another side of the side wall of the emitter trench 17 with respect to the first direction X.

[0073] Each of the emitter contact electrode layers 51 has a first section region 53 that intersects the gate electrode layer 14 in a top view. At the first section region 53, each of the emitter contact electrode layers 51 faces the gate electrode layer 14, with the embedded emitter insulating layer 16 located between the emitter contact electrode layer 51 and the gate electrode layer 14 in the normal direction Z and the second direction Y. Each of the emitter contact electrode layers 51 is insulated from the gate electrode layer 14 via the embedded gate insulating layer 16.

[0074] Each of the emitter contact electrode layers 51 has a second section region 54 that intersects the emitter electrode layer 19 in a top view. At the second section region 54, each of the emitter contact electrode layers 51 faces the emitter electrode layer 19, with the embedded emitter insulating layer 21 lying between the emitter contact electrode layer 51 and the emitter electrode layer 19 in the normal direction Z. Each of the emitter contact electrode layers is insulated from the emitter electrode layer 19 via the embedded emitter insulating layer.

[0075] Each of the emitter contact electrode layers 51 has a connection region 55 through which the first cut region 53 and the second cut region 54 are connected to each other in a top view in the region between the gate trench 12 and the emitter trench 17. In the connection region 55, each of the emitter contact electrode layers 51 is connected to the body region 8, to the emitter region 25 and to the contact region 36.

[0076] With reference to Fig. 5 the thickness of the embedded gate insulating layer 16, which lies between each of the emitter contact electrode layers 51 and the gate electrode layer 14, can be substantially equal to the thickness of the embedded emitter insulating layer 21, which lies between each of the emitter contact electrode layers 51 and the emitter electrode layer 19.

[0077] A collector electrode layer 61, serving as a second main electrode layer, is formed on the second main surface 4 of the semiconductor layer 2. The collector electrode layer 61 is connected to the collector region 5. A gate main surface electrode layer (not shown), which has the same structure as the emitter main surface electrode layer 43, can be formed on the insulating intermediate layer 41. The gate main surface electrode layer can be electrically connected to the gate electrode layer 14 by a gate contact hole formed in the insulating intermediate layer 41.

[0078] Fig. Figure 7 is a perspective sectional view showing an area of ​​a part of a semiconductor device 62 according to a reference example, in which a structure on the main surface 3 has been removed. In the semiconductor device 62 according to the reference example, the same reference symbol is used for a component that corresponds to a component of semiconductor device 1, and a description of this component is omitted.

[0079] The semiconductor device 62 according to the reference example includes a contact hole 63 and an emitter contact electrode layer 64 instead of the first contact hole 31 and the emitter contact electrode layer 51. The contact hole 63 is formed in the region between the gate trench 12 and the emitter trench 17 in the surface layer part of the first main surface 3.

[0080] The contact hole 63 is spaced apart from the gate trench 12 and the emitter trench 17. The contact hole 63 is ribbon-shaped and extends along the second direction Y in the top view. The emitter contact electrode layer 64 is embedded in the contact hole 63.

[0081] The width PA of contact hole 63 in the first direction exceeds 0.2 µm. The distance PB between contact hole 63 and gate trench 12 exceeds 0.2 µm. The distance PC between contact hole 63 and emitter trench 17 exceeds 0.2 µm. In other words, the trench spacing PX between gate trench 12 and emitter trench 17 exceeds 0.6 µm.

[0082] The distance PB and the distance PC are generally set taking into account a dimensional tolerance of the emitter contact electrode layer 64. In the semiconductor device 62 according to the reference example, the trench spacing PX is set to a predetermined value that exceeds 0.6 µm in accordance with the dimensional tolerance of the emitter contact electrode layer 64. Therefore, it is difficult to set the trench spacing PX in the semiconductor device 62 so that it is less than 0.6 µm according to the reference example 62.

[0083] In other words, the narrowing of the trench spacing PX is hindered by the aforementioned dimensional tolerance. Therefore, it is difficult to achieve a hole storage effect between the gate trench 12 and the emitter trench 17. This results in limitations on electrical properties such as switching speed and voltage withstand capability.

[0084] In contrast, the semiconductor device 1 has a structure in which the emitter contact electrode layer 51 intersects the gate electrode layer 14 with the embedded gate insulating layer 16 in the surface layer portion of the first main surface 3. Therefore, it is not necessary to form the emitter contact electrode layer 51 away from the gate electrode layer 14, and thus it is possible to reduce the limitations caused by the dimensional tolerance of the emitter electrode layer 51. This makes it possible to narrow the trench spacing P0 between the gate trench 12 and the emitter trench 17.

[0085] In semiconductor device 1, it is possible to achieve a trench spacing P0 of no less than 0.2 µm and no more than 0.4 µm (e.g., approximately 0.25 µm). This makes it possible to reduce the distance between the gate trench 12 and the emitter trench 17, thus enabling semiconductor device 1 to contribute to further miniaturization.

[0086] Furthermore, it is possible to reduce the distance between Gate Trench 12 and Emitter Trench 17, thereby increasing the hole storage effect between Gate Trench 12 and Emitter Trench 17. This makes it possible to... Fig. 8 and Fig. to obtain the electrical properties shown in 9.

[0087] Fig. Figure 8 is a graph of the current-voltage characteristic curves obtained through simulations. Fig. 8 the ordinate axis represents a collector current IC [A] and the abscissa axis represents a collector-emitter voltage VCE [V].

[0088] A first characteristic curve L1 and a second characteristic curve L2 are in Fig. Figure 8 shows the first characteristic curve L1. This curve represents features of the semiconductor device 62 according to the reference example. This curve L2 represents the properties of the semiconductor device 1. Both the first characteristic curve L1 and the second characteristic curve L2 represent current-voltage characteristics when the collector-emitter voltage VCE is changed from 0 V to 2 V.

[0089] For the first characteristic curve L1, the collector-emitter voltage VCE of the semiconductor device 62 according to the reference example is 0.96 V, 1.22 V, 1.42 V and 1.61 V when the collector current IC is 200 A, 400 A, 600 A and 800 A respectively.

[0090] For the second characteristic curve L2, the collector-emitter voltage VCE of semiconductor device 1 is 0.86 V, 1.06 V, 1.22 V and 1.37 V when the collector current IC is 200 A, 400 A, 600 A and 800 A respectively.

[0091] As described above, according to semiconductor device 1 it is possible to make a collector-emitter voltage VCE required for increasing operation smaller than that of semiconductor device 62 according to the reference example, and therefore it was understood that the switching speed can be increased.

[0092] Fig. Figure 9 is a diagram of a collector peak current ICP obtained through simulations. Fig. 9 the ordinate axis represents a collector current IC [A] and the abscissa axis represents a collector-emitter voltage VCE [V].

[0093] A first characteristic curve L1 and a second characteristic curve L2 are in Fig. Figure 9 shows the current-voltage characteristic of semiconductor device 62 according to the reference example. The second characteristic L12 represents the current-voltage characteristic of semiconductor device 1. Both the first characteristic L11 and the second characteristic L12 represent the characteristics when the collector-emitter voltage VCE is changed from 0 V to 15 V.

[0094] In the first characteristic curve L11, the collector peak current ICP exceeds 5000 A in the semiconductor device 62 according to the reference example when the collector-emitter voltage VCE is not less than 10 V and not more than 15 V.

[0095] For the second characteristic curve L12 of the semiconductor device 1, the collector peak current ICP is less than 5000 A (not less than 4500 A and less than 5000 A) when the collector-emitter voltage VCE is not less than 10 V and not more than 15 V.

[0096] As described above, it is possible to make the collector peak current ICP smaller in semiconductor device 1 than in semiconductor device 62 according to the reference example, and therefore it can be assumed that the short-circuit capacitance can be increased.

[0097] Fig. 10A to Fig. Figures 10N are each a perspective sectional view to describe an example of a method for manufacturing the semiconductor device 1. Fig. 10A to Fig. 10N are each perspective sectional views showing parts of the Fig. 1 corresponds.

[0098] In Fig. 10A will first be the n -The p-type semiconductor layer 2 is prepared. Subsequently, the p-type collector region 5 and the n-type charge storage region 6 are formed within the semiconductor layer 2. The collector region 5 is formed by introducing p-type impurities into the second main surface 4 of the semiconductor layer 2. The collector region 5 can be formed in the surface layer portion of the second main surface 4 of the semiconductor layer 2 using an ion implantation process via an ion implantation mask (not shown).

[0099] The charge storage region 6 is formed by introducing n-type impurities into the first main surface 3. The charge storage region 6 can be formed in the surface layer portion of the first main surface 3 using an ion implantation process via an ion implantation mask (not shown).

[0100] Then in Fig. 10B a mask 71 with a predetermined pattern is formed on the first main surface 3. The mask 71 has a plurality of openings 72 through which areas are exposed in which the gate trench 12 and the emitter trench 17 are formed.

[0101] Then, in Fig. 10C, an unnecessary part of semiconductor layer 2 is removed from the first main surface 3. The superfluous part of semiconductor layer 2 can be removed by an etching process (e.g., a wet etching process) using mask 71. Therefore, gate trench 12 and emitter trench 17 are formed. Afterwards, mask 71 is removed.

[0102] Then in Fig. 10D a base insulating layer 73, which serves as the base of both the gate insulating layer 13 and the emitter insulating layer 18, is configured to cover the first main surface 3. The base insulating layer 73 can be formed on the first main surface 3 by an oxidation treatment process.

[0103] The oxidation treatment method can be a thermal oxidation treatment method or a wet oxidation treatment method. The base insulating layer 73 can contain silicon oxide. The base insulating layer 73 can be formed by a CVD (chemical vapor deposition) process instead of the oxidation treatment method.

[0104] Then, with reference to Fig. On the first main surface 3, a first base conductor layer 74 is formed, which serves as the base for both the gate electrode layer 14 and the emitter electrode layer 19. The first base conductor layer 74 can be an electrically conductive polysilicon layer. The first base conductor layer 74 can be formed by a CVD process. The CVD process can be a low-pressure CVD (LP-CVD) process.

[0105] Then, a superfluous portion of the first base conductor layer 74 is removed. This superfluous portion is removed until at least the base insulating layer 73 is exposed. The superfluous portion of the first base conductor layer 74 can be removed by an etching process (e.g., a wet etching process).

[0106] The superfluous part of the first base conductor layer 74 can be removed by an etching process (e.g. a wet etching process) after a main area of ​​the first base conductor layer 74 has been flattened by a CMP (Chemical Mechanical Polishing) process.

[0107] Then in Fig. 10F a mask 75 with a predetermined pattern is formed on the first main surface 3. The mask 75 has a plurality of openings 76 through which areas are exposed in which the gate embedding hole 15 and the emitter embedding hole 20 are formed.

[0108] Next, a superfluous portion of the gate electrode layer 14 and a superfluous portion of the emitter electrode layer 19 are removed. This superfluous portion can be removed by an etching process (e.g., a wet etching process) using the mask 75. This creates the gate embedding hole 15 and the emitter embedding hole 20.

[0109] Then, in Fig. 10G, mask 75 removed. The gate embedding hole 15 and the emitter embedding hole 20 can be individually configured using different masks (not shown). In other words, the gate embedding hole 15 and the emitter embedding hole 20 can be created with different depths relative to each other.

[0110] Then, with reference to Fig. 10H on the first main surface 3 forms a base insulating layer 77, which serves as the base for both the embedded gate insulating layer 16 and the embedded emitter insulating layer 21. The base insulating layer 77 can contain silicon oxide. The base insulating layer 77 can be formed by a CVD process. The CVD process can be an LP-CVD process.

[0111] Then in Fig. 10I An unnecessary part of the base insulating layer 77 is removed. The superfluous part of the base insulating layer 73 can be removed by an etching process (e.g., a wet etching process). This forms the embedded emitter insulating layer 16 and the embedded emitter insulating layer 21.

[0112] In this step, the portion covering the first main surface 3 in the base insulating layer 73 is also removed. This results in the formation of the gate insulating layer 13 and the emitter insulating layer 18. The gate-trough electrode structure 10 and the trench-emitter electrode structure 11 are also formed as a result.

[0113] Then, in Fig. 10J, in semiconductor layer 2 the p-like body region 8 and the n + -type emitter region 25 is formed. Body region 8 is formed by introducing p-type impurities into the first main surface 3. Body region 8 can be formed in the surface layer portion of the first main surface 3 by an ion implantation procedure using an ion implantation mask (not shown).

[0114] The emitter region 25 is formed by introducing n-type impurities into the first main surface 3. The emitter region 25 can be formed in the surface layer portion of the first main surface 3 using an ion implantation method via an ion implantation mask (not shown).

[0115] Then in Fig. The insulating intermediate layer 41 is formed on the first main surface 3 at a thickness of 10K. The insulating intermediate layer 41 is formed on the first main surface 3 such that it covers the gate-trough electrode structures 10 and the trench-emitter electrode structure 11. This step can include the formation of a BPSG film (e.g., 5000 Å) and a PSG film (e.g., 4000 Å) in that order from the top of the first main surface 3 by a CVD process.

[0116] Then in Fig. 10L a mask 78 with a predetermined pattern is formed on the insulating intermediate layer 41. The mask 78 has a plurality of openings 79 through which areas are exposed in which the first contact hole 31 and the second contact hole 42 are formed.

[0117] Then in Fig. 10M removes a superfluous part of the insulating intermediate layer 41, a superfluous part of the embedded gate insulating layer 16, and a superfluous part of the embedded emitter insulating layer 21. The superfluous parts of the insulating intermediate layer 41, etc., can be removed by an etching process (e.g., a dry etching process) using the mask 78.

[0118] In this step, the superfluous parts of the insulating intermediate layer 41, etc., are also removed, and then a superfluous part of the semiconductor layer 2 is removed. The superfluous part of the semiconductor layer 2 can be removed by an etching process (e.g., a dry etching process) using the mask 78.

[0119] The first contact hole 31 is thus formed in the first main surface 3. The second contact hole 42, which communicates with the first contact hole 31, is formed in the insulating intermediate layer 41. The mask 78 is then removed.

[0120] The contact region 36 is then formed in the surface layer portion of the first main surface 3. More precisely, the contact region 36 is formed in an area along the bottom wall of the first contact hole 31 in the surface layer portion of body region 8. The contact region 36 can be formed in an area along the side wall and the bottom wall of the first contact hole 31.

[0121] The contact region 36 is formed by introducing p-type impurities into the first contact hole 31. The contact region 36 can be introduced into the first contact hole 31 using an ion implantation method via an ion implantation mask (not shown). In this way, the contact region 36 is formed along the bottom wall of the first contact hole 31.

[0122] Contact region 36 can be created by introducing p-type impurities into the first main surface 3 in the step of Fig. 10J are formed. In this case, the contact region 36 in the surface layer part of the first main surface 3 can be formed using an ion implantation method via an ion implantation mask (not shown). The contact region 36 along the bottom wall of the first contact hole 31 is also formed by this step.

[0123] Then in Fig. 10N the emitter main surface electrode layer 43 is formed on the insulating intermediate layer 41. This step includes a step to form the first electrode layer 44 and the second electrode layer 45 in that order on the insulating intermediate layer 41.

[0124] The step of forming the first electrode layer 44 comprises the formation of the titanium layer and the titanium nitride layer in that order on the insulating intermediate layer 41. The titanium layer and the titanium nitride layer can each be formed by a sputtering process or a CVD process. The step of forming the second electrode layer 45 comprises the formation of a tungsten layer on the first electrode layer 44. The tungsten layer can be formed by a CVD process.

[0125] The emitter main surface electrode layer 43 is formed on the insulating intermediate layer 41. Subsequently, the emitter contact electrode layer 51 is formed by a portion that enters the first contact hole 31 in the emitter main surface electrode layer 43. Furthermore, the collector electrode layer 61 is formed on the second main surface 4 of the semiconductor layer 2. The semiconductor device 1 is formed by these steps.

[0126] Fig. Figure 11 is a perspective sectional view showing a region of a part of a semiconductor device 81 according to a second preferred embodiment of the present invention, wherein a structure on the first main surface 3 has been removed. The same reference numeral is assigned below to a component corresponding to a component of the semiconductor device 1 mentioned above, and a description of this component is omitted.

[0127] In Fig. In a top view, 11 of each of the first contact holes 31 in the present preferred embodiment intersects only the gate trench 12. The withdrawn section 32 of each of the first contact holes 31 is formed away from the emitter trench 17. In other words, the withdrawn section 32 does not reach the emitter trench 17.

[0128] In the present preferred embodiment, each of the emitter contact electrode layers 51 intersects only the gate trench 12 in a top view. The pulled-out section 52 of each of the emitter contact electrode layers 51 is formed away from the emitter trench 17. In other words, the pulled-out section 52 does not reach the emitter trench 17.

[0129] As described above, the same effect can be achieved with semiconductor device 81 as with semiconductor device 1. Semiconductor device 81 can be manufactured by changing the layout of each mask in the manufacturing process of semiconductor device 1.

[0130] Fig. Figure 12 is a perspective sectional view showing an area of ​​a part of a semiconductor device 91 according to a third preferred embodiment of the present invention, wherein a structure on the first main surface 3 has been removed. The same reference numeral is assigned below to a component corresponding to a component of the semiconductor device 1 mentioned above, and a description of this component is omitted.

[0131] In Fig. In the present preferred embodiment, the first contact holes 31 contain a first contact hole 92A and a second contact hole 92B. In plan view, the first contact hole 92A intersects only the gate trench 12. In plan view, the first contact hole 92B intersects only the emitter trench 17.

[0132] In the present preferred embodiment, the emitter contact electrode layers 51 comprise an emitter contact electrode layer 93A and an emitter contact electrode layer 93B. The emitter contact electrode layer 93A is embedded in the first contact hole 92A. In plan view, the emitter contact electrode layer 93A intersects only the gate trench 12. The emitter contact electrode layer 93B is embedded in the first contact hole 92B. In plan view, the emitter contact electrode layer 93B intersects only the emitter trench 17.

[0133] As described above, the same effect can be achieved with semiconductor device 91 as with semiconductor device 1. Semiconductor device 91 can be manufactured by changing the layout of the masks in the manufacturing process of semiconductor device 1.

[0134] Fig. Figure 13 is a perspective sectional view showing a region of a part of a semiconductor device 101 according to a fourth preferred embodiment of the present invention, wherein a structure on the first main surface 3 has been removed. The same reference numeral is assigned below to a component corresponding to a component of the semiconductor device 1 mentioned above, and a description of this component is omitted.

[0135] In Fig. In the present preferred embodiment, the semiconductor device 101 comprises a trench-emitter electrode structure 102 instead of the trench-emitter electrode structure 11. The trench-emitter electrode structure 102 has the same structure as the gate-trough electrode structure 10.

[0136] More precisely, the trench-emitter electrode structure 102 comprises an emitter trench 103, an emitter insulating layer 104, an emitter electrode layer 105, a plurality of emitter embedding holes 106 and a plurality of embedded emitter insulating layers 107.

[0137] The emitter trench 103, the emitter insulating layer 104, the emitter electrode layer 105, the emitter embedding hole 106, and the embedded emitter insulating layer 107 have the same structure as the gate trench 12, the gate insulating layer 13, the gate electrode layer 14, the gate embedding hole 15, and the embedded emitter insulating layer 16, respectively. A detailed description of the trench-emitter electrode structure 102 is omitted.

[0138] In the present preferred embodiment, each of the first contact holes 31 has a first cutting region 108 that intersects the gate electrode layer 14 in a top view. In the first cutting region 108, a side wall and a bottom wall of the first contact holes 31 are defined by the embedded gate insulating layer 16.

[0139] Each of the first contact holes 31 has a second cut region 109 that intersects the emitter electrode layer 105 in a top view. At the second cut region 109, the side wall and bottom wall of each of the first contact holes 31 are defined by the embedded emitter insulating layer 107.

[0140] Each of the first contact holes 31 has a connecting region 110 through which the first cut region 108 and the second cut region 109 are connected in a plan view in a region between the gate trench 12 and the emitter trench 17. In the connecting region 110, the side wall and the bottom wall of each of the first contact holes 31 are defined by the semiconductor layer 2.

[0141] The side wall of each of the first contact holes 31 is designed to be flush with the first cutting region 108, the second cutting region 109, and the connecting region 110. The bottom wall of each of the first contact holes 31 is designed to be flush with the first cutting region 108, the second cutting region 109, and the connecting region 110.

[0142] In the present preferred embodiment, each of the emitter contact electrode layers 51 has a first section 111 that intersects the gate electrode layer 14 in a top view. At the first section 111, each of the emitter contact electrode layers 51 faces the gate electrode layer 14, with the embedded gate insulating layer 16 located between the emitter contact electrode layer 51 and the gate electrode layer 14 in the normal direction Z and the second direction Y. Each of the emitter contact electrode layers 51 is insulated from the gate electrode layer 14 via the embedded gate insulating layer 16.

[0143] Each of the emitter contact electrode layers 51 has a second section region 112 that intersects the emitter electrode layer 105 in a top view. At the second section region 112, each of the emitter contact electrode layers 51 faces the emitter electrode layer 105, with the embedded emitter insulating layer 107 lying between the emitter contact electrode layers 51 and the emitter electrode layer 105 in the normal direction Z and the second direction Y. Each of the emitter contact electrode layers is connected to the emitter electrode layer 105 via the embedded emitter insulating layer 107.

[0144] Each of the emitter contact electrode layers 51 has a connection region 113 through which the first cut region 111 and the second cut region 112 are connected to each other in a top view in the region between the gate trench 12 and the emitter trench 17. In the connection region 113, each of the emitter contact electrode layers 51 is connected to the body region 8, to the emitter region 25 and to the contact region 36.

[0145] As described above, the same effect can be achieved with semiconductor device 101 as with semiconductor device 1. Semiconductor device 101 can be manufactured by changing the layout of the masks in the manufacturing process of semiconductor device 1.

[0146] Fig. Figure 14 is a perspective sectional view showing a region of a part of a semiconductor device 121 according to a fifth preferred embodiment of the present invention, wherein a structure on the first main surface 3 has been removed. The same reference numeral is assigned below to a component corresponding to a component of the semiconductor device 101 mentioned above, and a description of this component is omitted.

[0147] In Fig. In a top view, each of the first contact holes 31 in the present preferred embodiment intersects only the gate trench 12. The withdrawn section 32 of each of the first contact holes 31 is formed away from the emitter trench 17. In other words, the withdrawn section 32 does not reach the emitter trench 17.

[0148] In the present preferred embodiment, each of the emitter contact electrode layers 51, in a top view, intersects only the gate trench 12. The pulled-out section 52 of each of the emitter contact electrode layers 51 is formed away from the emitter trench 17. In other words, the pulled-out section 52 does not reach the emitter trench 17.

[0149] In the configuration thus provided, the trench-emitter electrode structure 102 is not strictly necessary to contain the emitter embedding hole 106 and the embedded emitter insulating layer 107, as shown in Fig. 14 shown.

[0150] As described above, the same effect can be achieved with semiconductor device 121 as with semiconductor device 1. Semiconductor device 121 can be manufactured by changing the layout of the masks in the manufacturing process of semiconductor device 1.

[0151] Fig. Figure 15 is a perspective sectional view showing a region of a part of a semiconductor device 131 according to a sixth preferred embodiment of the present invention, wherein a structure on the first main surface 3 has been removed. The same reference numeral is assigned below to a component corresponding to a component of the semiconductor device 101 mentioned above, and a description of this component is omitted.

[0152] In Fig. In the present preferred embodiment, the first contact holes 31 contain a first contact hole 132A and a second contact hole 132B. In plan view, the first contact hole 132A intersects only the gate trench 12. In plan view, the first contact hole 132B intersects only the emitter trench 17.

[0153] In the present preferred embodiment, the emitter contact electrode layers 51 comprise an emitter contact electrode layer 133A and an emitter contact electrode layer 133B. The emitter contact electrode layer 133A is embedded in the first contact hole 132A. In plan view, the emitter contact electrode layer 133A intersects only the gate trench 12. The emitter contact electrode layer 133B is embedded in the first contact hole 132B. In plan view, the emitter contact electrode layer 133B intersects only the emitter trench 17.

[0154] As described above, the same effect can be achieved with semiconductor device 131 as with semiconductor device 1. Semiconductor device 131 can be manufactured by changing the layout of the masks in the manufacturing process of semiconductor device 1.

[0155] Fig. Figure 16 is a perspective sectional view showing a region of a part of a semiconductor device 141 according to a second preferred embodiment of the present invention, wherein a structure on the first main surface 3 has been removed. The same reference numeral is assigned below to a component corresponding to a component of the semiconductor device 1 mentioned above, and a description of this component is omitted.

[0156] In Fig. In the present preferred embodiment, the semiconductor device 141 includes a second gate-trough electrode structure 142 instead of the trench-emitter electrode structure 11. The second gate-trough electrode structure 142 has the same structure as the gate-trough electrode structure 10.

[0157] More precisely, the second gate-trough electrode structure 142 comprises a second gate trench 143, a second gate insulating layer 144, a second gate electrode layer 145, a plurality of second gate embedding holes 146, and a plurality of second embedded gate insulating layers 147. The second gate electrode layer 145 is at the same electrical potential as the gate electrode layer 14.

[0158] The second gate trench 143, the second gate insulating layer 144, the second gate electrode layer 145, the second gate embedding hole 146, and the second embedded gate insulating layer 147 have the same structure as the gate trench 12, the gate insulating layer 13, the gate electrode layer 14, the gate embedding hole 15, and the embedded gate insulating layer 16, respectively. A detailed description of the second gate trench electrode structure 142 is omitted.

[0159] The n +The emitter region 25 is formed in a region along the side wall of the second gate trench 143 in the surface layer portion of body region 8. The emitter regions 25 are formed along one side of the side wall and the other side of the side wall of the second gate trench 143 with respect to the first direction X. The emitter regions 25 are each band-shaped along the second direction Y.

[0160] In the present preferred embodiment, the emitter region 25 formed along the side wall of the gate trench 12 is formed integrally with the emitter region 25 formed along the side wall of the second gate trench 143. In other words, the emitter region 25 is divided between the gate trench 12 and the second gate trench 143 within a region between the gate trench 12 and the second gate trench 143.

[0161] Each of the first contact holes 31 has a first cutting region 148 that intersects the gate electrode layer 14 in a top view. At the first cutting region 148, a side wall and a bottom wall of the first contact holes 31 are defined by the embedded gate insulating layer 16.

[0162] Each of the first contact holes 31 has a second cut region 149 that intersects the second gate electrode layer 145 in a top view. At the second cut region 149, the side wall and bottom wall of each of the first contact holes 31 are defined by the second embedded gate insulating layer 147.

[0163] Each of the first contact holes 31 has a connecting region 150 through which the first cut region 148 and the second cut region 149 are connected in a plan view in a region between the gate trench 12 and the second gate trench 143. In the connecting region 150, the side wall and the bottom wall of each of the first contact holes 31 are defined by the semiconductor layer 2.

[0164] The side wall of each of the first contact holes 31 is designed to be flush with the first cutting region 148, the second cutting region 149, and the connecting region 150. The bottom wall of each of the first contact holes 31 is designed to be flush with the first cutting region 148, the second cutting region 149, and the connecting region 150.

[0165] In the present preferred embodiment, each of the emitter contact electrode layers 51 has a first cutting region 151 that intersects the gate electrode layer 14 in a top view. At the first cutting region 151, each of the emitter contact electrode layers 51 faces the gate electrode layer 14, with the embedded gate insulating layer 16 located between the emitter contact electrode layer 51 and the gate electrode layer 14 in the normal direction Z and the second direction Y. Each of the emitter contact electrode layers 51 is insulated from the gate electrode layer 14 via the embedded gate insulating layer 16.

[0166] Each of the emitter contact electrode layers 51 has a second section region 152 that intersects the second gate electrode layer 145 in a top view. At the second section region 152, each of the emitter contact electrode layers 51 is opposite the second gate electrode layer 145, with the second embedded emitter insulating layer 147 located between the emitter contact electrode layer 51 and the second gate electrode layer 145 with respect to the normal direction Z and the second direction Y.

[0167] Each of the emitter contact electrode layers 51 has a connection region 153 through which the first section region 151 and the second section region 152 are connected to each other in a top view in the region between the gate trench 12 and the emitter trench 143. In the connection region 153, each of the emitter contact electrode layers 51 is connected to the body region 8, to the emitter region 25, and to the contact region 36.

[0168] As described above, the same effect can be achieved with semiconductor device 141 as with semiconductor device 1. Semiconductor device 141 can be manufactured by changing the layout of the masks in the manufacturing process of semiconductor device 1.

[0169] Fig. Figure 17 is a perspective sectional view showing a region of a part of a semiconductor device 161 according to an eighth preferred embodiment of the present invention, wherein a structure on the first main surface 3 has been removed. The same reference numeral is assigned below to a component corresponding to a component of the semiconductor device 141 mentioned above, and a description of this component is omitted.

[0170] In Fig. In the present preferred embodiment, the first contact holes 31 contain a first contact hole 162A and a second contact hole 162B. In plan view, the first contact hole 162A intersects only the gate trench 12. In plan view, the first contact hole 162B intersects only the second gate trench 143.

[0171] In the present preferred embodiment, the emitter contact electrode layers 51 comprise an emitter contact electrode layer 163A and an emitter contact electrode layer 163B. The emitter contact electrode layer 163A is embedded in the first contact hole 162A. In the top view, the emitter contact electrode layer 163A intersects only the gate trench 12. The emitter contact electrode layer 163B is embedded in the first contact hole 162A. In the top view, the emitter contact electrode layer 163B intersects only the second gate trench 143.

[0172] As described above, the same effect can be achieved with semiconductor device 161 as with semiconductor device 1. Semiconductor device 161 can be manufactured by changing the layout of the masks in the manufacturing process of semiconductor device 1.

[0173] Fig. Figure 18 is a perspective sectional view showing a region of a part of a semiconductor device 171 according to a ninth preferred embodiment of the present invention, wherein a structure on the first main surface 3 has been removed. The same reference numeral is assigned below to a component corresponding to a component of the semiconductor device 1 mentioned above, and a description of this component is omitted.

[0174] In Fig. In the present preferred embodiment, the gate-trough electrode structures 10 are formed in the surface layer portion of the first main surface 3. In this preferred embodiment, the gate-trough electrode structures 10 comprise a first gate-trough electrode structure 172 and a second gate-trough electrode structure 173, which are formed with a space between them.

[0175] The first gate-trough electrode structure 172 and the second gate-trough electrode structure 173 are arranged at a distance along the first direction X. In a top view, the first gate-trough electrode structure 172 and the second gate-trough electrode structure 173 extend in a band-like fashion along the second direction Y.

[0176] The trench spacing PT between the first gate-trench electrode structure 172 and the second gate-trench electrode structure 173 should be not less than 1.6 µm and not more than 4.8 µm. The spacing PR should be not less than 1.6 µm and not more than 2.4 µm, not less than 2.4 µm and not more than 3.2 µm, not less than 3.2 µm and not more than 4.0 µm, or not less than 4.0 µm and not more than 4.8 µm. Preferably, the trench spacing P0 should be not less than 0.2 µm and not more than 0.4 µm (for example, about 0.25 µm).

[0177] The first gate-trough electrode structure 172 comprises a first gate trench 174, a first gate insulating layer 175, a first gate electrode layer 176, a plurality of first gate embedding holes 177 and a plurality of first embedded gate insulating layers 178.

[0178] The first gate trench 174, the first gate insulating layer 175, the first gate electrode layer 176, the first gate embedding hole 177, and the first embedded gate insulating layer 178 have the same structure as the gate trench 12, the gate insulating layer 13, the gate electrode layer 14, the gate embedding hole 15, and the embedded gate insulating layer 16, respectively, according to the first preferred embodiment. A detailed description of the first gate trench electrode structure 172 is omitted.

[0179] More precisely, the second gate trench electrode structure 173 comprises a second gate trench 184, a second gate insulating layer 185, a second gate electrode layer 186, a plurality of second gate embedding holes 187 and a plurality of second embedded gate insulating layers 188.

[0180] The second gate trench 184, the second gate insulating layer 185, the second gate electrode layer 186, the second gate embedding hole 187, and the second embedded gate insulating layer 188 have the same structure as the gate trench 12, the gate insulating layer 13, the gate electrode layer 14, the gate embedding hole 15, and the embedded gate insulating layer 16 according to the first preferred embodiment. A detailed description of the second gate trench electrode structure 173 is omitted.

[0181] A plurality of (two or more) trench-emitter electrode structures 11 are formed in a region between the first gate-trench electrode structure 172 and the second gate-trench electrode structure 173 in the surface layer portion of the first main surface 3. In the present preferred embodiment, the trench-emitter electrode structures 11 comprise a first trench-emitter electrode structure 191 and a second trench-emitter electrode structure 192, which are formed at a distance from each other.

[0182] Only one trench-emitter electrode structure should be formed in the region between the first trench-emitter electrode structure 172 and the second gate-trough electrode structure 173. Furthermore, four or more trench-emitter electrode structures 11 can be formed in the region between the first gate-trough electrode structure 172 and the second gate-trough electrode structure 173.

[0183] The first trench-emitter electrode structure 191 and the second trench-emitter electrode structure 192 are formed at a distance from each other along the first direction X. In a top view, the first trench-emitter electrode structure 191 and the second trench-emitter electrode structure 192 extend in a band-like fashion along the second direction Y.

[0184] The first trench-emitter electrode structure 191 comprises a first emitter trench 193, a first emitter insulating layer 194, a first emitter electrode layer 195, a first emitter embedding hole 196 and a first embedded emitter insulating layer 197.

[0185] The first emitter trench 193, the first emitter insulating layer 194, the first emitter electrode layer 195, the first emitter embedding hole 196, and the first embedded emitter insulating layer 197 have the same structure as the emitter trench 17, the emitter insulating layer 18, the emitter electrode layer 19, the emitter embedding hole 20, and the embedded emitter insulating layer 21, respectively, according to the first preferred embodiment. A detailed description of the first trench-emitter electrode structure 191 is omitted.

[0186] The second trench-emitter electrode structure 192 comprises a second emitter trench 203, a second emitter insulating layer 204, a second emitter electrode layer 205, a second emitter embedding hole 206 and a second embedded emitter insulating layer 207.

[0187] The second emitter trench 203, the second emitter insulating layer 204, the second emitter electrode layer 205, the second emitter embedding hole 206, and the second embedded emitter insulating layer 207 have the same structure as the emitter trench 17, the emitter insulating layer 18, the emitter electrode layer 19, the emitter embedding hole 20, and the embedded emitter insulating layer 21, respectively, according to the first preferred embodiment. A detailed description of the second trench-emitter electrode structure 192 is omitted.

[0188] The first trench spacing P1 between the first trench-gate electrode structure 172 and the first trench-emitter electrode structure 191 should be not less than 0.1 µm and less than 0.6 µm. The first trench spacing P1 should be not less than 0.1 µm and not more than 0.2 µm, not less than 0.2 µm and not more than 0.3 µm, not less than 0.3 µm and not more than 0.4 µm, not less than 0.4 µm and not more than 0.5 µm, or not less than 0.5 µm and less than 0.6 µm. Preferably, the first trench spacing P1 should be not less than 0.2 µm and not more than 0.4 µm (for example, about 0.25 µm).

[0189] The second trench spacing P2 between the first trench-emitter electrode structure 191 and the second trench-emitter electrode structure 192 should be not less than 0.1 µm and less than 0.6 µm. The second trench spacing P2 should be not less than 0.1 µm and not more than 0.2 µm, not less than 0.2 µm and not more than 0.3 µm, not less than 0.3 µm and not more than 0.4 µm, not less than 0.4 µm and not more than 0.5 µm, or not less than 0.5 µm and less than 0.6 µm. Preferably, the second trench spacing P2 should be not less than 0.2 µm and not more than 0.4 µm (for example, about 0.25 µm).

[0190] The third trench spacing P3 between the second trench-gate electrode structure 173 and the second trench-emitter electrode structure 192 should be not less than 0.1 µm and less than 0.6 µm. The third trench spacing P3 should be not less than 0.1 µm and not more than 0.2 µm, not less than 0.2 µm and not more than 0.3 µm, not less than 0.3 µm and not more than 0.4 µm, not less than 0.4 µm and not more than 0.5 µm, or not less than 0.5 µm and less than 0.6 µm. Preferably, the third trench spacing P3 should be not less than 0.2 µm and not more than 0.4 µm (for example, about 0.25 µm).

[0191] The emitter region 25 is not formed in the region between the first trench-emitter electrode structure 191 and the second trench-emitter electrode structure 192 in the surface layer portion of the first main surface 3. A p-like contamination region 208 is formed in the region between the first trench-emitter electrode structure 191 and the second trench-emitter electrode structure 192 in the surface layer portion of the first main surface 3.

[0192] Contamination region 208 is exposed from the side wall of the first emitter trench 193 and from the side wall of the second emitter trench 203. Contamination region 208 is formed in the surface layer portion of charge storage region 6. Contamination region 208 is exposed from the first main surface 3. Contamination region 208 is formed at a depth corresponding to the depth of body region 8. Contamination region 208 has a p-type contamination concentration corresponding to the p-type contamination concentration of body region 8. Contamination region 208 differs from body region 8 in its electrical properties in that it is not electrically connected to emitter region 25.

[0193] In the present preferred embodiment, the first contact holes 31 are configured with spacings between them along the second direction Y, each extending in a band-like fashion along the first direction X in a top view. In the present preferred embodiment, each of the first contact holes 31 intersects the first gate-trough electrode structure 172, the first trench-emitter electrode structure 191, the second trench-emitter electrode structure 192, and the second gate-trough electrode structure 173.

[0194] In the present preferred embodiment, the emitter contact electrode layers 51 are configured with spacings between them along the second direction Y, which, in plan view, extend in a band-like fashion along the first direction X. In the present preferred embodiment, each of the emitter contact electrode layers 51 intersects the first gate-trough electrode structure 172, the first trench-emitter electrode structure 191, the second trench-emitter electrode structure 192, and the second gate-trough electrode structure 173. Each of the emitter contact electrode layers 51 is connected to the body region 8, the emitter region 25, the contact region 36, and the impurity region 208 in a portion adjacent to the semiconductor layer 2.

[0195] As described above, the same effect can be achieved with semiconductor device 171 as with semiconductor device 1. Semiconductor device 171 can be manufactured by changing the layout of the masks in the manufacturing process of semiconductor device 1.

[0196] Fig. Figure 19 is a perspective sectional view showing a region of a part of a semiconductor device 211 according to a tenth preferred embodiment of the present invention, in which a structure on the first main surface 3 has been removed. The same reference numeral is assigned below to a component corresponding to a component of the semiconductor device 171 mentioned above, and a description of this component is omitted.

[0197] In Fig. In the present preferred embodiment, the first contact holes 31 comprise a plurality of first contact holes 212A and a plurality of first contact holes 212B. The first contact holes 212A are arranged with spacings between them along the first gate trench 174 (second direction Y) in a top view. Each first contact hole 212A intersects only the first gate trench 174 in a top view.

[0198] The first contact holes 212B are arranged with intervals between them along the second gate trench 184 (second direction Y) in a top view. In the present preferred embodiment, the first contact holes 212B are opposite the corresponding first contact holes 212A along the first direction X. The first contact holes 212A each intersect only the second gate trench 184 in a top view.

[0199] In the present preferred embodiment, the emitter contact electrode layers 51 comprise a plurality of emitter contact electrode layers 213A and a plurality of emitter contact electrode layers 213B. The emitter contact electrode layers 213A are each embedded in corresponding first contact holes 212A. The emitter contact electrode layers 213A are formed with spacings between them along the first gate trench 174 (second direction Y) in a top view. In a top view, the emitter contact electrode layers 213A only intersect the first gate trench 174.

[0200] The emitter contact electrode layers 213B are each embedded in corresponding first contact holes 212B. The emitter contact electrode layers 213B are formed with spacing between them along the first gate trench 184 (second direction Y) in plan view. In plan view, the emitter contact electrode layers 213B only intersect the second gate trench 184. In other words, in this preferred embodiment, each of the emitter contact electrode layers 51 is not electrically connected to the impurity region 208. The impurity region 208 is formed in an electrically suspended state.

[0201] As described above, the same effect can be achieved with semiconductor device 211 as with semiconductor device 1. Semiconductor device 211 can be manufactured by changing the layout of the masks in the manufacturing process of semiconductor device 1.

[0202] Fig. Figure 20 is a perspective sectional view showing a region of a part of a semiconductor device 221 according to an eleventh preferred embodiment of the present invention, in which a structure on the first main surface 3 has been removed. Hereafter, the same reference numeral is used for a component corresponding to a component of the semiconductor device 171 shown according to the ninth preferred embodiment, and a description of this component is omitted.

[0203] An example was described in which the p-like collector region 5 was formed in the surface layer portion of the second main surface 4 in the semiconductor device 171. In contrast, in the semiconductor device 221, an n-like drain region 222 is formed instead of the p-like collector region 5 in the surface layer portion of the second main surface 4.

[0204] Accordingly, the semiconductor device 221 has a basic form of a gate-trough type MISFET (metal-insulator-semiconductor field-effect transistor). A description of the semiconductor device 171 applies analogously to the semiconductor device 221, whereby "emitter" is read as "source" and "collector" as "drain".

[0205] As described above, the same effect can be achieved with semiconductor device 221 as with semiconductor device 1. Semiconductor device 221 can be fabricated by simply forming the n-type drain region 222 instead of the p-type collector region 5 and by changing the mask layout in the fabrication process of semiconductor device 1.

[0206] Naturally, a structure in which the drain region 222 is formed can also be applied to preferred embodiments other than the ninth preferred embodiment (semiconductor device 171). In this case, “emitter” is read as “source” and “collector” as “drain” in the respective preferred embodiment in which the drain region 222 is used.

[0207] Fig. Figure 21 is a perspective sectional view showing a region of a part of a semiconductor device 241 according to a twelfth preferred embodiment of the present invention, in which a structure on the first main surface 3 has been removed. The same reference numeral is assigned below to a component corresponding to a component of the semiconductor device 171 mentioned above, and a description of this component is omitted.

[0208] The semiconductor device 241 has a structure in which the semiconductor device 141 (see Fig. 16) according to the seventh preferred embodiment with the semiconductor device 171 (see Fig. 18) according to the ninth preferred embodiment. In other words, the semiconductor device 241 does not contain a trench-emitter electrode structure 11. The semiconductor device 241 has a plurality of gate-trench electrode structures 10.

[0209] The gate-trough electrode structures 10 are formed with spacing between them along the first direction X. The gate-trough electrode structures 10 extend in a band-like fashion along the second direction Y in a top view.

[0210] The trench spacing PG between the gate-trough electrode structure 10 should be not less than 0.1 µm and not less than 0.6 µm. The trench spacing PG should be not less than 0.1 µm and not more than 0.2 µm, not less than 0.2 µm and not more than 0.3 µm, not less than 0.3 µm and not more than 0.4 µm, not less than 0.4 µm and not more than 0.5 µm, or not less than 0.5 µm and less than 0.6 µm. Preferably, each trench spacing PG should be no less than 0.2 µm and no more than 0.4 µm (for example, approximately 0.25 µm). The trench spacings PG can be configured so that they have the same value, or they can be configured so that they have different values.

[0211] The gate-trough electrode structure 10 each has the gate trench 12, the gate insulating layer 13, the gate electrode layer 14, the gate embedding holes 15 and the embedded gate insulating layer 16. A description of the gate trench 12, the gate insulating layer 13, the gate electrode layer 14, the gate embedding holes 15 and the embedded gate insulating layer 16 is omitted.

[0212] In the present preferred embodiment, the first contact holes 31 are configured with spacings between them along the second direction Y in a top view, each extending in a band-like fashion along the first direction X. In the present preferred embodiment, the first contact holes 31 intersect the gate-trough electrode structure 10 in a top view.

[0213] In the present preferred embodiment, the emitter contact electrode layers 51 are configured with spacings between them along the second direction Y in a top view, each extending in a band-like fashion along the first direction X. In this preferred embodiment, the emitter contact electrode layers 51 intersect the gate-trough electrode structure 10 in a top view. Each of the emitter contact electrode layers 51 is connected to the body region 8, the emitter region 25, and the contact region 36 in a portion adjacent to the semiconductor layer 2.

[0214] As described above, the same effect can be achieved with semiconductor device 241 as with semiconductor device 1. Semiconductor device 241 can be manufactured by changing the layout of the masks in the manufacturing process of semiconductor device 1.

[0215] Fig. Figure 22 is a perspective sectional view showing an area of ​​part of a semiconductor device 251 according to a thirteenth preferred embodiment of the present invention. Fig. Figure 23 is a perspective sectional view showing the area of ​​part 251 of the semiconductor device. Fig. Figure 22 shows a structure removed from the first main surface 3. Fig. 24 is a top view of Fig. 23. Fig. 25 is a sectional view along line XXV-XXV in Fig. 24. Hereinafter, the same reference numeral will be used for a component corresponding to a component of the semiconductor device 211 mentioned above (see Fig. ), and a description of this component is omitted.

[0216] In Fig. 22 to Fig. 25 contain the first contact holes 31 a plurality of first contact holes 212A and a plurality of first contact holes 212B in the same way as the semiconductor device 211. In Fig. In the present preferred embodiment, the bottom wall of each of the first contact holes 212A is formed in a non-uniform shape, rising towards the first main surface 3 and descending towards the second main surface 4. More precisely, each of the first contact holes 212A contains a first region 252, which is formed in the first gate groove 174, and a second region 253, which is formed in the semiconductor layer 2.

[0217] The side wall and bottom wall of the first region 252 are defined by the first gate insulating layer 175 and the first embedded gate insulating layer 178, respectively. The bottom wall of the first region 252 is located on the side of the second main surface 4 relative to the first main surface 3 with respect to the thickness direction of the semiconductor layer 2. More precisely, the bottom wall of the first region 252 is located in a region between the first main surface 3 and the lower part of the body region 8 with respect to the thickness direction of the semiconductor layer 2. Of course, the bottom wall of the first region 252 can also be located on the same plane as the first main surface 3. In other words, a first contact hole 212A without a first region 252 can be formed.

[0218] A side wall and a bottom wall of the second region 253 are defined by the semiconductor layer 2 and by the gate-trough electrode structure 10 (the first gate-trough electrode structure 172). The side wall of the second region 253 can be defined by the first gate insulating layer 175 and / or by the first embedded gate insulating layer 178. The bottom wall of the second region 253 is located in a region between the bottom wall of the first region 252 and the lower part of the body region 8 with respect to the thickness direction of the semiconductor layer 2. More precisely, the bottom wall of the second region 253 is located in a region between the lower part of the emitter region 25 and the lower part of the body region 8 with respect to the thickness direction of the semiconductor layer 2.

[0219] In relation to Fig. In the present preferred embodiment, the bottom wall of each of the first contact holes 212B is formed in a non-uniform shape, rising towards the first main surface 3 and descending towards the second main surface 4. More precisely, each of the first contact holes 212A contains a first region 254, which is formed in the first gate groove 184, and a second region 255, which is formed in the semiconductor layer 2.

[0220] The side wall and bottom wall of the first region 254 are defined by the second gate insulating layer 185 and the second embedded gate insulating layer 188, respectively. The bottom wall of the first region 254 is located on the side of the second main surface 4 relative to the first main surface 3 with respect to the thickness direction of semiconductor layer 2. More precisely, the bottom wall of the first region 254 is positioned in the region between the first main surface 3 and the lower part of body region 8 with respect to the thickness direction of semiconductor layer 2. Of course, the bottom wall of the first region 254 can be arranged on the same plane as the first main surface 3. In other words, a first contact hole 212B without a first region 254 can be formed.

[0221] A side wall and a bottom wall of the second region 255 are defined by the semiconductor layer 2 and by the gate-trough electrode structure 10. The side wall of the second region 255 can be defined by the second gate insulating layer 185 and / or by the second embedded gate insulating layer 188.

[0222] The bottom wall of the second region 255 is located in a region between the bottom wall of the first region 254 and the lower part of body region 8 with respect to the thickness direction of semiconductor layer 2. More precisely, the bottom wall of the second region 255 is located in a region between the lower part of emitter region 25 and the lower part of body region 8 with respect to the thickness direction of semiconductor layer 2.

[0223] The first contact holes 31 according to the present preferred embodiment can be produced by changing the layout of the masks and the etching conditions in the fabrication process of the semiconductor device 1. In other words, the first contact holes 31 are formed by removing an unnecessary portion of the semiconductor layer 2, such that the bottom wall of the first contact hole 31 is located in a region on the side of the second main surface 4 relative to the upper surface of the first embedded gate insulating layer 178 (the second embedded gate insulating layer 188) when a step to remove the semiconductor layer 2 is performed (see Fig. At this point, the first gate insulating layer 175, which is intended to define the second region 253, can be completely or partially removed by the etching method. The second gate insulating layer 185, which is intended to define the second region 255, can also be completely or partially removed by an etching process.

[0224] The emitter main surface electrode layer 43 comprises a plurality of emitter contact electrode layers 51 and a main surface electrode layer 256. The emitter contact electrode layers 51 comprise a plurality of emitter contact electrode layers 213A and a plurality of emitter contact electrode layers 213B.

[0225] The emitter contact electrode layers 213A are each embedded in corresponding first contact holes 212A. Each of the emitter contact electrode layers 213A has an uneven section that engages with the first region 252 and with the second region 253 in the corresponding first contact hole 212A.

[0226] Each of the emitter contact electrode layers 213A contains a first electrode layer 44 and a second electrode layer 45. The first electrode layer 44 defines a concave first space SP1 in the first region 252. The first electrode layer 44 further defines a concave second space SP2 in the second region 253. If the bottom wall of the first region 252 lies on the same plane as the first main surface 3, the first space SP1 is not formed, and only the second space SP2 is formed.

[0227] The second electrode layer 45 fills the first space SP1 and the second space SP2 in the first contact hole 212A. In this way, each of the emitter contact electrode layers 213A is formed, which has an uneven section that engages with the first region 252 and with the second region 253.

[0228] The emitter contact electrode layers 213B are each embedded in corresponding first contact holes 212B. Each of the emitter contact electrode layers 213B has an uneven section that engages with the first region 254 and with the second region 255 in the corresponding first contact hole 212B.

[0229] Each of the emitter contact electrode layers 213B contains the first electrode layer 44 and the second electrode layer 45. The first electrode layer 44 defines a concave first space SP3 in the first region 254. The first electrode layer 44 further defines a concave second space SP4 in the second region 255. If the bottom wall of the first region 254 lies on the same plane as the first main surface 3, the first space SP3 is not formed, and only the second space SP4 is formed.

[0230] The second electrode layer 45 fills the first space SP3 and the second space SP4 in the first contact hole 212B. In this way, each of the emitter contact electrode layers 213B is formed, which has an uneven section that engages with the first region 254 and with the second region 255.

[0231] The main surface electrode layer 256 covers the emitter main surface electrode layer 51 on the insulating intermediate layer 41. The main surface electrode layer 256 has a layered structure with a first main surface electrode layer 257 and a second main surface electrode layer 258, which are stacked on top of each other in this order from the side of the insulating intermediate layer 41.

[0232] The first main surface electrode layer 257 serves as the base layer of the second main surface electrode layer 258. The first main surface electrode layer 257 is designed as a barrier electrode layer that suppresses diffusion of the second main surface electrode layer 258.

[0233] The first main surface electrode layer 257 is formed in film form along the main surface of the insulating intermediate layer 41 and together covers the emitter contact electrode layers 51. The first main surface electrode layer 257 is connected to the emitter contact electrode layers 51.

[0234] The first main surface electrode layer 257 can have a layered structure with a titanium layer and a titanium nitride layer, stacked on top of each other in that order from the side of the insulating intermediate layer 41. The first main surface electrode layer 257 can have a single-layer structure with either a titanium layer or a titanium nitride layer.

[0235] The second main surface electrode layer 258 is formed in film form on the first main surface electrode layer 257. The second main surface electrode layer 258 is electrically connected to the emitter contact electrode layers 51 via the first electrode layer 44.

[0236] The second main surface electrode layer 258 can contain at least one type of aluminum, copper, an aluminum alloy, and a copper alloy. Preferably, the second main surface electrode layer 258 consists of a conductive material containing aluminum as the main element. The second main surface electrode layer 258 can contain an Al-Si-Cu (aluminum-silicon-copper) alloy, an Al-Si (aluminum-silicon) alloy, and / or an Al-Cu (aluminum-copper) alloy, each of which is an example of the aluminum alloy.

[0237] The main surface electrode layer 256 is formed on the insulating intermediate layer 41 after the emitter contact electrode layers 51 have each been embedded in corresponding contact holes 31. One step to form the main surface electrode layer 256 comprises a step to form the first main surface electrode layer 257 and the second main surface electrode layer 258 in that order from the side of the insulating intermediate layer 41.

[0238] The first main surface electrode layer 257 can be formed by a sputtering process. The second main surface electrode layer 258 can be formed by a cathode sputtering process, a vapor deposition process, a CVD process, or a plating process.

[0239] As described above, the same effect can be achieved with semiconductor device 251 as with semiconductor device 1. Naturally, the structure of semiconductor device 251 is also applicable to preferred embodiments other than the thirteenth preferred embodiment.

[0240] Fig. Figure 26 is a perspective sectional view of the region accordingly. Fig. 22, which shows a region of a part of a semiconductor device 261 according to a fourteenth preferred embodiment of the present invention. Fig. 27 is a sectional view of the area which Fig. 25 corresponds to, and shows an area of ​​a part of the semiconductor device 261, which is in Fig. 26 is shown. The same reference symbol is subsequently used for a component corresponding to a component of the semiconductor device 251 mentioned above (see Fig. ), and a description of this component is omitted.

[0241] In Fig. 26 and Fig. 27 The emitter contact electrode layers 51 contain a plurality of emitter contact electrode layers 213A and a plurality of emitter contact electrode layers 213B. In the present preferred embodiment, each of the emitter contact electrode layers 213A contains a first contact electrode layer 262 and a second contact electrode 263, both of which contain mutually different conductive materials as principal elements.

[0242] The first contact electrode layer 262 contains tungsten as its main element and is embedded in the first contact hole 212A. The second contact electrode 263 contains aluminum as its main element and is embedded in the second contact hole 42, which is connected to the first contact hole 212A.

[0243] More precisely, the first contact electrode layer 262 is embedded in the second region 253 of the first contact hole 212A. The first contact electrode layer 262 is connected to body region 8, emitter region 25, and contact region 36 in the second region 253.

[0244] An upper end section of the first contact electrode layer 262 can be arranged on the same plane as the bottom wall of the first region 252 or on the bottom section side of the body region 8 relative to the bottom wall of the first region 252.

[0245] The first contact electrode layer 262 comprises a first electrode layer 44 and a second electrode layer 45. The first electrode layer 44 is formed in film form along an inner wall of the second region 253. The first electrode layer 44 defines a concavely shaped space in the second region 253. The first electrode layer 44 is connected to the body region 8, the emitter region 25, and the contact region 36.

[0246] The second electrode layer 45 is embedded in a concave space defined by the first electrode layer 44 in the second region 253. The second electrode layer 45 is electrically connected to body region 8, emitter region 25, and contact region 36 via the first electrode layer 44.

[0247] The second contact electrode 263 is formed by using a portion of the main surface electrode layer 256. In the present preferred embodiment, the main surface electrode layer 256 extends from above out of the insulating intermediate layer 41 into the second contact hole 42. In the present preferred embodiment, the main surface electrode layer 256 also extends into the first contact hole 31 (the first region 252) from the second contact hole 42. If the first region 252 is not formed in the first contact hole 212A, the main surface electrode layer 256 is structured such that it is embedded only in the second contact hole 42.

[0248] More precisely, the first main surface electrode layer 257 of the main surface electrode layer 256 is formed in film form along the main surface of the insulating intermediate layer 41 and the inner wall of the second contact hole 42. The first main surface electrode layer 257 defines a concavely shaped space in the second contact hole 42. The first main surface electrode layer 257 is connected to the first contact electrode layer 262 in the second contact hole 42. The first main surface electrode layer 257 can be connected to the emitter region 25 according to the position of the upper end portion of the first contact electrode layer 262.

[0249] The second main surface electrode layer 258 of the main surface electrode layer 256 is formed on the first main surface electrode layer 257. The second main surface electrode layer 258 enters the second contact hole 42 from above through the insulating intermediate layer 41. The second main surface electrode layer 258 fills a concave space defined by the first main surface electrode layer 257 in the second contact hole 42. The second main surface electrode layer 258 is electrically connected to the first contact electrode layer 262 via the first main surface electrode layer 257.

[0250] In this way, the second contact electrode 263 is formed using a portion of the main surface electrode layer 256. Of course, the second contact electrode 263 can be designed as a structurally independent component from the main surface electrode layer 256.

[0251] In the present preferred embodiment, each of the emitter contact electrode layers 213B comprises a first contact electrode layer 264 and a second contact electrode 265, both of which contain mutually different conductive materials as their principal elements. The first contact electrode layer 264 and the second contact electrode layer 265 have a structure corresponding to the first contact electrode layer 262 and a structure corresponding to the second contact electrode 263, respectively. A detailed description of the first contact electrode layer 264 and the second contact electrode layer 265 is omitted.

[0252] As described above, the same effect can be achieved with semiconductor device 261 as with semiconductor device 1. Naturally, the structure of semiconductor device 261 is also applicable to preferred embodiments other than the fourteenth preferred embodiment.

[0253] Fig. 28 is a top view of the region accordingly Fig. 24, which shows a region of a part of a semiconductor device 271 according to a fifteenth preferred embodiment of the present invention. Fig. 29 is a sectional view along line XXIX-XXIX in Fig. 28. Hereinafter, the same reference numeral will be used for a component corresponding to a component of the semiconductor device 251 mentioned above (see Fig. ), and a description of this component is omitted.

[0254] In Fig. 28 and Fig. In the currently preferred embodiment, the first contact holes 212A comprise a first sidewall contact hole 272 and a second sidewall contact hole 273. The first sidewall contact hole 272 is formed on one side of the wall side of the first gate trench 174. The second sidewall contact hole 273 is formed on the other side of the wall side of the first gate trench 174.

[0255] The first sidewall contact holes 272 are formed with spacing between them along the second direction Y. Each of the first sidewall contact holes 272 extends through one sidewall from the inside of the first gate groove 174 and is pulled out to the surface layer portion of the first main surface 3 of the semiconductor layer 2.

[0256] In the present preferred embodiment, each of the first sidewall contact holes 272 passes through a sidewall of the emitter trench 17 (of the second emitter trench 203) that adjoins a sidewall of the first gate trench 174 and extends into the emitter trench 17 (not shown in detail). Each of the first sidewall contact holes 272 need not necessarily extend into the emitter trench 17 and may be formed extending away from the emitter trench 17.

[0257] Each of the first sidewall contact holes 272 has one end section located in the first gate trench 174 and another end section located in the emitter trench 17 with respect to the first direction X. The end section of each of the first sidewall contact holes 272 is formed away from the other sidewall of the first gate trench 174. The other end section of each of the first sidewall contact holes 272 is formed away from the other sidewall of the emitter trench 17.

[0258] Each of the first sidewall contact holes 272 is rectangular in plan view. In the present preferred embodiment, each of the first sidewall contact holes 272 is ribbon-shaped (rectangular) and extends along the first direction X in plan view. The width WX in the first direction X of each of the first sidewall contact holes 272 is greater than 0 µm and not greater than 1 µm. The width WY in the second direction Y of each of the first sidewall contact holes 272 is greater than 0 µm and not greater than 1 µm.

[0259] The second side wall contact holes 273 are configured with spacing between them along the second direction Y. In the present preferred embodiment, each of the second side wall contact holes 273 is opposite a corresponding first side wall contact hole 272 along the first direction X.

[0260] Each of the second sidewall contact holes 273 extends from the inside of the first gate trench 174 through the other sidewall and is drawn out to the surface layer portion of the first main face 3 of the semiconductor layer 2. In the present preferred embodiment, each of the second sidewall contact holes 273 extends through one sidewall of the first emitter trench 193 and is drawn out into the first emitter trench 193. Each of the second sidewall contact holes 273 is not necessarily drawn into the first emitter trench 193 and may be formed extending away from the first emitter trench 193.

[0261] Each of the second sidewall contact holes 273 has one end section located in the first gate trench 174 and another end section located in the first emitter trench 193 with respect to the first direction X. One end section of each of the second sidewall contact holes 273 is formed away from one sidewall of the first gate trench 174. More precisely, one end section of each of the second sidewall contact holes 273 is formed away from the first sidewall contact hole 272. The other end section of each of the second sidewall contact holes 273 is formed away from the other sidewall of the first emitter trench 193.

[0262] Each of the second sidewall contact holes 273 is rectangular in plan view. In the present preferred embodiment, each of the first sidewall contact holes 273 is ribbon-shaped (rectangular) and extends along the first direction X in plan view. The width WX in the first direction X of each of the first sidewall contact holes 273 is greater than 0 µm and not greater than 1 µm. The width WY in the second direction Y of each of the first sidewall contact holes 273 is greater than 0 µm and not greater than 1 µm.

[0263] One end section of each of the first sidewall contact holes 272 and one end section of each of the second sidewall contact holes 273 are jointly defined by the first embedded gate insulating layer 178 in the first gate trench 174. A portion of the first embedded gate insulating layer 178 is located in a region between one end section of each of the first sidewall contact holes 272 and one end section of each of the second sidewall contact holes 273.

[0264] In the present preferred embodiment, the first contact holes 212B comprise a first sidewall contact hole 274 and a second sidewall contact hole 275. The first sidewall contact hole 274 is formed on the first side of the wall side of the second gate trench 184. The second sidewall contact hole 275 is formed on the far side of the wall side of the second gate trench 184.

[0265] The first sidewall contact holes 274 are formed with spacing between them along the second direction Y. Each of the first sidewall contact holes 274 extends through one sidewall from the inside of the second gate trench 184 and is drawn out to the surface layer portion of the first main surface 3 of the semiconductor layer 2. In the present preferred embodiment, each of the first sidewall contact holes 274 extends through one sidewall of the second emitter trench 203 and is drawn out into the second emitter trench 203. Each of the first sidewall contact holes 274 need not necessarily be drawn out into the second emitter trench 203 and can be formed extending away from the second emitter trench 203.

[0266] Each of the first sidewall contact holes 274 has one end section located in the second gate trench 184 and another end section located in the second emitter trench 203 with respect to the first direction X. One end section of each of the first sidewall contact holes 274 is formed away from the other sidewall of the second gate trench 184. The other end section of each of the first sidewall contact holes 274 is formed away from the other sidewall of the emitter trench 203.

[0267] Each of the first sidewall contact holes 274 is rectangular in plan view. In the present preferred embodiment, each of the first sidewall contact holes 274 is ribbon-shaped (rectangular) and extends along the first direction X in plan view. The width WX in the first direction X of each of the first sidewall contact holes 274 is greater than 0 µm and not greater than 1 µm. The width WY in the second direction Y of each of the first sidewall contact holes 274 is greater than 0 µm and not greater than 1 µm.

[0268] The second sidewall contact holes 275 are configured with spacing between them along the second direction Y. In the present preferred embodiment, each of the second sidewall contact holes 275 is opposite a corresponding first sidewall contact hole 274 along the first direction X. The second sidewall contact holes 275 extend from the inside of the second gate groove 184 through the other sidewall and are each drawn out to the surface layer portion of the first main surface 3 of the semiconductor layer 2.

[0269] In the present preferred embodiment, each of the second sidewall contact holes 275 extends through one sidewall of the emitter trench 17 (of the first emitter trench 193), which adjoins the other sidewall of the second gate trench 184, and is drawn out into the emitter trench 17 (not shown in detail). Each of the first sidewall contact holes 275 need not necessarily be drawn into the emitter trench 17 and can be formed facing away from the emitter trench 17.

[0270] Each of the second sidewall contact holes 275 has one end section located in the first gate trench 184 and another end section located in the first emitter trench 17 with respect to the first direction X. One end section of each of the second sidewall contact holes 275 is formed away from one sidewall of the first gate trench 184. More precisely, one end section of each of the second sidewall contact holes 275 is formed away from the first sidewall contact hole 274. The other end section of each of the first sidewall contact holes 275 is formed away from the other sidewall of the emitter trench 17.

[0271] Each of the second sidewall contact holes 275 is rectangular in plan view. In the present preferred embodiment, each of the first sidewall contact holes 275 is ribbon-shaped (rectangular) and extends along the first direction X in plan view. The width WX in the first direction X of each of the first sidewall contact holes 275 is greater than 0 µm and not greater than 1 µm. The width WY in the second direction Y of each of the first sidewall contact holes 275 is greater than 0 µm and not greater than 1 µm.

[0272] One end section of each of the first sidewall contact holes 274 and one end section of each of the second sidewall contact holes 275 are jointly defined by the second embedded gate insulating layer 188 in the first gate groove 184. A portion of the second embedded gate insulating layer 188 is located in a region between one end section of each of the first sidewall contact holes 274 and one end section of each of the second sidewall contact holes 275.

[0273] The second contact holes 42 are each connected to a first sidewall contact hole 272, a second sidewall contact hole 273, a first sidewall contact hole 274, and a second sidewall contact hole 275, which are each assigned to the second contact hole 42 in a one-to-one correspondence. A portion of the insulating intermediate layer 41 is arranged in a region between two adjacent second contact holes 42 on the first embedded gate insulating layer 178. A portion of the insulating intermediate layer 41 is arranged in a region between two adjacent second contact holes 42 on the second embedded gate insulating layer 188.

[0274] The emitter contact electrode layers 51 contain a plurality of emitter contact electrode layers 213A and a plurality of emitter contact electrode layers 213B in the same manner as in the semiconductor device 251. The emitter contact electrode layers 213A are each embedded in the first sidewall contact holes 272 and the second sidewall contact holes 273 in the same manner as in the semiconductor device 251. The emitter contact electrode layers 213A are each embedded in the first sidewall contact holes 274 and the second sidewall contact holes 275 in the same manner as in the semiconductor device 251.

[0275] As described above, the same effect can be achieved in semiconductor device 271 as in semiconductor device 1. The first sidewall contact hole 272, the second sidewall contact hole 273, the first sidewall contact hole 274, and the second sidewall contact hole 275, in which the width WX is equal to or less than 1 µm and the width WY is equal to or less than 1 µm, are formed accordingly in semiconductor device 271. Therefore, the emitter contact electrode layer 51 (in particular the second electrode layer 45 with tungsten) can be suitably embedded in the first sidewall contact hole 272, the second sidewall contact hole 273, the first sidewall contact hole 274, and the second sidewall contact hole 275. Naturally, the structure of semiconductor device 271 is also applicable to preferred embodiments other than the fifteenth preferred embodiment.

[0276] Fig. 30 is a cross-sectional view of the region accordingly Fig. 29, which shows a region of a part of a semiconductor device 281 according to a sixteenth preferred embodiment of the present invention. Hereinafter, the same reference numeral is used for a component corresponding to a component of the semiconductor device 271 mentioned above (see Fig. ), and a description of this component is omitted.

[0277] In Fig. In the present preferred embodiment, the first sidewall contact hole 272 is formed in a region between the gate-trough electrode structure 10 and the trench-emitter electrode structure 11, both of which are adjacent to each other in the surface layer portion of the first main surface 3 of the semiconductor layer 2. The first sidewall contact hole 272 is defined by the semiconductor layer 2, by the gate-trough electrode structure 10, and by the trench-emitter electrode structure 11.

[0278] One end section of the first sidewall contact hole 272 can be defined by the first gate insulating layer 175 and / or by the first embedded gate insulating layer 178. This one end section of the first sidewall contact hole 272 can be located remotely from the gate-trough electrode structure 10. In other words, this one end section of the first sidewall contact hole 272 can face the gate-trough electrode structure 10, with a portion of the semiconductor layer 2 situated between the first sidewall contact hole 272 and the gate-trough electrode structure 10.

[0279] The other end section of the first sidewall contact hole 272 can be defined by the emitter insulating layer 18 and / or the embedded emitter insulating layer 21 (the second emitter insulating layer 204 and / or the second embedded emitter insulating layer 207), which is not shown in detail here. The other end section of the first sidewall contact hole 272 can be located remotely from the trench-emitter electrode structure 11. In other words, the other end section of the first sidewall contact hole 272 can face the trench-emitter electrode structure 11, with a portion of the semiconductor layer 2 situated between the first sidewall contact hole 272 and the trench-emitter electrode structure 11.

[0280] In the present preferred embodiment, the second sidewall contact hole 273 is formed in a region between the gate-trough electrode structure 10 and the trench-emitter electrode structure 11, both of which are adjacent to each other in the surface layer portion of the first main surface 3 of the semiconductor layer 2. The second sidewall contact hole 273 is defined by the semiconductor layer 2, by the gate-trough electrode structure 10, and by the trench-emitter electrode structure 11.

[0281] One end section of the second sidewall contact hole 273 can be defined by the first gate insulating layer 175 and / or by the first embedded gate insulating layer 178. One end section of the second sidewall contact hole 273 can be located remotely from the gate-trough electrode structure 10. In other words, one end section of the first sidewall contact hole 272 can face the gate-trough electrode structure 10, with a portion of the semiconductor layer 2 situated between the first sidewall contact hole 272 and the gate-trough electrode structure 10.

[0282] The other end section of the second sidewall contact hole 273 can be defined by the first emitter insulating layer 194 and / or by the first embedded emitter insulating layer 197. The other end section of the second sidewall contact hole 273 can be located remotely from the trench-emitter electrode structure 11. In other words, the other end section of the first sidewall contact hole 272 can face the gate-trench electrode structure 10, with a portion of the semiconductor layer 2 situated between the first sidewall contact hole 272 and the trench-emitter electrode structure 11.

[0283] The first side wall contact hole 274 and the second side wall contact hole 275 are formed in the same way as the first side wall contact hole 272 and the second side wall contact hole 273, respectively. A detailed description of the first side wall contact hole 274 and the second side wall contact hole 275 is omitted.

[0284] The second contact holes 42 are each connected to the first side wall contact hole 272, the second side wall contact hole 273, the first side wall contact hole 274, and the first side wall contact hole 274, which are each assigned to the second contact hole 42 in a one-to-one correspondence. The opening width of each of the second contact holes 42 exceeds the opening width of the first side wall contact hole 272, the opening width of the second side wall contact hole 273, the opening width of the first side wall contact hole 274, and the opening width of the first side wall contact hole 274, which each correspond to the second contact hole 42.

[0285] Each of the second contact holes 42 exposes a portion of the gate-trough electrode structure 10 corresponding to the second contact hole 42 and a portion of the trench-emitter electrode structure 11 corresponding to the second contact hole 42. The side wall of each of the second contact holes 42 is arranged on the gate-trough electrode structure 10 corresponding to the second contact hole 42 and on the trench-emitter electrode structure 11 corresponding to the second contact hole 42.

[0286] As described above, the same effect can be achieved with semiconductor device 281 as with semiconductor device 1. Semiconductor device 281 can be produced simply by changing the mask layout or the etching conditions in the manufacturing process of semiconductor device 271. Naturally, the structure of semiconductor device 281 is also applicable to preferred embodiments other than the sixteenth preferred embodiment.

[0287] Fig. 31 is a cross-sectional view of the region accordingly Fig. 29, which shows a region of a part of a semiconductor device 291 according to a seventeenth preferred embodiment of the present invention. In Fig. 31 The semiconductor device 291 has a structure in which the structure of the semiconductor device 261 (see Fig. 26) with the structure of the semiconductor device 271 (see Fig. 29) was combined.

[0288] In other words, each of the emitter contact electrode layers 213A contains the first contact electrode layer 262 and the second contact electrode 263, both of which contain mutually different conductive materials as their main elements. The first contact electrode layer 262 contains tungsten as its main element and is embedded in the first contact hole 212A. The second contact electrode 263 contains aluminum as its main element and is embedded in the second contact hole 42, which is connected to the first contact hole 212A.

[0289] Here too, each of the emitter contact electrode layers 213A contains the first contact electrode layer 264 and the second contact electrode 265, both of which contain mutually different conductive materials as their main elements. The first contact electrode layer 264 and the second contact electrode layer 265 have structures corresponding to the first contact electrode layer 262 and the second contact electrode 263, respectively.

[0290] Furthermore, the same reference symbol is used for a component that corresponds to a component of the above-mentioned semiconductor device 261 (see Fig. ) or corresponds to a component of the above-mentioned semiconductor device 271 (see Fig. ), and a description of these components is omitted.

[0291] As described above, the same effect can be achieved with semiconductor device 291 as with semiconductor device 1. Naturally, the structure of semiconductor device 291 is also applicable to preferred embodiments other than the seventeenth preferred embodiment.

[0292] Fig. 32 is a cross-sectional view of the region accordingly Fig. 29, which shows a region of a part of a semiconductor device 301 according to an eighteenth preferred embodiment of the present invention. In Fig. 32 The semiconductor device 301 has a structure in which the structure of the semiconductor device 261 (see Fig. 26) with the structure of the semiconductor device 281 (see Fig. 30) was combined.

[0293] In other words, each of the emitter contact electrode layers 213A contains the first contact electrode layer 262 and the second contact electrode 263, both of which contain mutually different conductive materials as their main elements. The first contact electrode layer 262 contains tungsten as its main element and is embedded in the first contact hole 212A. The second contact electrode 263 contains aluminum as its main element and is embedded in the second contact hole 42, which is connected to the first contact hole 212A.

[0294] Here too, each of the emitter contact electrode layers 213A contains the first contact electrode layer 264 and the second contact electrode 265, both of which contain mutually different conductive materials as their main elements. The first contact electrode layer 264 and the second contact electrode layer 265 have structures corresponding to the first contact electrode layer 262 and the second contact electrode 263, respectively.

[0295] Furthermore, the same reference symbol is used for a component that corresponds to a component of the above-mentioned semiconductor device 261 (see Fig. ) or corresponds to a component of the above-mentioned semiconductor device 281 (see Fig. ), and a description of these components is omitted.

[0296] As described above, the same effect can be achieved with semiconductor device 301 as with semiconductor device 1. Naturally, the structure of semiconductor device 301 is also applicable to preferred embodiments other than the eighteenth preferred embodiment.

[0297] The present invention can also be implemented in other ways, and only the preferred embodiments of the present invention have been described above.

[0298] The in Fig. The structure shown in Figure 33 can be used in any of the preferred embodiments mentioned above. Fig. Figure 33 is a top view of the part that Fig. 2 corresponds to and shows a modification of semiconductor layer 2. Below, the same reference numeral is assigned to a component corresponding to a component of the semiconductor device 1 mentioned above, and a description of this component is omitted. The structure described below is also applicable to the second to eighteenth preferred embodiments.

[0299] With reference to Fig. 33 The semiconductor layer 2 can have a layer structure comprising a silicon-made p-type semiconductor substrate 2A and a silicon-made n - -like epitaxial layer 2B, which is formed on the semiconductor substrate 2A instead of the silicon single crystal substrate.

[0300] The second main area 4 of the semiconductor layer 2 is formed by the p-like semiconductor substrate 2A. The first main area 3 consists of the n --like epitaxial layer 2B. In this case, the p-like semiconductor substrate 2A corresponds to the collector region 5. Likewise, the n-like epitaxial layer 2B corresponds to the drift region 7.

[0301] Of course, semiconductor layer 2 can have a layer structure comprising a silicon-based n-type semiconductor substrate 2A and a silicon-based n - -like epitaxial layer 2B is formed on the semiconductor substrate 2A instead of the silicon single crystal substrate.

[0302] The second main area 4 of the semiconductor layer 2 is formed by the n-like semiconductor substrate 2A. The first main area 3 consists of the n - -like epitaxial layer 2B. In this case, the n-like semiconductor substrate 2A corresponds to the drain region. Likewise, the n-like epitaxial layer 2B corresponds to the drift region 7.

[0303] The in Fig. The structure shown in Figure 34 can be used in any of the preferred embodiments mentioned above. Fig. Figure 34 is a top view of the part accordingly. Fig. Figure 4 shows a modification of the embedded gate insulating layer 16. Below, the same reference numeral is assigned to a component corresponding to a component of the semiconductor device 1 mentioned above, and a description of this component is omitted. The structure described below is also applicable to the second to eighteenth preferred embodiments.

[0304] In this example, the gate embedding hole 15 has a width in the first direction that is greater than the width of the gate trench 12 in the first direction. A first side of the side face and another side of the side face of the gate embedding hole 15 are located in a region outside the gate trench 12 with respect to the first direction X, and the semiconductor layer 2 is exposed.

[0305] The embedded gate insulating layer 16 is embedded in the gate embedding hole 15 with the structure thus formed. As a result, the embedded gate insulating layer 16 has a width in the first direction that is greater than the width of the gate trench 12 in the first direction.

[0306] One side of the embedded gate insulating layer 16 and another side of the embedded gate insulating layer 16 are located outside the gate trench 12 with respect to the first direction X and are continuous with the semiconductor layer 2. The first contact hole 31 and the emitter contact electrode layer 51 intersect the embedded gate insulating layer 16 in a top view.

[0307] Even if the embedded gate insulating layer 16 is formed with the aforementioned structure, the same effect as in the semiconductor device 1 can be achieved. The structure thus formed can be produced by changing the layout of the masks in the manufacturing process of the semiconductor device 1.

[0308] The emitter contact electrode layer 51 with the in Fig. The structure shown in Figure 35 can be used in any of the preferred embodiments mentioned above. Fig. 35 is a top view of the part that Fig. 4 corresponds to, and shows a modification of the emitter contact electrode layer 51. Below, the same reference numeral is assigned to a component corresponding to a component of the semiconductor device 1 mentioned above, and a description of this component is omitted. The structure described below is also applicable to the second to eighteenth preferred embodiments.

[0309] In Fig. In this example, the gate embedding holes 15 contain a gate embedding hole 231A and a gate embedding hole 231B. The gate embedding hole 231A and the gate embedding hole 231B are formed with a distance between them along the gate trench 12 (second direction Y).

[0310] The gate embedding hole 231A is formed away from the other side wall of the gate trench 12 with respect to the first direction X and in the vicinity of the one-sided side wall of the gate trench 12. A portion of the gate electrode layer 14 is located in a region between the gate embedding hole 231A and the other side wall of the gate trench 12. In this example, the side wall of the gate embedding hole 231A is defined by the gate insulating layer 13 and by the gate electrode layer 14.

[0311] The gate embedding hole 231B is formed with respect to the first direction X away from one side wall of the gate trench 12 and near the other side wall of the gate trench 12. A portion of the gate electrode layer 14 is located in a region between the gate embedding hole 231B and the one side wall of the gate trench 12. In this example, the side wall of the gate embedding hole 231B is defined by the gate insulating layer 13 and by the gate electrode layer 14.

[0312] In this example, the embedded gate insulating layer 16 contains an embedded gate insulating layer 232A and an embedded gate insulating layer 232B. The embedded gate insulating layer 232A is embedded in the gate embedding hole 231A. The embedded gate insulating layer 232B is embedded in the gate embedding hole 231B.

[0313] In this example, the first contact holes 31 contain a first contact hole 233A and a first contact hole 233B. The first contact hole 233A and the first contact hole 233B are formed with a distance between them along the gate trench 12 (second direction Y).

[0314] The first contact hole 233A extends only through one side of the side wall of the gate trench 12 from an inner region of the embedded gate insulating layer 232A with respect to the first direction X. The first contact hole 233A is formed away from the far side of the side wall of the gate trench 12.

[0315] The first contact hole 233B extends only through the far side of the gate trench 12's side wall from an inner region of the embedded gate insulating layer 232 with respect to the first direction X. The first contact hole 233B is formed away from the one-sided side wall of the gate trench.

[0316] In this example, the emitter contact electrode layers 51 contain an emitter contact electrode layer 234A and an emitter contact electrode layer 234B. The emitter contact electrode layer 234A is embedded in the first contact hole 233A. As a result, the emitter contact electrode layer 234A only penetrates one side of the gate trench 12 side wall from the inner region of the embedded gate insulating layer 232A with respect to the first direction X. The emitter contact electrode layer 234A is formed from the far side of the gate trench 12 side wall.

[0317] The emitter contact electrode layer 234A is embedded in the first contact hole 233B. As a result, the emitter contact electrode layer 234B only penetrates one side of the gate trench 12 side wall from the inner region of the embedded gate insulating layer 232B with respect to the first direction X. The emitter contact electrode layer 234B is formed from the far side of the gate trench 12 side wall.

[0318] Even if the in Fig. Using the structure shown in Figure 35, it is possible to achieve the same effect as with semiconductor device 1. The structure shown in Figure 35 is used. Fig. The structure shown in Figure 35 can be produced by changing the layout of the masks in the semiconductor device manufacturing process 1.

[0319] In each of the preferred embodiments mentioned above, a structure can be used in which the conductivity type of each semiconductor part is reversed. In other words, a p-type part can be configured as n-type and an n-type part can be configured as p-type.

[0320] Semiconductor layer 2 consists of a silicon single crystal, as described in each of the preferred embodiments mentioned above. However, semiconductor layer 2 can also contain SiC. Likewise, semiconductor layer 2 can consist of a SiC single crystal. 1 Semiconductor device 2 Semiconductor layer 3 First main area 8 Body Region 12 Gate Trench 13 Gate insulating layer 14 Gate electrode layer 16 embedded gate insulating layer 17 Emitter Trench 19 Emitter electrode layer 21 embedded emitter insulating layer 25 Emitter Region 41 insulating intermediate layer 51 Emitter contact electrode layer 81 Semiconductor device 91 Semiconductor device 93A Emitter contact electrode layer 93B Emitter contact electrode layer 101 Semiconductor device 103 Emitter Trench 105 Emitter electrode layer 107 embedded emitter insulating layer 121 Semiconductor device 131 Semiconductor device 133A Emitter contact electrode layer 133B Emitter contact electrode layer 141 Semiconductor device 143 Second Gate Trench 144 Second gate insulating layer 145 Second gate electrode layer 147 Second embedded gate insulating layer 161 Semiconductor device 163A Emitter contact electrode layer 163B Emitter contact electrode layer 171 Semiconductor device 174 First Gate Trench 175 First gate insulating layer 176 First gate electrode layer 178 First embedded gate insulating layer 184 Second Gate Trench 185 Second gate insulating layer 186 Second gate electrode layer 188 Second embedded gate insulating layer 193 First Emitter Trench 195 First emitter electrode layer 197 First embedded emitter insulating layer 203 Second Emitter Trench 205 Second emitter electrode layer 207 Second embedded emitter insulating layer 211 Semiconductor device 213A Emitter contact electrode layer 213B Emitter contact electrode layer 221 Semiconductor device 232A embedded gate insulating layer 232B embedded gate insulating layer 234A Emitter contact electrode layer 234B Emitter contact electrode layer 251 Semiconductor device 261 Semiconductor device 271 Semiconductor device 281 Semiconductor device 291 Semiconductor device 301 Semiconductor device P0 Trench spacing P1 First trench spacing P2 Second trench spacing P3 Third trench spacing X First direction Y Second direction

Claims

[1] Semiconductor device comprising: a semiconductor layer (2) having a main surface (3) in which trenches are formed, wherein a first trench (12) and a second trench (17, 143) run in the same second direction (Y) and have a gap in plan view; a body region (8) of a first conductivity type, which is formed along side walls of the trenches in a surface layer part of the main surface (3) of the semiconductor layer (2); a contamination region (25) of a second conductivity type, which is formed along the side wall of the first trench (12) in a surface layer part of the body region (8); a gate insulating layer (13) formed on an inner wall of the first trench (12); a gate electrode (14) embedded in the first trench (12) and facing the body region (8) and the contamination region (25), wherein the gate insulating layer (13) is arranged between the gate electrode (14) and the body region (8) and between the gate electrode (14) and the contamination region (25); a trench insulation layer (18, 144) formed on an inner wall of the second trench (17, 143); a trench electrode (19, 145) embedded in the second trench (17, 143) and facing the body region (8), wherein the trench insulating layer (18, 144) is arranged between the trench electrode (19, 145) and the body region (8); and a contact hole (31) formed in a surface layer part of the main surface (3) and extending along a first direction (X) orthogonal to the second direction (Y), wherein a contact electrode (51) is embedded in the contact hole (31), wherein the contact hole (31) has a first cutting region (33) with the gate electrode (14), a second cutting region (34) with the trench electrode (19, 145) and a connecting region (35) that connects the first cutting region (33) and the second cutting region (34) in a region between the first trench (12) and the second trench (17, 143), wherein a bottom wall of the contact hole (31) is formed flush in the first cut region (33), the second cut region (34) and the connection region (35), and wherein the bottom wall of the contact hole (31) is arranged below the main surface (3) of the semiconductor layer (2). [2] Semiconductor device according to claim 1, wherein the contact electrode (51) in the first groove (12) of the gate electrode (14) is directed in a perpendicular direction to the main surface (3) of the semiconductor layer (2) and in a tangential direction to the main surface (3) of the semiconductor layer (2). [3] Semiconductor device according to claim 1 or 2, wherein with respect to the second direction (Y) a width of the contact electrode (51) is smaller than a width of the first trench (12). [4] Semiconductor device according to one of claims 1 to 3, wherein the contact electrode (51) passes through a first side of the side wall and a further side of the side wall of the first trench (12) from inside the first trench (12) and is pulled out to the surface layer part of the semiconductor layer (2). [5] Semiconductor device according to any one of claims 1 to 4, further comprising: an insulating layer (41) covering the main area (3) of the semiconductor layer (2), wherein the contact electrode (51) passes through the insulating layer (41) to reach the interior of the first trench (12) and the surface layer part of the semiconductor layer (2). [6] Semiconductor device according to claim 5, wherein an embedded insulating layer (16) is exposed through an opening of the first trench (12), and the insulating layer (41) covers the embedded insulating layer (16). [7] Semiconductor device according to one of claims 1 to 6, wherein the contact electrode (51) is pulled out such that it passes through a side wall of the second trench (17, 143) from the surface layer part of the semiconductor layer (2) and extends into the interior of the second trench (17, 143). [8] Semiconductor device according to claim 7, further comprising: an inner wall insulation layer (18) formed on an inner wall of the second trench (17); an embedded electrode layer (19) which is embedded in an intermediate section in the depth direction of the second trench (17), wherein the inner wall insulating layer (18) lies between the embedded electrode layer (19) and the second trench (17); and a second embedded insulating layer (21) which is arranged between the embedded electrode layer (19) and the contact electrode (51) in the second trench (17) and which insulates the embedded electrode layer (19) and the contact electrode (51). [9] Semiconductor device according to claim 8, wherein a voltage which is less than a gate voltage applied to the gate electrode (14) is applied to the embedded electrode layer (19). [10] Semiconductor device according to claim 7, further comprising: a second gate insulation layer (18) formed on an inner wall of the second trench (17); a second gate electrode (19) embedded in the second trench (17), wherein the second gate insulating layer (18) lies between the second gate electrode (19) and the second trench (17); and a second embedded insulating layer (21) which is arranged between the second gate electrode (19) and the contact electrode (51) in the second trench (17) and which insulates the second gate electrode (19) and the contact electrode (51). [11] Semiconductor device according to claim 10, wherein the second gate electrode (19) has the same electrical potential as the gate electrode (14). [12] Semiconductor device according to any one of claims 1 to 11, wherein the distance between the first trench (12) and the second trench (17) is at least 0.1 µm and less than 0.6 µm. [13] Semiconductor device according to any one of claims 1 to 12, wherein the distance between the first trench (12) and the second trench (17) is at least 0.2 µm and less than 0.4 pm. [14] Semiconductor device according to any one of claims 1 to 13, wherein the impurity region (25) is an emitter region and the contact electrode (51) is an emitter contact electrode. [15] Semiconductor device according to any one of claims 1 to 13, wherein the contamination region (25) is a source region and the contact electrode is a source contact electrode. [16] Semiconductor device according to claim 1, wherein the second trench (143) is a gate trench and the trench electrode (145) is a gate electrode.

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