TECHNIQUES FOR POWER REDUCTION AND POWER IMPROVEMENT FOR A DELTA-SIGMA MODULATOR

Abstract

Delta-sigma analog-to-digital converter (ADC), which includes the following: a delta-sigma modulator that includes the following: a first summing node for summing an analog input signal and a feedback signal and outputting a first summed analog signal; a loop filter that filters the first summed analog signal according to a noise shaping function and outputs a filtered analog signal; a quantizer that quantizes the filtered analog signal and outputs a quantized output signal; a feedback path that connects an output of the quantizer to an input of the summing node; and a feedback DAC in the feedback path that receives the quantized output signal and converts the quantized output signal into the feedback signal that is delivered to the first summing node, and wherein the feedback DAC includes a switch-capacitor circuit, wherein the switch-capacitor circuit includes several unit elements, wherein the switch-capacitor circuit is configured to selectively connect each of the respective unit elements into different connection states depending on a DAC code of the quantized output signal, wherein the different connection states include the following: a first connection state in which the respective unit element is connected to deliver a first signal to an output of the feedback DAC, wherein the first connection state corresponds to a first signal level; a second connection state in which the respective unit element is connected to supply a second signal to the output of the feedback DAC, the second connection state corresponding to a second signal level; and a third connection state in which the respective unit element is disconnected from the output of the feedback DAC, wherein the third connection state corresponds to a third signal level characterized by the fact that The switching network is configured in the third connection state to connect the unit element to a common-mode voltage.

Description

CROSS-REFERENCE TO RELATED REGISTRATIONS

[0001] This application claims priority over the preliminary US application with serial number 62 / 611,586 and titled “POWER REDUCTION AND PERFORMANCE ENHANCEMENT TECHNIQUES FOR DELTA SIGMA MODULATOR” by Ganta et al., filed on December 29, 2017. TECHNICAL AREA

[0002] This invention relates to a delta-sigma analog-to-digital converter according to the preamble of claim 1, as known from US 2009 / 0096648 A1. The invention further relates to a delta-sigma modulator.

[0003] US 2012 / 0306678 A1, US 5982316 A and DE 4311724 A1 each disclose a three-state feedback DAC in a sigma-delta modulator. BACKGROUND

[0004] Delta-sigma modulation is a popular technique for implementing high-resolution ADCs and digital-to-analog converters (DACs). It offers the advantage of reducing the power consumption of delta-sigma modulators (ΔΣM) and improving their performance.

[0005] The invention is defined in independent claims 1, 7 and 13. BRIEF DESCRIPTION OF THE DRAWINGS Fig. Figure 1 shows a general implementation of a digital-to-analog converter (DAC) in a discrete-time (DT) delta-sigma modulator (DSM or ΔΣM). Fig. Figure 2 is a table showing a DAC circuit diagram in a conventional DT-DSM. Fig. 3 represents a multi-bit reference scaling technique according to the present disclosure. Fig. Figure 4 is a table showing a DAC switching sequence in a DT-DSM with reference scaling. Fig. Figure 5 shows a DAC input code versus an output charge for a reference-scaled system with an even number of quantization levels. Fig. Figure 6 is a graph that shows a simulated dynamic range comparison for the data with reference to Fig. The 5 discussed cases are shown. Fig. Figure 7 represents a multi-bit reference scaling technique for an odd number of quantization levels according to the present disclosure. Fig. Figure 8 is a table showing a DAC switching sequence in a DT-DSM with reference scaling for odd numbers of quantization levels. Fig. Figure 9 is a graphical representation showing a DAC input code versus an output charge for a reference-scaled system with an odd number of quantization levels. Fig. Figure 10 is a graph that shows a simulated dynamic range comparison for the data with reference to Fig. The 9 discussed cases are shown. Fig. Figure 11 shows a block diagram of a reference-scaled one-bit delta-sigma modulator. Fig. Figure 12 is a schematic representation of a circuit implementation of the delta-sigma modulator from Fig. 11. Fig. Figure 13 shows a block diagram of a generalized reference scaling implementation for a one-bit delta-sigma modulator. Fig. Figure 14 is a graphical representation showing a DAC input code versus an output charge for a reference-scaled system with triple-level quantization. Fig. Figure 15 is a block diagram of a conventional discrete-time integrator. Fig. Figure 16 is a block diagram of a dual-sampling integrator. Fig. Figure 17 presents an example of a DSM that uses an operational amplifier balancing loop filter design. Fig. 18 shows a spectral analysis of the DSM ( Fig. 17), which uses the operational amplifier equalization loop filter. Fig. 19 is a time domain illustration from the DSM ( Fig. 17), which uses the operational amplifier equalization loop filter. Fig. 20 is a simplified example of a chopper-stabilized differential DT integrator. Fig. Figure 21 shows a DAC mapping function for positive and negative offset. Fig. Figure 22 is a model of the DAC offset in an operational amplifier compensation loop filter design. Fig. Figure 23 shows a spectral analysis of the DSM using the operational amplifier equalization loop filter. Fig. Figure 24 shows a simulated dynamic range comparison for a multi-bit ADC that combines the proposed techniques. Fig. Figure 25 shows a one-bit DSM with reference scaling, operational amplifier balancing, and chopping. Fig. Table 26 shows a compensation for lagging and non-lagging integrators. Fig. Figure 27 shows an example of a signal transition based on Fig. 22 with a non-delaying integrator in H1(z). DETAILED DESCRIPTION

[0006] For the purpose of promoting an understanding of the principles of the disclosure, reference is now made to the embodiments illustrated in the drawings and described in the following written description. It is understood that this is not intended to limit the scope of protection of the disclosure. It is further understood that the present disclosure includes any variations and modifications to the illustrated embodiments and further applications of the principles of the disclosure, such as would normally occur to a person skilled in the art in the technical field to which this disclosure belongs.

[0007] This disclosure proposes techniques for reducing power consumption and improving the performance of delta-sigma modulators and delta-sigma ADCs. As discussed in more detail below, these techniques include reference scaling, operational amplifier balancing, and chopper stabilization at the sampling frequency.

[0008] The disclosure presents a low-power delta-sigma ADC that uses a reference scaling technique which reduces thermal noise and decreases power dissipation by approximately 50%. With reference to Fig. 1 Previously known multi-bit oversampling delta-sigma ADCs often use switch-capacitor feedback DACs 10 with 2-level (+1, -1) unit elements 12 (e.g., capacitors). As in Fig. As shown in Figure 1, the unit elements 12 are represented by reference voltages V. ref- or V ref+The output of the DAC is the sum of the voltages of the actuated unit elements 12, which forms the feedback analog signal that essentially represents the digital output signal.

[0009] Switches 14 are used to connect the unit elements with either V ref- or V ref+ to connect. Switches 14 are controlled according to a DAC code. The DAC code is typically provided by the output of the ADC's quantizer. Fig. 2 summarizes a typical switching sequence for a DAC, as in Fig. 1 shown, together. In the embodiment from Fig. 1. The DAC has six codes, represented by +5, +3, +1, -1, -3 and -5.

[0010] As in Fig. As can be seen in Figure 2, for a DAC code of +5, the switches for the five unit elements 12 (pairs) have a control state of "1", so that each unit element is controlled by V ref+is controlled. For a DAC of +3, four of the five switches have a control state of "1", so that four unit elements are controlled by V ref+ can be controlled while the switch for the fifth unit element has a control state of “0”, so that the unit elements associated with this switch are controlled by V ref- The switches are controlled as follows: For a DAC code of +1, three switches have a control state of "1" and two switches have a control state of "0". For DAC codes -1, -3, and -5, the control states of the switches are reversed with respect to DAC codes +1, +3, and +5, respectively.

[0011] As shown in the last column of the table Fig. As can be seen in Figure 2, the offset error is the same for each DAC code, e.g. -5V. os C uThis is because the reference capacitors are always connected to an active circuit arrangement, regardless of the switch state. Consequently, the thermal noise and power consumption of the reference capacitors are always factors in the device's operation.

[0012] This disclosure proposes a reference scaling technique that enables a significant reduction in the thermal noise and power consumption of the delta-sigma modulator. Specifically, the delta-sigma ADC according to this disclosure is configured to have a 3-level (+1, 0, -1) switch capacitor feedback DAC architecture, in which each reference capacitor has the ability to be driven by either V ref- , V ref+ to be controlled or not to be connected to active circuit arrangements.

[0013] An exemplary implementation of the proposed reference scaling technique is shown in Fig. 3 shown, while switching sequences for different DAC control codes in the Fig. The information is summarized in the table shown in section 4. As in Fig. As can be seen in Figure 3, the DAC 30 includes a switch-capacitor network 32 with several unit element (reference capacitor) pairs 34. There are five unit element pairs 34 in the embodiment shown. Fig. 3.

[0014] The switching network 32 includes several switches associated with each unit element and designed to electrically connect the unit elements in such a way that a reference voltage, either V ref- or V ref+ , is supplied to the output circuit arrangement. For example, the first unit element includes switches d1n and d1p for connecting the unit element to V. ref- or V ref+ ; includes the second unit element, switches d2n and d2p for connecting the unit element to V ref- or V ref+; and so forth.

[0015] Each unit element includes switches dxz for electrically isolating the unit element from the output circuit arrangement. For example, the first unit element includes switches d1z and d1z for isolating the unit element Cu1 from the output circuit arrangement; the second unit element includes switches d2z and d2z for isolating the unit element from the output circuit arrangement; and so on. In the embodiment shown Fig. 3. The switches dxz are designed to disconnect the corresponding unit elements from the common-mode voltage V. cm to separate.

[0016] The unit elements from Fig. 3 exhibit control states defined by "1 / 0", "0 / 1", and "0 / 0", which are the control states of the switches dxn and dxp associated with the unit element. A unit element with the control state "1 / 0" is associated with V ref+connected and produces a signal level of +1. Likewise, a unit element with the control state "0 / 1" is connected to V. ref+ When connected, it produces a signal level of -1. Conversely, when an element is in the "0 / 0" state, it is not connected to an active circuit arrangement and therefore does not supply any signal charge or thermal noise charge to the circuit arrangement. This results in a significant reduction in the contribution of thermal noise from the element.

[0017] Fig. Figure 4 is a table showing the control states for the unit element switches corresponding to the DAC codes +5, +3, +1, -1, -3, and -5. The offset fault charge depends on the number of unit elements connected to the active circuit arrangement. Therefore, the offset fault charge is reduced for lower DAC code values, as shown in the last column of the table. Fig. Figure 4 shows that for small signals, only a small number of unit elements are attached to the virtual ground, resulting in an effective reduction of thermal noise. This technique can reduce the power dissipation of an ADC by approximately 50%.

[0018] A critical side effect of the triple-level unit element feedback DAC is the loss of intrinsic linearity inherent in the two-level system. This non-linearity causes varying degrees of performance degradation and is discussed for two different cases: an even number of quantization levels and an odd number of quantization levels.

[0019] If the feedback DAC input has an even number of quantization levels, as in Fig. As shown in Figure 3, the system exhibits good signal-to-noise ratio (SNR) and signal-to-noise ratio (SNDR) for small signals, using only DAC codes of +1 and -1. As the signal increases, triggering the use of more DAC codes, SNDR degradation occurs due to DAC nonlinearity, but this is acceptable for applications where SNDR requirements are relaxed with increasing signal power, such as MEMS microphones.

[0020] Fig. Figure 5 illustrates the cause of this degradation by showing the input and output mapping of a feedback DAC that uses a reference scaling for an even number of quantization levels. The corresponding SNDR for each case as a function of the input level is shown in Fig. 6 shown. Fig. Figure 6 shows the ideal curve in the dashed line, where the effective charge for a DAC code of n is given by (nC).u ΔV ref ) is given, where ΔV ref = V ref+ - V ref- This applies. With the presence of an offset in the integrator (Vos in Fig. 3) The effective charge supplied by the feedback DAC becomes (nC u ΔV ref - |n|C u V os ), which is a non-linear assignment, as shown in the solid curve from Fig. Figure 5 shows that for a conventional DAC without reference scaling, the offset is independent of the signal, with only a DC offset being introduced in the mapping, and therefore does not cause a problem for the SNDR.

[0021] As from Fig. As shown in Figure 5, for this specific design of a reference scaling with an even number of quantization levels, the DAC and consequently the ADC behave like a one-bit ADC for small input signals. The inherent linearity of the one-bit DAC ensures good performance at low signal levels. As the DAC input rises above the one-bit level, the change in slope causes non-linearity and degrades the SNDR, as shown in Figure 5. Fig. Figure 6 is shown. For certain applications, e.g., audio systems where SNDR requirements are relaxed with increasing signal power, the nonlinearity due to the reference scaling in the feedback DAC input with an even number of quantization levels is acceptable.

[0022] Fig. Figure 7 shows an example implementation of a reference scaling for an odd number of feedback DAC quantization levels. In this embodiment, four unit element pairs 74 are used in the switch-capacitor network 72 of the DAC 70. The switch network 72 is otherwise the same as the switch network of the embodiment consisting of Fig. 3 similar. Switches dxn, dxp are used to select the unit element V. ref+ or V ref- to connect and the switches dxz are designed to disconnect the unit elements from the active circuit arrangement by connecting the unit elements to the common-mode voltage V cm be connected.

[0023] The corresponding switching sequences are in the Fig. Table 8 summarizes the different DAC codes. To implement an odd number of quantization levels, the unit elements according to the DAC codes are +4, +2, 0, -2, and -4. The unit elements have a control state of "1 / 0" to deliver a +1 signal level to the output and a control state of "0 / 1" to deliver a -1 signal level to the output.

[0024] Fig. Figure 9 shows the input and output mapping of a feedback DAC, as in Fig. Figure 7 shows a reference scaling circuit that uses an odd number of quantization levels. For DAC code 0, all unit elements have a control state of "0 / 0" and are therefore isolated from the active circuitry. This results in no offset error voltage for DAC code 0. Consequently, a reference scaling circuit combined with an offset introduces nonlinearity at zero crossings. As a result, the SNDR is affected by both small and large signals, leading to... Fig. 10 is illustrated.

[0025] In summary, the presence of amplifier offsets introduces nonlinearity into a reference-scaled multi-bit DAC. An operational amplifier compensation technique is proposed below to address the nonlinearity problems associated with reference scaling. But first, a reference scaling technique for one-bit delta-sigma modulators is discussed.

[0026] Traditionally, a one-bit delta-sigma ADC has only one quantizer whose output is either +1 or -1. In other words, the DAC transmits either a charge proportional to +V or -1. ref or to -V ref To apply a reference scaling, a triple-level feedback, i.e. [+1, 0, -1], is necessary.

[0027] To generate the third level, the following scheme is proposed. When the input signal is small, the output current of the DSM exhibits a high density of alternating pairs of +1 and -1, which conceptually zeros out the feedback signal and results in a "0" state in a three-level design. Therefore, the idea is to design a finite impulse response (FIR) filter to detect alternating pairs of +1 and -1 from the output. Upon detection of such an event, the 1-bit DAC is deactivated (i.e., not connected to the ADC input summing node), effectively implementing reference scaling.

[0028] Fig. Figure 11 shows an example implementation of this idea. The Delta-Sigma Modulator 100 from Fig. Component 11 includes a summing node 102, a loop filter 104, a one-bit quantizer 106, and a feedback path 108 with an FIR filter 110. The summing node 102 receives an analog input signal and a feedback signal from the FIR filter 110 and outputs a summed signal to the loop filter 104. The loop filter 104 filters the first summed analog signal according to a noise-shaping function and outputs a filtered analog signal to the one-bit quantizer 106. The one-bit quantizer 106 quantizes the analog signal and outputs a stream of bits with a value of +1 or -1.

[0029] The FIR filter 110 processes the quantizer output according to a transfer function. 12(1+z−1), before it is sent to the DAC. In the case of small input signals, where the quantizer output has a high density of alternating pairs of +1 and -1, the filter output produces a high density of zeros, thus inputting a 0 value into the DAC code.

[0030] With reference to Fig. 12 is the circuit implementation of the reference-scaled three-level feedback [+1, 0, -1] similar to Fig. 7 with a single pair of unit elements and with DAC codes +1, 0, -1, which are provided in the output of the FIR filter. The DAC code +1 would, for example, result in a control state of "1 / 0" for controlling the unit element with V. ref+ This would lead to a DAC code of -1 resulting in a control state of "0 / 1" for controlling the unit element with V. ref-This would result in the DAC code 0 being set to a control state of "0 / 0" for the unit element, with the unit element being isolated from the active circuit arrangement.

[0031] Adding a filter 110 to the feedback path 108 changes the originally designed noise transfer function. Therefore, a compensation feedback path 112, which taps at a different point in the loop, is introduced in the delta-sigma modulator 100. This is described in Fig. Figure 11 illustrates a compensation feedback path 112 and a compensation filter 114. The loop filter 104 is divided into a first integrator 116 and a second integrator 118. A summing node 120 receives the output of the first integrator 116 and a compensation feedback signal from the compensation filter 114. The second integrator 118 receives the output of the summing node 120, and the one-bit quantizer 106 receives the output of the second integrator 118.

[0032] The compensation feedback path 112 taps the loop filter 104 at the summing node 120 between a first integrator 116 and the second integrator 118. The transfer function of the compensation filter 114 depends on the transfer function of the loop filter 104. If the first integrator is a delaying integrator with a transfer function z -1 / (1 - z -1 ) is, is the transfer function of the compensation filter 114 by 12(z−1) Given that the first integrator 116 is a non-delaying integrator with a transfer function 1 / (1 - z) -1 The transfer function of compensation filter 114 is given by 1 / 2. Using compensation filter 114 restores the original noise transfer function. A generalized block diagram of the FIR feedback for a one-bit DSM is given in Fig. 13 shown.

[0033] Similar to the multi-bit delta-sigma modulator with an odd number of quantization levels, the triple-level DAC in the one-bit delta-sigma modulator causes non-linearity, as shown in Fig. Figure 14 shows the input and output assignment for the feedback DAC. Fig. 11.

[0034] An operational amplifier compensation technique is proposed to address the nonlinearity due to reference scaling. Fig. Figure 15 shows a conventional integrator in a discrete-time (DT) delta-sigma modulator, driven according to two non-overlapping clock phases ϕ1 and ϕ2. The input charge is applied in one clock phase (ϕ1 in Fig. 15) is sampled and is used in the next clock phase (ϕ2 in Fig. 15) integrated. This means that the integrator's power is wasted during the signal sampling phase, as the operational amplifier is inactive and performing no task.

[0035] To avoid such an inactive state of the operational amplifier, the sampling capacity is divided into two parts, an upper path 160 and a lower path 162, as shown in Fig. Figure 16 illustrates this. While the upper capacitor path 160 samples the input, the lower capacitor path 162 integrates the charge at ϕ1 and vice versa at ϕ2. Such a system provides a 3dB performance advantage compared to a conventional architecture with a similar data rate. Furthermore, the signal is integrated at twice the frequency compared to the conventional integrator. This technique, when used in delta-sigma modulators, is known as "dual sampling".

[0036] A major disadvantage of double-sampled delta-sigma modulators is the folding of high-frequency shaped noise due to the discrepancy between the DAC capacitances ϕ1 and ϕ2. This discrepancy modulates the input with a discrete cosine signal, which is multiplied by 2f. s is clocked and its frequency is equal to f s has (see Fig. 16). Therefore, the integrator output is the sum of the input and a modulated version of the input.

[0037] The sampling frequency for double-sampled delta-sigma modulators is given by 2f s Given that the signal injected into the first integrator consists of two parts, the input signal and the feedback from the DAC, the input signal is typically band-limited with respect to a low-frequency component by an anti-aliasing filter. Therefore, its modulated component is present in a frequency band close to the frequency f. sand is significantly attenuated by a subsequent digital low-pass filter, resulting in only minor consequences for performance. On the other hand, the feedback signal from the DAC exhibits a large high-frequency quantization noise power at frequency f. s , i.e. half the effective scanning frequency, which is 2f s This is the case for a double-sampled DSM. As a result, the quantization noise is downmixed to the baseband, increasing the in-band noise power and drastically reducing the SNR.

[0038] To solve this problem, an "operational amplifier balancing" technique is proposed. The main difference with this technique is that the DAC value is held at the same level in ϕ1 and ϕ2 for one sampling period. Fig. Figure 17 illustrates a delta-sigma modulator 170 that uses operational amplifier balancing integrators, where the output of the quantizer Y QThe downsampling is 172 (by Y). OUT , Y FB (represented) before being fed back into the input node. An imaginary intermediate node, Y IMG , is inserted to aid in the analysis of the frequency domain conversion between Y OUT and Y FB to help.

[0039] Fig. Figure 18 shows the frequency domain response at different nodes. Y is used for conversion between different clock domains. OUT , which has a well-defined spectrum with its peak at p, first sampled upwards (174, Fig. 17), e.g. by a factor of two using zero insertion. In the frequency domain, it is equivalent to the spectrum of Y OUT to compress, as through the spectrum at Y IMG is shown. The upclocking (174) is followed by a holding filter (176, Fig. 17) with a holding filter function 1+z -1, to repeat (or hold) the same DAC signal for ϕ1 and ϕ2. This filter effectively zeros out the frequency content of the feedback signal at f. s , thereby making the system immune to deterioration due to the previously mentioned problem of capacitive discrepancy.

[0040] Fig. Figure 19 provides a time-domain perspective of this immunity. Due to the capacitor discrepancy in ϕ1 and ϕ2, the output step size differs. Since only the sampled values ​​of the quantizer (Y) Q in Fig. 17) When ϕ2 is taken into account for generating the feedback signal, this difference in step size does not cause any noise degradation in the band.

[0041] The proposed operational amplifier balancing can reduce the power consumption of a delta-sigma ADC by 50%. Furthermore, it solves the problem of DAC noise folding due to capacitance discrepancy in a conventional dual-sampling delta-sigma ADC.

[0042] The low-frequency DC offset and I / f noise cannot be filtered out by a low-pass filter, and therefore this noise is passed through the filter along with the signal information. One approach to minimizing low-frequency noise in an ADC using a delta-sigma modulator is to chop up the operational transconductance amplifier (OTA) and modulate its flicker noise from the signal band, as in Fig. 20 is shown. As in Fig. As shown in Figure 20, the integrator 200 of the delta-sigma modulator can include an OTA 202, an input chopper 204 and an output chopper 206.

[0043] The chopping frequency of the chopper must be at least one order of magnitude away from the signal bandwidth to prevent the remaining flicker noise from affecting the signal bandwidth. Unfortunately, the quantization noise of a DSM is already drastically increased at a frequency one order of magnitude away from the signal bandwidth, especially for a higher-order loop filter design. Consequently, although the chopper stabilization itself acts to minimize the low-frequency noise, there is a possibility that the high-frequency quantization noise will be down-modulated into a baseband of the modulator, resulting in a significant degradation of the SQNR and a decrease in the dynamic range of the converter.

[0044] If the OTA operates at a chopper frequency equal to the sampling frequency f sBeing able to use chopper stabilization would prevent high-frequency quantization noise from being modulated down into the baseband, since the DAC noise transfer function has a zero at the sampling frequency (see Y). OUT in Fig. 18). The conventional discrete-time delta-sigma modulator can only be used with a “maximum” rate of f s / 2 modulated. It is obvious to the average person that an operational amplifier according to this disclosure can perform chopping at the sampling frequency f. s This is permitted. Therefore, we can take advantage of chopping without the concerns regarding quantization noise folding.

[0045] Performance degradation due to DAC nonlinearity in a reference-scaled system under the presence of an offset voltage is effectively solved by the proposed operational amplifier compensation and the f s-Chopping, as discussed above, is used. The mechanisms by which the combination of these two techniques eliminates offset-induced DAC errors are discussed in the following paragraph.

[0046] Conceptually, operational amplifier balancing forces the same code for ϕ1 and ϕ2 and chopping at the sampling frequency f. s This implies that the DAC experiences an offset error of opposite polarity and with the same magnitude for ϕ1 and ϕ2. The corresponding DAC mapping function for each case is given in Fig. Figure 21 shows the resulting effect as an averaged waveform (dotted line) that is linear.

[0047] An explanation of this removal mechanism based on a spectral analysis is presented for a deeper understanding. The error induced by DAC nonlinearity, which is caused by Eos(Yout)=Vos|Yout|, Given, it is modeled as an additional feedback path to the input, as in Fig. Figure 22 is shown. It is noted that this example is based on a multi-bit delta-sigma modulator, which incorporates reference scaling, operational amplifier balancing, and sampling frequency f. s -Chopping combined. The one-bit implementation is discussed below. The described analysis for a multi-bit implementation can easily be extended to the one-bit implementation.

[0048] Based on the model in Fig. 22 illustrates Fig. 23 the frequency response of this error term, E os , showing a distorted, shaped spectrum with increased background noise at the low frequency, which affects our band of interest. The inherent filter (1+z -1 ) in the operational amplifier compensation scheme, this noise is transformed and a zero is created at f. s (see E OS,FB). The subsequent f s -Chopping (by the chopping sequence S) CH (represented) shifts the zero to the baseband (see E OS,CH ) As a result, the error due to DAC non-linearity at the baseband is attenuated and becomes negligible.

[0049] The SNDR degradation when using a standalone reference-scaled DAC with both even and odd numbers of quantizer levels has been discussed above. Fig. 24 compares these capabilities with our implementation, which includes reference scaling, operational amplifier balancing, and f s -Chopping combined. It is evident that the SNR degradation is fully restored with the proposed techniques.

[0050] Fig. Figure 25 shows the block diagram of a one-bit DS-ADC, reference scaling, operational amplifier compensation, and f. s-Chopping is used. EI FIR first-order filter, 0.5(1+z) -1 ), is applied in the feedback path to enable reference scaling (described in Section 1.3), while a compensation path is added to ensure the restoration of the loop filter design. The in Fig. Table 26 summarizes the compensators for a delaying integrator design and a non-delaying integrator design. It is important to note that, while the FIR filter with f s is clocked, the compensators with 2f s must be timed.

[0051] An example of signal transitions at Y OUT , Y FB and Y CMP out of Fig. 25 is given in Table 6 assuming the case of a non-delaying integrator in H1(z). Some characteristics can be derived from the feedback signal, Y. FB, can be observed in this example and are the result of our techniques, which are briefly summarized below.

[0052] The FIR feedback produces a DAC code 0 and a control state “0 / 0”, which means that no reference capacitors are attached to the active circuit arrangement, effectively reducing the contribution of thermal noise in the feedback path.

[0053] The operational amplifier balancing scheme enforces the same feedback codes from ϕ1 to ϕ2, so that the delta-sigma modulator is immune to a capacitor discrepancy between the sampling capacitors and a f s -Chopping enabled.

[0054] The combination of an operational amplifier compensation and f s -Chopping also eliminates the offset-induced DAC nonlinearity problem associated with reference-scaled DAC.

[0055] Unlike Y FBDue to the compensator, it is not guaranteed that Y CMP exhibits the same code from ϕ1 to ϕ2. Violation of the operational amplifier balancing scheme causes Y to CMP It suffers from offset-induced DAC nonlinearity. To avoid any performance degradation from this problem, the compensator function is implemented in the analog domain, so that the DAC of the compensation path is directly by Y. OUT The signal being controlled is a two-level signal, +1 and -1. Consequently, the absence of reference scaling does not imply a DAC nonlinearity problem. Since the noise is noise-shaped by the compensation provided by the first integrator, its contribution to the DSM is inherently small, even without the aid of reference scaling.

Claims

[1] Delta-sigma analog-to-digital converter (ADC), comprising the following: a delta-sigma modulator that includes the following: a first summing node for summing an analog input signal and a feedback signal and outputting a first summed analog signal; a loop filter that filters the first summed analog signal according to a noise shaping function and outputs a filtered analog signal; a quantizer that quantizes the filtered analog signal and outputs a quantized output signal; a feedback path that connects an output of the quantizer to an input of the summing node; and a feedback DAC in the feedback path that receives the quantized output signal and converts the quantized output signal into the feedback signal that is delivered to the first summing node, and wherein the feedback DAC includes a switch-capacitor circuit, wherein the switch-capacitor circuit includes several unit elements, wherein the switch-capacitor circuit is configured to selectively connect each of the respective unit elements into different connection states depending on a DAC code of the quantized output signal, wherein the different connection states include the following: a first connection state in which the respective unit element is connected to deliver a first signal to an output of the feedback DAC, wherein the first connection state corresponds to a first signal level; a second connection state in which the respective unit element is connected to supply a second signal to the output of the feedback DAC, the second connection state corresponding to a second signal level; and a third connection state in which the respective unit element is disconnected from the output of the feedback DAC, wherein the third connection state corresponds to a third signal level characterized by , that The switching network is configured in the third connection state to connect the unit element to a common-mode voltage. [2] Delta-sigma-ADC according to claim 1, wherein the feedback DAC is a one-bit DAC and the quantizer is a one-bit quantizer. [3] Delta-sigma-ADC according to claim 2, further comprising: A finite impulse response (FIR) filter that filters the quantized output signal before it reaches the feedback DAC, wherein the FIR filter is configured to output a filtered quantized output signal in which parts of the quantized output signal that alternate between the first value and the second value at a predetermined rate are replaced with a signal part that has a third quantization value. [4] Delta-sigma-ADC according to claim 3, further comprising: a compensation feedback path that connects the output of the quantizer to the loop filter; and a compensation filter in the compensation feedback path, where the loop filter has a noise transfer function, where the FIR filter changes the noise transfer function, and where the compensation filter compensates the FIR filter in such a way that the noise transfer function is restored. [5] Delta-sigma-ADC according to claim 4, wherein the loop filter includes a first integrator receiving the first summed analog signal, a second integrator outputting the filtered analog signal, and a second summing node, wherein the second summing node has a first input that receives the output of the first integrator, a second input that is connected to the compensation feedback path, and an output that is connected to an input of the second integrator, wherein the first integrator receives the first summed analog signal and outputs a first integrated analog signal to the first input of the second summing node, wherein the compensation filter outputs a compensation signal to the second input of the second summing node, wherein the second summing node outputs a second summed analog signal which is a sum of the first integrated analog signal and the compensation signal, and where the second integrator integrates the second summed signal to form the filtered analog signal. [6] Delta-sigma-ADC according to claim 3, wherein the FIR filter has a 1 transfer function 12(1+z−1) exhibits. [7] Delta-sigma modulator comprising the following: a first clock phase signal and a second clock phase signal that do not overlap with each other; a summing node that sums an analog input signal and a feedback signal; A loop filter that filters the first summed analog signal according to a noise-shaping function and outputs a filtered analog signal, wherein the loop filter includes the following: a dual-sampling integrator including a first capacitor path and a second capacitor path, wherein the first capacitor path samples the analog input signal and the second capacitor path integrates a sample value during the first clock phase signal, and wherein the second capacitor path integrates a sample value and the second capacitor path samples the analog input signal during the second clock phase signal; a quantizer that quantizes the output of the dual-sampling integrator; a feedback path that connects an output of the quantizer to the summing node; and a holding filter in the feedback path, where the first capacitor path and the second capacitor path have a first sampling frequency, wherein the dual-sampling integrator has a second sampling frequency which is twice the first sampling frequency, where an output of the quantizer is downsampled by a predetermined factor to form a downsampled signal that is output to the feedback path, where the downsampled signal is upsampled by the predetermined factor in the feedback path before being fed into the holding filter, where the sampled signal includes DAC codes, and where the holding filter holds a value of the DAC code of the upsampled signal at a constant level during each period of the first clock phase signal and the second clock phase signal to generate the feedback signal. [8] Delta-sigma modulator according to claim 7, wherein the holding filter function 1+z -1 is. [9] Delta-sigma modulator according to claim 8, wherein the holding filter function zeros out a frequency content of the feedback signal at the first sampling frequency. [10] Delta-sigma modulator according to claim 7, wherein the DAC codes specified by the upsampled signal during periods of only the first clock phase signal or only the second clock phase signal are used to generate the feedback signal. [11] Delta-sigma modulator according to claim 7, wherein the predetermined factor is two. [12] Delta-sigma modulator according to claim 7, wherein the dual-sampling integrator includes an operational transconductance amplifier (OTA), an input chopper circuit for chopping an input to the OTA and an output chopper circuit for chopping an output of the OTA, wherein the input chopper circuit and the output chopper circuit have a chopping frequency, and where the chopping frequency corresponds to the first sampling frequency. [13] Delta-sigma ADC, which includes the following: a first clock phase signal and a second clock phase signal that do not overlap with each other; a delta-sigma modulator that includes the following: a first summing node for summing an analog input signal and a feedback signal and outputting a first summed analog signal; a loop filter that filters the first summed analog signal according to a noise shaping function and outputs a filtered analog signal; a quantizer that quantizes the filtered analog signal and outputs a quantized output signal; a feedback path that connects an output of the quantizer to an input of the summing node; and a feedback DAC in the feedback path that receives the quantized output signal and converts the quantized output signal into the feedback signal that is delivered to the first summing node; and wherein the feedback DAC includes a switch-capacitor circuit, wherein the switch-capacitor circuit includes several unit elements, wherein the switch-capacitor circuit is configured to selectively connect each of the respective unit elements into different connection states depending on a DAC code of the quantized output signal, wherein the different connection states include the following: a first connection state in which the respective unit element is connected to deliver a first signal to an output of the feedback DAC, wherein the first connection state corresponds to a first signal level; a second connection state in which the respective unit element is connected to supply a second signal to the output of the feedback DAC, the second connection state corresponding to a second signal level; and a third connection state in which the respective unit element is disconnected from the output of the feedback DAC, wherein the third connection state corresponds to a third signal level, and wherein the loop filter includes a dual-sampling integrator with a first capacitor path and a second capacitor path, wherein the first capacitor path samples the analog input signal and the second capacitor path integrates a sample value during the first clock phase signal, and wherein the second capacitor path integrates a sample value and the second capacitor path samples the analog input signal during the second clock phase signal, where the quantizer quantizes the output of the dual-sampling integrator, where the feedback path includes a holding filter, where the first capacitor path and the second capacitor path have a first sampling frequency, wherein the dual-sampling integrator has a second sampling frequency which is twice the first sampling frequency, where an output of the quantizer is downsampled by a predetermined factor to form a downsampled signal that is output to the feedback path, where the downsampled signal is upsampled by the predetermined factor in the feedback path before being fed into the holding filter, where the sampled signal includes DAC codes, and where the holding filter holds a value of the DAC code of the upsampled signal at a constant level during each period of the first clock phase signal and the second clock phase signal to generate the feedback signal. [14] Delta-sigma-ADC according to claim 13, wherein the switching network in the third connection state is configured to connect the unit element to a common-mode voltage. [15] Delta-sigma-ADC according to claim 13, wherein the dual-sampling integrator includes an operational transconductance amplifier (OTA), an input chopper circuit for chopping an input into the OTA and an output chopper circuit for chopping an output of the OTA, wherein the input chopper circuit and the output chopper circuit have a chopping frequency, and where the chopping frequency corresponds to the first sampling frequency. [16] Delta-sigma-ADC according to claim 13, wherein the holding filter function 1+z -1 is. [17] Delta-sigma-ADC according to claim 14, wherein the holding filter function zeros out a frequency content of the feedback signal at the first sampling frequency. [18] Delta-sigma ADC according to claim 13, wherein the feedback DAC is a one-bit DAC and the quantizer is a one-bit quantizer, and further comprising: a finite impulse response (FIR) filter that filters the quantized output signal before it reaches the feedback DAC, wherein the FIR filter is configured to output a filtered quantized output signal in which parts of the quantized output signal that alternate between the first value and the second value at a predetermined rate are replaced with a signal part that has a third quantization value. [19] Delta-sigma-ADC according to claim 18, further comprising: a compensation feedback path that connects the output of the quantizer to the loop filter; and a compensation filter in the compensation feedback path, where the loop filter has a noise transfer function, where the FIR filter changes the noise transfer function, and where the compensation filter compensates the FIR filter in such a way that the noise transfer function is restored.

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