VERTICAL FET WITH REDUCED PARASITARY CAPACITY AND METHOD FOR ITS MANUFACTURE

Abstract

Method for reducing the parasitic capacitance of a semiconductor structure (50), wherein the method comprises: Formation (104) of a first source / drain zone (16) under a fin structure (12); Omission (110) of the first source / drain zone in exposed areas (24); Forming (112) a zone of shallow trench isolation (26), hereinafter referred to as STI, within the exposed areas (24) of the recessed first source / drain zone; Deposition (114) of a lower spacer (28) above the STI zone and in direct contact with the first source / drain zone, wherein the lower spacer defines a reverse-stepped structural configuration; Forming (116) a metal gate stack (30) above the lower spacer, so that gate-to-source / drain capacitances are reduced by extending the STI zone between the metal gate stack and the first source / drain zone; where: a distance between the metal gate stack and the first source / drain zone is more than 10 nm and / or the procedure has one or more of: Forming (106) the first spacer (20) adjacent to the fin structure and cutting (120) the metal gate stack after forming the first spacers (20) adjacent to the fin structure; or Form (108) a second spacer (22) adjacent to the first source / drain zone; or Forming (124) contacts (40, 41, 42) such that the STI zone extends over a length between the metal gate stack and the first source / drain zone.

Description

TECHNICAL AREA

[0001] The present invention relates generally to semiconductor devices and in particular to the fabrication of a vertical field-effect transistor (FET) with reduced parasitic capacitance. BACKGROUND

[0002] A field-effect transistor (FET) is a transistor with a source, a gate, and a drain. The operation of the FET depends on the flow of majority charge carriers along a channel between the source and the drain, passing through the gate. Current through the channel between the source and the drain is controlled by the transverse electric field under the gate. More than one gate (multi-gate) can be used to control the channel more effectively. The gate length determines how quickly the FET switches.

[0003] The size of FETs has been reduced by using one or more fin-shaped channels. A FET employing such a channel structure can be called a FinFET. In fins, a vertical channel structure is used to maximize the surface area of ​​the channel exposed to the gate. The gate controls the channel more effectively because it extends over more than one side (surface) of the channel. In some units, the gate can completely enclose the channel; that is, a suspended channel passes through the gate, and all surfaces of the channel are exposed to the gate. One challenge in fabricating multi-gate FETs is their inherently high parasitic capacitance compared to conventional planar FETs.

[0004] Document US 2015 / 0069475A1 relates to a semiconductor device comprising: a first-type region comprising a first conductivity type; a second-type region comprising a second conductivity type; a channel region extending between the first-type region and the second-type region, the channel region being separated from a first section of the first-type region by a first distance; and a gate region surrounding the channel region, the first section of the gate region being separated from the first section of the first-type region by a second distance, the second distance being greater than the first distance. SUMMARY

[0005] The invention relates to a method for reducing the parasitic capacitance of a semiconductor structure and to a semiconductor structure for reducing the parasitic capacitance, the features of which are specified in the corresponding independent claims. Embodiments of the invention are specified in the dependent claims.

[0006] A method for reducing the parasitic capacitance of a semiconductor structure is provided. The method includes forming a fin structure over a substrate, forming a first source / drain zone between the fin structure and the substrate, forming a first spacer adjacent to the fin structure, forming a second spacer adjacent to the first source / drain zone, and omitting the first source / drain zone in exposed areas.The process further includes forming a zone of shallow trench insulation (STI) within the exposed areas of the recessed first source / drain zone, depositing a lower spacer over the STI zone, forming a metal gate stack over the lower spacer, depositing an upper spacer over the metal gate stack, cutting the metal gate stack, forming a second source / drain zone over the fin structure, and forming contacts such that the STI zone extends over a length between the metal gate stack and the first source / drain zone.

[0007] Furthermore, a semiconductor structure is provided to reduce parasitic capacitance. The semiconductor structure comprises a fin structure formed over a substrate, a first source / drain zone formed between the fin structure and the substrate, first spacers formed adjacent to the fin structure, and second spacers formed adjacent to the first source / drain zone, with the first source / drain zone being recessed in exposed areas.The semiconductor structure further comprises a shallow trench insulation (STI) zone formed within the exposed areas of the recessed first source / drain zone, a lower spacer deposited over the STI zone, a metal gate stack formed over the lower spacer, an upper spacer formed over the metal gate stack with the metal gate stack cut, a second source / drain zone formed over the fin structure, and contacts configured such that the STI zone extends over a length between the metal gate stack and the first source / drain zone.

[0008] It should be noted that the exemplary embodiments are described in relation to different objects. In particular, some embodiments are described in relation to claims of the method type, while other embodiments are described in relation to claims of the device type. However, the person skilled in the art will recognize from the above and the following description that, unless otherwise stated, in addition to any combination of features belonging to one object type, any combination of features relating to different object types, in particular features of claims of the method type and features of claims of the device type, is also to be considered as described within this document.

[0009] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments, which should be read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the following description of preferred embodiments, details of the invention are provided with reference to the following figures, wherein: Fig. 1 a perspective view of a fin formed over a semiconductor substrate according to the present invention; Fig. 2 a perspective view of the structure of Fig. 1 according to the present invention, wherein the fin is cut; Fig. 3 a perspective view of the structure of Fig. 2 according to the present invention, wherein a cut is made to form an active zone; Fig. 4 a cross-sectional view of the structure of Fig. 3 according to the present invention, in which a section through the fin along the axis AA' is shown; Fig. 5 a cross-sectional view of the structure of Fig. 4 according to the present invention, wherein a first source / drain zone is formed and a shape-adapted dielectric lining is deposited; Fig. 6 a cross-sectional view of the structure of Fig. 5 according to the present invention, wherein an etching is carried out to form a first set of spacers in the vicinity of the first source / drain zone and a second set of spacers in the vicinity of the fin; Fig. 7 a cross-sectional view of the structure of Fig. 6 according to the present invention, wherein the first source / drain zone is recessed in exposed areas; Fig. 8 a cross-sectional view of the structure of Fig. 7 according to the present invention, wherein a zone of shallow trench insulation (STI) is formed over the first source / drain zones; Fig. 9 a cross-sectional view of the structure of Fig. 8 according to the present invention, wherein the second set of spacers in the vicinity of the fins is selectively removed and a lower spacer is deposited above the STI and the exposed zones of the first source / drain zones; Fig. 10 a cross-sectional view of the structure of Fig. 9 according to the present invention, wherein a metal gate stack is formed above the lower spacer; Fig. 11 a cross-sectional view of the structure of Fig. 10 according to the present invention, wherein an upper spacer is formed above the metal gate stack; Fig. 12 a cross-sectional view of the structure of Fig. 11 according to the present invention, wherein the metal gate stack is cut; Fig. 13 a cross-sectional view of the structure of Fig. 12 according to the present invention, wherein an upper source / drain zone is formed directly above the fin; Fig. 14 a cross-sectional view of the structure of Fig. 13 according to the present invention, wherein upper and lower contacts are formed; and Fig. 15 is a block diagram / flowchart of a method for reducing parasitic capacity according to the present invention.

[0011] Throughout the drawings, identical or similar reference numbers represent identical or similar elements. DETAILED DESCRIPTION

[0012] Embodiments according to the present invention provide methods and units for reducing parasitic capacitance in vertical field-effect transistor (VFET) units. FETs are typically formed on semiconductor substrates and comprise a channel region located between the source and drain regions, and a gate configured to electrically connect the source and drain regions through the channel region. Structures in which the channel region is parallel to the main surface of the substrate are referred to as planar FET structures, while structures in which the channel region is perpendicular to the main surface of the substrate are referred to as VFETs. Therefore, in a VFET unit, the direction of current flow between the source and drain regions is normal to the main surface of the substrate. A VFET unit comprises a vertical fin or a vertical nanowire extending upward from the substrate.The fin or nanowire forms the channel region of the transistor. A source region and a drain region are in electrical contact with the top and bottom ends of the channel region, while the gate is located on one or more of the side walls of the fin or nanowire. In a vertical FET architecture, the contacted gate center distance can be decoupled from the gate length. However, in a vertical FET, the contact to the lower source / drain (S / D) is formed from the top of the structure such that the lower S / D contact overlaps the gate. This overlapping configuration creates an undesirable parasitic capacitance between adjacent conductive elements.

[0013] Embodiments according to the present invention provide methods and units for reducing parasitic capacitance by decreasing the overlap between the gate and the lower source / drain (S / D). The distance between the gate and the lower S / D is extended to more than 10 nm, which in turn increases the maximum voltage (Vmax) of the unit. Embodiments according to the present invention provide methods and units for forming VFETs with hybrid spacers of an inverted stepped shape to further reduce the gate-to-source / drain capacitances and improve the maximum operating voltage.

[0014] It is understood that the present invention is described in the form of a given illustrative architecture, but that other architectures, structures, substrate materials, process features, and steps / blocks may also be used as variations within the scope of the present invention. It should be noted that, for the sake of clarity, certain features may not be shown in all figures.

[0015] Fig. Figure 1 is a perspective view of a fin formed over a semiconductor substrate according to the present invention.

[0016] A semiconductor structure 5 comprises a semiconductor substrate 10. A fin 12 is formed over the substrate 10. A hard mask 14 can be formed over the fin 12.

[0017] In one or more embodiments, the substrate 10 can be a semiconductor or an insulator with an active surface semiconductor layer. The substrate 10 can be crystalline, semicrystalline, microcrystalline, or amorphous.

[0018] Fig. 2 is a perspective view of the structure of Fig. 1 according to the present invention, wherein the fin is cut.

[0019] In various exemplary embodiments, the fin 12 is cut. The fin 12 can be cut by etching. Conventionally, two separate fin removal or "fin cutting" etching processes are carried out to remove the unwanted fins (or parts thereof), using two different etching masks. One of these fin removal etching processes is sometimes referred to as an "FC-cut" process, while the other fin removal etching process is sometimes referred to as an "FH-cut" process. The FC-cut and the FH-cut can be carried out in any order, although usually the FC-cut process is carried out first. The FC-cut process is carried out to cut the fins 12 in the direction that intersects the majority of the fins 12 by removing portions of the axial length of the fins that are defined by an FC-cutting mask (e.g.,a photoresist) are released.

[0020] Fig. Figure 3 is a perspective view of the structure of Fig. 2 according to the present invention, wherein a cut is made to form an active zone.

[0021] Fig. Figure 4 is a cross-sectional view of the structure of the Fig. 3 according to the present invention, in which a section through the fin along the axis AA' is shown.

[0022] In various embodiments, the section is made along the axis AA'. The cross-sectional view shows the substrate 10, the fin 12 formed above the substrate, and the hard mask 14 formed above the fin 12.

[0023] Fig. Figure 5 is a cross-sectional view of the structure of the Fig. 4 according to the present invention, wherein a first source / drain zone is formed and a shape-adapted dielectric lining is deposited.

[0024] In various embodiments, a source / drain zone 16 is formed above the substrate 10. The source / drain zone 16 can be referred to as a doped lower S / D zone 16. The doped lower S / D zone 16 can have a thickness greater than the thickness of the substrate 10.

[0025] In various embodiments, a dielectric lining 18 is deposited over the structure. The dielectric lining 18 can be a form-fitting dielectric lining. The dielectric lining 18 can have a thickness greater than 10 nm. The dielectric lining 18 can, for example, be a silicon nitride (SiN) lining. The lining material can also be another dielectric material, for example, a low-k material (e.g., SiBCN, SiOC, etc.). The lining 18 covers the sidewalls of the fin 12 as well as the sidewalls / upper surfaces of the hard mask 14. The lining 18 also covers the exposed parts / sections of the doped lower S / D zone 16. The lining 18 further covers all exposed parts of the substrate 10. The lining 18 covers the entire hard mask 14.

[0026] In various embodiments, the doped source / drain 16 is advantageously deposited or formed by epitaxial growth. Depending on the progression of the epitaxial growth, it may be necessary to anisotropically etch the epitaxially grown material to obtain an upper surface of the source / drain zone 16 suitable for subsequent processing. The dopant can be supplied to the doped zone(s) 16 (e.g., source / drain zone(s)) by ion implantation, and the source / drains can be formed by annealing the doped zone(s) 16.

[0027] Fig. Figure 6 is a cross-sectional view of the structure of the Fig. 5 according to the present invention, wherein an etching is carried out to form a first set of spacers in the vicinity of the first source / drain zone and a second set of spacers in the vicinity of the fin.

[0028] In various embodiments, the dielectric lining 18 is etched to form a first set of spacers 20 adjacent to the fin 12 and side wall portions of the hard mask 14. The dielectric lining 18 is also etched to form a second set of spacers 22 adjacent to the substrate 10 and side wall portions of the doped lower S / D 16. The etching can be, for example, RIE etching. The etching also exposes the upper surface 15 of the hard mask 14. The etching also exposes the upper surfaces 17 of the doped lower S / D 16. The spacers 20 contact the entire side wall surface of the fin 12. The spacers 22 contact a major portion of the side wall surface of the doped lower S / D 16.

[0029] Fig. Figure 7 is a cross-sectional view of the structure of the Fig. 6 according to the present invention, wherein the first source / drain zone is recessed in exposed areas.

[0030] In various embodiments, the doped lower S / D is etched to form recesses 24 in areas not covered by the dielectric lining 18 (or the second set of spacers 22). The recesses 24 extend a length “A” into the doped lower S / D 16. In one example, the recesses extend a length “B” on one side of the fin 12 and a length “C” on the other side of the fin 12, where lengths “B” and “C” may be different from each other. Of course, the person skilled in the art can also provide for such lengths to be substantially equal.

[0031] Fig. Figure 8 is a cross-sectional view of the structure of the Fig. 7 according to the present invention, wherein a zone of shallow trench insulation (STI) is formed over the first source / drain zones.

[0032] In various embodiments, STI zones 26 are formed within the recesses 24. The STI zones 26 cover the entire second set of spacers 22. The STI zones 26 extend a distance or length “D” above the doped lower S / D 16, such that the STI zones 26 contact a side wall of the first set of spacers 20. Thus, the STI zones 26 cover the entire recessed areas 24, extending upwards to the first set of spacers 20. In other words, the STI zones 26 are formed and recessed / planarized to a height that lies above the lower section / part of the fin 12. Therefore, the upper surface 25 of the STI zones 26 extends above a lower surface 13 of the fin 12.

[0033] The shallow trench insulation (STI) zones 26 are formed by etching a trench in the doped lower S / D 16 by a conventional dry etching process, such as RIE or plasma etching. The trenches may optionally be lined with a conventional lining material, such as silicon nitride or silicon oxynitride, and then a CVD or other similar deposition process is applied to fill the trench with silicon oxide or another similar STI dielectric material. The STI dielectric may optionally be compacted after deposition. If desired, a conventional planarization process, such as chemical-mechanical polishing (CMP), may be applied to provide a planar structure.

[0034] Fig. Figure 9 is a cross-sectional view of the structure of the Fig. 8 according to the present invention, wherein the second set of spacers in the vicinity of the fin is selectively removed and a lower spacer is deposited above the STI and the exposed zones of the first source / drain zones.

[0035] In various embodiments, the first set of spacers 20 is selectively removed, and a lower spacer is deposited. In other words, a first spacer or lower spacer 28 is deposited by a directional deposition process, such as high-density plasma deposition (HDP) or gas clustering ion beam deposition (GCIB). Directional deposition means that the deposition preferably takes place on horizontal surfaces rather than vertical surfaces. After directional deposition, wet deposition can be performed to remove the unwanted lower spacer material 28 from the vertical surfaces. Thus, the lower spacer 28 contacts or covers the STI zones 26 and the upper surface 15 of the hard mask 14. The lower spacer 28 can, for example, be a nitride thin film.In one embodiment, the lower spacer 28 can be an oxide, for example silicon oxide (SiO), a nitride, for example silicon nitride (SiN), or an oxynitride, for example silicon oxynitride (SiON).

[0036] Fig. Figure 10 is a cross-sectional view of the structure of the Fig. 9 according to the present invention, wherein a metal gate stack is formed above the lower spacer.

[0037] In various embodiments, a metal gate 30 or a high-k metal gate (HKMG) 30 is formed over the lower spacers 28, which are formed over the STI zones 26. The thickness of the HKMG 30 is greater than the thickness of the lower spacer 28. The thickness of the HKMG 30 is greater than the thickness of the STI zones 26 that are formed over the lower spacer 28. The HKMG 30 extends along the side walls of the fin 12. However, the HKMG 30 does not contact the entire side wall surface of the fin 12. In fact, a length "H" of the side wall of the fin 12 remains uncovered.

[0038] In various embodiments, the HKMG 30 can, but is not limited to, emitter working metals such as titanium nitride, titanium carbide, titanium aluminum carbide, tantalum nitride and tantalum carbide; conductive metals such as tungsten, aluminum and copper; and oxides such as silicon dioxide (SiO2), hafnium oxide (e.g. HfO2), hafnium silicon oxide (e.g. HfSiO4), hafnium silicon oxynitride (Hfw Si x O y N z ), Lanthanum oxide (e.g., La2O3), lanthanum aluminum oxide (e.g., LaAlO3), zirconium oxide (e.g., ZrO2), zirconium silicon oxide (e.g., ZrSiO4), zirconium silicon oxynitride (Zr w Si x O y N z ), tantalum oxide (e.g., TaO2, Ta2O5), titanium oxide (e.g., TiO2), barium strontium titanium oxide (e.g., BaTiO3-SrTiO3), barium titanium oxide (e.g., BaTiO3), strontium titanium oxide (e.g., SrTiO3), yttrium oxide (e.g., Y2O3), aluminum oxide (e.g., Al2O3), lead scandium tantalum oxide (Pb(Sc x Ta 1-x )O3) and lead zinc niobate (e.g. PbZn 1 / 3 Note 2 / 3 O3).

[0039] Fig. Figure 11 is a cross-sectional view of the structure of the Fig. 10 according to the present invention, wherein an upper spacer is formed above the metal gate stack.

[0040] In various embodiments, an upper spacer is deposited. The upper spacer is a second spacer 32, which is deposited and etched back such that the upper spacer 32 is deposited above the HKMG 30. The upper spacer 32 can, for example, be a nitride thin film. In one embodiment, the upper spacer 32 can be an oxide, for example silicon oxide (SiO), a nitride, for example silicon nitride (SiN), or an oxynitride, for example silicon oxynitride (SiON).

[0041] Fig. Figure 12 is a cross-sectional view of the structure of the Fig. 11 according to the present invention, wherein the metal gate stack is cut.

[0042] In various embodiments, a gate cut is performed such that a portion of the metal gate 30 is cut away to expose the upper surface 27 of the lower spacer 28. The cut 34 extends over a distance “X” to the upper surface 27 of the lower spacer 28.

[0043] Fig. Figure 13 is a cross-sectional view of the structure of the Fig. 12 according to the present invention, wherein after selective removal of the materials 32 and 14 on top of the fin 12 by etching an upper source / drain zone is formed over the fin.

[0044] In various embodiments, the material is filled with an interlayer dielectric (ILD) oxide. The ILD 36 is planarized. The ILD 36 encloses, envelops, or surrounds the upper spacer 32 in one section and the lower spacer 28 in another section (the cut section). After ILD planarization, the materials 32 and 14 on top of the fin 12 are selectively removed by an etching process. Subsequently, a doped upper source / drain zone 38 is formed above the fin 12.

[0045] In an exemplary embodiment, the ILD 36 extends to an upper point of the doped upper S / D 38. In other words, an upper surface 35 of the ILD 36 is flush with an upper surface 37 of the doped upper S / D 38. The doped upper S / D 38 can cover the entire upper surface of the fin 12. In the gate cut zone 34, the ILD 36 contacts the upper spacer 32 as well as an exposed side wall surface of the HKMG 30. The ILD 36 can be selected from the group consisting of silicon-containing materials such as SiO2, Si3N4, SiO x N y -, SiC, SiCO, SiCOH and SiCH compounds.

[0046] Fig. Figure 14 is a cross-sectional view of the structure of the Fig. 13 according to the present invention, wherein upper and lower contacts are formed.

[0047] In various embodiments, a gate contact 40, an upper contact 41, and a lower contact 42 are formed. The gate contact 40 extends into the HKMG 30. The upper contact 41 extends to the doped upper S / D 38 formed above the fin 12. The lower contact 42 extends to an upper surface of the doped lower S / D 16, the upper surface of the second spacer 22, and the upper surface of the STI zone 26. The ILD oxide 36 is further removed to form the contacts 40, 41, and 42. The remaining ILD oxide is designated 36'. The upper surface 35' of the remaining ILD oxide 36' is flush with the upper surfaces of the contacts 40, 41, and 42. Additionally, a portion of the upper spacer 32 is removed to make room for the gate contact 40. The remaining upper spacer can be labelled 32'. The finished semiconductor structure 50 is in Fig. 14 shown.

[0048] In various embodiments, the structure 50 reduces gate-to-source / drain capacitances by extending the STI zone 26 between the metal gate stack 30 and the first source / drain zone 16. The distance between the metal gate stack 30 and the first source / drain zone 16 is greater than approximately 10 nm. Furthermore, the lower spacer 28 formed above the STI zone 26 defines a reverse-stepped structural configuration. Therefore, the structure 50 reduces parasitic capacitance by decreasing the overlap between the gate and the lower source / drain (S / D). The distance between the gate and the lower S / D is extended to greater than approximately 10 nm, which in turn increases the Vmax of the unit. Furthermore, VFETs are formed with hybrid spacers of an inverted stepped shape to further reduce the gate-to-source / drain capacitances and improve the maximum operating voltage.

[0049] Fig. Figure 15 is a block diagram / flowchart of a method for reducing parasitic capacity according to the present invention.

[0050] In block 102, a fin structure is formed over a substrate.

[0051] In block 104, a first source / drain zone is formed between the fin structure and the substrate.

[0052] In block 106, the first spacers are formed adjacent to the fin structure. These first spacers are created by etching a dielectric lining adjacent to the fin.

[0053] In block 108, second spacers are formed adjacent to the first source / drain zone. These second spacers are formed by etching the dielectric lining adjacent to the first source / drain zone.

[0054] In block 110, the first source / drain zone is omitted in exposed areas. These exposed areas are those not covered by the dielectric lining.

[0055] In Block 112, a shallow trench insulation (STI) zone is formed within the exposed areas of the first source / drain zone. The STI zones also cover the second set of spacers adjacent to the first source / drain zone.

[0056] In block 114, a lower spacer is deposited above the STI zone.

[0057] In block 116, a metal gate stack is formed above the lower spacer.

[0058] In block 118, an upper spacer is formed above the metal gate stack.

[0059] Block 120 cuts the metal gate stack.

[0060] In block 122, a second source / drain zone is formed directly above the fin structure.

[0061] In block 124, contacts are formed such that the STI zone extends over a length between the metal gate stack and the first source / drain zone.

[0062] It is understood that the present invention is described in the form of a given illustrative architecture, but that within the scope of the present invention other architectures, structures, substrate materials and process features and steps / blocks may also be used as variations.

[0063] It is also understood that when an element such as a layer, zone, or substrate is described as being "on" or "above" another element, it may be located directly on top of the other element, or there may be elements positioned between them. However, when an element is described as being "directly on" or "directly above" another element, there are no elements positioned between them. Similarly, when an element is described as being "connected" or "linked" to another element, it may be directly connected or linked to the other element, or there may be elements positioned between them. However, when an element is described as being "directly connected" or "directly linked" to another element, there are no elements positioned between them.

[0064] The embodiments of the present invention may comprise a design for an integrated circuit (IC) chip, which can be generated in a graphical computer programming language and stored on a computer storage medium (e.g., a disk, tape, physical hard disk drive, or virtual hard disk drive, e.g., a storage access network). If the developer does not manufacture chips or photolithographic masks used for chip fabrication, the developer may send the resulting design directly or indirectly to such companies, either through physical mechanisms (e.g., by providing a copy of the storage medium on which the design is stored) or electronically (e.g., via the internet). The stored design is then converted into the correct format (e.g., GDSII) for the fabrication of photolithographic masks, comprising multiple copies of the chip design to be formed on a wafer.Photolithography masks are used to define areas of the wafer (and / or the layers on it) to be etched or otherwise processed.

[0065] Methods such as those described herein can be applied in the fabrication of IC chips. The resulting IC chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer containing multiple unencapsulated chips), as a bare die, or in an encapsulated form. In the latter case, the chip is mounted in a single-chip encapsulation (e.g., a plastic substrate with traces attached to a motherboard or other higher-level support) or in a multi-chip encapsulation (e.g., a ceramic substrate having surface interconnects and / or buried interconnects). In each case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing units as part of (a) an intermediate product, e.g., a motherboard, or (b) a final product.The end product can be any product that includes IC chips, ranging from toys and other simple applications to highly sophisticated computer products that feature a display unit, a keyboard or other input device, and a central processing unit.

[0066] It is also understood that material compounds are described in the form of listed elements, such as SiGe. These compounds comprise different proportions of the elements within the compound; for example, SiGe comprises Si x Ge 1-x , where x is less than or equal to 1, etc. Furthermore, other elements may be included in the compound and still function according to the embodiments of the present invention. Compounds with additional elements are referred to herein as alloys.

[0067] A reference in the description to "an embodiment" of the present invention, as well as variations thereof, means that a particular feature, structure, property, etc., described in connection with the embodiment, is included in at least one embodiment of the present invention. Therefore, if the term "in an embodiment," as well as any variation thereof, appears at different points in the description, it does not necessarily refer to the same embodiment each time.

[0068] It should be noted that the use of “ / ”, “and / or” or “at least one of”, for example in the case of “A / B”, “A and / or B” and “at least one of A and B”, is intended to include the selection of the first listed option (A) alone, or the selection of the second listed option (B) alone, or the selection of both options (A and B).As a further example, in the case of "A, B and / or C" and "at least one of A, B and C", these expressions are to include the selection of the first listed option (A) alone, or the selection of the second listed option (B) alone, or the selection of the third listed option (C) alone, or the selection of only the first and second listed options (A and B), or the selection of only the first and third listed options (A and C), or the selection of only the second and third listed options (B and C), or the selection of all three options (A, B and C). As the person skilled in the art in these and related fields will readily recognize, this can be extended to as many elements as are listed.

[0069] The terminology used herein serves only to describe specific embodiments and is not intended to limit exemplary embodiments. As used herein, the singular forms "a," "an," and "the" are to include the plural forms as well, unless the context clearly indicates otherwise. It is further understood that the terms "indicates," "shows," "show," "comprises," and / or "comprise," when used herein, describe the presence of specified features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0070] To simplify the description, terms of spatial relationship such as "below," "under," "lower," "above," "upper," and the like can be used to describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. It is understood that, in addition to the orientation shown in the figures, these terms of spatial relationship are intended to encompass other orientations of the unit in use or operation. For example, if the unit in the figures is reversed, elements described as being "below" or "underneath" other elements or features would then be oriented "above" the other elements or features. Thus, the term "below" can encompass both an orientation "above" and an orientation "below."The unit may be oriented differently (rotated by 90 degrees or have other orientations), and the descriptors of spatial relationship used herein may be interpreted accordingly. Furthermore, it is understood that when a layer is described as being "between" two layers, it may be the only layer between the two layers, or there may also be one or more layers positioned between them.

[0071] It is understood that, although the terms first, second, etc. may be used herein to describe different elements, these elements are not intended to be limited by these terms. These terms are used only to distinguish one element from another. Thus, a first element described below could be referred to as a second element without altering the scope of the concept of the present invention.

[0072] Having now described preferred embodiments of a method for manufacturing a unit and a semiconductor unit thereby produced for reducing the parasitic capacitance in vertical FETs (which are intended to be illustrative and not limiting), it should be noted that the person skilled in the art may make modifications and variations in light of the above teachings. It is therefore understood that changes may be made to the described specific embodiments that fall within the scope of the invention, as outlined by the appended claims. Having thus described manifestations of the invention in detail and with the precision required by patent law, the appended claims set out what is claimed and protected by the patent.

[0073] The invention can further be described, without limitation and only by way of example, by the following embodiments. The following embodiments may include preferred embodiments. Accordingly, the term "clause" used therein may refer to such a "preferred embodiment". Clause 1. Method for reducing the parasitic capacitance of a semiconductor structure, wherein the method comprises: Forming a fin structure over a substrate, Forming an initial source / drain zone between the fin structure and the substrate; Forming the first spacer in the vicinity of the fin structure; Form a second spacer adjacent to the first source / drain zone; Omitting the first source / drain zone in exposed areas; Forming a zone of shallow trench insulation (STI) within the exposed areas of the recessed first source / drain zone; Cutting a lower spacer above the STI zone; Forming a metal gate stack above the lower spacer; Cutting an upper spacer above the metal gate stack; Cutting the metal gate stack; Forming a second source / drain zone above the fin structure; and Forming contacts so that the STI zone extends over a length between the metal gate stack and the first source / drain zone. Clause 2. Method according to Clause 1, wherein gate-to-source / drain capacities are reduced by extending the STI zone between the metal gate stack and the first source / drain zone. Clause 3. Method according to Clause 1, wherein the first and second spacers are form-fitting dielectric linings. Clause 4. Method according to Clause 3, wherein the thickness of the shape-conforming dielectric linings is more than 10 nm. Clause 5. Procedure according to Clause 1, wherein the STI contacts a portion of the first spacers in the vicinity of the fin structure. Clause 6. Procedure according to Clause 1, wherein the STI covers the second spacers adjacent to the first source / drain zone in their entirety. Clause 7. Procedure according to Clause 1, wherein the second spacers adjacent to the first source / drain zone are selectively removed before the lower spacer is deposited above the STI zone. Clause 8. Procedure according to Clause 1, wherein the lower spacer formed above the STI zone defines a reverse-stepped structural configuration. Clause 9. Procedure according to Clause 1, wherein the STI zone extends over part of the first source / drain zone at opposite ends of the fin structure. Clause 10. Method according to Clause 1, wherein the distance between the metal gate stack and the first source / drain zone is more than 10 nm. Clause 11. Semiconductor structure for reducing parasitic capacitance, wherein the structure comprises: a fin structure that is formed over a substrate; a first source / drain zone that is formed between the fin structure and the substrate; first spacers formed in the vicinity of the fin structure; second spacers located adjacent to the first source / drain zone are formed, with the first source / drain zone being omitted in exposed areas; a zone of shallow trench insulation (STI) formed within the exposed areas of the recessed first source / drain zone; a lower spacer that is separated above the STI zone; a metal gate stack formed above the lower spacer; an upper spacer formed above the metal gate stack, with the metal gate stack being cut; a second source / drain zone formed above the fin structure; and Contacts designed so that the STI zone extends over a length between the metal gate stack and the first source / drain zone. Clause 12. Structure according to Clause 11, wherein gate-to-source / drain capacities are reduced by extending the STI zone between the metal gate stack and the first source / drain zone. Clause 13. Structure according to Clause 11, wherein the first and second spacers are form-fitting dielectric linings. Clause 14. Structure according to Clause 13, wherein the thickness of the shape-conforming dielectric linings is more than 10 nm. Clause 15. Structure according to Clause 11, wherein the STI contacts a portion of the first spacers in the vicinity of the fin structure. Clause 16. Structure according to Clause 11, wherein the STI covers the second spacers adjacent to the first source / drain zone in their entirety. Clause 17. Structure according to Clause 11, wherein the second spacers adjacent to the first source / drain zone are selectively removed before the lower spacer is deposited above the STI zone. Clause 18. Structure according to Clause 11, wherein the lower spacer formed above the STI zone defines a reverse-stepped structural configuration. Clause 19. Structure according to Clause 11, wherein the STI zone extends over part of the first source / drain zone at opposite ends of the fin structure. Clause 20. Structure according to Clause 11, wherein the distance between the metal gate stack and the first source / drain zone is more than 10 nm.

Claims

[1] Method for reducing the parasitic capacitance of a semiconductor structure (50), wherein the method comprises: Formation (104) of a first source / drain zone (16) under a fin structure (12); Omission (110) of the first source / drain zone in exposed areas (24); Forming (112) a zone of shallow trench isolation (26), hereinafter referred to as STI, within the exposed areas (24) of the recessed first source / drain zone; Deposition (114) of a lower spacer (28) above the STI zone and in direct contact with the first source / drain zone, wherein the lower spacer defines a reverse-stepped structural configuration; Forming (116) a metal gate stack (30) above the lower spacer, so that gate-to-source / drain capacitances are reduced by extending the STI zone between the metal gate stack and the first source / drain zone; where: a distance between the metal gate stack and the first source / drain zone is more than 10 nm and / or the procedure has one or more of: Forming (106) the first spacer (20) adjacent to the fin structure and cutting (120) the metal gate stack after forming the first spacers (20) adjacent to the fin structure; or Form (108) a second spacer (22) adjacent to the first source / drain zone; or Forming (124) contacts (40, 41, 42) such that the STI zone extends over a length between the metal gate stack and the first source / drain zone. [2] Method according to claim 1, further comprising a deposition (118) of an upper spacer (32) above the metal gate stack. [3] Method according to claim 1 or 2, further comprising forming (122) a second source / drain zone (38) over the fin structure after cutting the metal gate stack. [4] Method according to any of the preceding claims, wherein the STI zone covers the second spacers adjacent to the first source / drain zone in their entirety. [5] Method according to any of the preceding claims, wherein the second spacers in the vicinity of the first source / drain zone are selectively removed before the lower spacer is deposited above the STI zone. [6] Semiconductor structure (50) for reducing parasitic capacitance, wherein the structure has: a first source / drain zone (16) formed under a fin structure (12); exposed areas (24) formed by omitting the first source / drain zone; a zone of shallow trench isolation (26), hereinafter referred to as STI, which is formed within the exposed areas of the recessed first source / drain zone; a lower spacer (28) deposited above the STI zone and in direct contact with the first source / drain zone, the lower spacer defining a reverse-stepped structural configuration; and a metal gate stack (30) formed above the lower spacer, such that gate-to-source / drain capacitances are reduced by extending the STI zone between the metal gate stack and the first source / drain zone; where: second spacers (22) are formed in the vicinity of the first source / drain zone; and / or an upper spacer (32) is deposited above the metal gate stack; and / or Contacts (40, 41, 42) are configured such that the STI zone extends over a length between the metal gate stack and the first source / drain zone; and / or; a distance between the metal gate stack and the first source / drain zone is more than 10 nm. [7] Structure according to claim 6, wherein first spacers (20) are formed in the vicinity of the fin structure. [8] Structure according to claim 7, wherein the metal gate stack is cut after the first spacer has been deposited. [9] Structure according to claim 8, wherein a second source / drain zone (38) is formed above the fin structure after cutting the metal gate stack. [10] Structure according to any one of claims 6 to 9, wherein the STI zone covers the second spacers adjacent to the first source / drain zone in their entirety. [11] Structure according to any one of claims 6 to 10, wherein the second spacers in the vicinity of the first source / drain zone are selectively removed before the lower spacer is deposited above the STI zone.

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