IGBT device

Abstract

Bipolar transistor device with insulated gate electrode, IGBT device comprising: an n-collector region (20), a p-collector region (30), an n-drift region (21) located above the n-collector region (20) and the p-collector region (30), and a metal oxide semiconductor field-effect transistor cell matrix, MOSFET cell matrix comprising multiple MOSFET cells (200, 201);wherein each of the multiple MOSFET cells (200, 201) comprises: a p-body region (22) located at an upper part of the n-drift region (21), an n-emitter region (23) located in the p-body region (22), and a gate structure located above the p-body region (22), the gate structure comprising a dielectric gate layer (24), a gate electrode (26), and an n-floating gate (25), wherein the gate electrode (26) and the n-floating gate (25) are located above the dielectric gate layer (24), the gate electrode (26) is located on one side near the n-emitter region (23), the n-floating gate (25) is located on one side near the n-drift region (21), and the gate electrode (26) acts on the n-floating gate (25) via a capacitive coupling;and wherein in the MOSFET cell matrix the n-floating gate (25) of at least one of the several MOSFET cells (200, 201) is insulated from the p-body region (22) by the dielectric gate layer (24) and the n-floating gate (25) of at least one of the several MOSFET cells (200, 201) contacts the p-body region (22) via an opening (28) so that a pn-area diode is formed, the opening (28) being located in the dielectric gate layer (24) below the n-floating gate (25).

Description

TECHNICAL FIELDThe present application belongs to the technical field of insulated gate bipolar transistor devices (Engl. Insulated Gate Bipolar Transistor - IGBT) and, for example, an IGBT device with adjustable reverse recovery speed.BACKGROUNDAn insulated gate bipolar transistor (IGBT) device is a device including a metal oxide semiconductor (IGBT) device. A metal oxide semiconductor (MOS) transistor and a bipolar transistor, wherein an input of the IGBT device is the MOS transistor and an output of the IGBT device is a PNP transistor. The turning on and off of the IGBT device of the related art is controlled by a gate-emitter voltage. When the gate-emitter voltage is higher than a threshold voltage Vth of the MOS transistor, a current channel is formed inside the MOS transistor, and a base current is supplied to the bipolar transistor, so that the IGBT device is turned on. When the gate-emitter voltage is lower than the threshold voltage Vth of the MOS transistor, the current channel inside the MOS transistor is turned off, and the base current of the bipolar transistor is turned off, so that the IGBT device is turned off. When the IGBT device of the related art is turned off when a collector-emitter voltage is less than 0 V, a parasitic body diode in the IGBT device is in a positive bias state, and a reverse current flows through the body diode from an emitter to a collector. In this case, the current in the body diode injects minority carriers, and the reverse recovery of these minority carriers occurs when the IGBT device is turned on again, thereby causing a relatively high reverse recovery current and a long reverse recovery time.From US 2009 / 0 026 532 A1 a power semiconductor device is known, which comprises a semiconductor body comprising a body region of a first conductivity type for forming a conductive channel of a second conductivity type therein; a gate electrode arranged next to the body region; and a floating electrode arranged between the gate electrode and the body region.JP 2001-94 099 A describes a MOSFET which has an n-collector region, an n-drift region and a MOSFET cell matrix.SUMMARYThe invention is defined by the independent claims. Advantageous embodiments are given in the dependent claims.The present invention provides an IGBT device with an adjustable reverse recovery speed to solve the long reverse recovery time problem caused by injection of minority carriers of a prior art IGBT device.An IGBT device is provided in an embodiment of the present invention and includes an n-collector region, a p-collector region, an n-drift region overlying the n-collector region and the p-collector region, and a metal oxide semiconductor field effect transistor (MOSFET) cell array having multiple MOSFET cells.Each of the plurality of MOSFET cells includes a p-body region located at the top of the n-drift region, an n-emitter region located in the p-body region, and a gate structure located over the p-body region, the gate structure including a gate dielectric layer, a gate electrode, and an n-floating gate, the gate electrode and the n-floating gate located over the gate dielectric layer, the gate electrode located on a side near the n-emitter region, the n-floating gate located on a side near the n-drift region, and the gate electrode acting on the n-floating gate via a capacitive coupling.In the MOSFET cell array, the n-type floating gate of at least one MOSFET cell is insulated from the p-type body region by the gate dielectric electrode, and the n-type floating gate of at least one MOSFET cell contacts the p-type body region via an opening, so that a p-n junction diode is formed, the opening in the gate dielectric layer being located below the n-type floating gate.Optionally, the IGBT device of the present invention further comprises an n-field blocking region overlying the n-collector region and the p-collector region, wherein the n-field blocking region overlies the n-drift region.Optionally, in the IGBT device of the present invention, the gate electrode extends over the n-floating gate.Optionally, in the IGBT device of the present invention, the gate electrode extends over the n-type floating gate and covers a sidewall of the n-type floating gate near the n-type drift region.Optionally, in the IGBT device of the present invention, the opening is under the n-floating gate and on a side near the n-drift region.Optionally, in the IGBT device of the present invention, a gate electrode of at least one MOSFET cell is electrically connected to the n-type emitter region.According to the IGBT device provided by the embodiment of the present invention, the reverse recovery speed of the IGBT device can be adjusted by controlling the number of MOSFET cells formed with p-n junction diodes in an appropriate and precise manner, so that the IGBT device has broader application. When the number of MOSFET cells formed with the p-n junction diodes is adjusted, only a mask for forming the opening in the gate dielectric layer needs to be changed, whereby the manufacturing cost of the IGBT device can be effectively controlled.BRIEF DESCRIPTION OF THE DRAWINGSDrawings used in the embodiments will be briefly described below. FIG. 1 is a sectional view of an IGBT device according to a first embodiment of the present invention; and FIG. 2 is a sectional view of an IGBT device according to a second embodiment of the present invention.DETAILED DESCRIPTIONThe concept of the present invention will be described below with reference to specific implementations together with the drawings in the embodiments of the present invention. Here, in the schematic diagrams illustrated in the drawings of the specification, the dimensions of the layers and the dimensions of the regions described in the present invention are shown enlarged, and the dimensions illustrated in the drawings do not represent the actual dimensions. The embodiments described in the specification are not intended to limit the ranges shown in the drawings to specific shapes, but include shapes obtained, for example, manufacturing-related dimensional deviations.FIG. 1 is a sectional view of an IGBT device according to a first embodiment of the present invention. As shown in FIG. 1, an IGBT device provided by an embodiment of the present invention includes an n-collector region 20, a p-collector region 30, an n-field blocking region 29 overlying the n-collector region 20 and the p-collector region 30, an n-drift region 21 overlying the n-field blocking region 29, and a MOSFET cell array consisting of a plurality of MOSFET cells. Two MOSFET cells (MOSFET cell 200 and MOSFET cell 201) are shown in FIG. 1 by way of example.The MOSFET cell of the embodiment of the present invention includes a p-body region 22 located at the upper part of the n-drift region 21, an n-emitter region 23 located in the p-body region 22, and a gate structure located above the p-body region 22. The gate structure includes a gate dielectric layer 24, an n-type floating gate 25, and a gate electrode 26. the gate electrode 26 overlies the gate dielectric layer 24 and lies on a side near the n-type emitter region 23 and extends to a side of the n-type drift region 21 so as to overlie the n-type floating gate 25. The n-type floating gate 25 overlies the gate dielectric layer 24 and is located on a side near the n-type drift region 21, the gate electrode 26 and the n-type floating gate 25 are insulated by a dielectric insulating film 27, and the gate electrode 26 acts on the n-type floating gate 25 via capacitive coupling.In the MOSFET cell array of the embodiment of the present invention, the n-type floating gate 25 of at least one MOSFET cell (such as the MOSFET cell 201 shown in FIG. 1 ) is separated from the p-type body region 22 by the gate dielectric layer 24, and the n-type floating gate 25 of at least one MOSFET cell (such as the MOSFET cell 200 shown in FIG. 1 ) contacts the p-type body region 22 via an opening 28 in the gate dielectric layer 24 that is below the n-type floating gate 25, so that a p-n junction diode is formed.In the embodiment of the present invention, the gate electrode 26 of the MOSFET cell may be located only on the side near the n-type emitter region 23, i.e., in the lateral direction, with the gate electrode 26 and the n-type floating gate 25 being arranged on the left and right, or the gate electrode 26 may be located on the side near the n-type emitter region 23 and extend to one side of the n-type drift region 21 so as to be located above the n-type floating gate 25 (as shown in FIG. 2 ). The gate electrode 26 extends over the n-type floating gate 25, whereby an area of the n-type floating gate 25 covered by the gate electrode 26 can be increased, and the capacitive coupling rate between the gate electrode 26 and the n-type floating gate 25 can be increased.In this embodiment of the present invention, when the IGBT device is in a forward blocking state, a high voltage is applied to the n-collector region 20 and the p-collector region 30, the p-n junction diode formed by the n-floating gate 25 and the p-body region 22 in the MOSFET cell 200 is forward biased, and the n-floating gate 25 in the MOSFET cell 200 is charged with a positive charge. As a result, a threshold voltage Vht1 of the current channel below the n-type floating gate 25 in the MOSFET cell 200 is reduced. The voltage of the n-type floating gate 25 in the MOSFET cell 200 is related to the location of the opening 28 in the gate dielectric layer 24. The opening 28 in the gate dielectric layer 24 is optionally below the n-type floating gate 25 and is on a side near the n-type drift region 21, so that the n-type floating gate 25 can be more easily charged with the positive charge.In this embodiment, when the IGBT device is in a forward blocking state and a forward turn-on state, the collector-emitter voltage Vce is higher than 0 V, the threshold voltage Vht 1 of the current channel under the n-type floating gate 25 in the MOSFET cell 200 has little influence on the threshold voltage Vth of the entire MOSFET cell 200, and the MOSFET cell 200 further has a high threshold voltage Vth. In this embodiment of the present invention, when the IGBT device is turned off and the emitter-collector voltage Vec is higher than 0 V, the threshold voltage Vht 1 of the current channel under the n-type floating gate 25 in the MOSFET cell 200 has a strong influence on the threshold voltage Vth of the entire MOSFET cell 200, so that the MOSFET cell 200 has a low threshold voltage Vth and thereby the current channel of the MOSFET cell 200 is turned on at a low gate voltage (or a voltage of 0 V). Thereby, the reverse current flowing through the MOSFET cell 200 can be increased, the current flowing through a parasitic body diode in the IGBT device can be reduced, and the reverse recovery speed of the entire IGBT device can be improved.According to the IGBT device provided by the embodiment of the present invention, by controlling the number of MOSFET cells formed with p-n junction diodes in the MOSFET cell array, the reverse recovery speed of the IGBT device can be adjusted appropriately and precisely, so that the IGBT device has broader application. When the number of MOSFET cells formed with the p-n junction diodes is adjusted, only a mask for forming the opening in the gate dielectric layer needs to be changed, whereby the manufacturing cost of the IGBT device can be effectively controlled.In the MOSFET cell array of the IGBT device of the embodiment of the present invention, the gate electrode 26 of at least one MOSFET cell may be electrically connected to the n-type emitter region 23, i.e., this part of the gate electrodes 26 is connected to the emitter voltage, whereby the gate charge of the IGBT device can be reduced.FIG. 2 is a sectional view of an IGBT device according to a second embodiment of the present invention. In contrast to the structure of the IGBT device of the embodiment of the present invention shown in FIG. 1, in the IGBT device of this embodiment, the gate electrode 26 of the MOSFET cell extends to one side of the n-drift region 21 so as to be located above the n-floating gate 25 and to cover a sidewall of the n-floating gate 25 near the n-drift region 21. This can increase the area of the n-type floating gate 25 covered by the gate electrode 26, and further increase the capacitive coupling rate between the gate electrode 26 and the n-type floating gate 25.

Claims

An insulated gate bipolar transistor, IGBT, device comprising: an n-collector region (20), a p-collector region (30), an n-drift region (21) overlying the n-collector region (20) and the p-collector region (30), and a metal oxide semiconductor field effect transistor, MOSFET, cell array having a plurality of MOSFET cells (200, 201); wherein each of the plurality of MOSFET cells (200, 201) comprises: a p-body region (22) overlying an upper portion of the n-drift region (21), an n-emitter region (23) overlying the p-body region (22), and a gate structure, which is situated above the p-body region (22), the gate structure comprising a gate dielectric layer (24), a gate electrode (26) and an n-floating gate (25), the gate electrode (26) and the n-floating gate (25) being situated above the gate dielectric layer (24), the gate electrode (26) being situated on a side close to the n-emitter region (23), the n-floating gate (25) being situated on a side close to the n-drift region (21) and the gate electrode (26) acting on the n-floating gate (25) via a capacitive coupling; and wherein in the MOSFET cell matrix, the n-floating gate (25) of at least one of the plurality of MOSFET cells (200, 201) is insulated from the p-body region (22) by the gate dielectric layer (24), and the n-floating gate (25) of at least one of the plurality of MOSFET cells (200, 201) contacts the p-body region (22) via an opening (28), such that a p-n junction diode is formed, wherein the opening (28) in the gate dielectric layer (24) lies below the n-floating gate (25).The IGBT device of claim 1, further comprising: an n-field blocking region (29) overlying the n-collector region (20) and the p-collector region (30), wherein the n-field blocking region (29) overlies the n-drift region (21).The IGBT device of claim 1, wherein the gate electrode (26) extends over the n-floating gate (25).The IGBT device of claim 1, wherein the gate electrode (26) extends over the n-type floating gate (25) and covers a sidewall of the n-type floating gate (25) near the n-type drift region (21).The IGBT device of claim 1, wherein the opening (28) is below the n-floating gate (25) and on a side near the n-drift region (21).The IGBT device of claim 1, wherein a gate electrode (26) of at least one of the plurality of MOSFET cells (200, 201) is electrically connected to the n-type emitter region (23).

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