Semiconductor module parallel connection and semiconductor module interconnect substrate

Abstract

Semiconductor module parallel circuit (1), with: a first power semiconductor module (10-1); a second power semiconductor module (10-2); and a multilayer substrate (100) for connecting a plurality of the power semiconductor modules, wherein Each of the power semiconductor modules features: a power semiconductor switching element (30; 40); a first signal terminal (11-1) which is connected to a gate potential of the power semiconductor switching element; and a second signal terminal (13-1) which is connected to a source potential of the power semiconductor switching element, the multilayer substrate exhibits: an external connection port (61); a first signal connection pattern (111-1) for the first power semiconductor module, wherein the first signal connection pattern for the first power semiconductor module is connected to the first signal terminal of the first power semiconductor module; a second signal connection pattern (113-1) for the first power semiconductor module, wherein the second signal connection pattern for the first power semiconductor module is connected to the second signal terminal of the first power semiconductor module; a first signal connection pattern (111-2) for the second power semiconductor module, wherein the first signal connection pattern for the second power semiconductor module is connected to the first signal terminal of the second power semiconductor module; and a second signal connection pattern (113-2) for the second power semiconductor module, wherein the second signal connection pattern for the second power semiconductor module is connected to the second signal terminal of the second power semiconductor module, and wherein an inductance of a gate line for the first power semiconductor module from the external connection terminal to the first signal connection pattern for the first power semiconductor module and from the second signal connection pattern for the first power semiconductor module to the external connection terminal, and an inductance of the gate line for the second power semiconductor module from the external connection terminal to the first signal connection pattern for the second power semiconductor module and from the second signal connection pattern for the second power semiconductor module to the external connection terminal are equal to each other, and wherein a line from the external connection terminal to the first signal connection pattern for the first power semiconductor module and a line from the external connection terminal to the first signal connection pattern for the second power semiconductor module are formed in a first layer and in a third layer of the multilayer substrate, and a line from the second signal connection pattern for the first power semiconductor module to the external connection terminal and a line from the second signal connection pattern for the second power semiconductor module to the external connection terminal are formed in a second layer of the multilayer substrate.

Description

Area

[0001] The present invention relates to a semiconductor module parallel circuit and a semiconductor module interconnect substrate. background

[0002] A technique for driving parallel-connected semiconductor switching elements is known from, for example, patent literature 1. Patent literature 1 discloses that twisted cables, which are a gate line to two IGBTs, are placed adjacent to connecting lines, such that electromotive forces generated in the twisted cables and their polarities are essentially equal to each other, and gate-emitter voltages of the individual elements are essentially equal to each other, thereby providing balanced currents flowing through the individual elements. Citation list of patent literature

[0003] Patent Literature 1: Japanese Patent Application Disclosure No. JP H09 - 261 948 A Brief description of the technical problem

[0004] In recent years, the susceptibility to the influence of inductance has increased with rising switching speeds. Patent literature 1 does not permit the influence of inductance. If a difference in inductance occurs between the semiconductor elements, an imbalance arises in the amount of current flowing through individual semiconductor elements. When such an imbalance occurs in the current flowing through the semiconductor elements, a larger amount of current flows through one of the semiconductor elements, leading to a shortened semiconductor lifetime. Solution to the problem

[0005] A semiconductor module parallel circuit of a first invention comprises: a first power semiconductor module; a second power semiconductor module; and a multilayer substrate for connecting a plurality of the power semiconductor modules, each of the power semiconductor modules comprising: a power semiconductor switching element; a first signal terminal connected to a gate potential of the power semiconductor switching element; and a second signal terminal connected to a source potential of the power semiconductor switching element, the multilayer substrate comprising: an external connection terminal; a first signal terminal connection pattern for the first power semiconductor module, the first signal terminal connection pattern for the first power semiconductor module being connected to the first signal terminal of the first power semiconductor module;a second signal connection pattern for the first power semiconductor module, wherein the second signal connection pattern for the first power semiconductor module is connected to the second signal terminal of the first power semiconductor module; a first signal connection pattern for the second power semiconductor module, wherein the first signal connection pattern for the second power semiconductor module is connected to the first signal terminal of the second power semiconductor module;and a second signal connection pattern for the second power semiconductor module, wherein the second signal connection pattern for the second power semiconductor module is connected to the second signal terminal of the second power semiconductor module, and an inductance of a gate line for the first power semiconductor module from the external connection terminal to the first signal connection pattern for the first power semiconductor module and from the second signal connection pattern for the first power semiconductor module to the external connection terminal, and an inductance of the gate line for the second power semiconductor module from the external connection terminal to the first signal connection pattern for the second power semiconductor module and from the second signal connection pattern for the second power semiconductor module to the external connection terminal are equal to each other.

[0006] A semiconductor module parallel circuit of a second invention comprises: a first power semiconductor module; a second power semiconductor module; and a multilayer substrate for connecting a plurality of the power semiconductor modules, each of the power semiconductor modules comprising: a power semiconductor switching element; a first signal terminal connected to a gate potential of the power semiconductor switching element; and a second signal terminal connected to a source potential of the power semiconductor switching element, the multilayer substrate comprising: an external connection terminal; a first signal terminal connection pattern for the first power semiconductor module, the first signal terminal connection pattern for the first power semiconductor module being connected to the first signal terminal of the first power semiconductor module;a second signal connection pattern for the first power semiconductor module, wherein the second signal connection pattern for the first power semiconductor module is connected to the second signal connection for the first power semiconductor module; a first signal connection pattern for the second power semiconductor module, wherein the first signal connection pattern for the second power semiconductor module is connected to the first signal connection of the second power semiconductor module;and a second signal connection pattern for the second power semiconductor module, wherein the second signal connection pattern for the second power semiconductor module is connected to the second signal terminal of the second power semiconductor module, and a length of a gate line for the first power semiconductor module from the external connection terminal to the first signal connection pattern for the first power semiconductor module and from the second signal connection pattern for the first power semiconductor module to the external connection terminal, and a length of a gate line for the second power semiconductor module from the external connection terminal to the first signal connection pattern for the second power semiconductor module and from the second signal connection pattern for the second power semiconductor module to the external connection terminal are equal to each other.

[0007] A semiconductor module interconnect substrate of a third invention comprises: an external interconnect port; a first signal connection pattern for a first power semiconductor module, wherein the first signal connection pattern for the first power semiconductor module is provided for connection to a first signal port of the first power semiconductor module; a second signal connection pattern for the first power semiconductor module, wherein the second signal connection pattern for the first power semiconductor module is provided for connection to a second signal port of the first power semiconductor module; a first signal connection pattern for a second power semiconductor module, wherein the first signal connection pattern for the second power semiconductor module is provided for connection to a first signal port of the second power semiconductor module;and a second signal connection pattern for the second power semiconductor module, wherein the second signal connection pattern for the second power semiconductor module is provided for connection to a second signal terminal of the second power semiconductor module, wherein an inductance of a gate line for the first power semiconductor module from the external connection terminal to the first signal connection pattern for the first power semiconductor module and from the second signal connection pattern for the first power semiconductor module to the external connection terminal, and an inductance of a gate line for the second power semiconductor module from the external connection terminal to the first signal connection pattern for the second power semiconductor module and from the second signal connection pattern for the second power semiconductor module to the external connection terminal are equal to each other. Advantageous effects of the invention

[0008] A semiconductor module parallel circuit according to the first invention comprises: a first power semiconductor module; a second power semiconductor module; and a multilayer substrate for connecting a plurality of the power semiconductor modules, each of the power semiconductor modules comprising: a power semiconductor switching element; a first signal terminal connected to a gate potential of the power semiconductor switching element; and a second signal terminal connected to a source potential of the power semiconductor switching element, the multilayer substrate comprising: an external connection terminal; a first signal terminal connection pattern for the first power semiconductor module, wherein the first signal terminal connection pattern for the first power semiconductor module is connected to the first signal terminal of the first power semiconductor module; a second signal terminal connection pattern for the first power semiconductor module.wherein the second signal connection pattern for the first power semiconductor module is connected to the second signal terminal of the first power semiconductor module; a first signal connection pattern for the second power semiconductor module, wherein the first signal connection pattern for the second power semiconductor module is connected to the first signal terminal of the second power semiconductor module; and a second signal connection pattern for the second power semiconductor module, wherein the second signal connection pattern for the second power semiconductor module is connected to the second signal terminal of the second power semiconductor module,and the inductance of a gate line for the first power semiconductor module from the external connection terminal to the first signal connection pattern for the first power semiconductor module and from the second signal connection pattern for the first power semiconductor module to the external connection terminal, and the inductance of a gate line for the second power semiconductor module from the external connection terminal to the first signal connection pattern for the second power semiconductor module and from the second signal connection pattern for the second power semiconductor module to the external connection terminal are equal to each other. As a result, it is possible to reduce the current imbalance between the semiconductor modules and to decrease the reduction in the lifetime of the semiconductor modules.

[0009] A semiconductor module parallel circuit according to the second invention comprises: a first power semiconductor module; a second power semiconductor module; and a multilayer substrate for connecting a plurality of the power semiconductor modules, each of the power semiconductor modules comprising: a power semiconductor switching element; a first signal terminal connected to a gate potential of the power semiconductor switching element; and a second signal terminal connected to a source potential of the power semiconductor switching element, the multilayer substrate comprising: an external connection terminal; a first signal terminal connection pattern for the first power semiconductor module, wherein the first signal terminal connection pattern for the first power semiconductor module is connected to the first signal terminal of the first power semiconductor module; a second signal terminal connection pattern for the first power semiconductor module.wherein the second signal connection pattern for the first power semiconductor module is connected to the second signal terminal of the first power semiconductor module; a first signal connection pattern for the second power semiconductor module, wherein the first signal connection pattern for the second power semiconductor module is connected to the first signal terminal of the second power semiconductor module; and a second signal connection pattern for the second power semiconductor module, wherein the second signal connection pattern for the second power semiconductor module is connected to the second signal terminal of the second power semiconductor module,and the length of a gate line for the first power semiconductor module from the external connection terminal to the first signal connection pattern for the first power semiconductor module and from the second signal connection pattern for the first power semiconductor module to the external connection terminal, and the length of a gate line for the second power semiconductor module from the external connection terminal to the first signal connection pattern for the second power semiconductor module and from the second signal connection pattern for the second power semiconductor module to the external connection terminal are equal to each other. As a result, it is possible to reduce an imbalance in the current between the semiconductor modules and to decrease the reduction in the lifetime of the semiconductor elements.

[0010] A semiconductor module interconnect substrate according to the third invention comprises: an external interconnect port; a first signal connection pattern for a first power semiconductor module, wherein the first signal connection pattern for the first power semiconductor module is provided for connection to a first signal port of the first power semiconductor module; a second signal connection pattern for the first power semiconductor module, wherein the second signal connection pattern for the first power semiconductor module is provided for connection to a second signal port of the first power semiconductor module; a first signal connection pattern for a second power semiconductor module,wherein the first signal connection pattern for the second power semiconductor module is provided for connection to a first signal terminal of the second power semiconductor module; and a second signal connection pattern for the second power semiconductor module, wherein the second signal connection pattern for the second power semiconductor module is provided for connection to a second signal terminal of the second power semiconductor module, wherein an inductance of a gate line for the first power semiconductor module from the external connection terminal to the first signal connection pattern for the first power semiconductor module and from the second signal connection pattern for the first power semiconductor module to the external connection terminal,and the inductance of a gate line for the second power semiconductor module from the external connection terminal to the first signal connection pattern for the second power semiconductor module and from the second signal connection pattern for the second power semiconductor module to the external connection terminal are equal to each other. As a result, it is possible to reduce current imbalances between the semiconductor modules and to decrease the reduction in the lifetime of the semiconductor modules. Brief description of drawings Fig. Figure 1 shows a view representing a semiconductor module parallel circuit according to a first embodiment. Fig. Figure 2 shows a schematic diagram of the semiconductor module parallel circuit according to the first embodiment. Fig. Figure 3 shows a top view of an assembly that accommodates a semiconductor module according to the first embodiment. Fig. Figure 4 shows a schematic diagram of the semiconductor module according to the first embodiment. Fig. Figure 5 shows a view representing a multilayer substrate according to the first embodiment. Fig. Figure 6 shows a view representing a conductor pattern on the multilayer substrate according to the first embodiment. Fig. Figure 7 shows a view representing a conductor pattern on the multilayer substrate according to the first embodiment. Fig. Figure 8 shows a view depicting a semiconductor module parallel circuit in a second embodiment. Fig. Figure 9 shows a view representing a multilayer substrate according to the second embodiment. Fig. Figure 10 shows a schematic view of the semiconductor module parallel circuit according to the second embodiment. Fig. Figure 11 shows a view representing a gate driver current in the semiconductor module parallel circuit according to the second embodiment. Fig. Figure 12 shows a view representing a semiconductor module parallel circuit in a third embodiment. Fig. Figure 13 shows a view representing a multilayer substrate according to the third embodiment. Fig. Figure 14 shows a schematic view of the semiconductor module parallel circuit according to the third embodiment. Fig. Figure 15 shows a view representing a semiconductor module parallel circuit in a fourth embodiment. Fig. Figure 16 shows a view representing a multilayer substrate according to the fourth embodiment. Fig. Figure 17 shows a schematic view of the semiconductor module parallel circuit according to the fourth embodiment. Fig. Figure 18 shows a view depicting a semiconductor module parallel circuit in a fifth embodiment. Fig. Figure 19 shows a view representing a multilayer substrate according to the fifth embodiment. Fig. Figure 20 shows a schematic view of the semiconductor module parallel circuit according to the fifth embodiment. Fig. Figure 21 shows a view representing a gate driver current in the semiconductor module parallel circuit according to the fifth embodiment. Description of embodiments: First embodiment

[0011] Fig. Figure 1 shows a view representing a semiconductor module parallel circuit 1 according to a first embodiment. The semiconductor module parallel circuit 1 comprises a semiconductor module 10-1, a semiconductor module 10-2, and a multilayer substrate 100. The multilayer substrate 100 is arranged directly above the semiconductor modules 10-1 and 10-2 and is physically fixed by a fastening element 50. The semiconductor modules 10-1 and 10-2 are electrically connected in parallel to each other by the multilayer substrate 100. In the following description, the semiconductor modules 10-1 and 10-2 are referred to as semiconductor modules 10, where it is not necessary to distinguish between them. Semiconductor module 10 is, for example, a power semiconductor module.

[0012] When used for a three-phase two-stage inverter circuit, the semiconductor module 10-1 and the semiconductor module 10-2, for example, define a U-phase leg of the three-phase two-stage inverter circuit.

[0013] Fig. Figure 2 shows a schematic diagram of the parallel semiconductor module circuit according to the first embodiment. Semiconductor module 10-1 and semiconductor module 10-2 are each surrounded by a dashed line.

[0014] The semiconductor module 10-1 has a semiconductor element 30-1 and a semiconductor element 40-1 connected in series, and a source terminal of the semiconductor element 30-1 and a drain terminal of the semiconductor element 40-1 are connected together.

[0015] The semiconductor module 10-2 has a semiconductor element 30-2 and a semiconductor element 40-2 connected in series, and a source terminal of the semiconductor element 30-2 and a drain terminal of the semiconductor element 40-2 are connected together.

[0016] A gate terminal 11-1 of semiconductor element 30-1 of semiconductor module 10-1, a gate terminal 11-2 of semiconductor element 30-2 of semiconductor module 10-2, and a first connection terminal 71-1 of an external connection terminal 61 of the multilayer substrate are electrically connected to each other. A sample-source terminal 13-1 of semiconductor element 30-1 of semiconductor module 10-1, a sample-source terminal 13-2 of semiconductor element 30-2 of semiconductor module 10-2, and a second connection terminal 72-1 of the external connection terminal 61 of the multilayer substrate are electrically connected to each other. The gate terminal 11-1 of the semiconductor element 30-1 of the semiconductor module 10-1 can be referred to as a first signal terminal 11-1 and the gate terminal 11-2 of the semiconductor element 30-2 of the semiconductor module 10-2 can be referred to as a first signal terminal 11-2.The sample-source terminal 13-1 of the semiconductor element 30-1 of the semiconductor module 10-1 can be designated as a second signal terminal 13-1, and the sample-source terminal 13-2 of the semiconductor element 30-2 of the semiconductor module 10-2 can be designated as a second signal terminal 13-2. The first signal terminal 11-1 of the semiconductor element 30-1 of the semiconductor module 10-1 and the first signal terminal 11-2 of the semiconductor element 30-2 of the semiconductor module 10-2 each have a gate potential. The second signal terminal 13-1 of the semiconductor element 30-1 of the semiconductor module 10-1 and the second signal terminal 13-2 of the semiconductor element 30-2 of the semiconductor module 10-2 each have a source potential.

[0017] A gate terminal 12-1 of semiconductor element 40-1 of semiconductor module 10-1, a gate terminal 12-2 of semiconductor element 40-2 of semiconductor module 10-2, and a first connection terminal 71-2 of an external connection terminal 62 of the multilayer substrate are electrically connected to each other. A sample-source terminal 14-1 of semiconductor element 40-1 of semiconductor module 10-1, a sample-source terminal 14-2 of semiconductor element 40-2 of semiconductor module 10-2, and a second connection terminal 72-2 of the external connection terminal 62 of the multilayer substrate are electrically connected to each other. The gate terminal 12-1 of the semiconductor element 40-1 of the semiconductor module 10-1 can be referred to as a third signal terminal 12-1, and the gate terminal 12-2 of the semiconductor element 40-2 of the semiconductor module 10-2 can be referred to as a third signal terminal 12-2.The sample-source terminal 14-1 of the semiconductor element 40-1 of the semiconductor module 10-1 can be designated as a fourth signal terminal 14-1, and the sample-source terminal 14-2 of the semiconductor element 40-2 of the semiconductor module 10-2 can be designated as a fourth signal terminal 14-2. The third signal terminal 12-1 of the semiconductor element 40-1 of the semiconductor module 10-1 and the third signal terminal 12-2 of the semiconductor element 40-2 of the semiconductor module 10-2 each have a gate potential. The fourth signal terminal 14-1 of the semiconductor element 40-1 of the semiconductor module 10-1 and the fourth signal terminal 14-2 of the semiconductor element 40-2 of the semiconductor module 10-2 each have a source potential.

[0018] A drain terminal of semiconductor element 30-1 of semiconductor module 10-1 and a drain terminal of semiconductor element 30-2 of semiconductor module 10-2 are connected to each other and to a DC bus on a high potential side (not shown).

[0019] A source terminal of semiconductor element 40-1 of semiconductor module 10-1 and a source terminal of semiconductor element 40-2 of semiconductor module 10-2 are connected to each other and to a DC bus on a low potential side (not shown).

[0020] Fig. Figure 3 shows a top view of an assembly 20 that houses a semiconductor module 10 according to the first embodiment. Although not in Fig. As shown in Figure 3, assembly 20 has semiconductor element 30-1 and semiconductor element 40-1 connected in series. As shown in Fig. As shown in Figure 3, main terminals 10P, 10N, and 10AC are provided on one surface side of the assembly 20. Two 10P main terminals provided on a longitudinal one-end section of the assembly 20 are arranged orthogonally to the longitudinal direction. Two 10N main terminals provided closer to a central section of the assembly 20 than the 10P main terminals are arranged orthogonally to the longitudinal direction of the assembly 20. The number of each 10P main terminal and 10N main terminal is not limited to two. There can be one, three, or more of each. Three 10AC main terminals provided on the longitudinal other-end section of the assembly 20 are arranged orthogonally to the longitudinal direction. The number of main 10AC connections is not limited to three.The number of main 10AC connections can be one or two, or four or more.

[0021] The main terminals 10P each define a DC positive terminal P in the semiconductor module 10, the main terminals 10N each define a DC negative terminal N in the semiconductor module 10, and the main terminals 10AC each define an AC terminal AC in the semiconductor module 10.

[0022] A first signal terminal 11, a second signal terminal 13, a third signal terminal 12, and a fourth signal terminal 14 are provided between the main terminals 10N and the main terminals 10AC. In other words, the first signal terminal 11, the second signal terminal 13, the third signal terminal 12, and the fourth signal terminal 14 are provided between the DC and AC terminals. The second signal terminal 13 and the first signal terminal 11 extend from one side of the main terminal 10AC along one side in the longitudinal direction of the assembly 20. Additionally, the third signal terminal 12 and the fourth signal terminal 14 extend from the side of the main terminal 10AC along the other side in the longitudinal direction of the assembly 20.

[0023] The first signal terminal 11, the second signal terminal 13, the third signal terminal 12 and the fourth signal terminal 14 are connected to the multilayer substrate 100.

[0024] Fig. Figure 4 shows a schematic diagram of the semiconductor module 10 according to the first embodiment. The semiconductor module 10 has a semiconductor element 30 connected to the main terminal 10P and a semiconductor element 40 connected to the main terminal 10N. The semiconductor element 30 and the semiconductor element 40 are connected in series, and an electrical connection point between them is connected to the main terminal 10AC.

[0025] The semiconductor element 30 has a drain terminal D1 connected to the main terminal 10P, a source terminal S1 connected to the main terminal 10AC, the first signal terminal 11, and the second signal terminal 13. The drain terminal has a drain potential, the source terminal has a source potential, and the first signal terminal 11 has a gate potential.

[0026] The semiconductor element 40 has a drain terminal D2 connected to the main terminal 10AC, a source terminal S2 connected to the main terminal 10N, a third signal terminal 12, and a fourth signal terminal 14. The drain terminal has a drain potential, the source terminal has a source potential, and the third signal terminal 12 has a gate potential.

[0027] In each of the semiconductor elements 30 and 40, a transistor element and a diode element are connected in parallel. Depending on the characteristics of a load, for example, in the case of a resistive load, the connection of each diode element may be omitted.

[0028] In the first embodiment, a MOSFET is represented as the transistor element, but the transistor element is not limited to the MOSFET, and any other device that is switchable between a low-resistance state and a high-resistance state according to an electrical signal can be used. For example, a transistor element such as an IGBT or a bipolar transistor can be used. In a case where the transistor element is an IGBT, the "drain terminal" is to be replaced with a "collector terminal," the "source terminal" is to be replaced with an "emitter terminal," and the "sampling source terminal" is to be replaced with a "sampling emitter terminal." Silicon (Si), silicon carbide (SiC), gallium nitride (GaN), and similar materials can be used as the materials for the transistor and diode elements that define semiconductor elements 30 and 40.

[0029] Fig. Figure 5 shows a top view of the multilayer substrate 100, which is used for the semiconductor module parallel connection 1 according to the first embodiment. Fig. In section 5, the multilayer substrate 100 has a plurality of layers. Fig. Figure 5 shows a first layer, which is a visible layer and is referred to as a front surface. A layer that is visible and located on one side opposite the front surface is called a back surface. The first and second layers can be invisible layers.

[0030] The external connection terminals 61 and 62 are attached to the front surface of the multilayer substrate 100. The external connection terminals 61 and 62 are connected to an external connection circuit (not shown). The external connection terminals 61 and 62 are located on the front surface in Fig. 5 are attached, but can be attached to the rear surface. The external connection ports 61 and 62 can be integrated together.

[0031] First signal connection patterns 111-1 and 111-2, second signal connection patterns 113-1 and 113-2, third signal connection patterns 112-1 and 112-2, and fourth signal connection patterns 114-1 and 114-2 are shown as examples. Third signal connection patterns 112-1 and 112-2 and fourth signal connection patterns 114-1 and 114-2 are not shown.

[0032] The first signal connection patterns 111-1 and 111-2, the second signal connection patterns 113-1 and 113-2, the third signal connection patterns 112-1 and 112-2 and the fourth signal connection patterns 114-1 and 114-2 are each electrically connected to a back surface pattern through a through hole.

[0033] The first signal connection pattern 111-1, the second signal connection pattern 113-1, the third signal connection pattern 112-1 and the fourth signal connection pattern 114-1 are patterns for connection to the first signal connection 11-1, the second signal connection 13-1, the third signal connection 12-1 and the fourth signal connection 14-1 respectively of the semiconductor module 10-1.

[0034] The first signal connection pattern 111-2, the second signal connection pattern 113-2, the third signal connection pattern 112-2 and the fourth signal connection pattern 114-2 are patterns for connecting the first signal connection 11-2, the second signal connection 13-2, the third signal connection 12-2 and the fourth signal connection 14-2 respectively of the semiconductor module 10-2.

[0035] Next, a description is given of the parallel connection of the semiconductor module 10-1 and the semiconductor module 10-2 by the multilayer substrate 100 of the semiconductor module parallel circuit 1 according to the first embodiment.

[0036] Fig. Figure 6 shows a view illustrating an example in which the first signal connection patterns 111-1 and 111-2 are interconnected in the multilayer substrate 100. Fig. 6 is a direction extending from the external connection terminal 61 of the multilayer substrate 100 to each semiconductor module, defined as an X-direction; a direction extending from the back face to the front face of the multilayer substrate is defined as a Z-direction (not shown); and a direction orthogonal to the X-direction and the Z-direction is defined as a Y-direction. Fig. In Figure 6, the first signal connection patterns 111-1 and 111-2 and the external connection pin 61 are connected or wired. The first signal connection patterns 111-1 and 111-2 share a common line from the external connection pin 61 to a point S. The line branches off from point S to connect the first signal connection pattern 111-1 and the first signal connection pattern 111-2. This means that point S is a branch point. For two semiconductor modules, point S can be the midpoint of the line between the first signal connection patterns 111-1 and 111-2. With the line laid out as described above, the line length from the external connection pin 61 to the first signal connection pattern 111-1 and the line length from the external connection pin 61 to the first signal connection pattern 111-2 can be equal. In Fig. 6. The connection from the external connection terminal 61 to the first signal connection patterns is formed in the same layer of the multilayer substrate 100, but it does not have to be in the same layer. Different layers of the multilayer substrate 100 can be used. For example, the wiring or connection from the external connection terminal 61 to point S and the wiring between 111-1 and 111-2 can be in different layers.

[0037] Descriptions and illustrations of the third signal connection patterns 112-1 and 112-2 are similar to those of the first signal connection patterns 111-1 and 111-2 and are therefore omitted.

[0038] Fig. Figure 7 shows a view that presents an example in which the second signal connection patterns 113-1 and 113-2 are connected to each other in the multilayer substrate 100. Fig. 7 is a direction extending from the external connection terminal 61 of the multilayer substrate 100 to each semiconductor module, defined as an X-direction; a direction extending from the back face to the front face of the multilayer substrate is defined as a Z-direction (not shown); and a direction orthogonal to the X-direction and the Z-direction is defined as a Y-direction. Fig. In Figure 7, the second signal connection patterns 113-1 and 113-2 and the external connection pin 61 are connected or wired. The second signal connection patterns 113-1 and 113-2 share a common line from the external connection pin 61 to a point T. The line branches off from point T into a connection with the second signal connection pattern 113-1 and the second signal connection pattern 113-2. This means that point T is a branch point. For two semiconductor modules, point T is a midpoint of the line between the second signal connection patterns 113-1 and 113-2. With the lines laid out as described above, the line length from the external connection pin 61 to the second signal connection pattern 113-1 and the line length from the external connection pin 61 to the second signal connection pattern 113-2 can be equal. Fig. 7. The connection from the external connection port 61 to the second signal connection pattern is formed in the same layer of the multilayer substrate 100, but it does not have to be in the same layer. Different layers of the multilayer substrate 100 can be used. For example, the connections from the external connection port 61 to point T and the connection between 113-1 and 113-2 can be in different layers.

[0039] Descriptions and illustrations of the fourth signal connection patterns 114-1 and 114-2 are similar to those of the second signal connection patterns 113-1 and 113-2 and are therefore omitted.

[0040] The wiring or connection, which is in the combination of the lines from the external connection terminal 61 to the first signal terminal of the semiconductor module 10-1 and lines from the second signal terminal of the semiconductor module 10-1 to the external connection terminal 61, is referred to as gate connection or gate line.

[0041] The gate interconnection for the semiconductor element 30-1 of the semiconductor module 10-1 is a combination of the lines from the external connection terminal 61 to the first signal connection pattern 111-1 and lines from the second signal connection pattern 113-1 to the external connection terminal 61.

[0042] Similarly, those connections that are a combination of the lines from the external connection terminal 61 to the first signal terminal of the semiconductor module 10-2 and lines from the second signal terminal of the semiconductor module 10-2 to the external connection terminal 61 are referred to as a gate connection. The gate connection for the semiconductor element 30-2 of the semiconductor module 10-2 is a combination of the lines from the external connection terminal 61 to the first signal connection pattern 111-2 and lines from the second signal connection pattern 113-2 to the external connection terminal 61.

[0043] With the external connection, the first signal connection patterns, and the second signal connection patterns, as described above, the length of the gate connection or gate trace for semiconductor element 30-1 of semiconductor module 10-1 and the length of the gate connection or gate trace for semiconductor element 30-2 of semiconductor module 10-2 can be the same. Since the length of the gate connection or gate trace for semiconductor element 30-1 of semiconductor module 10-1 and the length of the gate connection or gate trace for semiconductor element 30-2 of semiconductor module 10-2 can be equal, it is possible to reduce any current imbalance between semiconductor element 30-1 and semiconductor element 30-2.

[0044] The gate inductance of semiconductor element 30-1 of semiconductor module 10-1 and the gate inductance of semiconductor element 30-2 of semiconductor module 10-2 can be equal. Because the gate inductance of semiconductor element 30-1 of semiconductor module 10-1 and the gate inductance of semiconductor element 30-2 of semiconductor module 10-2 can be equal, it is possible to reduce any current imbalance between semiconductor element 30-1 and semiconductor element 30-2.

[0045] Although not explicitly described, the gate line or gate circuit for semiconductor element 40-1 of semiconductor module 10-1 and the gate line or gate circuit for semiconductor element 40-2 of semiconductor module 10-2 are designed in the same way as described above, such that the gate inductance of the gate circuit for semiconductor element 40-1 of semiconductor module 10-1 and the gate inductance of semiconductor element 40-2 of semiconductor module 10-2 can be equal. As a result, it is possible to reduce any current imbalance between semiconductor element 40-1 and semiconductor element 40-2.

[0046] Inductances of a line, which are a source of voltage drops, provide equal amounts of voltage drops caused by the individual line inductances if the inductances of the line are equal to each other, so that current flows through the line can be equal to each other.

[0047] In the first embodiment, the lengths of the conductors are considered equal to each other if any imbalance in the current between the semiconductor modules is such that it has essentially no effect. Similarly, the inductances of conductors are considered equal to each other if any imbalance in the current between the semiconductor modules is such that it has essentially no effect.

[0048] The gate line, which is formed in the multilayer substrate 100 as described above to reduce an imbalance in the current between the semiconductor modules, can be achieved in a smaller number of layers.

[0049] It is preferred that the gate lines in the multilayer substrate 100 have essentially the same widths for the conductor patterns or circuit patterns as described above. In the multilayer substrate 100 according to the first embodiment, the distance in the Z-direction between the external connection terminal and the first signal connection patterns is preferably short, and the distance in the Z-direction between the external connection terminal and the second signal connection patterns is preferably short. This means that the external connection and the first signal connection patterns, and the external connection and the second signal connection patterns, preferably have traces designed such that the trace patterns overlap when the multilayer substrate 100 is viewed in the positive direction of the Z-direction. With the traces or interconnections laid out as described above, it is possible to achieve a configuration that is less susceptible to noise. The preceding description is given as one in which two semiconductor modules are arranged in parallel, but a similar configuration can be applied when three or more semiconductor modules are arranged in parallel.In the preceding description, the lead lengths from the branch point (point S) to the first signal connection patterns of the two semiconductor modules are equal, and the lead lengths from the branch point (point T) to the second signal connection patterns of the two semiconductor modules are equal. Similarly, in the case of three semiconductor modules, the lead lengths from the branch point to the first signal connection patterns of the three semiconductor modules are equal, and the lead lengths from the branch point to the second signal connection patterns of the three semiconductor modules are equal. As a result, the individual gate lead lengths for the three semiconductor modules can be identical. Because the individual gate lead lengths for the three semiconductor modules are equal, it is possible to reduce any current imbalance among the three semiconductor modules.The preceding description is an example where the branch points are used for routing from the external interconnect to the first signal connection patterns of the semiconductor modules and from the external interconnect to the second signal connection patterns of the semiconductor modules, but this is not a limitation. The routing from the external interconnect to the first signal connection patterns of the semiconductor modules and from the external interconnect to the second signal connection patterns of the semiconductor modules can be configured without using the branch points. Even in this case, the individual gate trace lengths are equal to each other, which makes it possible to reduce any current imbalance among the three semiconductor elements.

[0050] The semiconductor module parallel circuit according to the first embodiment comprises: a first power semiconductor module; a second power semiconductor module; and a multilayer substrate connecting a plurality of the power semiconductor modules, each of the power semiconductor modules comprising: a power semiconductor switching element; a first signal terminal connected to a gate potential of the power semiconductor switching element; and a second signal terminal connected to a source potential of the power semiconductor switching element, the multilayer substrate comprising: an external connection terminal; a first signal terminal connection pattern for the first power semiconductor module, wherein the first signal terminal connection pattern for the first power semiconductor module is connected to the first signal terminal of the first power semiconductor module; a second signal terminal connection pattern for the first power semiconductor module.wherein the second signal connection pattern for the first power semiconductor module is connected to the second signal terminal of the first power semiconductor module; a first signal connection pattern for the second power semiconductor module, wherein the first signal connection pattern for the second power semiconductor module is connected to the first signal terminal of the second power semiconductor module; and a second signal connection pattern for the second power semiconductor module, wherein the second signal connection pattern for the second power semiconductor module is connected to the second signal terminal of the second power semiconductor module,and an inductance of a gate line for the first power semiconductor module from the external connection terminal to the first signal connection pattern for the first power semiconductor module and from the second signal connection pattern for the first power semiconductor module to the external connection terminal, and an inductance of a gate line for the second power semiconductor module from the external connection terminal to the first signal connection pattern for the second power semiconductor module and from the second signal connection pattern for the second power semiconductor module to the external connection terminal are equal to each other, making it possible to reduce an imbalance in the current between the semiconductor modules.

[0051] The semiconductor module parallel circuit according to the first embodiment comprises: a first power semiconductor module; a second power semiconductor module; and a multilayer substrate connecting a plurality of the power semiconductor modules, each of the power semiconductor modules comprising: a power semiconductor switching element; a first signal terminal connected to a gate potential of the power semiconductor switching element; and a second signal terminal connected to a source potential of the power semiconductor switching element, the multilayer substrate comprising: an external connection terminal; a first signal terminal connection pattern for the first power semiconductor module, wherein the first signal terminal connection pattern for the first power semiconductor module is connected to the first signal terminal of the first power semiconductor module; a second signal terminal connection pattern for the first power semiconductor module.wherein the second signal connection pattern for the first power semiconductor module is connected to the second signal terminal of the first power semiconductor module; a first signal connection pattern for the second power semiconductor module, wherein the first signal connection pattern for the second power semiconductor module is connected to the first signal terminal of the second power semiconductor module; and a second signal connection pattern for the second power semiconductor module, wherein the second signal connection pattern for the second power semiconductor module is connected to the second signal terminal of the second power semiconductor module,and the length of a gate line for the first power semiconductor module from the external connection terminal to the first signal connection pattern for the first power semiconductor module and from the second signal connection pattern for the first power semiconductor module to the external connection terminal, and the length of the gate line for the second power semiconductor module from the external connection terminal to the first signal connection pattern for the second power semiconductor module and from the second signal connection pattern for the second power semiconductor module to the external connection terminal are equal to each other, making it possible to reduce an imbalance in the current between the semiconductor modules and to decrease the reduction in the lifetime of the semiconductor modules.

[0052] In the semiconductor module parallel circuit according to the first embodiment, the gate lead length for the first power semiconductor module from the external connection terminal to the first signal connection pattern for the first power semiconductor module and from the second signal connection pattern for the first power semiconductor module to the external connection terminal, and the gate lead length for the second power semiconductor module from the external connection terminal to the first signal connection pattern for the second power semiconductor module and from the second signal connection pattern for the second power semiconductor module to the external connection terminal are equal to each other, making it possible to reduce the imbalance in the current between the semiconductor modules.

[0053] In the semiconductor module parallel circuit according to the first embodiment, the lines from the external connection terminal to the first signal connection pattern for the first power semiconductor module and the lines from the external connection terminal to the first signal connection pattern for the second power semiconductor module are formed in a first layer of the multilayer substrate, and the lines from the second signal connection pattern for the first power semiconductor module to the external connection terminal and the lines from the second signal connection pattern for the second power semiconductor module to the external connection terminal are formed in a second layer of the multilayer substrate, making it possible to reduce an imbalance in the current between the semiconductor modules.

[0054] The semiconductor module interconnect substrate according to the first embodiment comprises: an external interconnect port; a first signal connection pattern for a first power semiconductor module, wherein the first signal connection pattern for the first power semiconductor module is provided for connection to a first signal port of the first power semiconductor module; a second signal connection pattern for the first power semiconductor module, wherein the second signal connection pattern for the first power semiconductor module is provided for connection to a second signal port of the first power semiconductor module; a first signal connection pattern for a second power semiconductor module,wherein the first signal connection pattern for the second power semiconductor module is provided for connection to a first signal terminal of the second power semiconductor module; and a second signal connection pattern for the second power semiconductor module, wherein the second signal connection pattern for the second power semiconductor module is provided for connection to a second signal terminal of the second power semiconductor module, and an inductance of a gate line for the first power semiconductor module from the external connection terminal to the first signal connection pattern for the first power semiconductor module and from the second signal connection pattern for the first power semiconductor module to the external connection terminal,and the inductance of a gate line for the second power semiconductor module from the external connection terminal to the first signal connection pattern for the second power semiconductor module and from the second signal connection pattern for the second power semiconductor module to the external connection terminal are equal to each other, making it possible to reduce an imbalance in the current between the semiconductor modules. Second embodiment

[0055] A parallel connection of the semiconductor module 10-1 and the semiconductor module 10-2 through a multilayer substrate 200 of a semiconductor module parallel circuit 2 in a second embodiment is described.

[0056] Fig. Figure 8 shows a view representing a configuration of the semiconductor module parallel circuit 2, in which two semiconductor modules are arranged in parallel to each other. Fig. Figure 9 shows a view representing the multilayer substrate 200 of the semiconductor module parallel circuit 2 in the second embodiment. Fig. Figure 10 shows a schematic view of a cross-section of the multilayer substrate 200. Fig. 9 along a line A-A'. In Fig. A direction extending from the external connection terminal 61 of the multilayer substrate 200 to each semiconductor module is defined as an X-direction; a direction extending from a back face to a front face of the multilayer substrate is defined as a Z-direction; and a direction orthogonal to the X-direction and the Z-direction is defined as a Y-direction (not shown). The multilayer substrate 200 is formed with three layers: a first layer 201; a second layer 202; and a third layer 203. In the X-direction, the coordinate position of the external connection terminal 61 is set to 0. In the Z-direction, the coordinate position of the third layer 203 of the multilayer substrate 200 in contact with the semiconductor modules 10-1 and 10-2 is set to 0. The first layer is defined as a front face, and the third layer is defined as a back face.The first and third layers can be invisible. Semiconductor module 10-1 and semiconductor module 10-2 are arranged parallel to each other in the X-direction, and semiconductor module 10-1 and semiconductor module 10-2 are arranged in this order, one side closer to the external connection terminal 61.

[0057] In Fig. In Figure 10, a solid line indicates a connection from the external connection terminal 61 to the first signal connection pattern, and a dashed line indicates a connection from the second signal connection pattern to the external connection terminal 61. The first signal connection patterns 111-1 and 111-2 and the second signal connection patterns 113-1 and 113-2 are formed in the third layer 203 of the multilayer substrate 200 for the purpose of connecting the individual signal terminals for the individual semiconductor modules.

[0058] The conductor formed in the first layer 201 of the multilayer substrate 200 is called the gate return, the conductor in the second layer 202 is called the gate forward, and the conductor formed in the third layer 203 is called the output. The gate forward is connected to the external connection terminal 61. The gate forward is connected to the gate return. The gate return is connected to the first signal connection patterns 111-1 and 111-2. The conductor from the gate return to the first signal connection pattern 111-1 is not connected to the gate forward. Similarly, the gate return from the first signal connection pattern 111-2 is not connected to the gate forward.A position in the X-direction where the gate return and the first signal connection pattern 111-2 are connected is closer to the external connection terminal 61 with respect to the X-direction than a position in the X-direction where the gate forward and gate return are connected. In other words, the gate forward formed in the second layer 202 is connected to the gate return formed in the first layer 201, and the gate return is connected to the first signal connection pattern 111-2 at the position offset in the opposite direction to the X-direction from the position where the gate forward formed in the second layer 202 is connected to the gate return formed in the first layer 201.

[0059] The position in the X direction where the gate return and the first signal connection pattern 111-2 are connected is called the branch point Q.

[0060] The second signal connection patterns 113-1 and 113-2 are connected to the output line. A position in the X-direction where the second signal connection pattern 113-1 is connected to the output line is closer to the external connection terminal 61 with respect to the X-direction than a position in the X-direction where the second signal connection pattern 113-2 is connected to the output line. The output line is connected to the external connection terminal 61.

[0061] The position in the X direction where the second signal connection pattern 113-1 is connected to the output line is referred to as a connection point P.

[0062] If a trace length from the external connection terminal 61 to the first signal connection pattern 111-1 is designated by Lenlg, and a trace length from the second signal connection pattern 113-1 to the external connection terminal 61 is designated by Lenls, then a trace length Len1 of the gate trace of the semiconductor module 10-1 is Lenlg+Lenls. Similarly, if a trace length from the external connection terminal 61 to the first signal connection pattern 111-2 is designated by Len2g, and a trace length from the second signal connection pattern 113-2 to the external connection terminal 61 is designated by Len2s, then a trace length Len2 of the gate trace of the semiconductor module 10-2 is Len2g+Len2s.In the second embodiment, the gate line is designed such that the gate line length (line length Len1) for the first power semiconductor module from the external connection terminal 61 to the first signal connection pattern for the first power semiconductor module and from the second signal connection pattern for the first power semiconductor module to the external connection terminal, and the gate line length (line length Len2) for the second power semiconductor module from the external connection terminal to the first signal connection pattern for the second power semiconductor module and from the second signal connection pattern for the second power semiconductor module to the external connection terminal are equal to each other (Len1=Len2).This means that the gate line is designed such that the line inductance generated in the gate line for semiconductor module 10-1 and the line inductance generated in the gate line for semiconductor module 10-2 are equal to each other.

[0063] Note that, for example, the first power semiconductor module is semiconductor module 10-1 and the second power semiconductor module is semiconductor module 10-2.

[0064] In Fig. 10. Len1g is the length of a line from the external connection port 61 to the first signal connection pattern 111-1. Lenls is the length of a combination of a line from the second signal connection pattern 113-1 to connection point P and a line from connection point P to the external connection port 61. Len2g is the length of a combination of a line from the external connection port 61 to branch point Q and a line from branch point Q to the first signal connection pattern 111-2. Len2s is the length of a line from the second signal connection pattern 113-2 to the external connection port 61.

[0065] In the second embodiment, the conductor is configured as described above, such that the conductor length of the gate conductor for semiconductor module 10-1 and the conductor length of the gate conductor for semiconductor module 10-2 can be equal to each other. This means that the gate conductor is configured such that Len1 = Len2 is true. The conductor inductance generated in the gate conductor for semiconductor module 10-1 and the conductor inductance generated in the gate conductor for semiconductor module 10-2 can be equal to each other.

[0066] Next, a gate driver current in the semiconductor module parallel circuit 2 is described. A current input from the external connection terminal 61 flows through the gate forward path formed in the second layer 202 of the multilayer substrate 200, and then through the gate return path formed in the first layer 201 of the multilayer substrate 200. The current then branches at the gate return branch point Q to provide current flows into the first signal connection pattern 111-1 and the first signal connection pattern 111-2.

[0067] One of the branched gate driver currents flows to the first signal terminal 11-1 of the semiconductor module 10-1 via the first signal terminal connection pattern 111-1, and similarly the other flows to the first signal terminal 11-2 of the semiconductor module 10-2 via the first signal terminal connection pattern 111-2.

[0068] Next, a current output from the second signal terminal 13-1 of the semiconductor module 10-1 flows into the output line of the multilayer substrate 200 via the second signal terminal connection pattern 113-1. Similarly, a current output from the second signal terminal 13-2 of the semiconductor module 10-2 flows into the output line of the multilayer substrate 200 via the second signal terminal connection pattern 113-2. The current output from the second signal terminal connection pattern 113-2 joins the current output from the second signal terminal connection pattern 113-1 at the junction point P on the output line. The combined current is output from the external connection terminal 61.

[0069] Fig. Figure 11 shows a view representing a gate driver current flowing through each layer of the multilayer substrate 200. When a current flows through the gate lead through Ig 12where a current flowing from the branch point Q to the first signal connection pattern 111-1 is designated by I1g and a current flowing from the branch point Q to the first signal connection pattern 111-2 is designated by I2g, the following equation (1) applies. Ig12=I1g+I2g

[0070] Current inputs to the first signal terminals of the semiconductor modules 10-1 and 10-2 can be approximated as in equation (2) below. I1g=I2g=Ig

[0071] Formula (3) below is derived from formulas (1) and (2). Ig12=2Ig

[0072] From formulas (2) and (3), the currents I1g and I2g, which are branched off at the branch point Q and of which 1 / 2 of the current Ig flows through the gate return path, are each 1 / 2 of the current Ig. 12 , which flows through the gate lead. In other words, the current Ig 12, which flows through the gate feeder, a current (2Ig) which is twice the current Ig (I1g, I2g) that branches off at the branch point Q and flows away from it.

[0073] Next, if a current flowing through the output line passes through Is 12 If a current flowing from the second signal connection pattern 113-2 is designated by I2s, and a current flowing from the second signal connection pattern 113-1 is designated by I1s, then the following formula (4) applies. I1s+I2s=Is12

[0074] Current outputs from the second signal terminals of semiconductor modules 10-1 and 10-2 are approximated as in formula (5). I1s=I2s=Is

[0075] Formula (6) below is derived from formulas (4) and (5). Is12=2Is

[0076] From formulas (5) and (6), the currents I1s and I2s flowing through the output line before joining at the connection point P are each 1 / 2 of the current Is 12 , which flows through the output line. In other words, the current Is 12 , which flows through the output line, a current (2Is) which is twice the current Is (I1s, I2s) flowing at the junction point P before joining.

[0077] The current (Ig) flowing from the branch point Q to the first signal terminal of the semiconductor module 10-1 and the current (Is) flowing from the second signal terminal to the semiconductor module 10-2 at the connection point P, can be equal to each other. This means that the voltage drop in the line extending from the branch point Q to the first signal terminal of semiconductor module 10-1 and the voltage drop in the line extending from the second signal terminal to semiconductor module 10-2 at connection point P can be equal to each other.

[0078] In the second embodiment, a current which is the sum of the gate currents flowing through the first signal terminals of the semiconductor modules 10-1 and 10-2 flows through the gate feeder formed in the multilayer substrate 200, such that the line inductances of the gate circuit for the semiconductor module 10-1 and the gate feeder for the semiconductor module 10-2 can be equal to each other.

[0079] Since the gate line inductance for semiconductor module 10-1 and the gate line inductance for semiconductor module 10-2 can be the same, it is possible to reduce any imbalance in the current generated between the semiconductor modules when the semiconductor modules are operated in parallel.

[0080] It is preferred to adapt the conductor pattern to have essentially the same width when forming the gate conductor in the multilayer substrate 200.

[0081] In the second embodiment, the line to the first signal terminals of the semiconductor modules in the two layers of the multilayer substrate 200 is designed such that the gate line lengths for the semiconductor modules can be the same as each other.

[0082] In the second embodiment, the lengths of the conductors are considered equal to each other if any imbalance in the current between the semiconductor modules is of such a magnitude that it has essentially no effect. Similarly, the inductances of the conductors are considered equal to each other if any imbalance in the current between the semiconductor modules is of such a magnitude that it has essentially no effect.

[0083] Although not explicitly described, the gate leads for semiconductor element 40-1 of semiconductor module 10-1 and the gate lead for semiconductor element 40-2 of semiconductor module 10-2 are arranged in the same manner as discussed above, such that the gate lead inductance for semiconductor element 40-1 of semiconductor module 10-1 and the gate lead inductance for semiconductor element 40-2 of semiconductor module 10-2 can be equal. As a result, it is possible to reduce any current imbalance between semiconductor element 40-1 and semiconductor element 40-2.

[0084] In the second embodiment, the gate return path is formed in the first layer 201 of the multilayer substrate 200, and the output path is formed in the third layer 203 of the multilayer substrate 200. Alternatively, the output path can be formed in the first layer 201 of the multilayer substrate 200, and the gate return path can be formed in the third layer 203 of the multilayer substrate 200.

[0085] In the semiconductor module parallel circuit according to the second embodiment, the line from the external connection terminal to the first signal connection pattern for the first power semiconductor module and the line from the external connection terminal to the first signal connection pattern of the second power semiconductor module are formed in the first layer 201 and the third layer 203 of the multilayer substrate, making it possible to reduce an imbalance in the current between the semiconductor modules. Third embodiment

[0086] The first and second embodiments described above provide an example in which two semiconductor modules are arranged parallel to each other. A third embodiment, described below, provides an example in which three semiconductor modules are arranged parallel to each other. Fig. Figure 12 shows a view representing a configuration of a semiconductor module parallel circuit 3 in which three semiconductor modules are arranged in parallel. Semiconductor modules 10-1 and 10-2 and a semiconductor module 10-3 are arranged in parallel. The third embodiment differs from the first and second embodiments in that the semiconductor module 10-3 is added. The semiconductor modules 10-1, 10-2, and 10-3 are connected to a multilayer substrate 300 and operated in parallel.

[0087] Fig. Figure 13 shows a view depicting the multilayer substrate 300 of the semiconductor module parallel circuit 3 in the third embodiment. Fig. 13 The multilayer substrate 300 differs from the multilayer substrates in the first and second embodiments in that a first signal connection pattern 111-3, a second signal connection pattern 113-3, a third signal connection pattern 112-3 and a fourth signal connection pattern 114-3, which are connected to the semiconductor module 10-3, are formed.

[0088] The first signal connection pattern 111-3, the second signal connection pattern 113-3, the third signal connection pattern 112-3 and the fourth signal connection pattern 114-3 are patterns for connecting to the first signal terminal 11-1, the second signal terminal 13-1, the third signal terminal 12-1 and the fourth signal terminal 14-1 respectively of the semiconductor module 10-3.

[0089] Fig. Figure 14 shows a schematic view of a cross-section of the multilayer substrate 300. Fig. 13 along a line B-B'. In Fig. A direction extending from the external connection terminal 61 of the multilayer substrate 300 to each semiconductor module is defined as an X-direction, a direction extending from a back face to a front face of the multilayer substrate 300 is defined as a Z-direction, and a direction orthogonal to the X-direction and the Z-direction is defined as a Y-direction (not shown). The multilayer substrate 300 is formed from three layers: a first layer 301; a second layer 302; and a third layer 303. The interlayer distances between the first layer 301 and the second layer 302 and between the second layer 302 and the third layer 303 are configured to be equal. In the X-direction, the coordinate position of the external connection terminal 61 is set to 0.In the Z-direction, the coordinate position of the third layer 303 of the multilayer substrate 300 is set to 0. The first layer is defined as a front surface and the third layer as a back surface. The first and third layers can be invisible. The semiconductor modules 10-1, 10-2, and 10-3 are arranged parallel to each other in the X-direction, and semiconductor module 10-1, semiconductor module 10-2, and semiconductor module 103 are arranged in that order, one side closer to the external connection terminal 61.

[0090] In Fig. In Figure 14, a solid line indicates a connection from the external connection terminal 61 to the first signal connection pattern, and a dashed line indicates a connection from the second signal connection pattern to the external connection terminal 61. The first signal connection patterns 111-1, 111-2, and 111-3 and the second signal connection patterns 113-1, 113-2, and 113-3 are formed in the third layer 303 of the multilayer substrate 300 for the purpose of connection to individual signal terminals for the individual semiconductor modules.

[0091] The connection or circuit formed in the first layer 301 of the multilayer substrate 300 is called the gate return, the connection or circuit formed in the second layer 302 is called the gate forward, and the connection or circuit formed in the third layer 303 is called the output. The gate forward is connected to the external connection terminal 61. The gate forward is connected to the gate return. The gate return is connected to the first signal connection patterns 111-1, 111-2, and 111-3. The connection from the gate return to the first signal connection pattern 111-1 is not connected to the gate forward. Similarly, the lines from the gate return to the first signal connection pattern 111-2 and the lines from the gate return to the first signal connection pattern 111-3 are not connected to the gate forward.A position in the X-direction where the gate return and the first signal connection pattern 111-3 are connected is closer to the external connection terminal 61 with respect to the X-direction than a position in the X-direction where the gate forward and gate return are connected. In other words, the gate forward formed in the second layer 302 is connected to the gate return formed in the first layer 301, and the gate return is connected to the first signal connection pattern 111-3 at the position offset in the opposite direction to the X-direction from the position where the gate forward formed in the second layer 302 is connected to the gate return formed in the first layer 301.A position in the X direction where the gate return and the first signal connection pattern 111-2 are connected is closer to the external connection terminal 61 with respect to the X direction than the position in the X direction where the gate return and the first signal connection pattern 111-3 are connected.

[0092] The position in the X-direction where the gate return and the first signal connection pattern 111-3 are connected is called branch point Q1. The position in the X-direction where the gate return and the first signal connection pattern 111-2 are connected is called branch point Q2.

[0093] The second signal connection patterns 113-1, 113-2, and 113-3 are connected to the output line. A position in the X-direction where the second signal connection pattern 113-2 is connected to the output line is closer to the external connection terminal 61 with respect to the X-direction than a position in the X-direction where the second signal connection pattern 113-3 is connected to the output line. Similarly, a position in the X-direction where the second signal connection pattern 113-1 is connected to the output line is closer to the external connection terminal 61 with respect to the X-direction than a position in the X-direction where the second signal connection pattern 113-2 is connected to the output line. The output line is connected to the external connection terminal 61.

[0094] The position in the X direction where the second signal connection pattern 113-2 is connected to the output line is referred to as a connection point P1, and the position in the X direction where the second signal connection pattern 113-1 is connected to the output line is referred to as a connection point P2.

[0095] If a trace length from the external connection terminal 61 to the first signal connection pattern 111-1 is designated by Lenlg and a trace length from the second signal connection pattern 113-1 to the external connection terminal 61 is designated by Lenls, then a trace length Len1 of a gate trace for the semiconductor module 10-1 is Lenlg+Lenls. Similarly, if a trace length from the external connection terminal 61 to the first signal connection pattern 111-2 is designated by Len2g and a trace length from the second signal connection pattern 113-2 to the external connection terminal 61 is designated by Len2s, then a trace length Len2 of a gate trace for the semiconductor module 10-2 is Len2g+Len2s.Similarly, if a line length from the external connection terminal 61 to the first signal connection pattern 111-3 is designated by Len3g and a line length from the second signal connection pattern 113-3 to the external connection terminal 61 is designated by Len3s, then a line length Len3 of a gate line for the semiconductor module 10-3 is Len3g+Len3s.

[0096] In the third embodiment, the gate line is configured such that the gate line length (line length Len1) for the first power semiconductor module extends from the external connection terminal 61 to the first signal connection pattern for the first power semiconductor module and from the second signal connection pattern for the first power semiconductor module to the external connection terminal 61, and the gate line length (line length Len2) for the second power semiconductor module extends from the external connection terminal 61 to the first signal connection pattern for the second power semiconductor module and from the second signal connection pattern for the second power semiconductor module to the external connection terminal 61.and the gate lead length (lead length Len3) for a third power semiconductor module from the external connection terminal 61 to the first signal connection pattern for the third power semiconductor module and from the second signal connection pattern for the third power semiconductor module to the external connection terminal 61 are equal to each other (Len1=Len2=Len3). This means that the gate lead is configured such that the lead inductances generated in the gate lead for semiconductor module 10-1 and in the gate lead for semiconductor module 10-2, and a lead inductance generated in the gate lead for semiconductor module 10-3, are equal to each other.

[0097] It is preferred to adapt the conduction patterns so that they have essentially the same widths when forming the gate conduction in the multilayer substrate 300.

[0098] In Fig. 14 Lenlg is a line length of a line from the external connection port 61 to the first signal connection pattern 111-1. Lenls is a line length of a combination of a line from the second signal connection pattern 113-1 to connection point P2 and a line from connection point P2 to external connection port 61. Len2g is a line length of a combination of a line from external connection port 61 to branch point Q2 and a line from branch point Q2 to the first signal connection pattern 111-2. Len2s is a line length of a combination of a line from the second signal connection pattern 113-2 to connection point P1 and a line from connection point P1 to external connection port 61.Len3g is the length of a combination of a line from the external connection port 61 to the branch point Q1 and a line from the branch point Q1 to the first signal connection pattern 111-3. Len3s is the length of a line from the second signal connection pattern 113-3 to the external connection port 61.

[0099] In the third embodiment, the conductor is configured as described above, such that the conductor lengths of the gate conductor for semiconductor module 10-1, the gate conductor lengths for semiconductor module 10-2, and the gate conductor lengths for semiconductor module 10-3 can be equal to each other. This means that the gate conductor is configured such that Len1 = Len2 = Len3. Since the gate conductor lengths of semiconductor modules 10-1, 10-2, and 10-3 can be equal to each other, it is possible to reduce any imbalance in the current generated between the semiconductor modules when they are operated in parallel.

[0100] In the third embodiment, the lead length of the gate circuit for semiconductor module 10-1, the lead length for the gate lead of semiconductor module 10-2, and the lead length for the gate lead of semiconductor module 10-3 are equal to each other, such that the amount of voltage drops due to the lead inductances can be equal to each other, thereby making it possible to counteract an imbalance in the current. to reduce the amount of radiation generated under the semiconductor modules when the semiconductor modules are operated in parallel.

[0101] In the third embodiment, the wiring of the first signal connections of the semiconductor modules in the two layers of the multilayer substrate 300 is designed such that the gate lead lengths of the semiconductor modules can be equal to each other.

[0102] In the third embodiment, the conductor lengths are considered equal if any current imbalance exists among the semiconductor modules to such an extent that it has essentially no effect. Similarly, the conductor inductances are considered equal if any current imbalance exists among the semiconductor modules to such an extent that it has essentially no effect.

[0103] In the third embodiment, the gate return path is formed in the first layer 301 of the multilayer substrate 300, and the output path is formed in the third layer 303 of the multilayer substrate 300. Alternatively, the output path can be formed in the first layer 301 of the multilayer substrate 300, and the gate return path can be formed in the third layer 303 of the multilayer substrate 300.

[0104] The semiconductor module parallel circuit according to the third embodiment comprises: a first power semiconductor module; a second power semiconductor module; a third power semiconductor module; and a multilayer substrate connecting a plurality of the power semiconductor modules together, each of the power semiconductor modules comprising: a power semiconductor switching element; a first signal terminal connected to a gate potential of the power semiconductor switching element; and a second signal terminal connected to a source potential of the power semiconductor switching element, the multilayer substrate comprising: an external connection terminal; a first signal terminal connection pattern for the first power semiconductor module,wherein the first signal connection pattern for the first power semiconductor module is connected to the first signal terminal of the first power semiconductor module; a second signal connection pattern for the first power semiconductor module, wherein the second signal connection pattern for the first power semiconductor module is connected to the second signal terminal of the first power semiconductor module; a first signal connection pattern for the second power semiconductor module, wherein the first signal connection pattern for the second power semiconductor module is connected to the first signal terminal of the second power semiconductor module; a second signal connection pattern for the second power semiconductor module,wherein the second signal connection pattern for the second power semiconductor module is connected to the second signal terminal of the second power semiconductor module; a first signal connection pattern for the third power semiconductor module, wherein the first signal connection pattern for the third power semiconductor module is connected to the first signal terminal of the third power semiconductor module; and a second signal connection pattern for the third power semiconductor module, wherein the second signal connection pattern for the third power semiconductor module is connected to the second signal terminal of the third power semiconductor module,and an inductance of a gate line for the first power semiconductor module from the external connection terminal to the first signal connection pattern for the first power semiconductor module and from the second signal connection pattern for the first power semiconductor module to the external connection terminal, an inductance of a gate line for the second power semiconductor module from the external connection terminal to the first signal connection pattern for the second power semiconductor module and from the second signal connection pattern for the second power semiconductor module to the external connection terminal,and the inductance of a gate line for the third power semiconductor module from the external connection terminal to the first signal connection pattern for the third power semiconductor module and from the second signal connection pattern for the third power semiconductor module to the external connection terminal are equal to each other, making it possible to reduce an imbalance in current among the semiconductor modules. Fourth embodiment

[0105] A fourth embodiment, as described below, provides an example in which the interlayer distances of a multilayer substrate are equal to each other. A description is given for an example in which two semiconductor modules are arranged in parallel. Fig. Figure 15 shows a view representing a semiconductor module parallel circuit 4 of the fourth embodiment. Fig. Figure 16 shows a view representing a multilayer substrate 400 of the semiconductor module parallel circuit 4 in the fourth embodiment. Fig. Figure 17 shows a schematic view of a cross-section of the multilayer substrate 400. Fig. 16 along a line C-C'. A basic configuration and each line connection are similar to those in the second embodiment. The fourth embodiment differs from the second embodiment in points that are described. In the multilayer substrate 400 of the Fig. 17. The interlayer distance between a first layer 401 and a second layer 402 and the interlayer distance between the second layer 402 and a third layer 403 are configured to be equal to each other. This means that the interlayer distance between the layer containing a gate return path and the layer containing a gate forward path, and the interlayer distance between the layer containing the gate forward path and the layer containing the output path, are equal to each other.

[0106] The interlayer distance between the layer containing the gate return path and the layer containing the gate forward path, and the interlayer distance between the layer containing the gate forward path and the layer containing the output path, are equal to each other, such that the influence of mutual inductance can be reduced.

[0107] A voltage drop due to a line inductance of the first layer 401 can be expressed by the following formula (7). ΔV1=L1×(diL1 / dt)−M12×(diL1 / dt)−M13×(diL1 / dt)

[0108] Similarly, a voltage drop due to a line inductance of the third layer 403 can be expressed by the following formula (8). ΔV3=L3×(diL3 / dt)−M23×(diL3 / dt)−M13×(diL3 / dt)

[0109] L1 represents a self-inductance of the first layer 401, L3 represents a self-inductance of the third layer 403, M13 represents a mutual inductance between the first layer 401 and the second layer 402, M23 represents a mutual inductance between the second layer 402 and the third layer 403, M12 represents a mutual inductance between the first layer 401 and the third layer 403, di L1 / dt represents a time differential of a current flowing through the first layer 401 and di L3 / dt represents a time differential of a current flowing through the third layer 403.

[0110] In the fourth embodiment, since the interlayer distance between the first layer 401 and the second layer 402 and the interlayer distance between the second layer 402 and the third layer 403 are configured to be equal to each other, the following formula (9) applies. M12=M23=M

[0111] Since a distance between the first signal connection pattern 111-1 and the first signal connection pattern 111-2 and a distance between the second signal connection pattern 113-1 and the second signal connection pattern 113-2 is designed to be equal to each other, a line length in the first layer 401 and a line length in the third layer 403 are equal to each other, and therefore the following formula (10) applies. L1=L3=L

[0112] Since a current flowing through the first layer 401 and a current flowing through the third layer 403 are equal to each other, the following formula (11) applies. diL1 / dt=diL3 / dt=di / dt

[0113] From formulas (7) to (11) the voltage drops due to the line inductances of the first layer 401 and the third layer 403 are expressed by formulas (12) and (13) as below. ΔV1=L×(di / dt)−M×(di / dt)−M13×(di / dt) ΔV3=L×(di / dt)−M×(di / dt)−M13×(di / dt)

[0114] It can be seen from formulas (12) and (13) that the voltage drops due to the line inductances of the first layer 401 and the third layer 403 are equal to each other.

[0115] In the fourth embodiment, the interlayer distance between the first layer 401 and the second layer 402 and the interlayer distance between the second layer 402 and the third layer 403 are configured to be equal to each other, so that the influence of mutual inductances can be reduced. Since the influence of mutual inductances can be reduced, the gate line inductance for semiconductor module 10-1 and the gate line inductance for semiconductor module 10-2 can be equal to each other.Since the gate line inductance for semiconductor module 10-1 and the gate line inductance for semiconductor module 10-2 can be equal to each other, the amounts of voltage drops due to the line inductances can be equal to each other, and it is possible to reduce an imbalance in the current generated between the semiconductor modules when the semiconductor modules are operated in parallel.

[0116] Although the fourth embodiment described above provides an example in which two semiconductor modules are arranged parallel to each other, the influence of mutual or reciprocal inductances can be similarly reduced even in a case where three semiconductor modules are arranged.

[0117] In the fourth embodiment, the lengths of the conductors are considered equal to each other if any current imbalance exists between the semiconductor modules to such an extent that it has essentially no effect. Similarly, the inductances of the conductors are considered equal to each other if any current imbalance exists between the semiconductor modules to such an extent that it has essentially no effect. Fifth embodiment

[0118] A fifth embodiment is one in which the influence of line inductance is further reduced. The fifth embodiment, described below, gives an example in which three semiconductor modules are arranged in parallel. Fig. Figure 18 shows a view representing a semiconductor module parallel circuit 5 according to the fifth embodiment. Fig. Figure 19 shows a view showing a multilayer substrate 500 of the semiconductor module parallel circuit 5 in the fifth embodiment.

[0119] Fig. Figure 20 shows a schematic view of a cross-section of the multilayer substrate 500 in Fig. 19 along a line D-D'. A basic configuration and each line connection are similar to those in the third embodiment. The fifth embodiment differs from the third embodiment in the points described below. For the sake of simplicity, a position of a gate return line in the X-direction corresponding to a position of the first signal connection pattern 111-1 in the X-direction is referred to as a branch point Q3. A position of the output line in the X-direction corresponding to a position of the second signal connection pattern 113-3 in the X-direction is referred to as a connection point P3.

[0120] In the gate return path, which is formed in a first layer 501 of the multilayer substrate 500 of the fifth embodiment, a conduction pattern from branch point Q1 to branch point Q2 is configured to have a width greater than the width of a conduction pattern from branch point Q2 to branch point Q3. In the output path, which is formed in a third layer 503 of the multilayer substrate 500, a conduction pattern from connection point P1 to connection point P2 is configured to have a width greater than the width of a conduction pattern from connection point P3 to connection point P1.

[0121] A gate driver current in the semiconductor module parallel circuit 5 is described. A current input from the external connection terminal 61 flows through a gate forward path formed in a second layer 502 of the multilayer substrate 500 and then through the gate return path formed in the first layer 501 of the multilayer substrate 500. Next, the current in the gate return path branches to provide current flows to the first signal connection patterns 111-1, 111-2, and 111-3.

[0122] One of the branched gate driver currents flows to the first signal terminal of semiconductor module 10-1 via the first signal terminal connection pattern 111-1. Similarly, another of the branched gate driver currents flows to the first signal terminal of semiconductor module 10-2 via the first signal terminal connection pattern 111-2, and the other of the branched gate driver currents flows to the first signal terminal of semiconductor module 10-3 via the first signal terminal connection pattern 111-3. The gate driver current branched at the gate return branch point Q1 flows to the first signal terminal connection pattern 111-3. The gate driver current branched at the gate return branch point Q2 flows to the first signal terminal connection pattern 111-2.

[0123] Next, a current output from the second signal terminal of semiconductor module 10-1 flows into the output line of the multilayer substrate 500 via the second signal terminal connection pattern 113-1. Similarly, a current output from the second signal terminal of semiconductor module 10-2 flows into the output line of the multilayer substrate 500 via the second signal terminal connection pattern 113-2. A current output from the second signal terminal of semiconductor module 10-3 flows into the output line of the multilayer substrate 500 via the second signal terminal connection pattern 113-3. The current output from the second signal terminal connection pattern 113-3 joins, or merges with, the current output from the second signal terminal connection pattern 113-2 at the connection point P1 of the output line.The current outputs from the second signal connection pattern 113-2 and the second signal connection pattern 113-3 converge with the current output from the second signal connection pattern 113-1 at connection point P2 of the output line. The combined currents at connection point P2 are output via the external connection port 61.

[0124] Fig. Figure 21 shows a view representing a gate driver current flowing through each layer of the multilayer substrate 500. When a current flowing through the gate lead passes through Ig 123If a current flowing from branch point Q3 to the first signal connection pattern 111-1 is designated by I1g, a current flowing from branch point Q1 to the first signal connection pattern 111-2 is designated by I2g, and a current flowing from branch point Q2 to the first signal connection pattern 111-3 is designated by I3g, then the following formula (14) is true. Ig123=I1g+I2g+Ig3

[0125] Current inputs to the first signal terminals of the semiconductor modules 10-1, 10-2 and 10-3 can be approximated in formula (15) as below. I1g=I2g=I3g=Ig

[0126] Formula (16) as below is derived from formulas (14) and (15). Ig123=3Ig

[0127] From the preceding formulas (15) and (16), the current flowing in the gate return path from branch point Q2 to the first signal connection pattern 111-1 is Ig. A current flowing from branch point Q1 to branch point Q2 is 2Ig.

[0128] Next, if a current flowing through the output line passes through Is 123 where a current or current output from the second signal connection pattern 113-3 is designated by I3s, a current output from the second signal connection pattern 113-2 is designated by I2s, and a current output from the second signal connection pattern 113-1 is designated by I1s, the following formula (17) applies. I1s+I2s+I3s=Is123

[0129] Current outputs from the second signal terminals of semiconductor modules 10-1, 10-2 and 10-3 can be approximated in formula (18) as below. I1s=I2s=I3s=Is

[0130] Formula (19) below is derived from formulas (17) and (18). Is123=3Is

[0131] From formulas (18) and (19), a current Is flowing in the output line from the second signal connection pattern 113-3 to connection point P1 is given. A current flowing from connection point P1 to connection point P2 is 2Is.

[0132] Based on the preceding description, the current in the gate return path from junction Q2 to junction Q3 is Ig. The current flowing from junction Q1 to junction Q2 is 2Ig. The current flowing from junction Q1 to junction Q2 is approximately twice the current flowing from junction Q2 to junction Q3. In the gate return path, there is a difference in the time-differentiated amount of current in the path from junction Q1 to junction Q2 and in the path from junction Q2 to junction Q3. Similarly, in the output path, the current flowing from junction P1 to junction P2 is 2Is. A current flowing from junction P3 to junction P1 is Is.The current flowing from junction P1 to junction P2 is approximately twice the current flowing from junction P3 to junction P1. In the output line, there is a difference in the time-differentiated current between the line from junction P1 to junction P2 and the line from junction P3 to junction P1. This difference in the time-differentiated current in the line is therefore present.

[0133] In the fourth embodiment described, the voltage drop across the line is expressed by the product of the line's self-inductance and a time-differentiated amount of current, as in formula (20) below. To simplify the description, the influence of mutual inductances is not considered here. ΔV=L×(di / dt)

[0134] L represents the self-inductance of a conductor and di / dt represents a time-differentiated amount of current. As can be seen from formula (20), a different time-differentiated amount of current results in a different amount of voltage drop.

[0135] In the gate return path of the multilayer substrate 500 of the fifth embodiment, the conductor pattern from branch point Q1 to branch point Q2 is configured to have a width greater than the conductor pattern from branch point Q2 to branch point Q3. Increasing the conductor pattern width can reduce the self-inductance of the conductor. This means that the conductor from branch point Q1 to branch point Q2 achieves a lower self-inductance than the conductor from branch point Q2 to branch point Q3.

[0136] As can be seen from formula (20), the self-inductance of the line is given by a first term on the right-hand side of formula (20), and the time-differentiated amount of current is given by a second term on the right-hand side of formula (20). The line from branch point Q1 to branch point Q2 provides a larger second term on the right-hand side of formula (20) than the line from branch point Q2 to branch point Q3. However, since the width of the line pattern from branch point Q1 to branch point Q2 is greater than the width of the line pattern from branch point Q2 to branch point Q3, the first term on the right-hand side of formula (20) can be reduced.

[0137] The foregoing applies similarly to the output line. The line from connection point P1 to connection point P2 represents a larger second term on the right-hand side of formula (20) than the line from connection point P3 to connection point P1. However, because the width of the line pattern from connection point P1 to connection point P2 is greater than the width of the line pattern from connection point P3 to connection point P1, the first term on the right-hand side of formula (20) can be reduced.

[0138] In the fifth embodiment, the self-inductance of the line and the time-differentiated amount of current are taken into account, making it possible to reduce the difference in the amount of voltage drop due to the inductance of the line.

[0139] In the fifth embodiment, because the voltage drop quantities of the gate line in the semiconductor module 10-1 and the gate line of the semiconductor module 10-2 can be equal to each other, it is possible to reduce an imbalance in the current that is generated between the semiconductor modules when the semiconductor modules are operated in parallel.

[0140] In the fifth embodiment, the line inductances are considered to be equal to each other if an imbalance in the current between the semiconductor modules exists to such an extent that it has essentially no effect.

[0141] Note that in the present invention the respective embodiments can be freely combined or the embodiments can be suitably modified or omitted within the scope of the invention. Reference symbol list

[0142] 1, 2, 3, 4, 5 Semiconductor module parallel connection; 10-1 Semiconductor module; 10-2 Semiconductor module; 10-3 Semiconductor module; 10P First main connection; 10N Second main connection; 10AC Third main connection; 11, 11-1, 11-2, 12, 12-1, 12-2 First signal connection; 13, 13-1, 13-2, 14, 14-1, 14-2 Second signal connection; 20 Assembly; 30, 30-1, 30-2 First semiconductor element; 40, 40-1, 40-2 Second semiconductor element; 50 Mounting element; 61, 62 External connection connection; 71-1, 71-2 First connection connection; 72-1, 72-2 Second connection connection; 100, 200, 300, 400, 500 multilayer substrate; 111-1, 111-2, 111-3, 112-1, 112-2, 112-3 first signal connection pattern; 113-1, 113-2, 113-3, 114-1, 114-2, 114-3 second signal connection pattern; 201, 301, 401, 501 first layer; 202, 302, 402, 502 second layer; 203, 303, 403, 503 third layer; D1, D2 drain connection; S1, S2 source connection.

Claims

[1] Semiconductor module parallel connection (1), with: a first power semiconductor module (10-1); a second power semiconductor module (10-2); and a multilayer substrate (100) for connecting a plurality of the power semiconductor modules, wherein Each of the power semiconductor modules features: a power semiconductor switching element (30; 40); a first signal terminal (11-1) which is connected to a gate potential of the power semiconductor switching element; and a second signal terminal (13-1) which is connected to a source potential of the power semiconductor switching element, the multilayer substrate exhibits: an external connection port (61); a first signal connection pattern (111-1) for the first power semiconductor module, wherein the first signal connection pattern for the first power semiconductor module is connected to the first signal terminal of the first power semiconductor module; a second signal connection pattern (113-1) for the first power semiconductor module, wherein the second signal connection pattern for the first power semiconductor module is connected to the second signal terminal of the first power semiconductor module; a first signal connection pattern (111-2) for the second power semiconductor module, wherein the first signal connection pattern for the second power semiconductor module is connected to the first signal terminal of the second power semiconductor module; and a second signal connection pattern (113-2) for the second power semiconductor module, wherein the second signal connection pattern for the second power semiconductor module is connected to the second signal terminal of the second power semiconductor module, and wherein an inductance of a gate line for the first power semiconductor module from the external connection terminal to the first signal connection pattern for the first power semiconductor module and from the second signal connection pattern for the first power semiconductor module to the external connection terminal, and an inductance of the gate line for the second power semiconductor module from the external connection terminal to the first signal connection pattern for the second power semiconductor module and from the second signal connection pattern for the second power semiconductor module to the external connection terminal are equal to each other, and wherein a line from the external connection terminal to the first signal connection pattern for the first power semiconductor module and a line from the external connection terminal to the first signal connection pattern for the second power semiconductor module are formed in a first layer and in a third layer of the multilayer substrate, and a line from the second signal connection pattern for the first power semiconductor module to the external connection terminal and a line from the second signal connection pattern for the second power semiconductor module to the external connection terminal are formed in a second layer of the multilayer substrate. [2] Semiconductor module parallel connection (1), with: a first power semiconductor module (10-1); a second power semiconductor module (10-2); and a multilayer substrate (100) for connecting a plurality of the power semiconductor modules, wherein Each of the power semiconductor modules features: a power semiconductor switching element (30; 40); a first signal terminal (11-1) which is connected to a gate potential of the power semiconductor switching element; and a second signal terminal (13-1) which is connected to a source potential of the power semiconductor switching element, the multilayer substrate exhibits: an external connection port (61); a first signal connection pattern (111-1) for the first power semiconductor module, wherein the first signal connection pattern for the first power semiconductor module is connected to the first signal terminal of the first power semiconductor module; a second signal connection pattern (113-1) for the first power semiconductor module, wherein the second signal connection pattern for the first power semiconductor module is connected to the second signal terminal of the first power semiconductor module; a first signal connection pattern (111-2) for the second power semiconductor module, wherein the first signal connection pattern for the second power semiconductor module is connected to the first signal terminal of the second power semiconductor module; and a second signal connection pattern (113-2) for the second power semiconductor module, wherein the second signal connection pattern for the second power semiconductor module is connected to the second signal terminal of the second power semiconductor module, and wherein a length of a gate line for the first power semiconductor module from the external connection terminal to the first signal connection pattern for the first power semiconductor module and from the second signal connection pattern for the first power semiconductor module to the external connection terminal, and a length of the gate line for the second power semiconductor module from the external connection terminal to the first signal connection pattern for the second power semiconductor module and from the second signal connection pattern for the second power semiconductor module to the external connection terminal are equal to each other, and wherein a line from the external connection terminal to the first signal connection pattern for the first power semiconductor module and a line from the external connection terminal to the first signal connection pattern for the second power semiconductor module are formed in a first layer and in a third layer of the multilayer substrate, and a line from the second signal connection pattern for the first power semiconductor module to the external connection terminal and a line from the second signal connection pattern for the second power semiconductor module to the external connection terminal are formed in a second layer of the multilayer substrate. [3] Semiconductor module parallel connection (3), with: a first power semiconductor module (10-1); a second power semiconductor module (10-2); a third power semiconductor module (10-3); and a multilayer substrate (300) for connecting a plurality of the power semiconductor modules, wherein Each of the power semiconductor modules features: a power semiconductor switching element (30; 40); a first signal terminal (11-1) which is connected to a gate potential of the power semiconductor switching element; and a second signal terminal (13-1) which is connected to a source potential of the power semiconductor switching element, the multilayer substrate exhibits: an external connection port (61); a first signal connection pattern (111-1) for the first power semiconductor module, wherein the first signal connection pattern for the first power semiconductor module is connected to the first signal terminal of the first power semiconductor module; a second signal connection pattern (113-1) for the first power semiconductor module, wherein the second signal connection pattern for the first power semiconductor module is connected to the second signal terminal of the first power semiconductor module; a first signal connection pattern (111-2) for the second power semiconductor module, wherein the first signal connection pattern for the second power semiconductor module is connected to the first signal terminal of the second power semiconductor module; a second signal connection pattern (113-2) for the second power semiconductor module, wherein the second signal connection pattern for the second power semiconductor module is connected to the second signal terminal of the second power semiconductor module; a first signal connection pattern (111-3) for the third power semiconductor module, wherein the first signal connection pattern for the third power semiconductor module is connected to the first signal terminal of the third power semiconductor module; and a second signal connection pattern (113-3) for the third power semiconductor module, wherein the second signal connection pattern for the third power semiconductor module is connected to the second signal terminal of the third power semiconductor module, and an inductance of the gate line for the first power semiconductor module from the external connection terminal to the first signal connection pattern for the first power semiconductor module and from the second signal connection pattern for the first power semiconductor module to the external connection terminal, an inductance of the gate line for the second power semiconductor module from the external connection terminal to the first signal connection pattern for the second power semiconductor module and from the second signal connection pattern for the second power semiconductor module to the external connection terminal, and an inductance of the gate line for the third power semiconductor module from the external connection terminal to the first signal connection pattern for the third power semiconductor module and from the second signal connection pattern for the third power semiconductor module to the external connection terminal are equal to each other,and whereby a line from the external connection port to the first signal connection pattern for the first power semiconductor module, a line from the external connection port to the first signal connection pattern for the second power semiconductor module and a line from the external connection port to the first signal connection pattern for the third power semiconductor module are formed in a first layer and in a third layer of the multilayer substrate, and a line from the second signal connection pattern for the first power semiconductor module to the external connection port, a line from the second signal connection pattern for the second power semiconductor module to the external connection port and a line from the second signal connection pattern for the third power semiconductor module to the external connection port are formed in a second layer of the multilayer substrate. [4] Semiconductor module parallel connection (3), with: a first power semiconductor module (10-1); a second power semiconductor module (10-2); a third power semiconductor module (10-3); and a multilayer substrate (300) for connecting a plurality of the power semiconductor modules, wherein Each of the power semiconductor modules features: a power semiconductor switching element (30; 40); a first signal terminal (11-1) which is connected to a gate potential of the power semiconductor switching element; and a second signal terminal (13-1) which is connected to a source potential of the power semiconductor switching element, the multilayer substrate exhibits: an external connection port (61); a first signal connection pattern (111-1) for the first power semiconductor module, wherein the first signal connection pattern for the first power semiconductor module is connected to the first signal terminal of the first power semiconductor module; a second signal connection pattern (113-1) for the first power semiconductor module, wherein the second signal connection pattern for the first power semiconductor module is connected to the second signal terminal of the first power semiconductor module; a first signal connection pattern (111-2) for the second power semiconductor module, wherein the first signal connection pattern for the second power semiconductor module is connected to the first signal terminal of the second power semiconductor module; a second signal connection pattern (113-2) for the second power semiconductor module, wherein the second signal connection pattern for the second power semiconductor module is connected to the second signal terminal of the second power semiconductor module; a first signal connection pattern (111-3) for the third power semiconductor module, wherein the first signal connection pattern for the third power semiconductor module is connected to the first signal terminal of the third power semiconductor module; and a second signal connection pattern (113-3) for the third power semiconductor module, wherein the second signal connection pattern for the third power semiconductor module is connected to the second signal terminal of the third power semiconductor module, and wherein a length of the gate line for the first power semiconductor module from the external connection terminal to the first signal connection pattern for the first power semiconductor module and from the second signal connection pattern for the first power semiconductor module to the external connection terminal, a length of a gate line for the second power semiconductor module from the external connection terminal to the first signal connection pattern for the second power semiconductor module and from the second signal connection pattern for the second power semiconductor module to the external connection terminal, and a length of a gate line for the third power semiconductor module from the external connection terminal to the first signal connection pattern for the third power semiconductor module and from the second signal connection pattern for the third power semiconductor module to the external connection terminal are equal to each other, and wherein a line from the external connection port to the first signal connection pattern for the first power semiconductor module, a line from the external connection port to the first signal connection pattern for the second power semiconductor module and a line from the external connection port to the first signal connection pattern for the third power semiconductor module are formed in a first layer and in a third layer of the multilayer substrate, and a line from the second signal connection pattern for the first power semiconductor module to the external connection port, a line from the second signal connection pattern for the second power semiconductor module to the external connection port and a line from the second signal connection pattern for the third power semiconductor module to the external connection port are formed in a second layer of the multilayer substrate. [5] Multilayer substrate (100), with: an external connection port (61); a first signal connection pattern (111-1) for a first power semiconductor module (10-1), wherein the first signal connection pattern for the first power semiconductor module is provided for connection to a first signal terminal of the first power semiconductor module; a second signal connection pattern (113-1) for the first power semiconductor module, wherein the second signal connection pattern for the first power semiconductor module is provided for connection to a second signal terminal of the first power semiconductor module; a first signal connection pattern (111-2) for a second power semiconductor module (10-2), wherein the first signal connection pattern for the second power semiconductor module is provided for connection to a first signal terminal of the second power semiconductor module; and a second signal connection pattern (113-2) for the second power semiconductor module, wherein the second signal connection pattern for the second power semiconductor module is provided for connection to a second signal terminal of the second power semiconductor module, wherein an inductance of a gate line for the first power semiconductor module from the external connection terminal to the first signal connection pattern for the first power semiconductor module and from the second signal connection pattern for the first power semiconductor module to the external connection terminal, and an inductance of a gate line for the second power semiconductor module from the external connection terminal to the first signal connection pattern for the second power semiconductor module and from the second signal connection pattern for the second power semiconductor module to the external connection terminal are equal to each other, and wherein A trace from the external connection terminal to the first signal connection pattern for the first power semiconductor module and a trace from the external connection terminal to the first signal connection pattern for the second power semiconductor module are formed in a first layer and in a third layer of the multilayer substrate, and a trace from the second signal connection pattern for the first power semiconductor module to the external connection terminal and a trace from the second signal connection pattern for the second power semiconductor module to the external connection terminal are formed in a second layer of the multilayer substrate. [6] Multilayer substrate (100), with: an external connection port (61); a first signal connection pattern (111-1) for a first power semiconductor module (10-1), wherein the first signal connection pattern for the first power semiconductor module is provided for connection to a first signal terminal of the first power semiconductor module; a second signal connection pattern (113-1) for the first power semiconductor module, wherein the second signal connection pattern for the first power semiconductor module is provided for connection to a second signal terminal of the first power semiconductor module; a first signal connection pattern (111-2) for a second power semiconductor module (10-2), wherein the first signal connection pattern for the second power semiconductor module is provided for connection to a first signal terminal of the second power semiconductor module; and a second signal connection pattern (113-2) for the second power semiconductor module, wherein the second signal connection pattern for the second power semiconductor module is provided for connection to a second signal terminal of the second power semiconductor module, wherein a length of a gate line for the first power semiconductor module from the external connection terminal to the first signal connection pattern for the first power semiconductor module and from the second signal connection pattern for the first power semiconductor module to the external connection terminal, and a length of a gate line for the second power semiconductor module from the external connection terminal to the first signal connection pattern for the second power semiconductor module and from the second signal connection pattern for the second power semiconductor module to the external connection terminal are equal to each other, and wherein a line from the external connection terminal to the first signal connection pattern for the first power semiconductor module and a line from the external connection terminal to the first signal connection pattern for the second power semiconductor module are formed in a first layer and in a third layer of the multilayer substrate, and a line from the second signal connection pattern for the first power semiconductor module to the external connection terminal and a line from the second signal connection pattern for the second power semiconductor module to the external connection terminal are formed in a second layer of the multilayer substrate.

Images