DEVELOPING A THIN FILM RESISTANCE (TFR) IN AN INTEGRATED CIRCUIT

Abstract

Method for forming an integrated circuit (IC) structure incorporating a thin-film resistor (TFR), wherein the method comprises: Forming at least one memory cell element (12A, 12B) over a semiconductor substrate (14), wherein the at least one memory cell element (12A, 12B) has at least one memory cell element contact area (20); Forming a first contact etch stop layer (30) over the at least one memory cell element (12A, 12B); Forming a TFR layer stack (40, 42, 44) in a pre-metal dielectric region (32) above the first contact etch stop layer (30) and laterally offset from the at least one memory cell element contact region, wherein the formation of the TFR layer stack (40, 42, 44) in a pre-metal dielectric region (32) comprises: Forming a TFR film layer (42), and Forming a second contact etch stop layer (44) over the TFR film layer (42); Annealing the TFR film layer (42) to match a value of the temperature coefficient of resistance, TCR, of the TFR film layer; Forming a structured mask (64) with at least one first mask opening (68A) aligned over the at least one IC element contact area ((20) and at least one second mask opening (68B) aligned over the TFR layer stack (40, 42, 44); Performing at least one etch through the first and second mask openings (68A, 68B) and through sections of the IC structure, including through both the first contact etch stop layer (30) and the second contact etch stop layer (44), to simultaneously (a) form at least one first contact opening (68A) that exposes the at least one contact area (20) of the memory cell element (12A, 12B) and (b) form at least one second contact opening (68B) that exposes the TFR film layer (42); and Filling the at least one first contact opening (68A) and the at least one second contact opening (68B) with conductive material to form at least one conductive contact (70A) to the at least one memory cell element (12A, 12B) and at least one conductive contact (70B) to the TFR film layer (42).

Description

[0001] The present disclosure relates to thin-film resistors (TFRs) and a method for forming thin-film resistors, e.g. systems and methods for forming a thin-film resistor that is integrated into an integrated semiconductor circuit (IC).

[0002] Many integrated circuits (“ICs”) incorporate thin-film resistors (TFRs), which offer several advantages over other resistor types. For example, TFRs can be highly accurate and can be finely tuned to provide a very precise resistance value. Furthermore, TFRs typically exhibit a low temperature coefficient of resistance (TCR), often achieved through a suitable annealing process to “tune” the TCR to near zero, which can provide stable operation over a wide range of operating temperatures. Additionally, TFRs typically have smaller parasitic components, resulting in advantageous high-frequency performance. A TFR can comprise any suitable metallic film formed on or within an insulating substrate. Some common IC-integrated TFR materials include SiCr, SiCCr, TaN, and TiN, although other suitable materials can also be used.A common disadvantage of thin-film resistors is that their fabrication typically requires additional processing steps, including several additional masking steps. For example, at least two masking steps are typically required to integrate a TFR into a process that uses AlCu as the backend compound.

[0003] A metal thin-film resistor and manufacturing process are known from US patent application US 2015 / 0187632A1.

[0004] The object of the present invention is to provide an improved technique for integrating a thin-film resistor (TFR) into an integrated semiconductor circuit (IC), which can offer cost reductions compared to conventional techniques. This and other objects are achieved by the independent claims. Further developments are characterized by the dependent claims. For example, some embodiments provide methods and systems for forming an integrated TFR using a single photomask process, compared to conventional methods that require at least two mask processes.

[0005] Embodiments of the present invention may provide one or more advantages over known multiple photomask TFR integration processes, including, for example, reduced costs, reduced cycle time and / or reduced defects in the integrated TFR.

[0006] Some embodiments utilize differences in etch selectivity between various layers in an IC stack to enable the insertion of a TFR into a pre-metallic dielectric region using only a single photomask. Specifically, an etch-resistant layer can be provided directly over a TFR film formed in an IC stack to control subsequent contact etching (an etching process to form contact grooves or holes) such that the contact etching exposes both the TFR film and the contact pads of IC elements (e.g., transistor or memory components) essentially simultaneously. Thus, a single etching process (and therefore a single mask) can be used to form both (a) TFR contacts and (b) contact(s) to underlying IC elements.For example, utilizing the fact that nitride generally etches much more slowly than oxide in contact etching processes, a nitride layer (e.g., SiN) can be provided directly over the TFR film to slow down the contact etching over the TFR film, while the contact etching continues at a normal etch rate in areas where the nitride layer is not present. This ensures that the contact etching reaches both the TFR film and the IC element's contact pads simultaneously. Thus, the nitride layer formed over the TFR film acts as a "hard mask," a feature not considered in conventional TFR formation techniques.

[0007] Exemplary aspects of the present revelation are described below in connection with the figures in which: Fig. 1A to Fig. 1L illustrates an exemplary method for integrating a thin-film resistor (TFR) into an integrated semiconductor circuit (IC) according to an exemplary embodiment of the invention; Fig. Figure 2 shows a further exemplary embodiment of the present invention, in which a TFR is formed directly on a first contact etch stop layer and a first dielectric layer at the bottom of the IC stack; and Fig. Figure 3 shows a further embodiment of the present invention in which a TFR is formed higher in the exemplary IC structure, between the second and third dielectric layers.

[0008] It is understood that the reference sign for each illustrated element appearing in several different figures has the same meaning across the several figures, and that the mention or discussion of each illustrated element herein in the context of a particular figure also applies to any other figure, if any, in which the same illustrated element is shown.

[0009] As discussed above, embodiments of the present invention provide an improved method for integrating a thin-film resistor (TFR) into an integrated semiconductor circuit (IC), which can offer cost reductions compared to conventional methods. For example, some embodiments provide methods and systems for forming an integrated TFR using a single photomask process, compared to conventional methods that require at least two mask processes.

[0010] A first aspect of the invention provides a method for forming an integrated circuit (IC) structure comprising a thin-film resistor (TFR). The method can comprise forming at least one IC element over a semiconductor substrate, wherein the at least one IC element has at least one IC element contact area; forming a first contact etch stop layer over the at least one IC element; and forming a TFR layer stack over the first contact etch stop layer and laterally offset from the at least one IC element contact area. The formation of the TFR layer stack can comprise: forming a TFR etch stop layer, forming a TFR film over the TFR etch stop layer, and forming a second contact etch stop layer over the TFR film. At least one dielectric layer can be formed above or below the TFR layer stack, i.e., before or after the formation of the TFR layer stack.A structured mask can be formed having at least one first mask opening aligned over the at least one IC element contact area and at least one second mask opening aligned over the TFR layer stack. At least one etching step can then be performed through the first and second mask openings and through portions of the IC structure, including both the first contact etch stop layer and the second contact etch stop layer, to simultaneously form (a) at least one first contact opening exposing the at least one contact area of ​​the IC element and (b) at least one second contact opening exposing the TFR film. The first and second contact openings can be filled with conductive material to form at least one conductive contact with the at least one IC element and at least one conductive contact with the TFR film.

[0011] In some embodiments, one or more dielectric layers can be deposited over the at least one IC element and over the first contact etch stop layer, and the TFR layer stack can be formed over one or more such dielectric layers. Furthermore, at least one dielectric layer can be deposited over the TFR layer stack.

[0012] In some embodiments, the TFR layer stack can be formed directly on the first contact etch stop layer.

[0013] In some embodiments, the first and second contact etch stop layers are formed from the same material. For example, both the first and second contact etch stop layers can comprise SiN layers. In other embodiments, the first and second contact etch stop layers can be formed from different materials.

[0014] For example, the first or second contact etch stop layer may comprise SiN, while the other may comprise SiC or SiON. In some embodiments, the second contact etch stop layer has a greater thickness than the first contact etch stop layer.

[0015] In some embodiments, performing at least one etching to simultaneously form (a) at least one first contact opening exposing the IC element contact area and (b) at least one second contact opening exposing the TFR film may comprise: (a) performing a first etching that stops at the first contact etch stop layer and the second contact etch stop layer; and (b) performing a second etching that extends through the first contact etch stop layer and the second contact etch stop layer to expose the at least one IC element contact area and the TFR film.

[0016] Another aspect of the invention provides a method for forming a thin-film resistor (TFR) which comprises forming a conductive contact area over a semiconductor substrate; forming a first contact etch stop layer over the conductive contact area; forming a TFR film over the first contact etch stop layer; and forming a second contact etch stop layer over the TFR film, wherein the TFR film and the second contact etch stop layer are laterally offset from the contact pad.The method may further comprise: forming a structured mask with a first mask opening aligned over the conductive contact area and at least one second mask opening aligned over the TFR film; performing at least one etching through the first and second mask openings and through both the first contact etch stop layer and the second contact etch stop layer to form both (a) a first contact opening exposing the conductive contact area and (b) at least one second contact opening exposing the TFR film; and filling the first contact opening and the at least one second contact opening with conductive material to form vertically extending contacts to the conductive contact area and the TFR film.

[0017] In some embodiments, the method may include forming an IC element over the semiconductor substrate, wherein the conductive contact area provides conductive coupling with the IC element; depositing at least one dielectric layer over the IC element, the conductive contact area and the first contact etch stop layer; and forming the TFR film over the at least one dielectric layer.

[0018] In some embodiments, the method may include: forming a TFR layer stack directly on the first contact etch stop layer by forming a TFR etch stop layer directly on the first contact etch stop layer; forming the TFR film over the TFR etch stop layer; and forming the second contact etch stop layer over the TFR film. Another aspect of the invention provides an integrated circuit (IC) structure comprising at least one IC element located over a semiconductor substrate, wherein the at least one IC element has at least one IC element contact area; a first contact etch stop layer over the at least one IC element; and a thin-film resistor (TFR) over the first contact etch stop layer and laterally offset from the at least one IC element contact area. The TFR layer stack may comprise a TFR film layer and a second contact etch stop layer over the TFR film layer.A lateral edge of the second contact etch stop layer coincides laterally with a lateral edge of the TFR film layer beneath the second contact etch stop layer. In some embodiments, the lateral edge of the second contact etch stop layer and the lateral edge of the underlying TFR film layer coincide laterally as a result of a masking and vertical etching process performed on the TFR layer stack. The IC structure may also include at least one conductive contact extending downwards towards the TFR film layer, thereby defining a TFR within the IC structure, and at least one conductive contact offset laterally from the TFR and extending downwards towards the at least one IC element.

[0019] In some embodiments, the IC structure also has at least one dielectric layer above the first contact etch stop layer and below the TFR layer stack.

[0020] In some embodiments, the TFR further comprises a TFR etch stop layer beneath the TFR film layer. In some embodiments, a lateral edge of the TFR etch stop layer may coincide laterally with the lateral edge of the TFR film layer and the lateral edge of the second contact etch stop layer. In some embodiments, the lateral edges of the second contact etch stop layer, the TFR film layer, and the TFR etch stop layer coincide laterally as a result of a masking and vertical etching process performed on the TFR layer stack.

[0021] Fig. 1A to Fig. 1L illustrate an exemplary method for integrating a thin-film resistor (TFR) into an integrated semiconductor circuit (IC) according to an exemplary embodiment.

[0022] Fig. Figure 1A illustrates an exemplary integrated circuit (IC) structure 10, e.g., during the fabrication of a chip or other device, which includes any number of IC elements or components 12, e.g., memory cells, transistors, gates (e.g., floating gates, control gates, erase gates), word lines, bit lines, conductive contacts, vias, or other metal conductors, without restriction to a substrate 14. Memory cells, transistors, or gates are collectively known as active elements. In this example, the illustrated section of the IC structure includes floating-gate memory elements 12A and 12B of an EEPROM or flash memory cell. IC elements 12A and 12B may have programmable layer structures 16 (e.g., gates) and a dielectric spacer layer 18 formed on the sidewall of the programmable layer structures 16.A silicide layer can define silicide contact pads 20 for IC elements 12A and 12B, or conductive coupling of the IC elements 12A and 12B with subsequently formed conductive contacts (see, for example, the ones discussed below). Fig. 1K and Fig. 1L), e.g. to apply selected voltages to IC elements 12A and 12B.

[0023] Fig. 1A can represent a state during an IC manufacturing process after the formation of the memory cell elements 12A and 12B and the deposition of a first contact etch stop layer 30 followed by a first dielectric layer 32 over the elements 12A and 12B. In one embodiment, the first contact etch stop layer 30 can comprise a self-aligned contact (SAC) SiN layer, and the first dielectric layer 32 can comprise a high-density plasma (HDP) pre-metal dielectric (PMD) oxide.

[0024] As in Fig. As shown in Figure 1B, a CMP process can be performed to planarize an upper surface of the first dielectric layer 32. In some embodiments, rapid thermal processing (RTP annealing) can be performed to further stabilize the first dielectric layer 32.

[0025] As in Fig. As shown in Figure 1C, a TFR layer stack 38 is deposited over the first dielectric layer 32. For example, a TFR film layer 42 (e.g., SiCCr, SiCr, TaN, TiN, or any other suitable TFR film material) can be deposited between a pair of etch stop layers, represented as a lower TFR etch stop layer 40 (e.g., SiN) and a second contact etch stop layer 44 (e.g., SiN). Furthermore, annealing is performed, e.g., before (or after) the deposition of the second contact etch stop layer 44, to tune or optimize a temperature coefficient of the TFR film layer 42.

[0026] The lower TFR etch stop layer 40 can be optional depending on the specific embodiment. Thus, some embodiments can omit the lower TFR etch stop layer 40, so that the TFR layer stack 38 comprises only a TFR film layer 42 and a second contact etch stop layer 44 above it.

[0027] The second contact etch stop layer 44 can be configured to act as a TFR hard mask. The thickness of the second contact etch stop layer 44 can be selected or adjusted to provide the desired etching results in a subsequent etching process, which is described below with reference to Fig. 1 year and Fig. 1K is discussed. For example, the thickness of the second contact etch stop layer 44 can be selected based on (a) the etch selectivity of the second contact etch stop layer 44 relative to one or more underlying layers, in this example the lower TFR etch stop layer 40 and the first dielectric layer 32, and / or (b) the thickness of the second layer of the contact etch stop layer 44 relative to the thickness of one or more underlying layers, since these thicknesses generally affect the etch rate through each respective layer.

[0028] In an exemplary embodiment, the formation of the TFR layer stack 38 comprises the deposition of a lower 32.5 nm (325 Å) SiN TFR etch stop layer 40, the deposition of a 22.5 nm (225 Å) SiCCr TFR film layer 42, the annealing of the SiCCr film layer 42 at 515°C for 30 minutes to optimize the temperature coefficient of the TFR film layer 42, and finally the deposition of ~100 nm (~1000 Å) (e.g., 50 nm - 150 nm (500 Å - 1500 Å)) of the second SiN contact etch stop layer 44, which acts as a hard mask during the Fig. The effects of etching performed in 1J are discussed below.

[0029] As in Fig. As shown in Figure 1D, a photoresist 50 can be deposited and structured over the TFR layer stack 38 at a desired location for TFR formation. As shown, the photoresist 50 can be structured at a location laterally offset from the silicide contact pads 20 to form a TFR that is laterally offset from the silicide contact pads 20, thereby enabling the simultaneous formation of contacts extending down to the silicide contact pads 20 and contacts extending downwards to the TFR, as discussed below.

[0030] As in Fig. As shown in Figure 1E, the constituent layers of the TFR layer stack 38, i.e., the optional lower TFR etch stop layer 40, the TFR film layer 42, and the second contact etch stop layer 44, can then be etched outside the area of ​​the photoresist 50 using a TFR etching process. In one embodiment, the TFR etching process is a two-stage etching process, including (a) a first etching to remove the second contact etch stop layer 44 and the TFR film layer 42 and stopping at the lower TFR etch stop layer 40 (e.g., due to the etch selectivity of the relevant layers), followed by (b) a second etching using a different etching chemistry than the first etching to remove the lower TFR etch stop layer 40, leaving photoresist 50 over the remaining portions of the TFR layer stack 38.The TFR etching process can define at least one lateral edge of the second contact etch stop layer 44, the TFR film layer 42, and the lower TFR etch stop layer 40 based on the lateral extent of the photomask 50. For example, as shown in . Fig. Figure 1E shows the TFR etching process (a) defining first lateral edges 44a, 42a and 40a (of the second contact etch stop layer 44, the TFR film layer 42 and the lower TFR etch stop layer 40 respectively) which are self-aligned by a first lateral edge 50a of the photomask 50 and thus coincide with each other, and (b) second lateral edges 44b, 42b and 40b (of the second contact etch stop layer 44, TFR film layer 42 and lower TFR etch stop layer 40) which are self-aligned by a second lateral edge 50b of the photomask 50 and thus coincide with each other. In such embodiments, the first side edges 44a, 42a and 40a and the second side edges 44b, 42b and 40b can be referred to as etch-defined side edges, which may be structurally distinguishable from side edges defined in other ways.

[0031] As in Fig. As shown in 1F, the remaining photoresist 50 can then be removed, e.g. using a photoresist peel-off / ashing process.

[0032] As in Fig. As shown in Figure 1G, a second dielectric layer 54 can be deposited over the structure. In some embodiments, the second dielectric layer 54 can comprise a pre-metal dielectric (PMD) oxide, e.g., PMD P TEOS (phosphorus-doped tetraethyl orthosilicate film). As shown, the deposited second dielectric layer 54 can cover the first and second lateral edges 44a / 44b, 42a / 42b, and 40a / 40b of the second contact etch stop layer 44, the TFR film layer 42, and the lower TFR etch stop layer 40, respectively.

[0033] As in Fig. As shown in 1H, a CMP process can be carried out to planarize an upper surface of the second dielectric layer 54. As in Fig. As shown in Figure 1I, a third dielectric layer 60, e.g., a PMD oxide top layer, can be deposited over the planarized upper surface of the second dielectric layer 54. This step may be optional depending on the specific embodiment.

[0034] As in Fig. As shown in Figure 1J, a contact photomask 64 can be deposited and structured, followed by an etching process to create openings for forming conductive contacts to the IC elements 12A and 12B and the TFR film layer 42. The etching process for creating contact openings is referred to herein as the “contact etching” process. In some embodiments, the contact etching process may comprise a sequence of multiple contact etchings, for example, using different etching chemistries or different etching parameters for each etching. In the illustrated embodiment, the contact etching process comprises a first contact etching followed by a second contact etching.

[0035] As in Fig. As shown in Figure 1J, a first contact etch is performed to simultaneously, at least partially, etch all contact openings (e.g., trenches or vias), including the first contact openings 68A, which are oriented laterally over the target structures of the IC elements 12A and 12B (including silicide pads 20), and second contact openings 68B, which are oriented laterally over the remaining portion of the TFR film layer 42. In some embodiments, the first contact etch stop layer 30 and the second contact etch stop layer 44 (e.g., nitride etch stop layers) can slow the etching progress above the respective underlying layers, based on the etch selectivity of each layer. In some embodiments, as shown in Fig. As shown in Figure 1J, the second contact openings 68B can extend over a partial distance into the second contact etch stop layer 44, while the etching of the first contact openings 68A continues down to the first contact etch stop layer 30 as soon as the upper surface of the first contact etch stop layer 30 is exposed, or alternatively, etching through a section of the first contact etch stop layer 30.

[0036] As in Fig. As shown in 1K, after the first contact etching has been carried out, a second contact etching can be performed using a different etching chemistry than that shown in Fig. The first contact etching shown in Figure 1J is performed to selectively etch the first contact etch stop layer 30 and the second contact etch stop layer 44. The etched structures (e.g., the composition and thickness of the different layers in the IC structure 10) and the chemistry and etching parameters of the second contact etching can be selected and adjusted such that the etching exposes all target structures, i.e., the remaining section of the TFR film layer 42 and the silicide contact pads 20 of the storage elements 12A, 12B, simultaneously or nearly simultaneously.

[0037] As in Fig. As shown in Figure 1L, the mask 64 can be removed and the conductive contacts 70A and 70B can be formed by depositing a conductive material (e.g., tungsten or other metal) in the etched contact openings (e.g., grooves or vias). A CMP can then be performed to planarize the top surface of the IC structure 10. As shown, the conductive contacts 70A can land on or otherwise contact the silicide contact pads 20 of the memory elements 12A, 12B, while the conductive TFR contacts 70B can land on them or otherwise contact corresponding locations of the TFR film layer 42. The formation of two conductive TFR contacts 70B in conductive contact with the TFR film layer 42 at predetermined locations defines a TFR 80. A metal layer can then be deposited over the Fig. The structure shown in 1L is formed to create metal contacts to the conductive contacts 70A and to the conductive TFR contacts 70B.

[0038] The disclosed process can enable any metal compound flow common to semiconductors, e.g., AlCu, AlSiCu, or Cu trenches. Furthermore, the TFR formation process can be integrated at various points in the fabrication process to form a TFR 80 at any depth within the IC structure 10, e.g., in, above, or below any dielectric layer in the IC structure 10. The in Fig. 1A to Fig. 1L illustrated exemplary process illustrates the formation of a TFR 80 between the first and the second dielectric layer 32 and 54.

[0039] Fig. Figure 2 shows a further exemplary embodiment of the present invention, in which a TFR 80A is formed further down in the exemplary IC structure 10A, in particular directly on the first contact etch stop layer 30 and under the first dielectric layer 32. TFR 80A can be formed by the Fig. 1C to Fig. The steps shown in 1F are carried out after the first contact etch stop layer 30 has been formed and before the first dielectric layer 32 is deposited, and otherwise as shown in Fig. 1G to Fig. Following the process shown in 1L, adapted to the increased depth of TFR 80A.

[0040] Fig. Figure 3 shows a further exemplary embodiment of the present invention, in which a TFR 80B is further developed in the exemplary IC structure 10B, in particular between the second dielectric layer 54 and a third dielectric layer 60. TFR 10B can be formed by carrying out the steps described in Fig. 1C to Fig. 1F are shown after the deposition of the second dielectric layer 54, and otherwise as shown in Fig. 1G to Fig. Following the process shown in 1L, which is set to the reduced depth of TFR 80B.

[0041] Thus, a TFR can be formed at any layer or depth in an IC structure according to the teachings disclosed herein.

[0042] As mentioned above, the second contact etch stop layer 44 formed over the TFR film 42 can be tailored to the relevant process or integration requirements. Both the first contact etch stop layer 30 and the second contact etch stop layer 44 can be formed from any suitable material or materials, including, for example, (a) SiN, (b) Si3N4, (c) SiON, (d) any other form of Si x O y N z , where each of x, y and z can be 0, 1, 2, 3, 4 or any other value, (e) any other dielectric nitride layer, (f) SiO2, (g) SiO x, where x<2, (h) SiC, or (i) any other material suitable for providing an etch-stop function. In some embodiments, the second contact etch-stop layer 44 has the same composition as the first contact etch-stop layer 30. For example, in some embodiments, both the first and second contact etch-stop layers 30 and 44 may contain SiN. In other embodiments, the second contact etch-stop layer 44 may have a different composition than the first contact etch-stop layer 30. For example, the first contact etch-stop layer 30 or the second contact etch-stop layer 44 may contain SiN, while the other may contain SiC or SiON.

[0043] If both the first contact etch stop layer 30 and the second contact etch stop layer 44 are formed from the same material, they have the same etch rate relative to the contact etch chemistry and would therefore also exhibit the same etch rate selectivity with respect to all dielectric layers in the IC structure 10 (e.g., dielectric layers 32, 54, and 60). Thus, the thickness of the second contact etch stop layer 44 can be selected based on the depth of the TFR 80 / 80A / 80B in the IC structure 10 and the etch selectivity between the second contact etch stop layer 44 and the dielectric layers (e.g., layers 32, 54, 60), so that the thickness of the second contact etch stop layer 44 can be determined after etching the dielectric layers (e.g., after the process described in Figure 10). Fig. 1J (shown and discussed above) is equal to or approximately equal to (e.g., within 25%) the thickness of the first contact etch stop layer 30. Thus, the second etch will remove each of the first contact etch stop layers 30 and the second contact etch stop layer 44, exposing the underlying structures (silicide contact pads 20 and TFR film layer 42) simultaneously or approximately simultaneously.

[0044] In such embodiments, i.e., where the first contact etch stop layer 30 and the second contact etch stop layer 44 are formed from the same material and wherein the second contact etch stop layer 44 is formed by the in Fig.Since the first etching shown in Figure 1J is partially reduced, the second contact etch stop layer 44 can be formed with a greater thickness than the first contact etch stop layer 30, such that the thickness of the partially reduced second contact etch stop layer 44 corresponds to that of the first contact etch stop layer 30. In some embodiments, the formed thickness of the second contact etch stop layer 44 can be 10–100% of the first contact etch stop layer 30. In certain embodiments, the formed thickness of the second contact etch stop layer 44 can be 30–100% greater than that of the first contact etch stop layer 30.

[0045] In other embodiments, the first contact etch stop layer 30 and the second contact etch stop layer 44 can have different compositions and thus different etch rates and / or selectivities. For example, the first contact etch stop layer 30 or the second contact etch stop layer 44 can contain SiN, while the other can contain SiC or SiON. In such embodiments, the thickness of the second contact etch stop layer 44 can be selected to allow simultaneous removal of the first contact etch stop layer 30 and the second contact etch stop layer 44. This flexibility enables a single contact mask and etch integration. It also allows the TFR to be formed at different depths in the IC structure.

Claims

[1] Method for forming an integrated circuit (IC) structure incorporating a thin-film resistor (TFR), wherein the method comprises: Forming at least one memory cell element (12A, 12B) over a semiconductor substrate (14), wherein the at least one memory cell element (12A, 12B) has at least one memory cell element contact area (20); Forming a first contact etch stop layer (30) over the at least one memory cell element (12A, 12B); Forming a TFR layer stack (40, 42, 44) in a pre-metal dielectric region (32) above the first contact etch stop layer (30) and laterally offset from the at least one memory cell element contact region, wherein the formation of the TFR layer stack (40, 42, 44) in a pre-metal dielectric region (32) comprises: Forming a TFR film layer (42), and Forming a second contact etch stop layer (44) over the TFR film layer (42); Annealing the TFR film layer (42) to match a value of the temperature coefficient of resistance, TCR, of the TFR film layer; Forming a structured mask (64) with at least one first mask opening (68A) aligned over the at least one IC element contact area ((20) and at least one second mask opening (68B) aligned over the TFR layer stack (40, 42, 44); Performing at least one etch through the first and second mask openings (68A, 68B) and through sections of the IC structure, including through both the first contact etch stop layer (30) and the second contact etch stop layer (44), to simultaneously (a) form at least one first contact opening (68A) that exposes the at least one contact area (20) of the memory cell element (12A, 12B) and (b) form at least one second contact opening (68B) that exposes the TFR film layer (42); and Filling the at least one first contact opening (68A) and the at least one second contact opening (68B) with conductive material to form at least one conductive contact (70A) to the at least one memory cell element (12A, 12B) and at least one conductive contact (70B) to the TFR film layer (42). [2] Method according to claim 1, wherein: the formation of the TFR layer stack (40, 42, 44) in the pre-metal dielectric region includes the deposition of a dielectric layer (32) over the at least one memory cell element (12A, 12B) and over the first contact etch stop layer (30); and the TFR layer stack (40, 42, 44) is formed over the deposited dielectric layer (32). [3] Method according to claim 1, wherein: the formation of the TFR layer stack (40, 42, 44) in the pre-metal dielectric region includes the deposition of several dielectric layers (32, 54) over the at least one memory cell element (12A, 12B) and over the first contact etch stop layer (30); and the TFR layer stack (40, 42, 44) is formed over the several dielectric layers (32). [4] Method according to any one of claims 1 to 3, wherein the formation of the TFR layer stack (40, 42, 44) in the pre-metal dielectric region comprises the deposition of at least one dielectric layer (54) over the TFR layer stack (40, 42, 44). [5] Method according to any one of claims 1 to 4, wherein the formation of the TFR layer stack (40, 42, 44) takes place directly on the first contact etch stop layer (30). [6] Method according to any one of claims 1 to 5, wherein the first contact etch stop layer (30) and the second contact etch stop layer (44) are formed from the same material. [7] Method according to any one of claims 1 to 6, wherein the first contact etch stop layer (30) and the second contact etch stop layer (44) are each formed from SiN or another dielectric nitride. [8] Method according to any one of claims 1 to 7, wherein the second contact etch stop layer (44) has a greater thickness than the first contact etch stop layer (30). [9] Method according to any one of claims 1 to 8, comprising performing at least one etching to simultaneously form (a) at least one first contact opening (68A) that exposes the contact area of ​​the memory cell element (12A, 12B), and (b) at least one second contact opening (68B) that exposes the TFR film layer (42): Performing a first etching that exposes the first contact etch stop layer (30) and the second contact etch stop layer (44); and Performing a second etch extending through the first contact etch stop layer (30) and the second contact etch stop layer (44) to expose the at least one memory cell element contact area (20) and the TFR film layer (42). [10] Method according to any one of claims 1 to 9, wherein forming the TFR layer stack (40, 42, 44) further comprises: Forming a TFR etch stop layer (40), wherein the formation of the TFR film layer (42) takes place over the formed TFR etch stop layer (40). [11] Integrated circuit (IC) structure which features: at least one memory cell element (12A, 12B) arranged over a semiconductor substrate (14), wherein the at least one memory cell element (12A, 12B) has at least one memory cell element contact area (20); a first contact etch stop layer (30) at least partially over the at least one memory cell element (12A, 12B); and a thin-film resistive (TFR) layer stack (40, 42, 44) in a pre-metal dielectric region (32) above the first contact etch stop layer (30) and laterally offset from the at least one memory cell element contact region (20), wherein the TFR layer stack (40, 42, 44) comprises: a tempered TFR film layer (42), wherein the temperature coefficient of resistance, TCR, of the TFR film layer is matched by tempering the TFR film layer (42); and a second contact etch stop layer (44) over the TFR film layer (42); wherein a first lateral edge of the second contact etch stop layer (44) coincides laterally with a first lateral edge of the TFR film layer (42) under the second contact etch stop layer (44). [12] IC structure according to claim 11, wherein the first side edge of the second contact etch stop layer (44) and the first side edge of the TFR film layer (42) are etch-defined side edges. [13] IC structure according to one of claims 11 to 12, wherein a second lateral edge of the second contact etch stop layer (44) coincides laterally with a second lateral edge of the TFR film layer (42). [14] IC structure according to one of claims 11 to 13, further comprising: at least one conductive contact (70B) extending to the TFR film layer (42), thereby defining a TFR in the IC structure; and at least one conductive contact (70A) that is offset laterally from the TFR and extends downwards to the at least one memory cell element (12A, 12B). [15] IC structure according to one of claims 11 to 14, further comprising at least one dielectric layer (32) above the first contact etch stop layer (30) and below the TFR layer stack (40, 42, 44). [16] IC structure according to one of claims 11 to 15, wherein the TFR layer stack (40, 42, 44) further comprises a TFR etch stop layer (40) below the TFR film layer (42). [17] IC structure according to claim 16, wherein a first lateral edge of the TFR etch stop layer (40) coincides laterally with the first lateral edge of the TFR film layer (42) and the first lateral edge of the second contact etch stop layer (44). [18] Integrated circuit (IC) structure which features: at least one memory cell element (12A, 12B) arranged over a semiconductor substrate (14), wherein the at least one memory cell element (12A, 12B) has at least one memory cell element contact area (20); a first contact etch stop layer (30) at least partially over the at least one memory cell element (12A, 12B); and a thin-film resistive (TFR) layer stack (40, 42, 44) formed by one of the methods of claims 1 to 10.

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