Fault-tolerant storage array and method for performing error correction in a storage array

Abstract

A method for providing error correction for a memory array (10), comprising: for each data word stored in a data storage section (12) of the memory array (10) that has at least one bit error, storing, in an error programmable read-only memory (PROM) (24), an error entry associated with an address of the data word in the data storage section (12) and including error data identifying a bit position of each bit error and correct bit data for each bit error, wherein storing includes programming into a programmable logic device a unique term that is a Boolean combination of the address of the data word in the data storage section (12) and a number of the bit error; monitoring memory addresses presented to the data storage section (12); when a memory address presented to the data storage section (12) is associated with a respective error entry in the error PROM (24), reading, from the error PROM (24), the bit position of each bit error and the correct bit data for each bit error and Substituting the correct bit data into each identified bit position of a memory read circuit arranged to read data from the data storage section (12).

Description

FIELD OF THE INVENTION

[0001] The present invention relates to programmable memory arrays. More specifically, the present invention relates to fault-tolerant programmable memory arrays. BACKGROUND

[0002] Small geometries currently limit the maximum voltage applied to metal. The metal line size cannot shrink unless the applied voltage also shrinks. This fact will ultimately eliminate electron storage as a viable technology. In fact, one manufacturer of a leading-edge magnetic pole storage technology has concluded that this technology will not scale below 28 nm.

[0003] It appears that future non-volatile memories (NVMs) will employ programming and erasing mechanisms based on a material structural change, such as phase-change memory (PCM) or resistive random access memory (ReRAM). Such a material structural change is based on the movement of atoms through a solid material.

[0004] Because this program and erase mechanism introduces fatigue and wear into the solid-state material, the error generation rate is likely to multiply. Memory designers must plan accordingly to account for the increased error generation rate.

[0005] Enterprise mass data storage already incorporates error correction. However, the solutions deployed utilize large volumes of spare storage and millisecond timeframes.

[0006] The memory of an integrated circuit has a limited range and timeframe of only microseconds to perform error correction, so error correction must be fast and use memory efficiently to enable manufacturing of NVMs with a low failure rate at low cost.

[0007] The document K Ithoh, VLSI Memory Chip Design, Springer Berlin Heidelberg, 2001, Chapter 3.9 Redundancy, pp.178-194 discloses a VLSI memory chip design.

[0008] The document US 3 588 830 A discloses a system for using mass-produced memories.

[0009] Document EP 0 136 443 B1 discloses a memory correction scheme using reserve arrays.

[0010] The document US 2016 / 0 196 179 A1 discloses a reconfigurable ECC for memory.

[0011] The document US 2009 / 0271 668 A1 discloses a method, an apparatus and a program product that identifies error events using error correction codes. SUMMARY

[0012] The invention is defined in the independent claims. The dependent claims define embodiments of the invention.

[0013] According to one aspect of the invention, a method for providing error correction for a memory array includes, for each data word stored in a user memory section of the memory array that has at least one bit error, storing in an error PROM an error entry associated with an address of the data word in the data memory section and including error data identifying a bit position of each bit error and correct bit data for each bit error, monitoring memory addresses presented to the user memory section when a memory address presented to the user memory section is the address of the data word in the data memory section, reading from the error PROM the bit position of each bit error and the correct bit data for each bit error, and substituting the correct bit data into each identified bit position of a memory read circuit,which is arranged to read data from the user memory section.,

[0014] According to one aspect of the invention, storing in the error PROM the error entry, including the bit position of each bit error, and the correct bit data for each bit error includes programming into a programmable logic device a unique term that is a Boolean combination of the address of the data word in the user memory section and the number of the bit error.

[0015] According to one aspect of the invention, the bit error number is defined by an output state of a counter that forms a portion of the unique term that is the Boolean combination.

[0016] According to one aspect of the invention, each bit error in the data word is accessed sequentially by incrementing the counter to provide a different unique term, and the counter is incremented until the unique term, which is a Boolean combination of the memory address of the data word and the output state of the counter, does not define an error entry.

[0017] According to one aspect of the invention, each error entry for a bit error at a memory address includes a next failure flag bit, the next failure flag bit for the most recently stored error entry for the memory address being in a first state and the next failure flag bit for all other stored error entries for the memory address being in a second state opposite to the first state, and the counter is no longer incremented when its initial state is associated with a unique term defining the number of the most recently entered bit error.

[0018] According to one aspect of the invention, reading from the error PROM the bit position of each bit error includes reading the bit position of each bit error from a memory in the error PROM, and reading from the memory in the error PROM the correct bit data for each bit error includes reading the correct bit data for each bit error from the memory in the error PROM.

[0019] According to one aspect of the invention, reading from the error PROM the correct bit data for each bit error includes reading multiple copies of the correct bit data for each bit error from the memory in the error PROM and determining a correct data value from the read multiple copies of the correct bit data.

[0020] According to one aspect of the invention, a method for providing error correction for a memory array includes supplying, to the memory array, a memory address identifying a data word to be read from the memory array, simultaneously supplying the memory address to an error PROM containing only data representing memory addresses identifying a data word of the memory array having erroneous data in at least one bit position, if the memory address supplied to the error PROM identifies the data word having erroneous data in the at least one bit position, outputting, from the error PROM, corrected data and information identifying the bit position of the erroneous data in the data word,reading the data word from the memory array into a memory reading circuit and replacing the corrected data from the error PROM into the identified bit position of the memory reading circuit.

[0021] According to one aspect of the invention, outputting corrected data from the error PROM includes outputting N copies of the corrected data and selecting, from the N copies, a single corrected data bit.

[0022] According to one aspect of the invention, an error-correcting memory array includes a user memory section containing memory data words, a sense amplifier section coupled to the user memory section, an address bus coupled to the user memory section, an error PROM coupled to the address bus, a user memory section error correction code (ECC) section operatively coupled to the user memory section, a controller coupled to the address bus, the controller configured to assert an address on the address bus to read a data word from the user memory section into the sense amplifier section, write a user memory section error entry to the error PROM in response to a signal from the user memory section error correction code (ECC) section,wherein the user memory section error entry identifies a data word stored in the user memory section that has at least one data bit error, the bit position in the word of the data bit error, and a corrected data value for the data bit error. The error PROM is responsive to addresses being asserted on the address bus and having error entries to read the correct data value for the data bit error and generate a correction signal to the sense amplifier section to replace the read correct data value for the data bit error at the identified bit position in the data word at the address having error entries.

[0023] According to one aspect of the invention, the error correcting memory array further includes an error PROM error correction code (ECC) portion operatively coupled to the error PROM, and the controller is further configured to respond to a signal from the error PROM error correction code (ECC) portion, the signal from the error PROM error correction code (ECC) portion identifying a data error entry stored in the error PROM memory that has at least one error, the response including writing a corrected PROM data error entry to the error PROM memory and disabling the identified user memory portion error entry stored in the error PROM memory.

[0024] According to one aspect of the invention, disabling the identified user memory section error entry stored in the error PROM memory includes programming an additional bit at the data entry error address.

[0025] According to one aspect of the invention, substituting the read correct data value for the data bit error at the identified bit position in the data word includes overwriting erroneous data initially written to the sense amplifier at the identified bit position in the data word.

[0026] According to one aspect of the invention, substituting the read correct data value for the data bit error at the identified bit position in the data word includes substituting the read correct data for erroneous data read from the user memory portion.

[0027] According to one aspect of the invention, the controller is further configured to increment a counter to locate multiple error entries for storing correct data values for multiple bit errors in a single data word stored in the user memory portion.

[0028] According to one aspect of the invention, the controller is further configured to stop incrementing the counter when the counter is incremented to a count state that does not locate an error entry in the error PROM memory.

[0029] According to one aspect of the invention, the counter reaches a state that locates the most recently entered error entry for the data word in the error PROM memory. BRIEF DESCRIPTION OF THE DRAWING FIGURES

[0030] The invention will be explained in more detail below with reference to embodiments and the drawing, in which: Fig. 1 is a block diagram showing an illustrative memory array with error correction according to one aspect of the present invention; Fig. 2 is a block diagram showing an illustrative configuration for an error correction PROM according to one aspect of the present invention; Fig. 3 is a diagram showing an illustrative configuration for an error PROM read decoder section of an error correction PROM according to one aspect of the present invention; Fig. Figure 4 is a diagram showing an illustrative circuit used to bias and program the error PROM read decoder section of Fig. 3 can be used; Fig. 5 is a schematic diagram of an illustrative data correctable sense amplifier that may be used as a memory read circuit in an error correcting data PROM according to one aspect of the present invention; Fig. 6 is a flowchart illustrating an example of a method for performing error correction in a memory array according to one aspect of the present invention; Fig. 7 is a flowchart illustrating another example of a method for performing error correction in a memory array according to an aspect of the present invention, which is a variation of the method described in Fig. 6 shown procedure; Fig. 8 is a flowchart illustrating an example of a method for setting a next failure flag at a location in a memory for address data of a faulty bit of a faulty PROM according to one aspect of the invention; Fig. 9 is a flowchart illustrating another example of a method for setting a next failure flag at a location in a memory for address data of a faulty bit of a faulty PROM according to an aspect of the invention; and Fig. 10A, Fig. 10B, Fig. 11A and Fig. 11B are flowcharts showing illustrative methods for writing new data to a selected memory address in the memory array according to one aspect of the invention. DETAILED DESCRIPTION

[0031] Those skilled in the art will recognize that the following description is illustrative only and not restrictive in any way. Other embodiments will readily occur to those skilled in the art.

[0032] Firstly, referring to Fig. Figure 1 shows a block diagram of an illustrative memory array 10 with error correction according to one aspect of the invention. Data is stored in a user memory section 12 of the memory array 10. An error correction (ECC) section 14 performs error correction on data read from the user memory section 12 before it is presented to the sense amplifiers 16. Memory operations are controlled by a controller 18 via an address bus 20. The address bus 20 also includes control lines for read and write operations (not explicitly shown). The ECC section 14 communicates with the controller 18 via bus 22.

[0033] According to one aspect of the present invention, an error programmable read-only memory (PROM) 24 is provided, which also communicates with the controller 18 to receive addresses via the address bus 20. An error correction (ECC) section 26, associated with the error PROM 24, performs error correction on data read from the error PROM 24 before it is presented to the sense amplifiers 16 via a bus 28. As described further below, the output from the error PROM 24 corrects bit errors in user data presented from the user memory section 12 to the sense amplifiers 16 by substituting corrected bit values before the sense amplifiers 16 output the addressed data from the user memory section 12. One of ordinary skill in the art will recognize that the sense amplifiers 16 could also be latches into which the user data from the user memory section 12 is transferred after being read.

[0034] Now referring to Fig. Figure 2 shows a block diagram of an illustrative configuration for the error PROM 24 of Fig. 1 according to one aspect of the present invention. In the Fig. 2, the error PROM 24 includes an error PROM read decoder section 30, a corrected data output section 32, and an error PROM write section 34.

[0035] The error PROM read decoder section 30 functions as a programmable decoder and is provided simultaneously on the address bus 20, with the same address being provided to the user memory section 12 of the memory array 10 when data is to be read from the user memory section 12. It further includes a counter 42, as disclosed herein. Each individual bit error identified is programmably decoded as an error entry, which is a combination of an address on the address bus 20 and the contents of the counter. As disclosed herein, the use of the counter allows multiple bit errors in a single word to each be programmed as a single bit error.

[0036] For each identified bit error, a faulty bit address data memory 36 of the corrected data output section 32 of the error PROM 24 stores data identifying both the bit column location of the error and the correct data for replacing the faulty bit values. The operation of the error PROM read decoder section 30 will be described with reference to Fig. 3 discussed in detail.

[0037] The programmable decoder of the error PROM read decoder section 30 is programmed to respond to a combination of the address on the address bus 20 and the state of a counter 42, as shown in Fig. 3. If the combination does not correspond to an error entry programmed into the error PROM read decoder section 30, the error PROM 24 performs no action. If the combination of the address on address bus 20 and the state of counter 42 corresponds to an error entry programmed into the error PROM read decoder section 30, the error PROM read decoder section 30 sets the error bit flag on line 54 active, which is supplied to the controller 18 via bus 22 (connection not shown). The error bit flag signal on line 54 may be provided in a variety of ways, examples of which are disclosed herein.

[0038] Each location in the faulty bit address data memory 36 represents an error entry and is programmed with data including the bit position of the error in a word read from the data memory 12 and corrected data to replace the faulty data. The locations in the data memory are preferably programmed in the order in which the errors occur.

[0039] The faulty bit address data memory 36 in the corrected data output section 32 drives a faulty bit column position decoder 38 and a corrected data determiner 48. If the combination of the address on address bus 20 and the state of counter 42 corresponds to an error entry in a faulty bit address data memory 36, the output from the faulty bit column position decoder 38 identifies the bit position in the data word of the bit at the address to be corrected, and the corrected data determiner 48 outputs the correct data.

[0040] The defective bit column position decoder 38 is a one-of-m decoder. It receives an m-bit output on lines 40 from the defective bit address data memory 36, which identifies the column location of the particular bit having the defective bit value and decodes it onto one of the lines 440 through 44n corresponding to the column location of the particular bit having the defective value. This signal on the one of the lines 440 through 44n of the defective bit column position decoder 38 is used to generate a decoded write error data strobe in the sense amplifiers, as described with reference to Fig. 5. The faulty bit address data memory 36 stores N different copies of the correct value for the faulty bit, where N ≥ 1, and outputs them on lines 46. The number of copies N can be selected to provide a desired degree of redundancy because the spare bits are stored using the same storage mechanism used for the memory cells in the user memory section 12 and are thus subject to the same error mechanisms as the cells of the user memory section 12. The use of N copies of the correct data value makes it possible to employ voting schemes, as known in the art, to enable correction even if one or more of the stored corrected data values stored in the faulty bit address data memory 36 become erroneous.In an exemplary embodiment, a corrected data determiner 48 receives the N copies of the correct data value output on lines 46 and uses a voting scheme to determine the correct data value and outputs the correct data value at the corrected data bit output 50. The use of N copies of the correct data value and the corrected data determiner 48 is not required, and in some embodiments, the erroneous bit address data memory 36 may output a single corrected value. Those skilled in the art will appreciate that using the erroneous bit column position decoder 38 saves storage space within the erroneous bit address data memory 36; however, in other embodiments, the decoded actual bit position is stored within the erroneous bit address data memory 36, which outputs lines 440-44n.The memory for address data of a faulty bit 36 does not need to store N identical copies of the correct data value. In one embodiment, the correct data value is stored in certain predetermined cells, and the complement of the correct data value is stored in other predetermined cells.

[0041] Reference numeral 52 identifies a next bit clock, the operation of which is described herein. Next bit clock 52 is used to increment counter 42 to provide the partial address that identifies the positions of one or more faulty bits in a word at a memory address on address bus 20 that has been identified as having one or more faulty bits. Use of counter 42 allows separate entries to be programmed into error PROM read decoder section 30 for each bit error of a data word stored at a single address on address bus 20. Each entry in error PROM read decoder section 30 addresses a unique address line in faulty bit address data memory 36. Reference numeral 54 identifies an output that signals the decoding of an error entry associated with a faulty bit.These inputs and outputs are referred to . Fig. 3 discussed.

[0042] The error PROM write section 34 receives instructions and data from the controller 18 from Fig. 1 via bus 22. The controller 18 communicates with the ECC section 14, which performs error correction on data read from the user memory section 12. Bit errors identified by the ECC section 14 are communicated to the controller 18. The controller 18 then transmits the location of the identified bit error, including its memory address, the bit column location within the memory word at that address, and the correct value for the erroneous bit, to the Error PROM Write section 34. As explained above, multiple copies of the correct value for the bit are preferably stored to provide error correction for the correct values for the erroneous bit. The Error PROM Write section 34 programs an error entry into the Error PROM Read Decoder section 30 (connection not shown).The error entry includes the address on address bus 20 containing the error and a bit count indicator (the count state output of counter 42) to indicate the current bit error number. The error PROM write section 34 further programs an m-bit data entry identifying the column location of the particular bit containing the erroneous bit value and N copies of the correct value for the bit into the erroneous bit address data store 36 into the associated address line, which is decoded by the error PROM read decoder section 30.

[0043] Once the bit position and the correct bit data have been programmed into the memory for address data of an erroneous bit 36 in the corrected data output section 32 and the address and the bit count indicator have been programmed into the error PROM decoder section 30, the error is corrected by the error PROM 24 the next time the error entry is decoded in the error PROM read decoder section 30. The handling of the memory for address data of an erroneous bit 36 in the corrected data output section 32 of the error correction PROM 24 will be described with reference to Fig. 3. The defective bit column position decoder 38 provides the column location of the bit being corrected, and the defective bit address data memory 36 provides the correct data value for replacement in the particular bit position in the sense amplifiers 16. As disclosed herein, the use of the counter 42 enables each individual fail bit in a word read from the user memory section 12 to be identified as a separate error entry and corrected using a replacement bit provided from the error PROM 24.

[0044] The error correcting memory array 10 of the present invention also monitors the output of the error PROM 24 and corrects errors generated by faulty memory locations in the error PROM read decoder section 30 in the error PROM 24. The Fig. The ECC 26 associated with the error PROM 24 shown in Figure 1 monitors the m-bit data on lines 40 and the N bits of corrected data on lines 46 from the faulty bit address data memory 36 and optional ECC information that may be stored together with the m-bit data on lines 40 and the N bits of corrected data in the faulty bit address data memory 36. The ECC 26 associated with the error PROM 24 communicates with the controller 18 of Fig. 1 when an error is detected. Errors identified and thereby corrected by the ECC section 26 are communicated to the controller 18. The controller 18 then instructs the error PROM write section 34 to deactivate the error entry that returned the erroneous data and substitute another address in the erroneous bit address data memory 36 for the address that returned the data containing an error, and provides the corrected data bits recovered by the ECC section 26 to be stored in the erroneous bit address data memory 36 associated with the newly replaced address. The error PROM read decoder section 30 is further reprogrammed by the error PROM write section 34 in response to the controller 18 to point to the newly replaced address.

[0045] The error-correcting memory array 10 operates by reading a data word from the user memory section 12 and latching it into the sense amplifiers 16. Simultaneously, correction data for known bit read errors stored in the error PROM 24 for the word being accessed in the user memory section 12 is accessed and written to the sense amplifiers 16.

[0046] An ECC check is performed by the ECC 14 on the data word in the sense amplifiers 16, which may contain the replaced corrected data bits from the error PROM 24. If the ECC 14 identifies a new error, a new error entry is written to the error PROM read decoder section 30 in the error PROM 24, and the m-bit position data and the N copies of a correct bit value generated by the ECC 14 are written by the error PROM write section 34 into the faulty bit address data memory 36. The error PROM read decoder section 30 is further programmed by the error PROM write section 34 in response to the controller 18 to point to the new error entry when the address appears on the address bus 20 and the counter 42 points to the current error number at that address.As previously mentioned, when the ECC 26 associated with the fault PROM 24 identifies a fault, the fault address location and corrected data generated by the ECC 26 are written to a new location in the fault PROM read decoder section 30 in the fault PROM 24, and the faulty word line location in the fault PROM 24 is disabled by reprogramming the fault PROM read decoder section 30 to point to the new location in the fault PROM read decoder section 30 when the address and counter have reached the current state as disclosed herein. This prevents the word line with the identified fault from being selected at any time. In some embodiments, a ReRAM element 78 is erased to prevent the word line with the identified fault from being selected at any time.

[0047] Now referring to Fig. 3 is a diagram showing an illustrative configuration for an error PROM read decoder section 30 of an error PROM 24 such as that of Fig. 2 according to one aspect of the present invention. The Fig. The particular solution shown in Figure 3 is implemented using a programmable decoder, such as a PLD-like addressing architecture, although it is understood that other addressing architectures may be used without exceeding the scope of protection.

[0048] The address bus 20, which is used to provide memory addresses to the user memory section 12, is also used to provide addresses to the error PROM read decoder section 30, which determines whether errors have previously been identified in the data contained in the address on the address bus 20. Individual address bits from the address bus 20 are provided to the buffers 56-0, 56-1, 56-2, and 56-3. One of ordinary skill in the art will recognize that although four address bits in Fig. 3, the number of an address bit used is equal to the number of address bits provided on the address bus 20.

[0049] Buffers 56-0, 56-1, 56-2, and 56-3 each have complementary inverting and non-inverting outputs, shown collectively at reference numeral 58. A plurality of lines 601 through 60n are shown intersecting the complementary inverting and non-inverting output lines 58 of buffers 56-0, 56-1, 56-2, and 56-3 and serve as output terms for Boolean logic implemented in the error PROM read decoder section 30. Each of lines 601 through 60n can be programmed to represent an address and error number at the represented address at which a data error was found, as disclosed herein. One of ordinary skill in the art will recognize that the number of lines n is a number that represents a maximum number of distinct addresses that have erroneous data bits that the designer specifies can be corrected. In larger memory arrays 10, the number n can be in the thousands.

[0050] According to one aspect of the present invention, the addresses of memory cells in the user memory section 12 having fail bits are efficiently written into the fail PROM read decoder section 30 of the fail PROM 24 in the order of failure occurrence using binary addresses that are mask-programmed to correspond to one of the lines 601 through 60n, with address 0 corresponding to line 601, and incremented for each new entry. The mask-programmed addresses are provided by binary decoder and write logic 62 in the fail PROM write section 34.Those of ordinary skill in the art will recognize that the binary decoder in the binary decoder and write circuitry 62 is organized as a binary-to-one-of-n-line decoder, which is well known to those of ordinary skill in the art, wherein 2(n-1) binary inputs (provided by the bus 22) are decoded to enable one of n output lines (in . Fig. 2 and Fig. 3 as lines 601 through 60n. The write circuitry in the binary decoder and write circuitry 62 may be any circuitry for programming the non-volatile memory elements in the error PROM 24, which are depicted as ReRAM elements in the illustrative embodiments disclosed herein. Details and operation of such programming circuitry are well known to those of ordinary skill in the art and are not discussed herein to avoid obscuring the disclosure and obscuring the details of the present invention.

[0051] The counter 42 has a next bit clock input 52 (previously referring to Fig. 2), a reset input 64, and a set of complementary outputs, collectively identified at reference numeral 66. Each counter state represents an error number at the address and is decoded to represent an error bit position in a data word stored in the user memory section 12 by an error bit address data store 36. As an example, in a memory organized as 32-bit words, the counter 42 is a 5-bit counter whose complementary outputs are decoded into a one-of-32 selection, as is known in the art. The counter state does not represent the actual bit location in the word, but rather whether this is the 1st, 2nd, or nth bit error to be corrected at that address; that is, each bit error is identified by an error number in the order in which the error was detected.Logical connections are programmed between the complementary outputs 66 of counter 42 and lines 601 through 60n to allow each of lines 601 through 60n to represent a bit error number of erroneous data at that address. Counter 42 is reset on line 64 each time a new address is asserted on address bus 20. Lines 601 through 60n can be individually programmed so that each line uniquely decodes an error identified by an address on address bus 20 and a count state of counter 42, thereby allowing more than one bit error in a data word read from data memory 12 to be corrected, as disclosed herein.

[0052] Each of the lines 601 through 60n is shown buffered by a buffer 68 and represented as address lines into the faulty address data memory 36. Since each of the lines 601 through 60n, when programmed as disclosed herein, responds to a single bit error defined by a unique combination of an address on the address bus 20 and a count state of the counter 42, only one of the lines 601 through 60n responds to a combination of an address on the address bus 20 and a status of the counter 24 previously identified as a single bit error, with the outputs of the buffers 68 thus forming decoded word line addresses into the faulty bit address data memory 36.

[0053] If an address represented on the address bus 20 includes one or more bit errors, an error bit flag 54 indicates the presence of the error. There are several ways to implement the bit flag 54. In a Fig. 3, the buffered lines 601 to 60n are presented to an OR gate 70. The output of the OR gate 70 at line 54 (previously referred to Fig. 2 identified) indicates whether or not there are known bad bits presented on the one of the lines 60-X that uniquely decoded a combination of the address on the address bus 20 and the counter state of the counter 42.

[0054] In another embodiment of the invention, which is described in Fig. 2, the OR gate 70 is shown in dashed lines, and its inputs can be driven by the bit column address lines 440 through 44m. In this configuration, the output of the OR gate 70 only goes to a high logic level when one of the bit column address lines 440 through 44m goes high to indicate the bit position of an error programmed into the faulty bit address data memory 36. In this embodiment of the invention, the OR gate 70 requires only m inputs, corresponding to the number of bit column address lines output by the decoder for a faulty bit column position, rather than a number of inputs equal to the number of word lines 601 through 60n in the fault PROM read decoder section 30 of the fault PROM 24.In embodiments of the invention that provide correction of a large number of single bit errors, the number of inputs to the OR gate 70 shown in . Fig. 3, large, and locating the OR gate 70, as shown in Fig. 2, saves die area and wiring area on the integrated circuit.

[0055] In another embodiment of the invention, which is also described in Fig. As shown in Figure 2, a column in the faulty bit address data memory 36 is used as the fault bit flag and is programmed to a logic high state, producing a logic high at the dashed line output of the faulty bit address data memory 36 (which becomes the fault bit flag 54) when any address is selected through lines 60- through 60-5. This scheme completely eliminates the OR gate 70, thereby saving die space on the integrated circuit.

[0056] According to one aspect of the present invention, before faulty addresses found in the user memory section 12 are programmed into the fault PROM read decoder section 30, all lines 601 through 60n are weakly held at a logic low level. Referring now to Fig. Figure 4 is a diagram showing an illustrative circuit used to bias lines 601 through 60n and program the error PROM read decoder section 30 of Fig. 3 can be used.

[0057] Fig. Figure 4 shows a representative line 60-X. Before information is programmed into the error PROM read decoder section 30, the n-channel transistor 72, which has a voltage threshold lower than the other transistors connected to the line 60-X, has a subthreshold leakage current to maintain the line 60-X at a low logic level. The p-channel transistor 74 is connected to the line 60-X as a pull-up device. The p-channel transistor 76 is connected in series with the ReRAM element 78 and an n-channel transistor 80. The gates of the p-channel transistor 76 and the n-channel transistor 80 are connected together. Initially, the ReRAM element 78 is unprogrammed (erased) and remains in a high-impedance state.P-channel transistor 76 has a voltage threshold low enough to have sufficient subthreshold leakage current to pull the gate of p-channel transistor 74 up to VDD to maintain it in an off state. The common gate connection of p-channel transistor 76 and n-channel transistor 80 is connected to an error PROM read line 82 (also shown in FIG. Fig. 2), which is held in a low logic state and activated by controller 18 to read the error PROM read decoder section 30. The N-channel transistor 80 is in an off state, and the p-channel transistor 76 is on. Since the ReRAM element 78 is unprogrammed, raising the voltage on the error PROM read line 82 to turn on the n-channel transistor 80 to read the memory 30 has no effect on the circuit because the subthreshold leakage of the p-channel transistor 76 provides a larger amount of current that can be delivered by the unprogrammed ReRAM element 78.

[0058] Referring again to Fig. 3, before information is programmed into the error PROM read decoder section 30, all lines 60-1 through 60-5 are held low by transistors 74, 76, and 80, as previously described. The inputs to the OR gate 70 buffered by buffers 68 are all in logic low states, and the output on line 54 of the OR gate 70 is in a logic low state.

[0059] When it is desired to assign the line 60-X to a memory address at which a faulty bit has been identified, the error PROM write section 34 programs the ReRAM element 78 identified by the reference to Fig. 4 is coupled to line 60-X, and also programs a combination of the ReRAM elements within programming circuits 84 and 98, i.e., ReRAM elements 86, 92, 100, and 106, each of which will uniquely enable line 60-X to be pulled high in response to an address on address bus 20 in combination with the next available count state of counter 42 (starting at count state 0 for the first error).After the ReRAM element 78 and the combination of programming circuits 84 and 98 have been programmed, each time the error PROM read line 82 is driven to a high logic level by asserting a signal from the controller 18 on the error PROM read line 82 to read the error PROM read decoder section 30, the n-channel transistor 80 is turned on and pulls the gate of the p-channel transistor 74 down to a low logic level due to the low resistance path through the ReRAM element 78.This turns on p-channel transistor 74, which overcomes the weak leakage of n-channel transistor 72 that had been holding line 60-X in a low logic state, and allows line 60-X to be pulled up to a high logic state when driven by a combination of a partial address provided by an address on address bus 20 and a partial address provided by the state of counter 42, which together provide an address to the faulty bit address data store 36, the output of which identifies the bit position in the addressed data word of the faulty bit and the correct data value for the faulty bit.

[0060] When the address from address bus 20 that was programmed into line 60-X to identify a faulty bit is presented to the fault PROM read decoder section 30 on address bus 20, and counter 42 is in the counting state that identifies the fault number of a faulty bit, only the combination of turned-on n-channel transistors (88, 94) (102, 108) and their respective series-connected ReRAM elements (86, 92) (100, 106) on line 60-X does not provide a circuit path to pull line 60-X down to ground because none of the ReRAM elements (86, 92) (100, 106) were programmed in the particular combination. Since one of the inputs to OR gate 70 from line 60-X is now high due to the programmed ReRAM element 78 and the unique combination of programming circuits 84 and 98, its output on line 54 (the error bit flag) changes to a high logic level.All other address and counter state combinations include at least one combination of an on n-channel transistor (88, 94), (100, 106) and its respective series-connected ReRAM element (86, 92), (100, 106) providing a circuit path to pull line 60-X down to ground.

[0061] When the memory address at which a faulty bit was identified by the ECC 14 is reached, the fault PROM write section 34, in response to the controller 18, programs that address into the next available one of lines 601 through 60n. The correct bit is written by the binary decoder and write logic 62 into the respective location in the faulty bit address data memory 36. As previously mentioned, before addresses are programmed into the fault PROM read decoder section 30, all lines 601 through 60n are weakly held at a low logic state by leakage current through the n-channel transistor 72.

[0062] The method for programming any line 60-X to respond to a memory address having a bad data bit is described by further examination of Fig. 3 and Fig. 4. The reference numeral 84 (which represents one of the small squares at all intersections of the lines 601 to 60n and the complementary outputs 58 of the buffers 56-0 to 56-3 in Fig. 3 and the switching logic within the dashed lines 84 of Fig. 4) represents a programmable circuit used to program an address into any of the lines 601 to 60n. In Fig. 4, it can be seen that the circuit logic 84 includes the first ReRAM element 86 in series with an n-channel transistor 88 between the line 60-X and ground. The gate of the n-channel transistor 88 is connected to the non-inverting output 90 of one of the buffers 56-0 to 56-3 in Fig. 3. The second ReRAM element 92 is connected in series with an n-channel transistor 94 between line 60-X and ground. The gate of the n-channel transistor 94 is connected to the inverting output 96 of one of the buffers 56-0 to 56-3. Fig. 3. When a logic high level is presented on output lines 90 or 96 of buffers 56-0 through 56-3, one of transistors 88 and 94 coupled to that line is turned on. If the ReRAM device has been programmed to its low-impedance state in series with this transistor, line 60-X is pulled down to ground, thereby overcoming pull-up p-channel transistor 74.

[0063] To program an address into the fault PROM read decoder 30, the ReRAM elements in the programmable circuits 84 associated with all buffers 56-0 through 56-3 are selectively programmed in a unique pattern such that when the selected address is presented to the fault PROM read decoder section 30 on the address bus 20, only one combination of turned-on n-channel transistors (88, 94) and their respective series-connected ReRAM elements (86, 92) does not provide a circuit path to pull line 60-X down to ground because none of the ReRAM elements have been programmed in the particular combination. All other address combinations include at least one combination of an on n-channel transistor (88, 94) and its respective series-connected ReRAM element (86, 92) providing a circuit path to pull line 60-X down to ground.

[0064] Those of ordinary skill in the art will recognize that conventional ReRAM programming circuitry and techniques may be employed to program the ReRAM elements (e.g., ReRAM elements 78, 84, and 98 shown in Fig. 3 and Fig. 4). Specific circuitry in the error PROM write section 34 for applying the appropriate programming potentials to the various ReRAM elements is not shown to avoid obscuring the disclosure and obscuring the present invention.

[0065] After an address and a bit error number, as described below, are programmed into the ReRAM elements in the programmable circuits 84 associated with all buffers 56-0 through 56-3 to present the unique pattern described above, the error PROM read decoder section 30 monitors the address bus 20.

[0066] Counter 42 allows multiple erroneous bits in a single data memory word to be corrected and is used to identify which bit error of the selected address programmed into one of lines 601 through 60n is faulty. The counter is reset each time an address on address bus 20 is set active, and thus starts at zero. The counter is controlled as shown in the flowchart of Fig. 6. In one non-limiting example of an embodiment of the present invention, a 5-bit counter allows up to 32 bit errors in a single memory word to be decoded using 5 complementary bit outputs, as is known in the art.

[0067] The method of programming any of 32 addresses to identify the bit error number in a word identified on one of the lines 601 to 60n is described by further investigation of Fig. 3 and Fig. 4. The reference numeral 98 (which represents one of the small squares at all intersections of the lines 601 to 60n and the complementary outputs 66 of the counters 42 in Fig. 3 and the switching logic within the dashed lines 98 of Fig. 4) represents a programmable circuit used to program one of the addresses, as a non-limiting example of one of the 32 addresses, from the counter 42 into any of the lines 601 to 60n to identify up to 32 error numbers of a faulty bit in a word identified on one of the lines 601 to 60n. In Fig. 4, it can be seen that the circuit logic 98 includes a first ReRAM element 100 in series with an n-channel transistor 102 between the line 60-X and ground. The gate of the n-channel transistor 102 is connected to the non-inverting output 104 of one of the complementary counter outputs 66 in Fig. 3. A second ReRAM element 106 is connected in series with an n-channel transistor 108 between line 60-X and ground. The gate of the n-channel transistor 108 is connected to the inverting output 104 of one of the complementary counter outputs 66 in Fig. 3. When a logic high level is presented on lines 104 or 110, one of transistors 102 and 108 coupled to that line is turned on. If the ReRAM device has been programmed to its low-impedance state in series with that transistor, line 60-X is pulled down to ground.

[0068] Thus, the bit error number is programmed into the error PROM read decoder section 30 by selectively programming the ReRAM elements in the programmable circuits 98 associated with all outputs of the counter 42 in a unique pattern such that, when the bit error number is presented at the output of the counter 42, only one combination of turned-on n-channel transistors (102, 108) and their respective series-connected ReRAM elements (100, 106) does not provide a circuit path to pull the line 60-X down to ground. All other combinations of turned-on n-channel transistors (102, 108) and their respective series-connected ReRAM elements (100, 106) provide at least one circuit path to pull the line 60-X down to ground.

[0069] When the address on bus 20 is presented to the error PROM 24, the counter 42 is in its zero state. If the address on bus 20 identifies a data word with a bit error, the error entry defined by the PLD address outputs of buffers 56-1 through 56-3 and the decoded zero count state of the complementary 5-bit count state at the output of counter 42 allows the one of lines 601 through 60n programmed to respond to this error to be pulled high, thereby setting the output 54, i.e., the error bit flag 54, to a high logic level.The single one of lines 601 through 60n that has been pulled high is fed into a faulty bit address data memory 36, where it acts as an active word line, thus selecting a single data word programmed into the faulty bit address data memory 36 to provide the m-bit column address as outputs to the faulty bit column position decoder 38, thereby causing the bit column address line (one of 440 through 44m) of the faulty bit column address to be activated, and N copies of the correct data to be presented to the corrected data determiner 48. As previously mentioned, multiple copies of the correct bit value may be stored to increase the reliability of the error correcting memory array 10.In the event that one of the N storage locations of the replacement bit becomes faulty, a voting scheme can be used to verify the correct value of the replacement bit in the corrected data determiner 48, which, as previously mentioned, may be, for example, a voting circuit. Voting circuits are well known in the art. The corrected data value is presented on output line 50.

[0070] In addition, as stated above, the data word programmed into the faulty bit address data memory 36 for each identified error may also include ECC bits for the data word as well as the optional bit for driving the error bit flag 54.

[0071] As previously mentioned, counter 42 allows multiple erroneous bits in a single data memory word to be corrected. Each bit error in a single data word read from memory is programmed as a single error entry on a different one of lines 601 through 60n in the error PROM read decoder section 30. The first error found in a data word is programmed so that the counter state "0" in combination with the address on bus 20 activates a first one of lines 601 through 60n to provide the address for that error to the erroneous bit address data store 36. In the event that a second bit error is found in the same data word in memory, the error bit flag 54 remains high after the next bit clock pulse on line 54 clocks counter 42 to the counter state "1."This second error is programmed onto another one of lines 601 through 60n in the error PROM read decoder section 30, so that the counter state "1" in combination with the address on bus 20 activates a second one of lines 601 through 60n to provide the address for this error to the faulty bit address data memory 36. Additional bit errors are identified by using successive count states of counter 42 in combination with the address on bus 20 to activate additional ones of lines 601 through 60n to provide the addresses to the faulty bit address data memory 36.

[0072] As an example of the operation of the error PROM 24, consider the case where a data word at data memory address XXXX is determined to have a single bit error at bit position 3. The next available one of lines 601 through 60n in the error PROM read decoder section 30 is programmed to respond to an address including a partial address XXXX from the address bus 20 on lines 56-0 through 56-3 and a partial address provided by the counter state "0" from the counter 42 on lines 66. Since the counter 42 is reset to the "0" state on line 64 each time a new address is asserted on the address bus 20, the programmed one of the lines 601 through 60n in the error PROM read decoder section 30 changes to a high logic level and the error bit flag 54 changes to a high logic level.The programmed one of lines 601 through 60n in the error PROM read decoder section 30 is a decoded word line address for the faulty address data memory 36, where the m-bit column address for the decoder for a column position of a faulty bit 38 is stored to provide the bit position of the faulty bit on one of lines 440 through 44n and the N copies of the corrected bit value to be read from the faulty address memory 360 and appear on the corrected data bit output line 50 from the corrected data determiner 48. The controller 18 writes the correct data bit to the sense amplifiers 16 in response to the error bit flag 54 of FIG. 16, as described further below. As mentioned, the data at the word line address in the faulty address data memory 36 may also include ECC bits and a control bit for the error bit flag 54.

[0073] The controller 18 then sets a next bit clock pulse on the line 52 in Fig. 2 active to increment counter 42. If a second faulty bit position has been programmed onto another one of lines 601 through 60n in fault PROM read decoder section 30, a word line address on one of lines 601 through 60n decoded from address bus 20 on lines 56-0 through 56-3 and the counter state "1" from counter 42 on lines 66 will cause the one of lines 601 through 60n in fault PROM read decoder section 30 programmed for that fault to transition to a high logic level, and fault bit flag 54 will again transition to a high logic level.It also causes the bad address memory 36 to access the bad bit column position decoder 38 to provide the bit position of the second bad bit from the addressed word on another one of the lines 440 through 44n, and causes the N copies of the corrected bit value to be read from the bad address memory 36 and appear on the corrected data bit output line 50 from the corrected data determiner 48. The controller 18 writes the correct data bit to the sense amplifiers 16 in response to the error bit flag 54 of FIG. 18, as described further below.

[0074] The controller 18 then sets a next bit clock pulse on the line 52 in Fig. 2 active to increment counter 42 to counter state "2." The above process is repeated until the address from address bus 20 and the partial address from counter 42 do not cause any of lines 601 through 60n in error PROM read decoder section 30 to change to a logic high level. In this state, error bit flag 54 is at a logic low level, indicating to controller 18 that no additional erroneous bits in the addressed word have been identified and programmed into error PROM read decoder section 30. In one embodiment where the counter is a 5-bit counter, this process can be performed to identify and correct up to 32 erroneous bits that have not failed simultaneously in a single addressed data word.

[0075] If line 60-X is active (representing an error entry) because the ReRAM element 78 has been programmed, and the Fig. 3 and Fig. If the circuit shown in Figure 4 is functioning properly, then one of the pair of ReRAM elements 86 and 92 and 100 and 106 is in a programmed state, and the other ReRAM element of the pair is in an unprogrammed state. There are two failure modes for the error PROM read decoder section 30.

[0076] In a first failure mode, one of the pair of ReRAM elements 86 and 92 and 100 and 106 that is intended to remain unprogrammed is erroneously programmed, resulting in both ReRAM elements in the pair being in a programmed state, and in a second failure mode, one of the pair of ReRAM elements 86 and 92 and 100 and 106 that is intended to be programmed is erroneously erased or cannot be programmed, resulting in both ReRAM elements being in the unprogrammed state.

[0077] In the first failure mode, in which both ReRAM elements in a pair are in a programmed state, line 60-X is never allowed to go high and replace a faulty bit in the sense amplifiers. This causes the ECC 14 associated with data memory 12 to report the uncorrected bit error to controller 18. Controller 18 responds by causing the error PROM write section 34 to reprogram the replacement of a faulty bit on another one of lines 60-1 through 60-5. This failure mode is thus self-correcting. The failed line 60-X deactivates itself because it cannot be selected at any time, and the ECC 14 associated with data memory 12 initiates a replacement error correction entry in the error PROM 24.

[0078] In the second failure mode, in which both ReRAM elements in a pair are in an unprogrammed state, the error is not self-correcting. This is because line 60-X can be mistakenly allowed to go high by the mistakenly unprogrammed one of the ReRAMs. One way to detect this error is to provide an xNOR gate 112 whose inputs are connected to ReRAMs 86 and 92. The output of xNOR gate 112 is ANDed to the state of line 60-X in AND gate 114. If both ReRAMs 86 and 92 are in an unprogrammed state, then the output of XNOR gate 112 is high, and the output of AND gate 114 at reference numeral 116, which communicates with controller 18, is also high, indicating a second failure mode type fault PROM error.

[0079] Similarly, the inputs of XNOR gate 118 are connected to ReRAMs 100 and 106. The output of XNOR gate 118 is ANDed to the state of line 60-X in AND gate 120. If both ReRAMs 100 and 106 are in an unprogrammed state, then the output of XNOR gate 118 is high, and the output of AND gate 120 at reference numeral 122, which communicates with controller 18, is also high, indicating a second failure mode PROM error.

[0080] The controller 18 responds to second failure mode errors reported on lines 116 and 122 by instructing the error PROM write section 34 to program the correction for the erroneous bit as an error entry on another one of the lines 60-1 through 60-5 and further to erase the ReRAM element 78 of line 60-X having the error or to program an additional ReRAM element on the affected line 60-X to thereby disable it.

[0081] One of ordinary skill in the art will recognize that other logic arrangements exist that provide the same error detection function. Such a person of ordinary skill in the art will also recognize that other possible solutions exist. For example, a periodic read operation of the error PROM 24 can be performed when it is idle by traversing the word lines driven by lines 601 through 60n. The ECC 26 (or ECC bits stored in the faulty bit address data memory 36) is used to detect a weak or faulty ReRAM bit, and the controller 18 can then either reprogram the weak bit or clear the PLD term by programming one or more additional ReRAM elements along line 60-X to disable them and then programming a replacement term, as previously discussed.

[0082] Now referring to Fig. 5 is a schematic diagram of an illustrative data-correctable memory read circuit in the form of a sense amplifier 130 that may be used in a memory array 10 with error correction according to one aspect of the present invention. Those of ordinary skill in the art will recognize that the circuit shown in Fig. 5 is only one non-limiting example of a memory read circuit that may be used with an error correcting memory array 10 according to one aspect of the present invention.

[0083] The data-correctable sense amplifier 130 includes a bistable cross-coupled latch 132 formed from a first p-channel transistor 134 connected in series with a first n-channel transistor 136 between a voltage source 138 and a read data strobe line 140. A second p-channel transistor 142 is connected in series with a second n-channel transistor 144 between the voltage source 138 and the read data strobe line 140. The gates of the first p-channel transistor 134 and the first n-channel transistor 136 are connected together to the common drain terminal of the second p-channel transistor 142 and the second n-channel transistor 144. The gates of the second p-channel transistor 142 and the second n-channel transistor 144 are connected together to the common drain terminal of the first p-channel transistor 134 and the first n-channel transistor 136.

[0084] The common drain of the first p-channel transistor 134 and the first n-channel transistor 136 are connected to a reference voltage at reference numeral 146 through a p-channel transistor 148. The common drain of the second p-channel transistor 142 and the second n-channel transistor 144 are connected to the data output from the selected cell in the user memory section 12 at reference numeral 150 through a p-channel transistor 152. The gates of transistors 148 and 152 are connected together to a load signal 150 from the controller 18. Up to this point, the data-correctable sense amplifier section 130 is a conventional sense amplifier circuit, and its operation is well known.

[0085] Corrected data on output line 50 from corrected data determiner 48 is presented on line 154 and is coupled to the common drain terminal of the first p-channel transistor 134 and the first n-channel transistor 136 through an n-channel transistor 156. An inverter 158 generates the complement of the corrected data, which is coupled to the common drain terminal of the second p-channel transistor 142 and the second n-channel transistor 144 through an n-channel transistor 160.

[0086] The gates of transistors 156 and 160 are collectively driven by a decoded write error strobe on line 162. The decoded write error signal on line 162 is generated in an AND gate 164 by an error write signal from controller 18 on line 166 and one of the bit column address lines 440 through 44n, which is activated by the erroneous bit column position decoder 38 to identify the column position of the bit error. The error write signal generated by controller 18 on line 166 is read by controller 18 in response to the error bit flag 54 of Fig. 2 (the output of the OR gate 70 of Fig. 3) is generated.

[0087] Depending on the speed at which the error signals become available in a particular embodiment of the invention, the controller 18 may first write the erroneous data from the selected cell in the user memory section 12 into the latch 130 by asserting an active low write (load) control signal on line 150, and then overwrite the erroneous data with the corrected data by asserting an active high write control signal on the decoded write error data strobe line 162. In cases where a data word contains multiple errors, error correction of all erroneous bits is likely to take some time and an overwrite procedure is used.

[0088] Now referring to Fig. Figure 6 illustrates a flowchart of an example of a method 170 for performing error correction in a memory array 10 according to one aspect of the present invention. The method begins at reference numeral 172.

[0089] At reference numeral 174, it is determined whether a new address has been asserted on memory address bus 20. If not, the method waits at reference numeral 174 until a new address has been asserted on memory address bus 20.

[0090] At reference number 176 it is determined whether the actively set address on the bus 20 as well as the current count value of the counter 42 of Fig. 3 is decoded as an error entry on one of the lines 601 to 60n to create a word in the memory for address data of an erroneous bit 36 of the section for the output of corrected data 32 of the error correction PROM 24 of Fig. 2 to be addressed.

[0091] If the active address on bus 20 and the current count value of counter 42 of Fig. 3 is not decoded as an error entry outputting a word stored in the erroneous bit address data memory 36 of the corrected data output section 32 of the error correction PROM 24 of Fig. 2, the method continues to reference numeral 178 where an ECC in the ECC 14 of Fig. 1 is performed on the data loaded into the sense amplifiers.

[0092] At reference numeral 180, it is determined whether the ECC 14 has read all errors in the data loaded into the sense amplifiers. If no errors were read in the data loaded into the sense amplifiers, the method proceeds to reference numeral 182, where the bit data is read from the sense amplifiers. The method then returns to traverse reference numeral 174 until a new address is asserted on the address bus 20.

[0093] If it has been determined at reference numeral 180 that the ECC 14 has read all errors in the data loaded into the sense amplifiers, the method proceeds to reference numeral 184 where it is determined whether the error is fatal. The most common error correction codes, such as a single error correction and double error detection (SECDED) Hamming code, allow a single-bit error to be corrected and (in the usual configuration with an additional parity bit) double-bit errors to be detected. As one of ordinary skill in the art will appreciate, if multiple bit errors are detected simultaneously in a word being read from memory, and the number of simultaneously detected bit errors exceeds the ability of the ECC to correct all of them, the bit values cannot be corrected. More complex ECC schemes allow more than one simultaneous bit error to be corrected, but at the cost of larger ECC memory sizes.If the number of concurrent bit errors exceeds the ability of the ECC to correct all of the faulty bits, the error is fatal and the method proceeds to reference numeral 186 where the memory array 10 is marked as faulty.

[0094] If it has been determined at reference numeral 184 that the error is not fatal, the method proceeds to reference numeral 188 where the bit correction data provided by the ECC 14 is written into the identified bit position in the sense amplifiers, and then to both reference numeral 182 where the data is read from the sense amplifiers, and to 190 where the address, bit position, and corrected bit data for the addressed memory word are written as a new error entry into the faulty bit address data memory 36 in the error PROM 24.As stated above, this involves programming one of the lines 601 through 60n in the error PROM read decoder section 30 with the address set active at reference numeral 174 and an error count value (the count state of counter 42) for that address as a pointer to the address in the error bit address data memory 36 where the bit position and the corrected bit data are stored.

[0095] The bit correction data provided by the ECC 14 is preferably written to the identified bit position in the sense amplifiers at reference numeral 188 before the address, bit position, and corrected bit data for the addressed memory word are written as a new error entry into the faulty bit address data storage 36 in the fault PROM 24 at reference numeral 190 to minimize the latency for reading the bit data from the sense amplifiers. Reading the bit data from the sense amplifiers at reference numeral 182 may occur at the same time that the address, bit position, and corrected bit data for the addressed memory word are written as a new error entry into the faulty bit address data storage 36 in the fault PROM 24 at reference numeral 190 to minimize the read delay from the data memory 12.The method then returns to wait at reference numeral 174 until a new address has been set active on the address bus 20.

[0096] If it is determined at reference numeral 176 that the active address on bus 20 and the current count value of counter 42 are Fig. 3 can be decoded as an error entry which outputs a word stored in the memory for address data of an erroneous bit 36 of the section for the output of corrected data 32 of the error correction PROM 24 of Fig. 2, the method continues to reference numeral 192 where the correction data associated with the error entry stored in the memory for address data of an erroneous bit 36 of Fig. 2 (including the m-bit output on lines 40 identifying the column location of the particular bit having the erroneous bit value and the N copies of the correct data) are read from the erroneous bit address data memory 36.

[0097] At reference numeral 194, an ECC in the ECC 26 of Fig. 1 is performed on the correction data read from the faulty bit address data memory 36. At reference numeral 196, it is determined whether the ECC 26, in combination with ECC bits stored as part of the data word in the faulty bit address data memory 36, has read all errors in the correction data read from the faulty bit address data memory 36.

[0098] If no errors were detected in the correction data read from the faulty bit address data memory 36, the method proceeds to reference numeral 198, where the bit correction data read from the faulty bit address data memory 36 is written to the column sense amplifier indicated by the correction data read from the faulty bit address data memory 36. The method then proceeds to reference numeral 200, where the counter is incremented. The method then returns to reference numeral 176 and repeats the previously described sequence until the counter is incremented to a count value that, together with the active address on bus 20, does not constitute an error entry, as described with reference numeral 176.

[0099] If it has been determined at reference numeral 196 that the ECC 26 has read all errors in the correction data read from the faulty bit address data memory 36, the method proceeds to reference numeral 202, where it is determined whether the errors are correctable. As previously mentioned, the number of simultaneous errors that can be corrected depends on how the ECC 26 is configured. If the ECC 26 can correct the errors, the method proceeds to reference numeral 198, where the ECC-corrected bit correction data read from the faulty bit address data memory 36 is written to the column sense amplifier indicated by the correction data read from the faulty bit address data memory 36, as previously described.At reference numeral 204, the currently addressed error entry in the error PROM read decoder section 30 that generated the ECC error is erased, and at reference numeral 206, a new error entry is written to the next available address in the error memory, and the corrected data from the ECC 26 is written to the error bit address data memory 36 at a location associated with the new error entry, as previously described.

[0100] If it is determined at reference numeral 202 that the errors are uncorrectable, the method proceeds to reference numeral 208, where the currently addressed error entry in the error PROM read decoder section 30 that generated the ECC error is erased. The method then proceeds to reference numeral 200, where the counter is incremented, and from there again to reference numeral 176 to determine whether the data word addressed in the data memory has additional associated error entries.

[0101] Those of ordinary skill in the art will recognize that the uncorrectable errors found at reference numeral 202 are not replaced in the sense amplifiers, and when the data word, including any other bits that were replaced, is examined by the ECC 14 in the data memory 12, another opportunity exists to correct the bit error for which erroneous correction data was read from the error memory, as described with respect to reference numerals 178-190.

[0102] According to one aspect of the invention, the read time for data in the data memory 12 can be reduced by including a next failure flag bit at each error entry in the faulty bit address memory 36. If the current error entry referenced by the faulty bit address data memory 36 of Fig. 2 does not represent the last faulty bit being corrected in the currently addressed data memory word read from data memory 12, the next fail flag bit is set at that error entry in the faulty bit address data memory. The controller monitors the next fail flag bit and asserts a next bit clock pulse on line 52 of the error PROM read decoder section to increment the counter state only when that bit has been set. Providing a next fail flag bit avoids unnecessarily clocking counter 42 beyond the last count state at which a faulty bit is found.

[0103] Now referring to Fig. 7 illustrates a flowchart of a method 210 used during the method 170 of Fig. 6, which uses the concept of the next faulty bit flag to avoid unnecessary incrementing of the counter 42. Fig. Figure 7 shows replacement steps that are used instead of incrementing the counter 42 at reference numeral 200 of Fig. 6. After either writing correction data to the sense amplifiers at reference numeral 198 or deleting a currently addressed error entry at reference numeral 208 of Fig. 6 continues the process of Fig. 7 to reference numeral 212 where it is determined whether the next failure flag has been set in the currently addressed fault entry.

[0104] When the next failure flag has been set in the currently addressed fault entry, the method returns to reference numeral 200 of method 170 in Fig. 6, where the counter is incremented. If the next failure flag in the currently addressed error entry has not been set, the method returns to reference numeral 178 of method 170 in Fig. 6, where an ECC in the ECC 14 of Fig. 1 is performed on the data that has been loaded into the sense amplifiers. One of ordinary skill in the art will appreciate that when the method 210 of Fig. 7 after a currently addressed error entry at reference numeral 208 in the method 170 of Fig. 6 is deleted, the reading of correction data from the error memory at reference number 192 of Fig. 6 includes reading the status of the next failure flag so that the next failure flag information is not deleted by deleting the currently addressed fault entry at reference numeral 208 in the method 170 of Fig. 6 were lost.

[0105] When a first error entry is created for a faulty bit in any addressed data word from data memory 12, the next failure flag bit in that error entry is in a reset state, i.e., it is not set. The next failure flag bit is set when an additional faulty bit is later detected in the same addressed data word, and an error entry is created for that later error.

[0106] Referring again to Fig. 2, a next failure flag bit output of the faulty bit address data memory 36 is shown at reference numeral 240. The next failure flag bit output 240 of the faulty bit address data memory 36 communicates with the controller 18. A setpoint, shown at reference numeral 242 for this next failure flag bit output 240, is presented to the faulty bit address data memory 36 on line 244.

[0107] A write enable pulse 250 for programming the setpoint 242 can be provided to the faulty bit address data memory 36 in a variety of ways. According to one aspect of the invention, a binary encoder 246 in the fault PROM write section 34 provides the binary address mask-programmed onto the current one of lines 601 through 60n to the controller 18 on lines 248. The binary encoder 246 converts an active input on one of lines 601 through 60n into a binary address in the range 2(n-1), thus performing the inverse function of the address decoder section of the binary decoder and write logic 62.The controller 18 provides a write enable command to the faulty bit address data memory 36 on line 250 to cause the fault PROM write section 34 to set the next fail flag bit in the faulty bit address data memory word line identified by the binary encoder 246. An example of a method for performing this action is shown in FIG. Fig. 8 shown.

[0108] According to one aspect of the invention, write circuitry of a faulty bit address data memory 252 in the fault PROM read decoder section 30 may respond to a command from the controller 18 on line 254 to issue a write enable command to the faulty bit address data memory 36 on line 256. An example of a method for performing this action is described in reference to Fig. 8 shown.

[0109] At the time an additional error is corrected in a memory word, the controller 18 sets the next bit failure flag in the most recently entered error entry for the memory word in the faulty bit address data memory 36 when the new error data is written in that given data word. Since the controller 18 does not know the binary address of the previous error entry for the addressed data word used by the error PROM write section 34, for each new error, it must scan the entire error PROM 24, looking for the PLD address that has the same data bus 20 as a first partial address and the highest count state of the counter 42 as a second partial address as the current error. This process may therefore add overhead time for writing failed bits to the error PROM 24.

[0110] This overhead can be eliminated by causing the controller 18 to set the next faulty bit flag in the current word in the faulty address data memory 36. This can be done in two ways.

[0111] According to a procedure which, with reference to Fig. 8, by adding some additional logic to the fault PROM write section 34 (e.g., the binary encoder 246 having input lines 601 through 60n), the address of the entry in the fault PROM write section 34 that enabled one of the lines 601 through 60n can be read from the binary encoder 248 in the fault PROM write section 34. The controller 18 then uses this address in the fault PROM write section 34 to write the next faulty bit flag. In the illustrative embodiments described herein, the write process is used to program selected ones of the ReRAM elements in the memory for address data of a faulty bit 36. As previously mentioned, the controller 18 may employ conventional ReRAM programming techniques to control programming circuitry in the error PROM write section 34, details of which are unnecessary for an understanding of the present invention.

[0112] According to another procedure, referring to Fig. 9, once the final pre-programmed fault entry for the data word fault entry (whose next fail flag has not been set) has been located, the controller 18 enables the write logic of a faulty bit address data memory 252 in the fault PROM read decoder section 30 to set the next fail flag in the faulty bit address decoder memory 36 for this final pre-programmed fault entry. This method requires fewer steps than that referring to Fig. 8 described procedures.

[0113] Now referring to Fig. Figure 8 illustrates a flowchart of an example of a method 260 for setting a next failure flag at a location in a memory for address data of a faulty bit of an error PROM and writing correction bit data to the error PROM according to one aspect of the invention. The method begins at reference numeral 262 in response to the controller 18 receiving an ECC error from the ECC 14 monitoring the output of the data memory 12. The method continues to reference numeral 264 where it is determined whether the data word being accessed from the data memory has a previously programmed data error. This is determined by Fig. 2 as well as Fig. 3 is examined. If the error bit is not set, there is no previously programmed error associated with the data word, and no next fail flag needs to be set. The method ends at reference numeral 266. If the data word being accessed from the data memory has a previously programmed data error, the method proceeds to reference numeral 268, where the controller 18 directs the error PROM write section 34 to the binary address provided by the binary encoder 246. The binary encoder 246 provides a convenient way to translate the identity of the currently addressed one of the word lines 601 through 60n into the binary address used by the error PROM write section 34 to address it when writing to it, because the binary encoder 246 outputs the binary address associated with the currently active word line containing the error entry.At reference numeral 270, the error PROM write section 34, specifically the binary decoder and write logic 62, sets the next failure flag bit in the faulty bit address data memory 36 at the location containing the correction data for the most recently entered error entry for the data word with the new bit failure.

[0114] At reference numeral 272, the controller 18 searches entries in the fault PROM read decoder section 30 to locate the next word line address that has no data and is available for a new fault entry. This is easily accomplished by the controller 18, for example, using a bubble search technique known in the art that can find the next available address in an N-bit address word in N operations by first setting the most significant address bit (MSB), the fault bit flag line 54 of Fig. 2 or Fig. 3 is tested and the test is repeated by successively setting lower-order address bits. This process is very efficient and takes less time than a memory write cycle to find the next unused binary address. At reference numeral 274, the error PROM write section 34 writes the address, bit position, and corrected bit data for the addressed memory word as a new error entry into an error buffer at the located word line address. The method ends at reference numeral 266.

[0115] Now referring to Fig. Figure 9 is a flowchart illustrating another example of a method 280 for setting a next failure flag at a location in a memory for address data of a faulty bit of an error PROM 24 and writing correction data to the error PROM 24 according to one aspect of the invention. The method begins at reference numeral 282 in response to the controller 18 receiving an ECC error from the ECC 14 monitoring the output of the data memory 12.

[0116] The method continues to reference numeral 284 where it is determined whether the data word being accessed from the data memory has a previously programmed data error. This is determined by Fig. 2 as well as Fig. 3 is examined. If the error bit is not set, there is no previously programmed error associated with the data word, and no next failure flag needs to be set. The method ends at reference numeral 286. If the data word accessed from data memory has a previously programmed data error, the method proceeds to reference numeral 288 where the error PROM read decoder section 30 sets the next failure flag bit in the faulty bit address data memory utilizing faulty bit address data memory write logic 252 at the current location containing the correction data for the last error entry associated with the current address bus address.

[0117] At reference numeral 290, the entries in the fault PROM read decoder section 30 are searched to locate the next word line address that has no data and is available for a new fault entry. This search can be performed in the same manner as the search performed at reference numeral 272 in Fig. 8. At reference numeral 292, the error PROM write section 34 writes the address, bit position, and corrected bit data for the addressed memory word as a new error entry into an error memory at the located word line address. The method ends at reference numeral 286.

[0118] When the data storage section 12 of the memory array 10 is in use, it is sometimes necessary to write new data to one or more addresses. According to one aspect of the invention, the data newly written to bit positions in memory address locations that previously contained data errors must also be corrected. Fig. 10A and Fig. 10B are flowcharts showing illustrative methods for writing new data to memory address locations to ensure that correction data is provided for one or more faulty bit positions that may be present at the memory address location. The difference between the Fig. 10A and Fig. 10B is that the Fig. 10A does not use the concept of the next faulty bit flag and the method shown in Fig. 10B, the method used to insert the next faulty bit flag.

[0119] Now referring to Fig. 10A, method 300 starts at reference numeral 302. At reference numeral 304, a data memory write request is received by controller 18. The controller asserts a write address on memory bus 20 at reference numeral 306.

[0120] At reference numeral 308, the data is written to the memory section 12 at the specified address. At reference numeral 310, it is determined whether the error bit flag 54 has been set. Fig. Figure 10A shows that this operation occurs simultaneously with the writing of the data at reference numeral 308 to improve the speed of the procedure.

[0121] If it is determined at reference numeral 310 that the error bit flag has not been set, the method ends at reference numeral 312. If it is determined at reference numeral 310 that the error bit flag has been set, the method continues to reference numeral 314 where N copies of the correct bit data for the bit position identified by the error entry in the faulty bit address memory 36 are written into the faulty bit address memory 36 by the faulty bit address data memory write logic 252.

[0122] The method then proceeds to reference numeral 316, where the counter is incremented. Next, at reference numeral 318, it is determined whether the error bit flag 54 has been set. If it is determined at reference numeral 318 that the error bit flag has not been set, the method ends at reference numeral 312. If it is determined at reference numeral 318 that the error bit flag has been set, the method returns to reference numeral 314.

[0123] Now referring to Fig. 10B, method 320 starts at reference numeral 322. At reference numeral 324, a data memory write request is received by controller 18. The controller asserts a write address on memory bus 20 at reference numeral 326.

[0124] At reference numeral 328, the data is written to memory section 12 at the specified address. At reference numeral 330, it is determined whether the error bit flag 54 has been set. Fig. Figure 10B shows that this operation occurs simultaneously with the writing of the data at reference numeral 328 to maximize the speed of the procedure.

[0125] If it is determined at reference numeral 330 that the error bit flag has not been set, the method ends at reference numeral 332. If it is determined at reference numeral 330 that the error bit flag has been set, the method continues to reference numeral 334 where N copies of the correct bit data for the bit position identified by the error entry in the faulty bit address memory 36 are written into the faulty bit address memory 36 by the faulty bit address data memory write logic 252.

[0126] The method then proceeds to reference numeral 336, where it is determined whether the next bit error flag has been set at that location. If the next bit error flag has not been set at that location, the method ends at reference numeral 332. If the next bit error flag has been set at that location, the method proceeds to reference numeral 338, where the counter is incremented. The method then returns to reference numeral 334.

[0127] Those of ordinary skill in the art will appreciate that, although the present invention has been described with reference to embodiments employing ReRAM memory technology, the present invention may be implemented with memories employing non-volatile memory technologies other than ReRAM technology.

[0128] Now referring to Fig. 11A and Fig. 11B show flowcharts of further illustrative methods for writing new data to a selected memory address in the memory section 12 of the memory array 10 according to one aspect of the invention. Fig. 11A and Fig. 11B may be used when the fault PROM read decoder section 30 of the fault PROM 24 does not include faulty bit address data memory write logic 252 that allows direct writing to the faulty bit address data memory 36 from the fault PROM read decoder section 30.

[0129] Fig. 11A illustrates a method 340 for writing new data to a selected memory address in the memory section 12 of the memory array 10 according to one aspect of the invention. The method starts at reference numeral 342.

[0130] At reference numeral 344, a data memory write request is received by controller 18. The controller asserts a write address on memory bus 20 at reference numeral 346.

[0131] At reference numeral 348, the data is written to memory section 12 at the specified address. At reference numeral 350, it is determined whether the error bit flag 54 has been set. Fig. Figure 11A shows that this operation occurs simultaneously with the writing of the data at reference numeral 348 to improve the speed of the procedure.

[0132] If it is determined at reference numeral 350 that the error bit flag has not been set, the method ends at reference numeral 352. If it is determined at reference numeral 370 that the error bit flag has been set, the method proceeds to reference numeral 354, where the controller reads the binary address pointing to the error entry for the bit error, which binary address may be encoded and provided to the controller 18 by the binary encoder 246. The method then proceeds to reference numeral 356, where the binary address is set active in the error PROM write section 34.

[0133] The method then proceeds to reference numeral 358 where N copies of the correct bit data for the bit position identified by the error entry in the faulty bit address memory 36 are written into the faulty bit address memory 36 by the error PROM read section 34, specifically by the binary decoder and write circuitry 62.

[0134] The method then proceeds to reference numeral 360, where the counter is incremented. Next, at reference numeral 362, it is determined whether the error bit flag 54 is set. If the error bit flag is not set, the method ends at reference numeral 352. If the error bit flag is set, the method returns to reference numeral 354.

[0135] Fig. 11B shows another method 370 for writing new data to a selected memory address in the memory section 12 of the memory array 10 according to one aspect of the invention. The method starts at reference numeral 372.

[0136] At reference numeral 374, a data memory write request is received by controller 18. The controller asserts a write address on memory bus 20 at reference numeral 376.

[0137] At reference numeral 378, the data is written to data section 12 at the specified address. At reference numeral 380, it is determined whether error bit flag 54 has been set. Fig. Figure 11A shows that this operation occurs simultaneously with the writing of the data at reference numeral 378 to improve the speed of the procedure.

[0138] If it is determined at reference numeral 380 that the error bit flag has not been set, the method ends at reference numeral 382. If it is determined at reference numeral 380 that the error bit flag has been set, the method proceeds to reference numeral 384, where the controller 18 reads the binary address pointing to the error entry for the bit error. As indicated above, the binary address may be encoded and provided to the controller 18 by the binary encoder 246. The method then proceeds to reference numeral 386, where the binary address is set active in the error PROM write section 34, preferably by the binary decoder and write circuitry 62.

[0139] The method then proceeds to reference numeral 388 where N copies of the correct bit data for the bit position identified by the error entry in the faulty bit address memory 36 are written into the faulty bit address memory 36 by the error PROM write section 34, specifically by the binary decoder and write circuitry 62.

[0140] The method then proceeds to reference numeral 390, where it is determined whether the next bit error flag in the faulty bit address data memory has been set. If the next bit error flag in the faulty bit address data memory has not been set, the method ends at reference numeral 382. If the next bit error flag in the faulty bit address data memory has been set, the method proceeds to reference numeral 392, where the counter is incremented. The method then returns to reference numeral 384.

[0141] Those of ordinary skill in the art will appreciate that, although the present invention has been disclosed using embodiments employing ReRAM elements as the non-volatile memory elements, it is intended that embodiments employing non-volatile memory elements other than ReRAM elements be within the scope of the present invention.

[0142] Although embodiments and applications of this invention have been shown and described, it will be apparent to those skilled in the art that many more modifications than those mentioned above are possible without departing from the inventive concepts contained herein. Therefore, the invention should not be limited except as defined in the appended claims.

Claims

[1] A method for providing error correction for a memory array (10), comprising: for each data word stored in a data storage section (12) of the memory array (10) that has at least one bit error, storing, in an error programmable read-only memory (PROM) (24), an error entry associated with an address of the data word in the data storage section (12) and including error data identifying a bit position of each bit error and correct bit data for each bit error, wherein storing includes programming into a programmable logic device a unique term that is a Boolean combination of the address of the data word in the data storage section (12) and a number of the bit error; monitoring memory addresses presented to the data storage section (12); when a memory address presented to the data storage section (12) is associated with a respective error entry in the error PROM (24), reading, from the error PROM (24), the bit position of each bit error and the correct bit data for each bit error and Substituting the correct bit data into each identified bit position of a memory read circuit arranged to read data from the data storage section (12). [2] The method of claim 1, wherein the number of bit errors is defined by an output state of a counter forming a portion of the unique term that is the Boolean combination. [3] The method of claim 2, wherein: each bit error in the data word is accessed sequentially by incrementing the counter (42) to provide a different unique term; and the counter (42) is incremented until the unique term, which is a Boolean combination of the memory address of the data word and the output state of the counter, does not define a respective error entry. [4] The method of claim 2, wherein each error entry in the error PROM (24) includes a next failure flag bit; the next failure flag bit for the last stored error entry for the memory address is in a first state and the next failure flag bit for all other stored error entries for the memory address is in a second state opposite to the first state and in response to the next failure flag bit, the counter (42) is no longer incremented if its output state is associated with a unique term defining the last stored error entry for the memory address. [5] The method of claim 2, wherein: reading, from the error PROM (24), the bit position of each bit error comprises reading the bit position of each bit error from a memory in the error PROM (24); and reading, from the memory in the error PROM (24), the correct bit data for each bit error comprises reading the correct bit data for each bit error from the memory in the error PROM (24). [6] The method of claim 5, wherein reading from the error PROM (24) the correct bit data for each bit error comprises: Reading multiple copies of the correct bit data for each bit error from the memory in the error PROM (24) and Determining a correct data value from the read multiple copies of the correct bit data. [7] A method for providing error correction for a memory array (10), comprising: Providing, to the memory array (10), a memory address identifying a data word to be read from the memory array (10); simultaneously providing the memory address to a fault programmable read-only memory (PROM) containing fault entries representing memory addresses identifying a data word of the memory array (10) having faulty data in at least one bit position and containing no entries for data words of the memory array (10) not having faulty data in at least one bit position, wherein storing the fault entries includes programming a unique term into a programmable logic device that is a Boolean combination of the memory address of the data word in a data storage section (12) of the memory array (10) and a number of the faulty data in the at least one bit position; if the memory address provided to the error PROM (24) identifies the data word having erroneous data in the at least one bit position, outputting, from the error PROM (24), corrected data comprising N copies of the corrected data and selecting from the N copies of the corrected data a single corrected data bit, and outputting information identifying the bit position of the erroneous data in the data word; Reading the data word from the memory array (10) into a memory reading circuit and Replacing the single corrected data bit into the identified bit position of the memory read circuit. [8] Memory array (10) with error correction, comprising: a data storage section (12) containing storage data words; a sense amplifier section coupled to the data storage section (12); an address bus (20) coupled to the data storage section (12); an error PROM (24) coupled to the address bus (20); a data storage section error correction code (ECC) section operatively coupled to the data storage section (12); an error PROM ECC section operatively coupled to the error PROM (24); a controller (18) coupled to the address bus (20), the controller (18) being configured to: activating an address on the address bus (20) to read a data word from the data storage section (12) into the sense amplifier section; Writing an error entry into the error PROM (24) in response to a signal from the data storage section error correction code (ECC) section, the error entry identifying a data word stored in the data storage section (12) that has at least one data bit error, the bit position in the word of the data bit error, and a corrected data value for the data bit error, wherein the writing includes programming a unique term into a programmable logic device that is a Boolean combination of the address of the data word in the data storage section (12) and a number of the data bit error; and Responding to a signal from the error PROM ECC section identifying a data error entry stored in the error PROM memory having at least one error, the response including writing a corrected PROM data error entry to the error PROM memory at a different error PROM address and disabling the identified error entry stored in the error PROM memory. wherein the error PROM (24) is responsive to addresses being asserted on the address bus (20) and having at least one error entry to read the correct data value for the data bit error and to generate a correction signal to the sense amplifier section to replace the read correct data value for the data bit error at the identified bit position in the data word at the address having error entries. [9] The memory array (10) of claim 8, wherein the fault PROM (24) comprises a fault PROM read decoder section, and wherein disabling the identified data storage section fault entry stored in the fault PROM memory comprises programming an additional bit in the fault PROM read decoder section. [10] The error correcting memory array (10) of claim 8, wherein replacing the read correct data value for the data bit error at the identified bit position in the data word comprises overwriting erroneous data initially written to the sense amplifier (16) at the identified bit position in the data word. [11] The error correcting memory array (10) of claim 8, wherein replacing the read correct data value for the data bit error at the identified bit position in the data word comprises replacing the read correct data for erroneous data read from the data storage section (12). [12] Memory array (10) with error correction, comprising: a data storage section (12) containing storage data words; a sense amplifier section coupled to the data storage section (12); an address bus (20) coupled to the data storage section (12); an error PROM (24) coupled to the address bus (20); a data storage section error correction code (ECC) section operatively coupled to the data storage section (12); a controller (18) coupled to the address bus (20), the controller (18) being configured to: activating an address on the address bus (20) to read a data word from the data storage section (12) into the sense amplifier section; Writing an error entry into the error PROM (24) in response to a signal from the data storage section ECC section, the error entry identifying a data word stored in the data storage section (12) having at least one data bit error, the bit position in the word of the data bit error, and a corrected data value for the data bit error, wherein the writing includes programming a unique term into a programmable logic device that is a Boolean combination of the address of the data word in the data storage section (12) and a number of the data bit error; Incrementing a counter to locate multiple error entries for multiple bit errors in a single data word stored in the data storage section (12); and wherein the error PROM (24) is responsive to addresses being asserted on the address bus (20) and having at least one error entry to read the correct data value for the data bit error and to generate a correction signal to the sense amplifier section to replace the read correct data value for the data bit error at the identified bit position in the data word at the address having error entries. [13] The error correcting memory array (10) of claim 12, wherein the controller (18) is further configured to stop incrementing the counter when the counter (42) is incremented to a count state that does not locate an error entry in the error PROM (24). [14] The error correcting memory array (10) of claim 12, wherein the controller (18) is further configured to stop incrementing the counter when the counter (42) reaches a state that locates the most recently entered error entry for the data word in the error PROM (24).

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