SOFT-BIT READ MODE SELECTION FOR NON-VOLATILE MEMORIES

Abstract

Device comprising: an array (200) of non-volatile memory cells; and a controller (206) configured to: Selecting a read mode from a plurality of read modes for reading data from a region of the array (200), the plurality of read modes comprising at least one time-based soft-bit read mode; Applying a set of bias conditions to cells (306, 406) of the region such that bit line currents associated with the cells (306, 406) of the region affect voltages on capacitors associated with the cells (306, 406) of the region; and in response to selecting the time-based soft bit read mode, reading hard bits and soft bits for the range by sampling the capacitor voltages resulting from the applied set of bias conditions at multiple integration times, wherein the controller (206) is configured to select the read mode based on error correction information for a second region of the array (200) and on metadata (135) recorded at write time for the region and the second region.

Description

TECHNICAL FIELD

[0001] The present disclosure relates, in various embodiments, to non-volatile memories, and more particularly to reading soft bit information for non-volatile memories. BACKGROUND

[0002] Various types of non-volatile memory store data by changing physical or electrical properties of non-volatile memory cells. A range of possible values ​​for a physical or electrical property, such as a stored charge, threshold voltage, magnetization, resistance, or the like, can be divided into states so that cells in different states record different data values. Data stored by changing the state of a cell can be read by sensing the state of a cell relative to read thresholds that define boundaries between states.

[0003] However, the variable physical or electrical property of a cell can shift after a write operation for various reasons, such as charge loss or other forms of energy dissipation, interference when reading or writing to neighboring cells, temperature effects, or the like. If the stored value of a cell shifts across a boundary between states, sampling the cell's state may produce an erroneous data value that differs from the data value originally stored in the cell.

[0004] To mitigate or avoid such errors, data can be encoded with an error-correcting code that adds redundant data before the encoded data is written to the cells. An error-correcting code decoder can use hard bits and soft bits to decode and recover the original data, where the hard bits are the encoded data as read (including redundant bits and possible errors), and where the soft bits indicate confidence in or reliability of the hard bits. For example, hard bits can be obtained by sampling cell states with respect to "hard" read thresholds that define boundaries between states, and soft bits can be obtained by sampling cell states with respect to additional "soft" read thresholds to determine whether the stored values ​​of cells have drifted near or possibly across a boundary between states.However, using additional time to sample cell states relative to additional read thresholds can significantly increase read latency. Furthermore, the disclosure of US 2021 / 0065819 A1, US 2019 / 0096479 A1, US 2014 / 0380108 A1, and DE 10 2012 108 545 A1 may be helpful for understanding the present invention.

[0005] US 2021 / 0065819 A1 describes a memory device comprising a memory cell array, a read operator, a shift level determiner, and a read operation controller. The read operator applies a read voltage to a selected word line connected to selected memory cells and reads the selected memory cells in response to an evaluation signal. The shift level determiner calculates a shift value indicating a difference between a number of memory cells read as on cells and a reference number and determines a shift level of a threshold voltage distribution for the selected memory cells. A soft read table memory stores soft read set parameters. The read operation controller determines a plurality of soft read voltages based on the shift level and the soft read set parameters and controls the read operator in response to the evaluation signal.

[0006] US 2019 / 0096479 A1 relates to a non-volatile memory device with multi-level cells. A reading method of the non-volatile memory device includes precharging a bit line and a sense node during a first precharge interval, identifying a first state of a selected memory cell by developing the sense node during a first development time, and detecting a first voltage level of the sense node. Furthermore, the reading method includes precharging the sense node to a second sense precharge voltage and identifying the first state of the selected memory cell from a second state adjacent thereto by developing the sense node during a second development time different from the first development time and detecting a second voltage level of the sense node.

[0007] US 2014 / 0380108 A1 discloses a device that may include a processor circuit, a processor circuit for retrieving data from a non-volatile memory, and a multi-strobe read module. The multi-strobe read module may be operable on the processor circuit to schedule a read operation for reading a memory cell over a plurality of read operations, each read operation being performed under a different read condition. The multi-strobe read module may be further operable to schedule a new read operation as a successor to a previous read operation of the plurality of read operations without recharging the word line if a value of one or more read conditions is within a preset range.

[0008] DE 10 2012 108 545 A1 describes a soft-decision read method of a non-volatile memory device, comprising receiving a soft-decision read command, applying a read voltage to a selected word line, precharging bit lines each connected to selected memory cells of the selected word line, and continuously sampling states of the selected memory cells. The precharged voltages of the bit lines and the read voltage supplied to the selected word line are not varied during the sampling of states of the selected memory cells. SUMMARY

[0009] The present invention relates to devices according to claims 1, 2 and 10 and methods according to claims 7 and 8. Advantageous embodiments may comprise features of dependent claims. Accordingly, devices for reading data are presented. In some embodiments, a device includes an array of non-volatile memory cells and a controller. In some embodiments, a controller is configured to select a read mode from a plurality of read modes for reading data from a region of the array. In further embodiments, a plurality of read modes includes at least one time-based soft-bit read mode. In some embodiments, a controller is configured to apply a set of bias conditions to cells of a region such that bitline currents associated with the cells of the region affect voltages on capacitors associated with the cells of the region.In some embodiments, a controller is configured to read hard bits and soft bits for a range by sampling capacitor voltages resulting from an applied set of bias conditions at multiple integration times in response to selecting a time-based soft bit read mode.

[0010] Furthermore, methods for reading data are presented. In some embodiments, a method includes determining whether to use a time-based soft-bit read mode for reading data from a region of non-volatile memory. In some embodiments, a method includes applying a set of bias voltages to cells of a region such that states of the cells affect analog voltages at sense amplifiers associated with the cells. In some embodiments, a method includes, in response to determining to use a time-based soft-bit read mode, reading hard bits and soft bits for a region by converting analog voltages affected by applied bias voltages into digital sense amplifier results at multiple integration times.

[0011] In another embodiment, a device includes means for selecting a read mode from a plurality of read modes for reading data from a region of non-volatile memory. In further embodiments, a plurality of read modes includes at least one time-based soft-bit read mode. In some embodiments, a device includes means for generating analog voltages based on data stored by cells of a region. In further embodiments, a device includes means for digitizing analog voltages at a number of integration times based on the selected read mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] A more specific description is included below with reference to specific embodiments illustrated in the accompanying drawings. Given that these drawings represent only certain embodiments of the disclosure and are therefore not to be considered limiting its scope, the disclosure will be described and explained with additional specificity and detail through the use of the accompanying drawings, in which: Fig. 1 is a schematic block diagram illustrating one embodiment of a system having reading components; Fig. 2 is a schematic block diagram illustrating one embodiment of a non-volatile memory element having a read component; Fig. 3 is a schematic block diagram illustrating one embodiment of a non-volatile memory cell and associated bias circuits; Fig. 4 is a schematic block diagram illustrating another embodiment of a non-volatile memory cell and associated bias circuits; Fig. 5 is a graph illustrating a distribution of threshold voltages for cells of a non-volatile memory array in one embodiment; Fig. 6 is a graph illustrating a distribution of threshold voltages near a boundary between states in one embodiment; Fig. 7 is a schematic block diagram illustrating one embodiment of a sense amplifier; Fig. 8 is a schematic block diagram illustrating another embodiment of a sense amplifier; Fig. 9 is a schematic block diagram illustrating one embodiment of a reading component; Fig. 10 is a schematic block diagram illustrating another embodiment of a reading component; Fig. 11 is a flowchart illustrating one embodiment of a method for reading data; and Fig. 12 is a flowchart illustrating another embodiment of a method for reading data. DETAILED DESCRIPTION

[0013] Aspects of the present disclosure may be embodied as a device, system, method, or computer program. Accordingly, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, or the like), or an embodiment combining software and hardware aspects, all of which may be generally referred to herein as a "circuit," "module," "device," or "system." Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more non-transitory computer-readable storage media storing computer-readable and / or executable program code.

[0014] Many of the functional units described in this patent have been referred to as modules to further emphasize their implementation independence. For example, a module may be implemented as a hardware circuit comprising custom VLSI circuits or gate arrays, off-the-shelf semiconductors such as logic chips, transistors, or other discrete components. A module may also be implemented in programmable hardware devices such as field-programmable gate arrays, programmable array logic, programmable logic devices, or the like.

[0015] Modules may also be implemented, at least in part, in software for execution by different types of processors. For example, an identified module of executable code may comprise one or more physical or logical blocks of computer instructions, which may be organized, for example, as an object, a procedure, or a function. Nevertheless, the executable programs of an identified module need not be physically located together, but may comprise different instructions stored in different locations that, when logically linked, comprise the module and fulfill the stated purpose for the module.

[0016] As a result, a module of executable code may include a single instruction or many instructions, and may even be distributed across multiple different code segments, in different programs, across multiple storage devices, or the like. Where a module or portions of a module are implemented in software, the software portions may be stored on one or more computer-readable and / or executable storage media. Any combination of one or more computer-readable storage media may be used. A computer-readable storage medium may be, for example, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or apparatus, or any suitable combination of the foregoing, but would not include propagating signals.In the context of this document, a computer-readable and / or executable storage medium may be any tangible and / or non-transitory medium that can contain or store a program for use by or in connection with an instruction execution system, device, processor, or apparatus.

[0017] Computer program code for performing operations for aspects of the present disclosure may be written in any combination of one or more programming languages, including an object-oriented programming language such as Python, Java, Smalltalk, C++, C#, Objective C, or the like, conventional procedural programming languages ​​such as the "C" programming language, scripting programming languages, and / or other similar programming languages. The program code may be executed partially or entirely on one or more user computers and / or on a remote computer or server via a data network or the like.

[0018] A component, as used herein, comprises a tangible, physical, non-transitory device. For example, a component may be implemented as hardware logic circuitry comprising custom VLSI circuits, gate arrays, or other integrated circuits; commercially available semiconductors such as logic chips, transistors, or other discrete devices; and / or other mechanical or electrical devices. A component may also be implemented in programmable hardware devices such as field-programmable gate arrays, programmable array logic, programmable logic devices, or the like. A component may comprise one or more silicon-based integrated circuit devices (e.g., chips, dies, die planes, packages) or other discrete electrical devices in electrical communication with one or more other components via electrical lines of a printed circuit board (PCB) or the like.Each of the modules described herein may, in certain embodiments, alternatively be embodied or implemented by a component.

[0019] A circuit, as used herein, comprises a set of one or more electrical and / or electronic components that provide one or more paths for electrical current. In certain embodiments, a circuit may include a return path for electrical current, such that the circuit is a closed loop. However, in another embodiment, a set of components that does not include a return path for electrical current may be referred to as a circuit (e.g., an open loop). For example, an integrated circuit may be referred to as a circuit regardless of whether the integrated circuit is coupled to ground (as a return path for electrical current) or not.In various embodiments, a circuit may include a portion of an integrated circuit, an integrated circuit, a set of integrated circuits, a set of non-integrated electrical and / or electrical components, with or without integrated circuit devices, or the like. In one embodiment, a circuit may include individual VLSI circuits, gate arrays, logic circuits, or other integrated circuits; commercially available semiconductors such as logic chips, transistors, or other discrete devices; and / or other mechanical or electrical devices. A circuit may also be implemented as a synthesized circuit in a programmable hardware device such as a field-programmable gate array, programmable array logic, programmable logic device, or the like (e.g., as firmware, netlist, or the like).A circuit may include one or more silicon-based integrated circuit devices (e.g., chips, dies, die planes, packages) or other discrete electrical devices electrically connected to one or more other components via electrical lines of a printed circuit board (PCB) or the like. Each of the modules described herein may be embodied or implemented by a circuit in certain embodiments.

[0020] Reference throughout this specification to "one embodiment," "an embodiment," or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Therefore, the terms "in an embodiment," "in the embodiment," and similar language, where they appear in this specification, may not necessarily all refer to the same embodiment, but may mean "one or more, but not all, embodiments" unless expressly stated otherwise. The terms "including," "comprising," "having," and variations thereof mean "including, but not limited to," unless expressly stated otherwise.An enumerative list of elements does not imply that any or all of the elements are mutually exclusive and / or inclusive, unless expressly stated otherwise. The terms "a / a" and "the" also refer to "one or more" unless expressly stated otherwise.

[0021] Aspects of the present disclosure are described below with reference to schematic flowcharts and / or schematic block diagrams of methods, apparatus, systems, and computer program products according to embodiments of the disclosure. It should be understood that each block of the schematic flowcharts and / or schematic block diagrams, and combinations of blocks in the schematic flowcharts and / or schematic block diagrams, may be implemented by computer program instructions.These computer program instructions may be provided to a processor of a computer or other programmable computing device to produce a machine, such that the instructions, executing via the processor or other programmable computing device, produce means for implementing the functions and / or steps specified in the schematic flowchart and / or schematic block diagram block or blocks.

[0022] It should also be noted that in some alternative implementations, the functions specified in the block may occur out of the order specified in the figures. For example, two blocks shown in succession may actually execute substantially concurrently, or the blocks may sometimes execute in the reverse order, depending on the functionality involved. Other steps and methods that are equivalent in function, logic, or effect to one or more blocks, or portions thereof, of the illustrated figures may be devised. Although various arrow styles and line styles may be used in the flowchart and / or block diagrams, they should be understood not to limit the scope of the corresponding embodiments.For example, an arrow may indicate a wait or monitoring period of unspecified duration between enumerated steps of the illustrated embodiment.

[0023] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof. The foregoing summary is illustrative only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, other aspects, embodiments, and features will become apparent upon reference to the drawings and the following detailed description. The description of elements in each figure may refer to elements of consecutive figures. Like reference numerals may refer to like elements throughout the figures, including alternative embodiments of like elements.

[0024] As used herein, a list with an "and / or" concatenation includes any single item in the list or a combination of items in the list. For example, a list of A, B, and / or C includes only A, only B, only C, a combination of A and B, a combination of B and C, a combination of A and C, or a combination of A, B, and C. As used herein, a list that uses the terminology "one or more of" includes any single item in the list or a combination of items in the list. For example, one or more of A, B, and C includes only A, only B, only C, a combination of A and B, a combination of B and C, a combination of A and C, or a combination of A, B, and C. As used herein, a list that uses the terminology "one of" includes one and only one of a single item in the list.For example, "one of A, B, and C" includes only A, only B, or only C, and excludes combinations of A, B, and C. As used herein, "a member selected from the group consisting of A, B, and C" excludes one and only one of A, B, or C, and excludes combinations of A, B, and C. As used herein, "a member selected from the group consisting of A, B, and C, and combinations thereof" includes only A, only B, only C, a combination of A and B, a combination of B and C, a combination of A and C, or a combination of A, B, and C.

[0025] Fig. 1 is a block diagram of one embodiment of a system 100 including read components 150 for a non-volatile memory device 120. The read components 150 may be part of non-volatile memory elements 123 and may be in communication with a device controller 126 external to the non-volatile memory elements 123, a device driver, or the like. The read components 150 may operate within a non-volatile memory system 102 of a computing device 110, which may include a processor 111, volatile memory 112, and a communications interface 113. The processor 111 may include one or more central processing units, one or more general-purpose processors, one or more application-specific processors, one or more virtual processors (e.g., the computing device 110 may be a virtual machine operating within a host), one or more processor cores, or the like.The communication interface 113 may include one or more network interfaces configured to couple the data processing device 110 and / or the non-volatile memory controller 124 to a communication network 115, such as an IP (Internet Protocol) network, a SAN (Storage Area Network), or the like.

[0026] The non-volatile memory device 120 may, in various embodiments, be disposed at one or more different locations relative to the computing device 110. In one embodiment, the non-volatile memory device 120 includes one or more non-volatile memory elements 123, such as semiconductor chips or packages or other integrated circuit devices disposed on one or more printed circuit boards, bearing housings, and / or other mechanical and / or electrical support structures. For example, the non-volatile memory device 120 may include one or more direct inline memory module (DIMM) cards, one or more expansion cards and / or daughter cards, a solid-state drive (SSD), or another hard disk device, and / or may have another memory and / or storage form factor.The non-volatile memory device 120 may be integrated into and / or mounted on a motherboard of the computing device 110, installed in a port and / or slot of the computing device 110, installed on another computing device 110 and / or a dedicated storage device on the network 115, in communication with the computing device 110 via an external bus (e.g., an external hard drive), or the like.

[0027] In one embodiment, non-volatile memory device 120 may be disposed on a memory bus of a processor 111 (e.g., on the same memory bus as volatile memory 112, on a different memory bus than volatile memory 112, instead of volatile memory 112, or the like). In another embodiment, non-volatile memory device 120 may be disposed on a peripheral bus of computing device 110, such as a Peripheral Component Interconnect Express (PCI Express or PCIe) bus, a Serial Advanced Technology Attachment (SATA) bus, a Parallel Advanced Technology Attachment (PATA) bus, a Small Computer System Interface (SCSI) bus, a FireWire bus, a Fibre Channel connection, a Universal Serial Bus (USB), a PCIe Advanced Switching (PCIe-AS) bus, or the like.In another embodiment, the non-volatile memory device 120 may be disposed on a data network 115, such as an Ethernet network, an Infiniband network, SCSI RDMA over a network 115, a storage area network (SAN), a local area network (LAN), a wide area network (WAN) such as the Internet, another wired and / or wireless network 115, or the like.

[0028] Computing device 110 may further include a non-transitory computer-readable storage medium 114. Computer-readable storage medium 114 may include executable instructions configured to cause computing device 110 (e.g., processor 111) to perform steps of one or more of the methods disclosed herein.

[0029] In the illustrated embodiment, non-volatile memory elements 123 include read components 150. In some embodiments, non-volatile memory elements 123 can store data in memory cells by changing physical or electrical properties of the cells. Different states for cells can correspond to different data values. In some embodiments, a read component 150 can read data from a non-volatile memory element 123 by applying bias conditions to memory cells via bit lines, word lines, source lines, and / or the like, such that electrical currents in bit lines are influenced by cell states. Thus, different bit line currents can correspond to different stored data values.For example, a current above a threshold may indicate that a stored data value is a binary "0", and a current below the threshold may indicate that the stored data value is a binary "1".

[0030] In some embodiments, small differences in bitline currents can be sampled or amplified by summing or integrating the bitline currents over a period of time. For example, bitlines can be coupled to capacitors that are charged or discharged by bitline currents, summing capacitor voltages or integrating the bitline currents over time. After an integration period, analog capacitor voltages can be sampled to generate digital data values. For example, a capacitor voltage can be compared to a reference voltage applied to the gate of a transistor to determine whether the capacitor voltage turns the transistor on or off, or the like to generate a binary zero or one. Various other or additional types of hardware can be used to convert bitline currents to analog voltages and then to digital data values.

[0031] However, the physical or electrical property of a memory cell that is altered to record data may shift after the data is written for various reasons, such as charge loss or other forms of energy dissipation, interference when reading or writing to neighboring cells, temperature effects, or the like. If the alterable cell property shifts across a boundary between states, a read component 150 may read erroneous data from the cell. Encoding data with an error-correcting code before storing the data can add redundancy, allowing the original data to be decoded despite the presence of some errors.A decoder can use hard bits and soft bits to decode and recover the original data, where the hard bits are the encoded data as read (including redundant bits and possible errors), and where the soft bits indicate confidence in or reliability of the hard bits.

[0032] In some embodiments, a read component 150 may read hard bits from cells using the above-described process of applying bias conditions to memory cells so that bitline currents affect capacitor voltages, which are sampled or converted to binary outputs after an integration time. In further embodiments, a read component 150 may read soft bits by repeating the same process with different bias conditions. For example, a read component 150 may output different soft bit values ​​indicating whether a corresponding hard bit is less reliable or more reliable, depending on whether a small increase or decrease in bias for a cell changes the resulting hard bit output or leaves the hard bit output unchanged.However, multiple iterations of the process of applying bias conditions and sampling results can significantly increase the read latency for a non-volatile memory element 123.

[0033] Thus, in some embodiments, a read component 150 may read hard bits and soft bits by applying bias conditions to memory cells so that bitline currents affect capacitor voltages, and by sampling or digitizing the resulting capacitor voltages at multiple integration times. Applying bias conditions to the cells once and sampling the resulting capacitor voltages at multiple times may allow a read component 150 to read hard bits and soft bits in less time than it would take to read the soft bits by repeatedly applying different bias conditions and sampling the resulting capacitor voltages.

[0034] Additionally, in some embodiments, a read component 150 may provide or select between multiple read modes with different reliability-speed tradeoffs. For example, a read component 150 may provide a higher-speed, lower-reliability hard-bit read mode in which it does not read soft bits, a medium-speed, medium-reliability time-based soft-bit read mode in which the read component 150 reads hard bits and soft bits by sampling capacitor voltages resulting from a single application of bias conditions, sampling the voltages at multiple integration times, and / or a bias-based soft-bit read mode in which the read component 150 reads hard bits and soft bits by repeatedly applying different bias conditions and sampling the resulting capacitor voltages.

[0035] In some embodiments, a read component 150 may select a read mode for reading data from a region of a non-volatile memory array (e.g., an array in a non-volatile memory element 123). The read component 150 may select the read mode from a variety of read modes, including at least one time-based soft-bit read mode. In some embodiments, a read component 150 may apply a set of bias conditions (e.g., one or more bias voltages) to cells of a region such that bitline currents associated with cells of the region affect voltages on capacitors associated with cells of the region. In response to selecting the time-based soft-bit read mode, the read component 150 may read hard bits and soft bits for a region by sampling capacitor voltages resulting from the applied set of bias conditions at multiple integration times.Providing multiple read modes may allow a read component 150 to avoid high-latency read times or high error rates by selecting a read mode based on conditions such as time since data was written, temperature difference since data was written, or the like. Read components 150 are further described below with reference to FIG. Fig. 2-12 described in more detail.

[0036] In one embodiment, non-volatile memory device 120 is configured to receive requests from a device driver or other executable application via buses 125, 127, a device controller 126, or the like. The non-volatile memory device 120 may be further configured to transfer data to / from a device driver and / or storage clients 116 via bus 125. Accordingly, in some embodiments, the non-volatile memory device 120 may include and / or be in communication with one or more direct memory access (DMA) modules, remote DMA modules, bus controllers, bridges, buffers, etc., to facilitate the transfer of memory requests and associated data. In another embodiment, the non-volatile memory device 120 may receive memory requests as an API call from a storage client 116, as an IO-CTL command, or the like.

[0037] According to various embodiments, a device controller 126 may manage one or more non-volatile memory devices 120 and / or non-volatile storage elements 123. The non-volatile memory device(s) 120 may include recording, storage, and / or storage devices, such as solid-state memory device(s) and / or semiconductor memory device(s), arranged as and / or partitioned into a plurality of addressable media storage locations. As used herein, a media storage location refers to any physical unit of memory (e.g., any quantity of physical storage media on a non-volatile memory device 120). Memory units may include, but are not limited to, pages, memory ranges, blocks, sectors, collections or sets of physical memory locations (e.g., logical pages, logical blocks), or the like.

[0038] A device driver and / or the device controller 126, in certain embodiments, may provide a logical address space 134 for the storage clients 116. As used herein, a logical address space 134 refers to a logical representation of storage resources. The logical address space 134 may include a plurality (e.g., a range) of logical addresses. As used herein, a logical address refers to any identifier for referencing a storage resource (e.g.,Data), including, but not limited to: a logical block address (LBA), a cylinder / head / sector (CHS) address, a file name, an object identifier, an inode, a universally unique identifier (UUID), a globally unique identifier (GUID), a hash code, a signature, an index entry, a range, a scope, or the like.

[0039] A device driver for the non-volatile storage device 120 may maintain metadata 135, such as a logical-to-physical address mapping structure, to map logical addresses of the logical address space 134 in media storage locations to the non-volatile storage device(s) 120. A device driver may be configured to provide storage services to one or more storage clients 116. The storage clients 116 may include local storage clients 116 operating on the computing device 110 and / or remote storage clients 116 accessible via the network 115 and / or the network interface 113. The storage clients 116 may include, but are not limited to, operating systems, file systems, database applications, server applications, kernel-level processes, user-level processes, applications, and the like.

[0040] A device driver may be communicatively coupled to one or more non-volatile storage devices 120. The one or more non-volatile storage devices 120 may include various types of non-volatile storage devices, including, but not limited to, solid-state storage devices, semiconductor storage devices, SAN storage resources, or the like. The one or more non-volatile storage devices 120 may include one or more respective controllers 126 and non-volatile storage media 122. A device driver may provide access to the one or more non-volatile storage devices 120 via a conventional block I / O interface 131. Additionally, a device driver may provide access to enhanced functionality via the SCM interface 132.The metadata 135 may be used to manage and / or track data operations performed by any of the block I / O interfaces 131, SCM interfaces 132, cache interfaces 133, or other related interfaces.

[0041] The cache interface 133 may expose cache-specific features accessible via a device driver for the non-volatile memory device 120. Also, in some embodiments, the SCM interface 132 presented to the storage clients 116 provides access to data transformations implemented by the one or more non-volatile memory devices 120 and / or the one or more device controllers 126.

[0042] A device driver may present a logical address space 134 to storage clients 116 via one or more interfaces. As discussed above, the logical address space 134 may include a plurality of logical addresses, each of which corresponds to the respective media locations of the one or more non-volatile storage devices 120. A device driver may manage metadata 135 that includes any-to-any mappings between logical addresses and media locations, or the like.

[0043] A device driver may further include a non-volatile memory device interface 139 configured to transfer data, commands, and / or requests to the one or more non-volatile memory devices 120 via a bus 125, which may include, but is not limited to, a processor 111 memory bus, a Peripheral Component Interconnect Express (PCI Express or PCIe) bus, an Advanced Technology Attachment (ATA) serial bus, a parallel ATA bus, a Small Computer System Interface (SCSI), FireWire, Fibre Channel, a Universal Serial Bus (USB), a PCIe Advanced Switching (PCIe-AS) bus, a network 115, Infiniband, SCSI RDMA, or the like.The non-volatile memory device interface 139 may communicate with the one or more non-volatile memory devices 120 using input-output control (EA-CTL) commands, EA-CTL command extension(s), direct remote memory access, or the like.

[0044] The communication interface 113 may include one or more network interfaces configured to communicatively couple the computing device 110 and / or the device controller 126 to a network 115 and / or to one or more remote, network-accessible storage clients 116. The storage clients 116 may include local storage clients 116 operating on the computing device 110 and / or remote storage clients 116 accessible via the network 115 and / or the network interface 113. The device controller 126 is part of and / or in communication with one or more non-volatile storage devices 120. Although Fig. 1 illustrates a single non-volatile memory device 120, the disclosure is not so limited and may be adapted to implement any number of non-volatile memory devices 120.

[0045] The non-volatile memory device 120 may include one or more elements 123 of non-volatile storage media 122, which may include, but are not limited to: ReRAM, memristor memory, programmable metallization cell memory, phase-change memory (PCM, PCME, PRAM, PCRAM, ovonic unified memory, chalcogenide RAM, or C-RAM), NAND flash memory (e.g., 2D NAND flash memory, 3D NAND flash memory), NOR flash memory, nano random access memory (Nano-RAM or NRAM), wire-based nanocrystal memory, silicon oxide-based sub-10 nanometer process memory, graphene memory, silicon oxide-nitride-oxide-silicon (SONOS), programmable metallization cells (PMC), conduction-bypass RAM (CBRAM), magnetoresistive RAM (MRAM), magnetic Storage media (e.g. hard disk, tape), optical storage media or the like.The one or more elements 123 of the non-volatile storage medium 122 may, in certain embodiments, comprise block and / or page addressable memory technologies, such as NAND flash, or may comprise byte addressable storage class memories (SCM).

[0046] While the non-volatile storage medium 122 is referred to herein as a "storage medium," in various embodiments, the non-volatile storage medium 122 may more generally comprise one or more non-volatile recording media capable of recording data, which may be referred to as a non-volatile storage medium, a non-volatile storage medium, or the like. Furthermore, in various embodiments, the non-volatile storage device 120 may comprise a non-volatile recording device, a non-volatile memory device, a non-volatile storage device, or the like. Similarly, in various embodiments, a non-volatile memory element 123 may comprise a non-volatile recording element, a non-volatile memory element 123, a non-volatile storage element, or the like.

[0047] The non-volatile storage medium 122 may include one or more non-volatile memory elements 123, which may include, but are not limited to, chips, packages, planes, dies, or the like. A device controller 126 external to the one or more non-volatile memory elements 123 may be configured to manage data operations on the non-volatile storage medium 122 and may include one or more processors, programmable processors (e.g., FPGAs), ASICs, microcontrollers, or the like. In some embodiments, the device controller 126 is configured to store data on and / or read data from the non-volatile storage medium 122, transfer data to / from the non-volatile storage device 120, and so on.

[0048] The device controller 126 may be communicatively coupled to the non-volatile storage medium 122 via a bus 127. The bus 127 may include an I / O bus for communicating data to / from the non-volatile memory elements 123. The bus 127 may further include a control bus for communicating addressing and other command and control information to the non-volatile memory elements 123. In some embodiments, the bus 127 may communicatively couple the non-volatile memory elements 123 to the device controller 126 in parallel. This parallel access may enable the non-volatile memory elements 123 to be managed as a group, thereby forming a logical memory element 129. The logical memory element may be divided into corresponding logical memory units (e.g., logical pages) and / or logical memory areas (e.g., logical blocks).The logical storage units may be formed by logically combining physical storage units of each of the non-volatile memory elements 123.

[0049] Device controller 126 may include and / or be in communication with a device driver executing on computing device 110. A device driver may provide storage services to storage clients 116 via one or more interfaces 131, 132, and / or 133. In some embodiments, a device driver provides a block device I / O interface 131 through which storage clients 116 perform block-level I / O operations. Alternatively or additionally, a device driver may provide a storage class memory (SCM) interface 132, which may provide other storage services to storage clients 116. In some embodiments, SCM interface 132 may include extensions to block device interface 131 (e.g., storage clients 116 may access SCM interface 132 via extensions or additions to block device interface 131).Alternatively or additionally, the SCM interface 132 may be provided as a separate API, service, and / or library. A device driver may further be configured to provide a cache interface 133 for caching data using the non-volatile memory system 102.

[0050] A device driver may further include a non-volatile memory device interface 139 configured to transmit data, commands, and / or queries to the device controller 126 via a bus 125, as described above.

[0051] Fig. 2 illustrates one embodiment of a non-volatile memory system 123. The non-volatile memory element 123 may be substantially similar to that described above with reference to Fig. 1 and may be a chip, a die, a die plane, or the like. In the illustrated embodiment, the non-volatile memory element 123 includes a memory array 200, row circuits 202, column circuits 204, and a die controller 206.

[0052] In various embodiments, a non-volatile memory element 123 may be an integrated circuit that includes both a core array 200 of memory cells (e.g., non-volatile memory cells) for data storage and peripheral components (e.g., row circuits 202, column circuits 204, and / or die controller 206) for communicating with the array 200. In certain embodiments, one or more non-volatile memory elements 123 may be included in the non-volatile memory device 120.

[0053] In the illustrated embodiment, array 200 includes a plurality of memory cells. In one embodiment, array 200 may be a two-dimensional array. In another embodiment, array 200 may be a three-dimensional array including multiple levels and / or layers of memory cells. In various embodiments, array 200 may be addressable by rows via series circuits 202 and by columns via column circuits 204.

[0054] Die controller 206, in certain embodiments, cooperates with series circuits 202 and column circuits 204 to perform memory operations on array 200. In various embodiments, die controller 206 may include components such as a power control circuit that controls the power and voltages supplied to series circuits 202 and column circuits 204 during memory operations, an address decoder that translates a received address into a hardware address used by series circuits 202 and column circuits 204, a state machine that implements and controls the memory operations, and the like. Die controller 206 may communicate with a computing device 110, a processor 115, a bus controller, a memory device controller, a memory module controller, or the like via bus 127 to receive command and address information, transfer data, or the like.

[0055] In one embodiment, the die controller 206 may include a read component 150 substantially similar to that described above with reference to Fig. 1 described reading component 150. Although the reading component 150 in Fig. 2 as a component of die controller 206, a read component 150 may, in some embodiments, include or communicate with components of row circuits 202, column circuits 204, or the like. For example, in some embodiments, bias circuits for applying bias conditions to word lines and bit lines may be included in row circuits 202 and column circuits 204, and read component 150 may include or communicate with the bias circuits.

[0056] Fig. 3 and Fig. 4 illustrate various embodiments of a non-volatile memory cell 306, 406 with associated bias circuits 302, 308, 314. Fig. 3 represents a memory cell 306 with three terminals, and Fig. 4 illustrates a memory cell 406 with two terminals. A memory array 200 as shown in Fig. 2, may include multiple memory cells 306, 406 in rows, columns, and / or layers. In various embodiments, a read component 150 may read different types of memory cells 306, 406 by applying bias conditions to cells 306, 406 so that bitline currents charge or discharge capacitors and then by sensing the capacitor voltages.

[0057] Fig. 3 illustrates one embodiment of a memory cell 306. In various embodiments, a "cell" may refer to a smallest or basic physical unit of storage or memory for an array 200 and may be interchangeably referred to as a "storage cell," a "memory cell," or the like. For example, a cell 306 may be a floating-gate transistor for NAND flash memory, a memristor for resistive memory, or the like. Thus, in another embodiment, an array 200 of cells 306 may be a two-dimensional grid, a three-dimensional block, a group, or other similar set of cells 306 in which data may be physically stored, for short-term storage use, long-term storage use, or the like.

[0058] A physical or electrical property of a memory cell 306 can be changed to store data. For example, transistor-based memory cells 306 (e.g., NAND) can store data based on a variable threshold voltage for turning on the transistor. Similarly, resistive memory cells 406 (e.g., PCM or MRAM) can store data based on a variable resistance. A range of possible values ​​for a variable physical property of a cell can be divided into states corresponding to data values.

[0059] In the illustrated embodiment, the memory cell 306 is a floating-gate transistor (e.g., as used in NAND flash memories), where the threshold voltage at which the transistor is "turned on" (e.g., switches from a non-conducting or low-current state to a conducting or high-current state when the voltage is applied to the transistor as a gate-source voltage) is variable by changing the amount of charge trapped in a floating gate or charge trap separated from the control gate and the substrate or channel by oxide (or other dielectric) layers.

[0060] In the illustrated embodiment, cell 306 is coupled to a wordline bias circuit 308 via a wordline 310, to bitline bias / sense circuits 302 via a bitline 304, and to a source bias circuit 314 via a source line 312. In various embodiments, bitline 304, wordline 310, and / or source line 312 are conductors coupled to columns, rows, layers, or other regions of cells 306 in an array 200. Although a single cell 306 in Fig. 3, a wordline 310 may couple a wordline bias circuit 308 to a plurality of cells 306 across a row or layer of an array 200. Similarly, a bitline 304 and / or a source line 312 may be coupled to a plurality of cells 306 in a column of the array.

[0061] In one embodiment, bit lines 304, word lines 310, and source lines 312 may couple bias circuits 302, 308, 314 directly to cells 306 (e.g., with other cells 306 connected in parallel with the lines). In another embodiment, connections between bias circuits 302, 308, 314 and a cell 306 may be indirect, with a current path passing through other cells 306 (or other components such as select transistors). For example, in a NAND flash memory, cells 306 may be connected in a series chain, with adjacent cells 306 in the chain connected source-to-drain. Bitline 304 may couple bitline bias / sense circuits 302 to a cell 306 at one end of the chain, and sourceline 312 may couple source bias circuit 314 to a cell 306 at the other end of the chain.To read data from one of the cells 306 in the chain, the other cells 306 in the chain may be "turned on" (e.g., by applying sufficiently high gate voltages across word lines 310 to those cells 306) so that the cell 306 being read is coupled to the bit line bias / sense circuits 302 and the source bias circuit 314 via the bit line 304, the source line 312, and the other cells 306 in the chain.

[0062] In various embodiments, a sense component 150 may use bias circuits 302, 308, 314 to apply bias conditions to cells 306 of an array 200 or within a region of an array 200. In various embodiments, "bias conditions" may be bias voltages, bias currents, or the like. Bias conditions may be applied to cells 306 via bit lines 304, word lines 310, and / or source lines 312, or other types of lines leading to cells in other types of memory arrays 200.In some embodiments, a bias condition may be an initial condition for a read or sense operation and may be a steady-state condition during the operation, such as a read voltage applied to a word line 310 during a sense operation, or may be a transient condition, such as a bit line precharge voltage that is initially applied and then allowed to vary depending on the state of the cells 306. More generally, bias conditions may be any set of voltages, currents, or other conditions that, when applied to cells 306 in a region of a memory array 200, result in another condition, such as a bit line current or capacitor voltage, that depends on the state of one or more cells 306.Thus, a sampling operation to determine which data value is stored by a cell 306 may include applying bias conditions and observing the resulting condition to determine the state of the cell 306.

[0063] In the illustrated embodiment, where the threshold voltage that turns on cell 306 is variable to store data, the range of possible threshold voltages for cell 306 is divided into states corresponding to data values. To read data from cell 306, a read voltage is applied as a gate-to-source voltage. A drain-to-source voltage is applied such that a current is generated through cell 306 when the applied read voltage is above the threshold voltage for cell 306. Conversely, when the applied read voltage is below the threshold voltage for cell 306, cell 306 is "off," and the current is zero (or a non-zero leakage current that is lower than the current for cell 306 in the "on" state).If cell 306 stores a single bit, using a high threshold voltage state and a low threshold voltage state to represent a 0 and a 1, then applying a read voltage that coincides with the boundary between states may be sufficient to determine whether the threshold voltage for cell 306 is above the read voltage and therefore in the high threshold voltage state, or below the read voltage and therefore in the low threshold voltage state. If cell 306 stores more than one bit (e.g., two bits using four states, three bits using eight states), further sampling by applying additional read voltages at boundaries between the additional states may allow the state of cell 306 to be determined.

[0064] In the illustrated embodiment, cell 306 is located in a NAND flash array 200, and the drain, gate, and source voltages described above are applied by bias circuits 302, 308, and 314 via bit lines 304, word lines 310, and source lines 312. In some embodiments, bit line bias / sense circuits 302, word line bias circuit 308, and / or source bias circuit 314 may include components that generate bias conditions, such as a bias voltage or bias current. Components that generate a bias voltage or other bias conditions may include voltage supplies, switching components for coupling or decoupling a node to a voltage supply, voltage regulators, charge pumps, level shifters, or the like. Various other or additional components may be included in the bias circuits 302, 308, 314.In some embodiments, bias circuits 302, 308, 314 may be controllable circuits capable of outputting multiple voltages. However, in some embodiments, one or more of bias circuits 302, 308, 314 may be implemented as a connection to a reference voltage in the illustrated embodiment. For example, in one embodiment, source bias circuit 314 may simply connect source line 312 to ground, VSS, or another reference voltage.

[0065] In the illustrated embodiment, for reading data from cells 306 in a NAND memory array 200, a wordline bias circuit 308 applies a read voltage across wordline 310 to control gates of a row of cells 306. Wordline bias circuits (not shown) for other rows of cells 306 apply a high voltage sufficient to "turn on" those cells 306 so that current through series chains of cells 306 is based on whether the read voltage applied to a row of cells 306 is above or below the threshold voltage for those cells 306. Source bias circuits 314 apply a source voltage (e.g., VSS or zero volts) across source lines 312 for multiple columns or chains of cells 306. Bitline bias / sense circuits 302 apply drain voltages (e.g., bitline precharge voltages) across bitlines 304 to the columns or strings of cells 306.When these bias conditions are applied to cells 306, the cells 306 coupled to wordline 310 are turned on or off depending on whether the read voltage applied to wordline 310 is above or below the threshold voltage for each of those cells 306, and thus bitline currents (e.g., the electrical current in each of bitlines 304) depend on the states of the cells 306 in that row. In further embodiments, bitline bias / sense circuits 302 may include sense amplifiers that convert analog electrical characteristics on bitlines 304, such as bitline voltages or currents, into digital results, such as logic levels or data values.

[0066] Fig. 4 illustrates another embodiment of a memory cell 406. In the illustrated embodiment, the memory cell 406 is a resistive memory cell, where the resistance of the cell 406 is variable to store data. For example, in one embodiment, a high resistance state may correspond to a binary zero, while a low resistance state corresponds to a binary one. In another embodiment, a cell 406 may store multiple bits using intermediate resistance states. Resistive memory cells 406, in various embodiments, may include magnetoresistive memory cells, phase-change memory cells, ovonic threshold switching memory cells, conductive shunt memory cells, ReRAM cells, or the like.In the illustrated embodiment, a wordline bias circuit 308 is coupled to a row of cells 406 via a wordline 310, and bitline bias / sense circuits 302 are coupled to a column of cells 406 via a bitline 304. The bitline bias / sense circuits 302, bitline 304, wordline bias circuit 308, and wordline 310 may be configured substantially as described above with reference to FIG. Fig. 3. However, for resistive memory cells 406 with two terminals, the current through a cell 406 may be a current between the word line 310 and the bit line 304, rather than between the bit line 304 and a source line 312. Thus, in the illustrated embodiment, a source line 312 and a source bias circuit 314 are omitted.

[0067] In the illustrated embodiment, a wordline bias circuit 308 applies a wordline bias voltage to a row of cells 406 via wordline 310 for reading data from cells 406 in an array 200. Bitline bias / sensing circuits 302 for columns of cells 406 apply bitline bias voltages to bitlines 304. When these bias conditions are applied to cells 406, bitline currents depend on the voltage difference between the wordline bias voltage and the bitline bias voltages and on the states of cells 406. A high bitline current may indicate that a cell 406 is in a low-impedance state, while a low bitline current may indicate that a cell 406 is in a high-impedance state. As described above with reference to Fig. 3, the bitline bias / sense circuits 302 may include sense amplifiers that convert analog electrical characteristics on the bitlines 304, such as bitline voltages or currents, into digital results, such as logic levels or data values. The sense amplifiers may digitize the analog bitline current to generate a digital data value.

[0068] In various embodiments, read thresholds may define boundaries between states. Different types of read thresholds may define states or boundaries between states in different ways for different types of cells 306, 406. For example, as described above with reference to Fig. 3, where the threshold voltage of a transistor-based cell 306 is variable to store data, a read threshold may be a voltage that separates the range of possible threshold voltages into states. Similarly, with reference to Fig. 4, where the resistance of a cell 406 is variable to store data, a read threshold may be a resistance value that separates the range of possible resistances into states. However, in some embodiments, a read threshold may define boundaries between states without direct reference to the variable property of the cell 306, 406 used to store data. For example, a read threshold that defines a boundary between a high-resistance state and a low-resistance state for resistive memory may be a current threshold, where a current above the threshold corresponds to the low-resistance state, so that the states are defined by a current rather than directly by a resistance. Various other or further types of read thresholds may be used to define states for cells 306, 406 of non-volatile memory.

[0069] Although the Fig. 3 and Fig. 4 illustrate transistor-based three-terminal cells 306 and resistor-based two-terminal cells 406, various other or additional types of memory cells may be similarly biased. For example, a three-terminal magnetoresistive memory may include separate read bit lines and write bit lines, and applying bias conditions to read data from the cells may include blocking the current in the write bit line (e.g., by operating a transistor to disconnect the write bit line). Additionally, in some embodiments, bias conditions may be applied to components included in the Fig. 3 and Fig. 4 are not shown. For example, applying bias conditions to cells may include applying select or deselect voltages to select transistors to select a row, column, level, or other region of a memory array 200.

[0070] Fig. 5 is a graph 500 illustrating a distribution of threshold voltages for cells of a non-volatile memory array 200 in one embodiment. In the illustrated embodiment, cells are flash memory cells, where the threshold voltage Vt of a cell is variable to store data, and the range of possible values ​​for the threshold voltage Vt is shown on the horizontal axis of the graph 500. References to a threshold voltage Vt are provided as a non-limiting example. In another embodiment, a non-volatile memory array 200 may include a different cell type with a different property that can be similarly divided into states for storing data. For a given threshold voltage on the horizontal axis, the height of the line on the graph 500 indicates the number or fraction of cells with that threshold voltage.

[0071] In the illustrated embodiment, the range of possible threshold voltages Vt for a NAND flash memory cell is divided into four sub-ranges or states L0-L3 by the read thresholds 502a-c, represented by vertical dashed lines. In another embodiment, a range of possible threshold voltages Vt for a NAND flash cell may be divided into more or fewer than four states. In the illustrated embodiment, cells are erased to the lowest state L0 and may be programmed to higher states L1-L3. The states L0-L3 correspond to data values. For example, in the illustrated embodiment, the four states L0, L1, L2, and L3 are mapped to the data values ​​"11," "01," "00," and "10," so that the cell stores two bits of information. Various other mappings between cell states and data values ​​may be used in various embodiments.Sense operations may determine whether the threshold voltage Vt for a cell is above or below one of the read thresholds 502, thereby determining the state of the cell and the corresponding data value. Sense operations may be performed as described above with reference to FIG. Fig. 3 and Fig. 4, by applying bias conditions to cells such that a bit line current or other electrical result depends on the state of the cell.

[0072] Graph 500 indicates that cells are programmed or erased to create a uniform distribution of threshold voltages among the L0-L3 states. In practice, the distribution of states for a set of cells may not be uniform. For example, if a long string of zeros is written to a set of cells, more cells may be in the L2 state, which encodes "00," than in the other states. However, data compression or whitening algorithms can make the distribution of states substantially uniform across a large set of cells.

[0073] Although the distribution of threshold voltages for cells among states L0-L3 may be substantially uniform, the distribution is illustrated as forming a bell-shaped peak in each state. In some embodiments, a cell may be programmed by outputting voltage pulses that change the threshold voltage Vt to cause the cell to be at or near a target voltage in the middle of the voltage range defining the state. Thus, a bell-shaped peak may be centered on the target programming voltage or the like. The width of the peaks may be affected by variations in the cells and the programming process, or by error-causing phenomena such as read disturb, program disturb, voltage-induced leakage current, or the like. Although symmetrical, bell-shaped peaks are shown, skewed distributions and other distributions are possible.Over time, the distributions can broaden or distort as the threshold voltage of cells moves away from their originally programmed values. Additionally, distributions can shift due to temperature. For example, the threshold voltage of a transistor can be temperature-dependent, so the location and width of the peaks change depending on the current temperature.

[0074] In the illustrated graph 500, each peak represents the distribution of cells originally programmed to a particular state. Thus, there are four peaks corresponding to the four L0-L3 states. However, cells originally programmed to threshold voltages in one state may have drifted over time to have threshold voltages in a different state. Thus, the individual peaks overlap significantly at or near the read thresholds 502. (The overall distribution for cells of the array may be a sum of the peaks shown for cells programmed to each state.) A scan operation that determines the current state of a cell relative to the read thresholds 502 may result in a data error if the threshold voltage for the cell has exceeded one of the read thresholds 502, such that the cell is not currently in the state to which it was programmed (or erased).

[0075] Fig. Figure 6 is a graph 600 illustrating a distribution of threshold voltages near a boundary between states. A dashed rectangle in Fig. 5 shows the area of ​​the distribution that Fig. 6 at or near the read threshold 502c between states L2 and L3. Read thresholds that define states (or boundaries between states), such as the read thresholds 502a-c of Fig. 5, may be referred to as “hard” read thresholds, and information about the cell states with respect to the boundary-defining “hard” read thresholds may be referred to herein as “hard bits.”

[0076] As mentioned above with reference to Fig. 5, the L0, L1, L2, and L3 states are mapped to the data values ​​"11," "01," "00," and "10." Thus, sensing the cell states relative to the read thresholds 502a-c can determine or read the hard bits for a cell. If Fig. 6, a read component 150 determines that the threshold voltage Vt for the cell is above the hard read threshold 502c, then the cell is in the L3 state, and the hard bits "10" have been read. Conversely, if a read component 150 determines that the threshold voltage Vt for the cell is below the hard read threshold 502c (and above the hard read threshold 502b, which in Fig. 5), then the cell is in the L3 state and the hard bits “00” have been read.

[0077] However, due to the overlap in the distributions of cells originally programmed to the L2 and L3 states, the hard bits may be erroneous. Therefore, in the illustrated embodiment, a read component 150 uses soft read thresholds 602 to read soft bits from the cells. In the illustrated embodiment, the soft read thresholds 602 are voltages known as read voltages (as described with reference to Fig. 3) to determine whether the threshold voltage Vt of a cell is above or below the applied read voltage. However, in another embodiment, a soft read threshold used to determine soft bits may be a resistance threshold, a current threshold, or the like, depending on the type of hard read threshold used to define the states.

[0078] In various embodiments, "soft bits" can be any form of information indicating reliability of the hard bits, confidence in the hard bits, or the like. For example, in some embodiments, soft bits can be multi-bit values, such as probabilities, log-likelihoods, log-likelihood ratios, or the like. In the illustrated embodiments, the soft bits are single-bit values, with a soft bit value of "1" indicating that hard bits are more reliable and a soft bit value of "0" indicating that the hard bits are less reliable. In another embodiment, soft bit values ​​can be inverted so that a "0" indicates greater reliability. Error-correcting code (ECC) decoders can use redundant information (encoded in the data at write time and read with the hard bits) to detect and correct errors in the data.Some ECC decoders may also use soft bits to help determine which of the hard bits are in error. In some embodiments, error-correcting code decoders that use soft bits may be able to detect and correct more errors than other comparable decoders that do not use soft bits to decode data.

[0079] In the illustrated embodiment, results of sensing whether the threshold voltage Vt for a cell is above or below two soft read thresholds 602a-b may be combined with an inverted exclusive-or (NXOR) operation that outputs a 0 if the inputs are different or a 1 if the inputs are the same to determine the soft bits. For example, if the threshold voltage Vt for a cell is above both soft read thresholds 602a-b or below both soft read thresholds 602a-b, then the resulting soft bit is a "1," indicating that the threshold voltage Vt for the cell is not close to the hard read threshold 502c and that the hard bits should be treated as reliable.However, if the threshold is above the first soft read threshold 602a but below the second soft read threshold 602b, then the resulting soft bit is a "0", indicating that the threshold voltage Vt for the cell is close to the hard read threshold 502c and that the hard bits should be treated as less reliable or possibly faulty.

[0080] In the illustrated embodiment, a reading component 150 determines soft bits relative to two soft read thresholds 602 for one hard read threshold 502. In another embodiment, a reading component 150 may determine soft bits relative to more or fewer than two soft read thresholds 602 per hard read threshold 502. For example, in one embodiment, sampling using four soft read thresholds 602, two on either side of the hard read threshold 502, may provide additional soft bits to indicate different levels of confidence for the hard bits.

[0081] In another embodiment, a read component 150 may determine that errors due to drift in one direction are more likely than errors due to drift in another direction, and may determine soft bits relative to the hard read threshold 502 and a single soft read threshold 602 in the more likely drift direction from the hard read threshold 502. For example, long retention times with infrequent data access may indicate that cells are more likely to drift to lower voltage states than to higher voltage states due to charge leakage, and a read component 150 may use a single soft read threshold 602 at a lower voltage than the hard read threshold 502.Conversely, short retention times with frequent data access may indicate that cells are more likely to drift to higher voltage states than to lower voltage states due to read disturbances or program disturbances, and a read component 150 may use a single soft read threshold 602 at a higher voltage than the hard read threshold 502. In some embodiments, a read component 150 may determine a number of read thresholds 502, 602 to use for sampling and a distance of the soft read thresholds 602 from the hard read threshold 502.For example, a read component 150 may determine numbers and positions of read thresholds based on factors such as current temperature, temperature at write time, data retention time, number of program / erase cycles, error rates for reading cells of one region of an array 200, error rates for reading cells of another region of an array 200, or the like.

[0082] In certain embodiments, a read component 150 that reads hard bits and soft bits using hard and soft read thresholds 502, 602 may take significantly longer to read data than a read component 150 that reads hard bits using hard read thresholds 502 without soft read thresholds 602. Repeatedly applying different bias conditions (e.g., read voltages on a word line 310 corresponding to different hard and soft read thresholds 502, 602) and sampling the resulting conditions on bit lines 304 may significantly increase the latency of a read operation. However, in a time-based soft bit read mode, a read component 150 may sample resulting conditions on bit lines 304 (or on capacitors coupled to bit lines 304) at multiple times for a single set of applied bias conditions (e.g.,The sampling results at different times may be equivalent or comparable to the results of using different bias conditions to read soft bits. In some embodiments, sampling resulting conditions at multiple times for a single set of applied bias conditions may take significantly less time than sampling by iteratively applying different bias conditions.

[0083] Fig. 7 and Fig. 8 illustrate a sense amplifier 700 in some embodiments. In certain embodiments, as described above, bitline bias / sense circuits 302 may include sense amplifiers 700 coupled to the bitlines 304 of a memory array 200. In various embodiments, sense amplifiers 700 may convert analog electrical characteristics on the bitlines 304, such as bitline voltages or currents, into digital results, such as logic levels or data values.

[0084] As in Fig. 7, in one embodiment, a sense amplifier 700 includes a current-to-voltage conversion circuit 702 and a voltage-to-digital conversion circuit 706. In various embodiments, a current-to-voltage conversion circuit 702 may be coupled to a bit line 304 and generate a voltage in the sense amplifier 700 (e.g., at node 704) based on a bit line current, such that the state of a cell coupled to the bit line 304 affects the analog sense amplifier voltage at node 704.

[0085] In various embodiments, a current-to-voltage conversion circuit 702 may convert bitline currents into analog sense amplifier voltages in various ways. For example, in one embodiment, a current-to-voltage conversion circuit 702 may use the bitline current to charge or discharge a capacitor such that the voltage across the capacitor is an analog voltage based on the bitline current. In another embodiment, a current-to-voltage conversion circuit 702 may use the inherent capacitance of the bitline 304 (e.g., its self-capacitance and / or its parasitic mutual capacitance with nearby components such as other bitlines 304) as a capacitor, generating an analog voltage without providing a separate or discrete capacitor for charging or discharging.In another embodiment, a current-to-voltage conversion circuit 702 may convert a bitline current to a voltage by passing the current through a resistor (e.g., to ground or another reference voltage) such that the voltage drop across the resistor depends on the bitline current. In another embodiment, a current-to-voltage conversion circuit 702 may include a bipolar transistor controlled by the input current. Various other or further components capable of generating an analog voltage based on the electrical state of a bitline 304 (which, in turn, is based on the state or data value stored by a cell) may be used in a current-to-voltage conversion circuit 702.

[0086] In the illustrated embodiment, sense amplifier 700 includes a voltage-to-digital conversion circuit 706 that converts analog voltages into digital sense amplifier results. In the illustrated embodiment, voltage-to-digital conversion circuit 706 converts an analog voltage at node 704 from current-to-voltage conversion circuit 702 into a digital sense amplifier result on an output line 708. The output line 708 of the sense amplifier may be coupled to circuitry that uses a digital result, such as latches that store and output a result, an error correction code decoder, or the like. Circuitry that uses a digital result may include column circuits 204, a die controller 206, or the like.

[0087] The term "digital," as used herein, can refer to any voltage, current, or other signal that is discretized or limited to a finite number of logic levels that represent data. For example, in one embodiment, a high logic level may represent a binary one, while a low logic level represents a binary zero. In another embodiment, four different logic levels may represent four different two-bit data values, eight logic levels may represent eight different three-bit data values, or the like. A logic level may be a value or a permissible range of values ​​for the voltage, current, or other discretized signal. The term "analog," on the other hand, can be used herein to refer to any voltage, current, or other signal that is not digital or not limited to a finite number of logic levels.

[0088] In certain embodiments, whether a signal is digital or analog may depend on the presence of defined logic levels. For example, an analog signal can be interpreted as a digital signal by defining logic levels that determine whether the signal represents a 0 or a 1 at a given time. (However, in the absence of a gap between permissible logic levels, such a signal may not be reliable for representing data, as a small amount of noise can change the represented data value.) Conversely, a digital signal may resemble an analog signal during transitions between logic levels or due to noise, voltage drift, or the like.However, in certain embodiments, the term "digital" may specifically refer to voltages, currents, or other signals that are directly usable as logic inputs by electronic components of a device, such as logic gates, latches, or the like of a non-volatile memory element 123. Conversely, the term "analog" may refer to voltages, currents, or other signals that are not directly usable as logic inputs by other electronic components of a device, even if the voltages, currents, or other signals represent or correspond to a data value in some sense.

[0089] In various embodiments, a voltage-to-digital conversion circuit 706 may digitize an analog sense amplifier voltage by converting the analog voltage into a digital signal, referred to herein as a sense amplifier result. The sense amplifier results may include hard bits and / or soft bits, as described above. In various embodiments, a voltage-to-digital conversion circuit 706 may convert analog sense amplifier voltages into digital sense amplifier results in various ways. For example, in one embodiment, the voltage-to-digital conversion circuit 706 may include a transistor that is turned on or off based on a gate-to-source voltage, where the gate (or source) of the transistor is coupled to the voltage at node 704, and where the source (or gate) of the transistor is coupled to a reference voltage or to ground.In another embodiment, voltage-to-digital conversion circuit 706 may include a comparator, and the input terminals of the comparator may be coupled to the voltage at node 704 and a reference voltage. In another embodiment, voltage-to-digital conversion circuit 706 may include a pair of inverters connected in a loop, with the voltage at node 704 and a reference voltage coupled to opposite sides of the loop, such that the feedback amplifies the difference between the voltages to digital levels. Various other or further components capable of converting an analog voltage at sense amplifier 700 into a digital sense amplifier result may be used in voltage-to-digital conversion circuit 706.

[0090] Fig. Figure 8 illustrates another embodiment of a sense amplifier 700 that is substantially similar to that described above with reference to Fig. 7, including a current-to-voltage conversion circuit 702 and a voltage-to-digital conversion circuit 706, which may be substantially as described above. In the illustrated embodiment, the current-to-voltage conversion circuit 702 includes a capacitor 804. In various embodiments, capacitors 804 associated with cells may be capacitors 804 in the sense amplifiers 700 that are coupled to cells via the bit lines 304. Capacitors 804 may be charged or discharged via electrical currents in bit lines 304. For example, in one embodiment, a capacitor 804 may be precharged or predischarged, then coupled to a bit line 304 for a period of time (e.g., while the switching transistor 802 is on) to discharge (or charge) the capacitor 804 via the bit line current.After a period of time, the voltage across capacitor 804 depends on the extent to which capacitor 804 has been charged or discharged via the bit line current.

[0091] Although the current-to-voltage conversion circuit 702 is shown in the illustrated embodiment as including a capacitor 804 and a switching transistor 802, another embodiment of a current-to-voltage conversion circuit 702 may include more or fewer components. For example, in one embodiment, the switching transistor 802 may be omitted, so that the capacitor 804 is directly coupled to the bit line 304 and initially precharged by the bit line bias / sense circuits 302. In another embodiment, a discrete capacitor 804 may be omitted, and a sense amplifier 700 may use the capacitance of the bit line 304 itself as a source of an analog voltage to be digitized. In another embodiment, a current-to-voltage conversion circuit 702 may include additional circuitry described in Fig. 8 are not shown, such as a capacitor bias circuit that sets an initial bias for capacitor 804, separate from a circuit that applies bias conditions to a bit line 304.

[0092] In the illustrated embodiment, voltage-to-digital conversion circuit 706 includes a sampling transistor 806. The source terminal of sampling transistor 806 is coupled to ground (or another reference voltage in another embodiment), and the gate terminal of sampling transistor 806 is coupled to the analog voltage generated by current-to-voltage conversion circuit 702 at node 704. Sampling transistor 806 generates a digital sense amplifier result on output line 708, which is stored in one or more data latches 808. Data latches 808 may store hard bits and soft bits for output or for use by other components, such as an error correction code decoder.

[0093] In the illustrated embodiment, the output line 708 can be precharged (via the Fig. 8 (circuit not shown). If the voltage at node 704 is insufficient to turn on the sampling transistor 806, the output line 708 remains high, and the digital sampling amplifier result recorded by the data latches 808 is a binary "1." (The latches 808 may be gated, edge-triggered, or the like to latch the result from the output line 708 at a particular time.) If the voltage at node 704 is sufficient to turn on the sampling transistor 806, then the output line 708 is pulled low, and the digital sampling amplifier result recorded by the data latches 808 is a binary "0."

[0094] In the illustrated embodiment, sense transistor 806 is an NMOS transistor that turns on when the voltage at node 704 is high. In another embodiment, sense transistor 806 may be a PMOS transistor that turns off when the voltage at node 704 is high. In various embodiments, sense transistor 806 may be an n-channel transistor, a p-channel transistor, an enhancement-mode transistor, a depletion-mode transistor, a junction field effect (JFET) transistor, or any other transistor or switching element that turns on or off based on an applied voltage. Similarly, output line 708 may initially be high and pulled low when sense transistor 806 turns on or off, or may initially be low and pulled high when sense transistor 806 turns on or off.

[0095] Although voltage-to-digital conversion circuit 706 includes a sampling transistor 806 in the illustrated embodiment, voltage-to-digital conversion circuit 706 in another embodiment may include various components for sampling analog capacitor voltages and generating a digital sense amplifier result. For example, voltage-to-digital conversion circuit 706 may include a comparator, a latch, a tri-state buffer, or another component capable of outputting a digital result.

[0096] Fig. 9 illustrates one embodiment of a reading component 150. In various embodiments, a reading component 150 may be configured substantially as described above with reference to the Fig. 1-8 and may include or communicate with bias circuits 302, 308, 314, a sense amplifier 700, or the like. In the illustrated embodiment, the read component 150 includes a read mode module 902, a bias module 904, and a sense module 906, which are described below.

[0097] In general, in various embodiments, the read component 150 may select between a plurality of read modes for reading data from a non-volatile memory array and may implement or control a read operation using the selected read mode. Different read modes may reflect different trade-offs between reliability and speed and may differ in aspects such as whether soft bits are obtained, how many soft bits are obtained for each hard bit, how the soft bits are obtained, or the like. Providing multiple read modes may enable a read component 150 to avoid high-latency read times or high error rates by selecting a read mode based on conditions such as time since data was written, temperature difference since data was written, or the like.

[0098] The read mode module 902, in the illustrated embodiment, is configured to select a read mode from a plurality of read modes for reading data from a portion of the non-volatile memory array 200. A read mode may, in various embodiments, refer to a manner of reading data from memory cells. For example, a read component 150 that selects or uses a first read mode may perform a particular series of steps to read data from memory cells, but may perform a different series of steps to read data from memory cells when selecting or using a second read mode. In some embodiments, selecting a read mode may include determining whether to use a time-based soft-bit read mode to read data from a portion of the non-volatile memory or whether to use a different read mode.

[0099] The read component 150 may use a read mode selected or determined by the read mode module 902 to perform a read operation that reads data from a region of a non-volatile memory array 200. A region from which data is read in a read operation may be based on the granularity of a read operation. For example, a region from which data is read may be eight cells for a byte-level read operation, or cells of a row or layer of an array for a page- or block-level read operation.

[0100] In the illustrated embodiment, the plurality of read modes (e.g., possible read modes) from which the read mode module 902 selects a read mode for reading data includes at least one time-based soft-bit read mode. In various embodiments, a time-based soft-bit read mode may be a mode in which a read component 150 performs a read operation performed by applying a single set of bias conditions to a range of cells and sampling resulting conditions (e.g., bitline currents, capacitor voltages, or the like) at multiple times. For example, a read operation in a time-based soft-bit read mode may include repeatedly digitizing capacitor voltages (or other analog sense amplifier voltages) to read both hard bits and soft bits.In further embodiments, a time-based read mode may involve reading soft bits without reapplying a new set of bias conditions to the range of cells.

[0101] For example, as described above, a sense amplifier 700 may output a digital result based on whether a voltage across a capacitor 804 meets (or fails to meet) a threshold to turn on (or off) a sense transistor 806. The voltage across capacitor 804 may integrate or sum a bitline current over time, where the bitline current depends on bias conditions applied to a cell and the state of the cell. If the bias conditions result in a high bitline current, from a transistor-based cell 306 being turned on, or from a resistor-based cell 406 being in a low-resistance state, then the capacitor 804 may be rapidly charged or discharged by the bitline current.Conversely, if bias conditions result in low or zero bitline current from a transistor-based cell 306 that is off or from a resistor-based cell 406 that is in a high-resistance state, then the capacitor 804 may be charged or discharged more slowly or not at all by the bitline current. Thus, sampling or digitizing the capacitor voltage after a certain period of time can identify whether the capacitor 804 is charged or discharged, thereby distinguishing between high bitline currents and low bitline currents, and between different states of a cell corresponding to different bitline currents.

[0102] Sampling or digitizing the capacitor voltage at multiple times may generate soft bits corresponding to soft read thresholds 602, as described above with reference to Fig. 6, without reapplying different bias conditions for different read thresholds 502, 602. When a single set of bias conditions is applied, a bitline current sufficient to charge or discharge a capacitor 804 above the threshold to switch a sense transistor 806 at a nominal integration time for reading the hard bits may be either a high bitline current that quickly charges or discharges the capacitor 804 above the threshold, or may be a medium bitline current that slowly charges or discharges the capacitor 804 above the threshold.Similarly, if the bitline current is insufficient to charge or discharge capacitor 804 above the threshold at the nominal integration time for reading the hard bits, the bitline current may be a low bitline current or a medium bitline current that would have charged or discharged capacitor 804 above the threshold after a slightly longer period of time. Sampling the capacitor voltage (e.g.,Digitizing the analog capacitor voltage by determining whether a sense transistor 806 has switched, or by using another type of voltage-to-digital conversion circuit 706, at one or more additional integration times before and / or after the nominal integration time may enable a sense component 150 to distinguish between higher, lower, and medium bitline currents to obtain a result corresponding to applying higher and lower read voltages to a cell's control gate as bias conditions. Read operations for a time-based soft-bit read mode are described in more detail below with reference to the bias module 904 and the sense module 906.

[0103] In various embodiments, a read mode module 902 selects a read mode from a plurality of read modes that includes at least one time-based soft bit read mode. In further embodiments, a plurality of read modes includes at least one other read mode in addition to the time-based soft bit read mode. For example, in various embodiments, a plurality of read modes may include a hard bit read mode in which the read component 150 reads hard bits without soft bits, and / or a bias-based soft bit read mode in which the read component 150 reads hard bits and soft bits by iteratively applying different bias conditions and sampling the resulting capacitor voltages.In some embodiments, a plurality of read modes may include more than one time-based soft-bit read mode, where the different time-based soft-bit read modes define different parameters for sampling results at multiple integration times. For example, reads in different time-based soft-bit read modes may include different numbers of integration times, different spacing between integration times, or the like. Similarly, in some embodiments, a plurality of read modes may include more than one bias-based soft-bit read mode defining different parameters, such as a number of soft read thresholds 602, spacing between soft read thresholds 602, or the like.Various other or additional read modes may be defined for performing read operations and may be included in a plurality of read modes from which the read mode module 902 selects a read mode.

[0104] In various embodiments, a read mode module 902 may select a read mode from a plurality of read modes in various ways. For example, the selection of a read mode may be based on an error rate, a data retention time, a number of program / erase cycles, a current temperature, or the like. In general, in various embodiments, a time-based soft-bit read mode may have medium latency and reliability compared to a low-latency, low-reliability hard-bit read mode (in which errors are more likely to be uncorrectable due to the lack of soft bits) or a high-latency, bias-based, high-reliability soft-bit read mode.

[0105] In fact, due to the high latency associated with iteratively applying different bias conditions, some die controllers 206 may read data using a bias-based soft-bit read mode as an exception to handle read errors that were uncorrectable when reading data in a lower-latency read mode (e.g., a hard-bit read mode). However, due to the lower latency of a time-based soft-bit read mode, a controller, such as device controller 126 or die controller 206, may, in some embodiments, use the time-based soft-bit read mode as the default read mode.With the time-based soft-bit read mode as the default read mode, a controller can perform read operations as defined by the time-based soft-bit read mode as a standard or default type of read operation, and can use other read modes in response to specific conditions, such as an explicit command to perform an operation in a different read mode, with a high error rate, or the like. In various embodiments, using a time-based soft-bit read mode as the default read mode can provide smooth read performance because a decoder has consistent access to soft bits without the high-latency error handling of rereading in a bias-based soft-bit read mode when a hard-bit read has uncorrectable errors.

[0106] In some embodiments, the read mode module 902 may select a read mode from a plurality of read modes based on information included in a read command received from a controller, such as a device controller 126 or a die controller 206. Information included in a read command may include the read command itself and / or any parameters of the read command. For example, in one embodiment, a command set for a non-volatile memory element 123 may include different read commands for different read modes, thereby allowing the read mode to be specified by a user, an application, an operating system, a device driver, a device controller 126, or the like, and the read mode module 902 may select a read mode according to the read mode specified by a read command.In another embodiment, different parameters for a read command may specify different read modes, and the read mode module 902 may select a read mode based on the value of a parameter for a read command, the presence or absence of a parameter for a read command, or the like. Various other or additional types of information that may be included in a read command may similarly be used by the read mode module 902 to select a read mode.

[0107] In some embodiments, the read mode module 902 may select a read mode for reading data from a region of a storage array 200 based on factors such as metadata for the region, error correction information for the region, metadata or error correction information for another region of the storage array 200, or the like. Other ways for a read mode module 902 to select a read mode are described below with reference to the metadata module 1010, the error correction module 1012, and the current conditions module 1014 of Fig. 10 described in more detail.

[0108] The biasing module 904 in the illustrated embodiment is configured to apply a set of bias conditions to cells of a region of a memory array 200. In various embodiments, when data is read from a region of an array 200, such as cells of a byte, page, or block, the read mode module 902 may select a read mode for the region, and the biasing module 904 may apply bias conditions to the region. In some embodiments, a biasing module 904 that applies bias conditions to cells in a region from which data is being read may apply further bias conditions to cells outside the region. For example, to read data from cells in a row of a NAND flash memory array, the biasing module 904 may apply a read bias via a word line 310 to cells in the row and may apply a high control gate voltage to cells of other rows.

[0109] As mentioned above with reference to the Fig. 3 and Fig. 4, bias conditions applied to cells may be electrical conditions, such as bias voltages, bias currents, or the like, and may be conditions that are maintained in a steady state for a period of time during a read operation (e.g., control gate voltages for reading from flash memory cells) or may be transient conditions that are allowed to deviate from an initially applied value (e.g., bitline precharge voltages). In some embodiments, applying bias conditions to cells may include applying precharge or bias voltages (or other electrical conditions) to peripheral components coupled to the cells, such as by precharging a capacitor 804 of a sense amplifier 700.In various embodiments, bias conditions may be any set of voltages, currents, or other conditions that, when applied to cells in a region of a memory array 200, result in another condition, such as a bitline current or a capacitor voltage, that depends on the state of one or more cells.

[0110] In various embodiments, bias module 904 may apply bias conditions to cells using circuitry such as bitline bias / sense circuitry 302, wordline bias circuitry 308, and / or source bias circuitry 314 coupled to the cells via bitlines 304, wordlines 310, and / or source lines 312. In various embodiments, bias module 904 may include or communicate with one or more bias circuitry 302, 308, 314.

[0111] In various embodiments, a biasing module 904 may apply bias conditions to cells of a region of an array 200 such that bitline currents associated with the cells of the region affect voltages on capacitors associated with the cells of the region. Bitline currents associated with the cells, in various embodiments, may be electrical currents in bitlines 304 coupled to the cells. In various embodiments, a current may be a positive current (e.g., in a direction defined as positive), a negative current (e.g., in a direction opposite to the direction defined as positive), or a zero current. The term "current" may be used herein to refer to a flow rate of electrical charge, whether the rate is zero or non-zero.

[0112] In various embodiments, capacitors associated with cells may be electrical components with a capacitance coupled to the cells or the bitlines 304. In one embodiment, capacitors associated with cells may be sense amplifier capacitors 804, as described above. In another embodiment, capacitors associated with cells may be the bitlines 304 themselves, including their capacitance relative to nearby components. A bitline current may affect a voltage across an associated capacitor by charging the capacitor, discharging the capacitor, or leaving the capacitor voltage unchanged (in the case of zero current).Thus, just as bitline currents can be positive, negative, or zero in various embodiments, capacitor voltages affected by bitline currents can be increased, decreased, or left unchanged by the bitline currents. Even if a capacitor voltage is unchanged due to a zero bitline current in a bitline 304 coupled to a capacitor 804, the capacitor voltage can be said to be "affected" by the bitline current because it is a result of the bitline current in the sense that a different bitline current would have produced a different capacitor voltage.

[0113] As mentioned above with reference to the Fig. 7 and Fig. 8, in some embodiments, a sense amplifier 700 may convert a bitline current into an analog sense amplifier voltage in various ways using various types of current-to-voltage conversion circuits 702. In various embodiments, bias voltages or other biasing conditions applied by the bias module 904 may affect analog voltages at sense amplifiers 700 associated with a cell. Analog voltages at sense amplifiers 700 associated with cells may include voltages generated by a current-to-voltage conversion circuit 702 coupled to a bitline 304. Sense amplifiers 700 associated with cells may include sense amplifiers 700 coupled to cells, such as sense amplifiers 700 in the bitline bias / sense circuits 302 that are coupled to cells via bitlines 304.

[0114] As described above with reference to capacitor voltages, analog sense amplifier voltages can be affected by bias conditions or bitline currents if the analog voltages result from the bias conditions or bitline currents, regardless of whether the resulting voltage would be increased, decreased, or left unchanged in a particular set of conditions such as zero bitline current if the resulting voltage had been changed in response to a different set of bias conditions or a different bitline current.

[0115] Sense module 906, in the illustrated embodiment, is configured to sample capacitor voltages resulting from a set of bias conditions applied by bias module 904. In response to read mode module 902 selecting the time-based soft-bit read mode, sense module 906 is configured to sample capacitor voltages at multiple integration times. Sense module 906 may include or communicate with various components for sampling capacitor voltages, converting analog voltages at sense amplifiers 700 into digital sense amplifier results, or digitizing sense amplifier results, such as sense transistor 806, voltage-to-digital conversion circuitry 706, sense amplifier 700, and / or bitline bias / sense circuitry 302.

[0116] In the illustrated embodiment, in response to the read mode module 902 selecting the time-based soft bit read mode for reading data from a region of a memory array, the sampling module 906 is configured to read hard bits and soft bits for the region by sampling capacitor voltages or otherwise converting analog voltages into a digital result at multiple integration times. As described above, hard bits may be data values ​​read from the cells, which may be data values ​​stored by the cells but are subject to errors that may have occurred while writing, retaining, or reading the data, while soft bits may be information indicating the reliability of the hard bits, confidence in the hard bits, error probabilities for the hard bits, or the like.A sensing module 906 may read hard bits and soft bits by determining the hard bits and soft bits based on capacitor voltages or other analog conditions corresponding to cell states.

[0117] The term "integration time" may, in various embodiments, refer to times at which capacitor voltages or other analog sense amplifier voltages are sampled or digitized. In particular, in some embodiments, an integration time may refer to a period of time during which a capacitor 804 integrates or sums an electrical current such that the resulting amount of charge on capacitor 804 generates a capacitor voltage. In such an embodiment, an integration time may begin when a bitline current is coupled to capacitor 804 (e.g., via switching transistor 802) and may end when the capacitor voltage is digitized or sampled.In another embodiment, an integration time may refer more generally to a period of time during which bias conditions generate analog sense amplifier voltages based on data values ​​stored by memory cells. The term integration time may be used interchangeably to refer to periods of time that end when analog voltages are digitized or sampled, or to the time when analog voltages are digitized or sampled.

[0118] With reference to time periods, multiple integration times may be overlapping time periods that begin at a common time relative to the bias module 904 applying bias conditions and that end at different times for sampling and digitizing capacitor voltages or other analog sense amplifier voltages. With reference to times, multiple integration times may be different times for sampling or digitizing the analog sense amplifier voltages resulting from a single applied set of bias conditions.

[0119] The term "multiple integration times" is used herein to refer to sampling and digitizing analog sense amplifier voltages resulting from a single application of bias conditions to cells at multiple times, when the analog sense amplifier voltage is based on that application of bias conditions to the cells. For example, bias conditions may be applied to cells so that a capacitor voltage evolves over time based on the bias conditions and on the data values ​​stored by the cells, and sampling at multiple integration times may involve repeatedly sampling or digitizing the capacitor voltage at multiple times as it charges or discharges in response to the initially applied bias conditions.

[0120] The term "multiple integration times" is not used herein to refer to times separated by the bias module 904 applying a different set of bias conditions. For example, in a bias-based soft bit read mode, a controller may iteratively apply different bias conditions and convert resulting analog sense amplifier voltages into digital sense amplifier results. Although multiple iterations of the bias, integration, and sampling process might each involve sampling a capacitor voltage at an integration time, the integration times separated by applying different bias conditions are not referred to as multiple integration times.Rather, in various embodiments, a sampling module 906 that samples at multiple integration times samples capacitor voltages (or other analog sense amplifier voltages) at multiple times in response to a single application of bias conditions by the bias module 904, without the bias module 904 reapplying other bias conditions.

[0121] In various embodiments, sampling capacitor voltages or other analog voltages may include using a voltage-to-digital conversion circuit 706 to generate a digital sense amplifier result and / or receiving or storing the digital sense amplifier result (e.g., in data latches 808). Thus, to sample capacitor voltages at multiple integration times, a sampling module 906 may control the timing of sense amplifier components. For example, with reference to Fig. 8, the capacitor 804 is directly coupled to the gate terminal of the sampling transistor 806, and the sampling transistor 806 can be turned on any time the capacitor voltage exceeds the threshold voltage for the sampling transistor 806. Thus, to sample the capacitor voltage at multiple integration times, the sampling module 906 can control or trigger data latches 808 so that the result on the output line 708 is latched into different data latches 808 at different integration times.In another embodiment, a sampling module 906 may control a switching component, such as a transistor that couples or decouples capacitor 804 (or the analog voltage at node 704) to sampling transistor 806 (or other voltage-to-digital conversion circuit 706), and may sample the analog voltage at multiple integration times by coupling the analog voltage to sampling transistor 806 at those integration times. Various other or further components of a sampling amplifier 700 may be similarly controlled by a sampling module 906 to sample or digitize capacitor voltages at multiple integration times.

[0122] In some embodiments, a sampling module 906 may read or determine hard bits and soft bits based on the digital sense amplifier results from multiple integration times. In one embodiment, hard bits may be bits read by a sampling module 906 at one of the multiple integration times; a soft bit may be calculated by the sampling module 906 based on the extent to which the bits from the other integration times agree or disagree with the hard bit result. In another embodiment, hard bits may be a "consensus" or majority result from multiple integration times, and soft bits may indicate a ratio or other measurement of how many of the integration times produced a result that differs from the hard bits.Various other or additional ways of combining digital sample amplifier results from multiple integration times may be used by a sampling module 906 to determine hard bits and soft bits.

[0123] Fig. Figure 10 illustrates another embodiment of a reading component 150. In the illustrated embodiment, the reading component 150 may be substantially similar to the embodiments described above with reference to Figures Fig. 1-9, including a read mode module 902, a bias module 904, and a scan module 906. In the illustrated embodiment, the read mode module 902 includes a hard bit read module 1002, a time-based soft bit read module 1004, and a bias-based soft bit read module 1006. In the illustrated embodiment, the read component 150 includes an integration time selection module 1008, a metadata module 1010, an error correction module 1012, and a current conditions module 1014.

[0124] In the illustrated embodiment, the plurality of read modes selectable by the read mode module 902 includes a time-based soft-bit read mode, as described above, as well as a hard-bit read mode and a bias-based soft-bit read mode. In response to the read mode module 902 selecting the time-based soft-bit read mode, the time-based soft-bit read module 1004 may communicate with the bias module 904 and the sampling module 906 to perform a time-based soft-bit read, as described above, including sampling or digitizing capacitor voltages resulting from an applied set of bias conditions at multiple integration times.

[0125] The hard-bit read module 1002, in the illustrated embodiment, is configured to communicate with the bias module 904 and the sensing module 906 to perform a hard-bit read in response to the read mode module 902 selecting a hard-bit read mode from the plurality of read modes. In the hard-bit read mode, the sensing module 906 may read hard bits for a range of memory cells by sampling the capacitor voltages (or other analog sense amplifier voltages) resulting from a set of bias conditions applied by the bias module 904 at a single integration time. In a hard-bit read mode, sampling at a single integration time may not provide enough information to read or determine soft bits, but may provide hard bits with lower latency than in a soft-bit read mode.In some embodiments, a read mode module 902 may select a hard-bit read mode when an error rate is expected to be low (e.g., at or below a rate correctable by an error correction code decoder without using soft bits), for example, when the data retention time is less than a threshold, program / erase counts are less than a threshold, error rates for reading data for other areas of the array 200 are low, or the like.

[0126] The bias-based soft-bit read module 1006, in the illustrated embodiment, is configured to communicate with the bias module 904 and the sampling module 906 to perform a bias-based soft-bit read in response to the read mode module 902 selecting a bias-based soft-bit read mode from the plurality of read modes. In the bias-based soft-bit read mode, the bias module 904 and the sampling module 906 may cooperate to iteratively apply different bias conditions and sample resulting capacitor voltages. The bias module 904 may apply a set of bias conditions, and the sampling module 906 may sample or digitize the capacitor voltages (or other analog sense amplifier voltages) resulting from the applied set of bias conditions, as described above.The bias module 904 may then apply one or more additional sets of bias conditions (at different bias / sampling iterations for each set of bias conditions), and the sampling module 906 may sample or digitize the capacitor voltages (or other analog sense amplifier voltages) resulting from the additional applied set of bias conditions. The sampling module 906 may combine multiple results from the different sets of bias conditions in a manner similar to that described above to combine digital sense amplifier results from multiple integration times to read or determine hard bits and soft bits for a range of memory cells.

[0127] In various embodiments, a bias-based soft-bit read using results from multiple sets of applied bias conditions may have a higher latency than a time-based soft-bit read due to the repeated application of bias conditions. However, in some embodiments, a bias-based soft-bit read may provide greater reliability or better error correction than the time-based soft-bit read mode. Thus, in some embodiments, a read mode module 902 may select a high-latency, high-reliability bias-based soft-bit read mode when an error rate is expected to be high (e.g.,above a rate correctable by an error correction code decoder using soft bits from a time-based soft bit read), for example, when the data retention time is above a threshold, program / erase counts are above a threshold, data read error rates for other areas of the array 200 are high, or the like.

[0128] In some embodiments, the time-based soft bit read module 1004 may provide multiple time-based soft bit read modes with different integration times, different numbers of integration times, or the like. In one embodiment, the read mode module 902 may select from a plurality of read modes, including a first time-based soft bit read mode and a second time-based soft bit read mode. In the first time-based soft bit read mode, the time-based soft bit read module 1004 may communicate with the sampling module 906 to sample or digitize capacitor voltages at two integration times. In the second time-based soft bit read mode, the time-based soft bit read module 1004 may communicate with the sampling module 906 to sample or digitize capacitor voltages at three integration times.The different time-based soft-bit read modes may reflect different trade-offs between reliability (from sampling to more integration times) and speed (from sampling to fewer integration times).

[0129] In various embodiments, the metadata module 1010 may record metadata for portions of a non-volatile memory array 200 (e.g., bytes, pages, blocks, or the like) at write time and / or may retrieve metadata at read time. In certain embodiments, the likelihood of data errors may depend on factors such as time and temperature. If data is read after a long retention time, or at a temperature significantly different from the time the data was written, errors may be more likely than if data is read after a short retention time, or at a temperature similar to the time the data was written. Thus, in some embodiments, the metadata module 1010 may record time and temperature metadata for a portion of memory cells at write time.In various embodiments, a metadata module 1010 may store and retrieve various other or additional types of metadata for different areas, such as program / erase cycle counts, error rates for previous reads, or the like.

[0130] Time metadata can include any information recording or corresponding to a write time, such as a date stamp, a time elapsed since a predefined epoch, a counter value for a periodically incremented counter, or the like. Similarly, temperature metadata can include any information recording a temperature at the write time, such as a Celsius temperature, a Fahrenheit temperature, an indication of whether a temperature was high or low relative to a predefined threshold, or the like.

[0131] The current conditions module 1014, in certain embodiments, may determine current conditions for values ​​recorded by the metadata module 1010, such as a current time and / or a current temperature. The current conditions module 1014, in some embodiments, may include or communicate with circuitry for determining current time or temperature conditions, such as clock circuits, counters, thermocouples, thermistors, or the like. At write time, the metadata module 1010 may record metadata based on current conditions from the current conditions module 1014. At read time, the read mode module 902, in some embodiments, may select a read mode based on metadata from the metadata module 1010 and / or based on current conditions from the current conditions module 1014.

[0132] In one embodiment, the read mode module 902 may select a read mode for reading data from a region of a memory array 200 based on metadata recorded by the metadata module 1010 at write time for the region. For example, in one embodiment, the read mode module 902 may select between a hard-bit read mode, a time-based soft-bit read mode, and / or a bias-based soft-bit read mode based on metadata such as a time / temperature tag indicating a time and temperature at write time for a region, a program / erase cycle count, or the like.

[0133] In some embodiments, the read mode module 902 may select a read mode for reading data from a region of a storage array 200 based on a comparison of the current time and temperature obtained from the current conditions module 1014 with time and temperature metadata recorded at write time for the region obtained from the metadata module 1010. For example, the read mode module 902 may select between lower latency, lower reliability read modes and higher latency, higher reliability read modes based on a time difference between write time and read time and / or a temperature that differs between write time and read time.

[0134] The error correction module 1012, in the illustrated embodiment, is configured to use hard bits and / or soft bits from the sampling module 906 to detect and correct data errors. In various embodiments, an error correction module 1012 may include or communicate with one or more error correction code decoders, such as a hard-decision decoder that uses hard bits without soft bits and / or a soft-decision decoder that uses hard bits and soft bits to detect and correct errors. In certain embodiments, the error correction module 1012 may provide error correction information to the read mode module 902. Error correction information may include information about raw error rates, correctable error rates, uncorrectable error rates, or the like.

[0135] In some embodiments, the read mode module 902 may select a read mode for reading data from a region of a memory array based on error correction information for a region obtained from the error correction module 1012. For example, if a previous read operation for the region resulted in uncorrectable errors or a significant error correction latency to decode data with a large number of correctable errors (e.g., relative to a predefined threshold), the read mode module 902 may transition to a higher-latency, higher-reliability read mode for reading data from that region. Conversely, if a previous read operation for the region resulted in a fewer number of correctable errors relative to a predefined threshold, the read mode module 902 may transition to a lower-latency, lower-reliability read mode for reading data from that region.

[0136] In some embodiments, read mode module 902 may select a read mode for reading data from a region of a storage array 200 based on error correction information and / or metadata for one or more other regions of the array 200. In one embodiment, read mode module 902 may identify or determine groups of regions (e.g., bytes, pages, blocks, or the like) with similar metadata. For example, if metadata module 1010 records write-time time and temperature metadata for regions of an array, read mode module 902 may use time-based thresholds to define groups of regions written to at similar times and / or may use temperature-based thresholds to define groups of regions written to at similar temperatures.In another embodiment, a group of ranges may include ranges for which both the data retention time and the write-time temperature are similar (e.g., within thresholds). Thresholds for defining groups may be predefined by a manufacturer, dynamically defined based on error rates for different data retention times or temperatures, or the like.

[0137] In some embodiments, the read mode module 902 selecting a read mode for a first region based on error correction information and / or metadata for a second region may include selecting a read mode for a group of regions defined based on metadata, where the group of regions includes the first region and the second region. In another embodiment, the read mode for the group of regions (and thus for reading data from the first region) may be based on error correction information generated by the error correction module 1012 when decoding data from the second region. For example, if a read operation for the second region results in uncorrectable errors or in a significant error correction latency for decoding data with a large number of correctable errors (e.g.,relative to a predefined threshold), the read mode module 902 may transition to a higher latency, higher reliability read mode for reading data from regions in the group. Conversely, if a read for the second region resulted in a lower number of correctable errors relative to a predefined threshold, the read mode module 902 may transition to a lower latency, lower reliability read mode for reading data from regions in the group.

[0138] The integration time selection module 1008, in the illustrated embodiment, is configured to select integration times used by the sampling module 906 for sampling at multiple integration times. In some embodiments, the multiple integration times used by the sampling module 906 in the time-based soft-bit read mode may include a set of integration times selected by the integration time selection module 1008. A set of integration times, in various embodiments, may include integration times defined in various ways, such as numbers of microseconds or nanoseconds since a start time, numbers of clock pulses since a start time, differences from a nominal integration time or a hard-bit integration time, or the like.Various other or additional ways of indicating a time for sampling or digitizing capacitor voltages (or other analog sense amplifier voltages) may be used by an integration time selection module 1008 to define or select a set of integration times for use by the sampling module 906.

[0139] In one embodiment, the integration time selection module 1008 may select integration times based on information included in a read command. For example, a read command itself or parameters of a read command may directly indicate integration times, or may indicate other information that an integration time selection module 1008 uses to select integration times. In another embodiment, the integration time selection module 1008 may select integration times for reading data from a region of an array 200 based on metadata for the region, error correction information for the region, error correction information for a second region or group of regions of the non-volatile memory array, and / or metadata recorded at write time for the second region or group of regions.Factors described above that may be used by the read mode module 902 to select a read mode may similarly be used by the integration time selection module 1008 to select integration times.

[0140] For example, in one embodiment, the integration time selection module 1008 may select an average, central, or nominal integration time for reading hard bits from a range of cells based on information such as a temperature difference since the write time, a data retention time, a program / erase cycle count, or the like. In some embodiments, the integration time selection module 1008 may select an average, central, or nominal integration time for reading hard bits based on a likely direction or amount of drift in the data-storing physical property of a cell.For example, the integration time selection module 1008 may select a hard-bit integration time corresponding to a lower hard read threshold 502 when the data retention time exceeds a threshold (indicating that charge leakage is likely), or may select a hard-bit integration time corresponding to a higher hard read threshold 502 when a number of operations for other areas exceeds a threshold (indicating that read disturb or program disturb errors are likely).

[0141] In another embodiment, the integration time selection module 1008 may select a number of soft-bit integration times (e.g., integration times for reading soft bits, in addition to a central or nominal integration time for reading hard bits) and / or may select one or more time differences between soft-bit integration times and the hard-bit integration time. For example, referring to the Fig. 5 and Fig. 6, where errors are associated with broadening and overlap of the peaks representing distributions of threshold voltages for cells in different states, the integration time selection module 1008 may select soft-bit integration times that are closer to a hard-bit integration time when a small amount of broadening and overlap is likely, or may select soft-bit integration times that are farther from a hard-bit integration time when a larger amount of broadening and overlap is likely. In another embodiment, the integration time selection module 1008 may increase the number of soft-bit integration times when a larger amount of broadening and overlap is likely.Thus, in some embodiments, the integration time selection module 1008 may select a number of soft-bit integration times and / or time differences between soft-bit integration times and the hard-bit integration time based on one or more factors associated with errors, such as a data retention time, a temperature shift, a read count, a program / erase cycle count, or the like.

[0142] Fig. 11 is a flowchart illustrating one embodiment of a method 1100 for reading data. The method 1100 begins, and a read mode module 902 determines 1102 whether to use a time-based soft-bit read mode to read data from a region of non-volatile memory. In response to the read mode module 902 determining 1102 that a time-based soft-bit read mode is not being used, a read component 150 reads 1108 data from the region in a different read mode, and the method 1100 ends.

[0143] In response to the read mode module 902 determining 1102 that a time-based soft-bit read mode is being used, a bias module 904 applies 1104 a set of bias voltages to cells of the range such that states of the cells affect analog voltages at sense amplifiers 700 associated with the cells. A sense module 906 reads hard bits and soft bits for the range by converting 1106 the analog voltages affected by the applied bias voltages into digital sense amplifier results at multiple integration times, and the method 1100 ends.

[0144] Fig.12 is a flowchart illustrating another embodiment of a method 1200 for reading data from a region of non-volatile memory. The method 1200 begins, and a read mode module 902 compares 1202 the current time and temperature (e.g., from the current conditions module 1014) with metadata for the region (e.g., from the metadata module 1010). The read mode module 902 determines 1204 whether a time difference or a temperature difference exceeds a threshold. If the time or temperature threshold is exceeded, the integration time selection module 1008 selects 1206 a number of integration times and determines the integration times. A bias module 904 applies 1208 a set of bias voltages to cells of the region so that states of the cells affect analog voltages at sense amplifiers 700 associated with the cells.A sampling module 906 reads hard bits and soft bits for the range by converting 1210 the analog voltages affected by the applied bias voltages into digital sense amplifier results at multiple integration times, and the method 1200 ends.

[0145] If the time or temperature threshold is not exceeded, a read component 150 reads 1212 data from the range in a different read mode. The error correction module 1012 determines 1214 whether an error rate is out of range (e.g., below a threshold for using a lower latency, lower reliability read mode or above a threshold for using a higher latency, higher reliability read mode). If the error rate is not out of range, the method 1200 ends. If the error rate is out of range, the read mode module 902 changes 1216 the read mode for future reads for a group of ranges defined based on time and / or temperature metadata, and the method 1200 ends.

[0146] Means for selecting a read mode from a plurality of read modes for reading data from a portion of non-volatile memory may, in various embodiments, include a read mode module 902, a read component 150, a die controller 206, a device controller 126, and / or other logical or electronic hardware. Other embodiments may include similar or equivalent means for selecting a read mode.

[0147] Means for generating analog voltages based on data stored by cells of a portion of non-volatile memory may, in various embodiments, include a bias module 904, a sense component 150, bitline bias / sense circuitry 302, wordline bias circuitry 308, source bias circuitry 314, a sense amplifier 700, a current-to-voltage conversion circuitry 702, a capacitor 804, a die controller 206, and / or other logic or electronic hardware. Other embodiments may include similar or equivalent means for generating analog voltages based on stored data.

[0148] Means for digitizing analog voltages at a number of integration times based on the selected read mode may, in various embodiments, include a sensing module 906, a read component 150, a die controller 206, a sense amplifier 700, a voltage-to-digital conversion circuit 706, a sense transistor 806, and / or other logic or electronic hardware. Other embodiments may include similar or equivalent means for digitizing analog voltages.

[0149] Means for comparing a current time and temperature with time and temperature metadata recorded at write time for a portion of non-volatile memory may, in various embodiments, include a read mode module 902, a metadata module 1010, a current conditions module 1014, a read component 150, a die controller 206, a device controller 126, and / or other logical or electronic hardware. Other embodiments may include similar or equivalent means for comparing times and temperatures.

[0150] Means for determining integration times may, in various embodiments, include an integration time selection module 1008, a metadata module 1010, a current conditions module 1014, an error correction module 1012, a read component 150, a die controller 206, a device controller 126, and / or other logical or electronic hardware. Other embodiments may include similar or equivalent means for determining integration times.

[0151] The present disclosure may be embodied in other specific forms without departing from its essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive. The scope of the disclosure is, therefore, indicated by the appended claims. All changes which come within the meaning and range of equivalence of the claims are intended to be embraced within their scope.

Claims

[1] Device comprising: an array (200) of non-volatile memory cells; and a controller (206) configured to: Selecting a read mode from a plurality of read modes for reading data from a region of the array (200), the plurality of read modes comprising at least one time-based soft-bit read mode; Applying a set of bias conditions to cells (306, 406) of the region such that bit line currents associated with the cells (306, 406) of the region affect voltages on capacitors associated with the cells (306, 406) of the region; and in response to selecting the time-based soft bit read mode, reading hard bits and soft bits for the range by sampling the capacitor voltages resulting from the applied set of bias conditions at multiple integration times, wherein the controller (206) is configured to select the read mode based on error correction information for a second region of the array (200) and on metadata (135) recorded at write time for the region and the second region. [2] Device comprising: an array (200) of non-volatile memory cells; and a controller (206) configured to: Selecting a read mode from a plurality of read modes for reading data from a region of the array (200), the plurality of read modes comprising at least one time-based soft-bit read mode; Applying a set of bias conditions to cells (306, 406) of the region such that bit line currents associated with the cells (306, 406) of the region affect voltages on capacitors associated with the cells (306, 406) of the region; and in response to selecting the time-based soft bit read mode, reading hard bits and soft bits for the range by sampling the capacitor voltages resulting from the applied set of bias conditions at multiple integration times, wherein the plurality of integration times comprises a set of times selected by the controller (206) based on one or more of: metadata (135) for the region, error correction information for the region, error correction information for a second region of the array (200), and metadata (135) recorded at write time for the second region. [3] Apparatus according to claim 1 or claim 2, wherein: the plurality of read modes further comprises a hard-bit read mode and a bias-based soft-bit read mode; and the controller (206) is further configured to: in response to selecting the hard bit read mode, reading hard bits for the range by sampling the capacitor voltages resulting from the applied set of bias conditions at a single integration time; and in response to selecting the bias-based soft bit read mode, read hard bits and soft bits for the range by sampling capacitor voltages resulting from the applied set of bias conditions, apply one or more additional sets of bias conditions, and sample capacitor voltages resulting from the one or more additional sets of bias conditions. [4] The device of claim 1 or claim 2, wherein the time-based soft bit read mode is a default read mode for the controller (206). [5] The apparatus of claim 1 or claim 2, wherein the controller (206) is configured to sample the capacitor voltages at two integration times in the time-based soft-bit read mode and to sample the capacitor voltages at three integration times in a second time-based soft-bit read mode. [6] The apparatus of claim 1 or claim 2, wherein the plurality of integration times comprises a set of times selected by the controller (206) based on information included in a read command received by the controller (206). [7] Method comprising: Determining (1102) whether to use a time-based soft-bit read mode to read data from an area of ​​non-volatile memory (120); Applying (1104) a set of bias voltages to cells (306, 406) of the region such that states of the cells (306, 406) affect analog voltages at sense amplifiers associated with the cells (306, 406); and in response to determining (1102) to use the time-based soft bit read mode, reading hard bits and soft bits for the range by converting (1106) the analog voltages affected by the applied bias voltages into digital sense amplifier results at multiple integration times, wherein determining (1102) whether to use a time-based soft-bit read mode is based on error correction information for a second region of the non-volatile memory and metadata (135) recorded at write time for the region and the second region. [8] Method comprising: Determining (1102) whether to use a time-based soft-bit read mode to read data from an area of ​​non-volatile memory (120); Applying (1104) a set of bias voltages to cells (306, 406) of the region such that states of the cells (306, 406) affect analog voltages at sense amplifiers associated with the cells (306, 406); and in response to determining (1102) to use the time-based soft bit read mode, reading hard bits and soft bits for the range by converting (1106) the analog voltages affected by the applied bias voltages into digital sense amplifier results at multiple integration times, wherein the method further comprises determining the plurality of integration times based on one or more of the following: Metadata (135) for the area, error correction information for the area, error correction information for a second area of ​​the non-volatile memory, and metadata (135) recorded at write time for the second area. [9] A method according to claim 7 or claim 8, further comprising selecting whether the analog voltages are converted to digital sense amplifier results at two integration times or at three integration times. [10] Device comprising: Means (902, 150, 206, 126) for selecting a read mode from a plurality of read modes for reading data from an area of ​​a non-volatile memory (120), the plurality of read modes comprising at least one time-based soft-bit read mode; Means (904, 150, 302, 308, 314, 700, 702, 804, 206) for generating analog voltages based on data stored by cells (306, 406) of the area; and Means (906, 150, 206, 700, 706, 806) for digitizing the analog voltages at a number of integration times based on the selected reading mode, wherein the device further comprises means (1008, 1010, 1014, 1012, 150, 206, 126) for determining the integration times based on one or more of: metadata (135) for the region, error correction information for the region, error correction information for a second region of the non-volatile memory, and metadata (135) recorded at write time for the second region.

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