POWER SHELL MODULE

Abstract

Power semiconductor module, which includes: an isolated substrate (99); a first conductive pattern (1) laid on the isolated substrate (99); several first power semiconductor chips (11, 12, 13) arranged on the first conductive pattern (1); a first wiring (31) which is formed in a bridging configuration and which is formed for directly connecting respective gate electrodes of the several first power semiconductor chips (11, 12, 13); and a second wiring (32) which is formed in a bridging manner and which is formed for directly connecting respective source electrodes of the several first power semiconductor chips (11, 12, 13); a gate control terminal (91) which is electrically isolated from the first conductive pattern (1) and is arranged in a resin housing; and a source detection control terminal (92) which is arranged separately in a housing away from the first conductive pattern (1), wherein the first wiring (31) is arranged next to the second wiring and is angled within 30 degrees with respect to the second wiring (32), and connects the gate control terminal (91) to a gate electrode of a power semiconductor chip, and wherein the second wiring (32) connects the source sensing control terminal (92) to a source electrode of the power semiconductor chip; wherein the power semiconductor module further comprises: a second conductive pattern (2) laid on the isolated substrate; several second power semiconductor chips arranged on the second conductive pattern (2); a third wiring (43) formed for bridging and directly connecting respective gate electrodes of the several second power semiconductor chips on the second conductive pattern (2); and a fourth wiring (44) formed to bridge and directly connect respective source electrodes of the multiple second power semiconductor chips on the second conductive pattern (2); wherein the third wiring (43) is arranged next to the fourth wiring (44) and is angled within 30 degrees with respect to the fourth wiring (42); wherein a third conductive pattern (3) is arranged between the first conductive pattern (1) and the second conductive pattern (2), adjacent to the second conductive pattern (2); and there is a section where the directions of the currents flowing through the second conductive pattern (2) and through the third conductive pattern (3) differ by 180 degrees; wherein the second conductive pattern (2) is connected by several contact wires (35A, 35B, 35C) to the source electrodes of the several first power semiconductor chips (11, 12, 13) on the first conductive pattern (1), wherein the source current path of a source current flowing from a power semiconductor chip (13) of the several first power semiconductor chips (11, 12, 13) that is closest to a feed point (64) of the second conductive pattern (2) via the second conductive pattern (2) to the feed point (64) is the shortest, and the source current path of a source current flowing from another power semiconductor chip (11) of the several first power semiconductor chips (11, 12, 13) via the second conductive pattern (2) to the feed point (64) is the longest, and wherein a first slot pattern (71A) is formed in an L-shape or in an I-shape in the second conductive pattern (2) to guide the source current path from the power semiconductor chip (13),to redirect the current path that is closest to the feed point (64), thereby reducing variations in the inductances of the source current paths from the several first power semiconductor chips (11, 12, 13) to the feed point (64); and , The third conductive pattern (3) is connected to the source electrodes of the multiple second power semiconductor chips on the second conductive pattern (2) by multiple contact wires (45A, 45B, 45C), wherein the source current path of a source current flowing from a power semiconductor chip of the multiple second power semiconductor chips nearest to a feed point (63) of the third conductive pattern (3) across the third conductive pattern (3) to the feed point (63) is the shortest, and the source current path of a source current flowing from another power semiconductor chip of the multiple second power semiconductor chips across the third conductive pattern to the feed point (63) is the longest, and wherein a second slot pattern (71B) is formed in an L-shape or in an I-shape in the third conductive pattern (3) to define the source current path from the power semiconductor chip nearest to the feed point (63) is nearest, to redirect,and thus reduce the variation in inductances of the source current paths from the multiple second power semiconductor chips to the feed point (63).

Description

Technical field

[0001] The present invention relates to a power semiconductor module structure and in particular to a technology that is effectively applicable to SiC power semiconductor modules that use a SiC substrate. State of the art

[0002] Power converters are used to control electrical power and motor operation in industrial equipment, electric rail vehicles, hybrid vehicles, electric vehicles, etc. A power converter consists of, among other things, electrical components such as power semiconductor modules and capacitors, wiring components to connect the electrical parts, and heat sinks to dissipate the heat generated by the power loss of the electrical components.

[0003] Up to now, there have been constant demands for power converters to reduce their volume and weight. For example, reducing the size of power converters in electric vehicles can lead to improvements; for instance, mounting new electrical components such as storage batteries in space freed up by the smaller power converters can deliver added value such as increased driving performance, or increasing passenger space can improve passenger comfort. Thus, for power semiconductor modules used as power converter components, a reduction in volume is required even while increasing their rated current. Volume reduction is also necessary for heat sinks.

[0004] One way to meet the requirement for reducing the size of these main electrical components is to apply composite semiconductor chips made of SiC (silicon carbide) or GaN (gallium nitride) to power semiconductor modules. Compared to conventional semiconductor chips using Si (silicon), the composite semiconductor chips offer several advantages, including high switching speed and a high upper operating temperature limit. Switching-related losses can be reduced through faster operation, and it is also possible to minimize heat dissipation because the composite semiconductor chips can operate at higher temperatures. This allows for the design of smaller heat sinks.

[0005] On the other hand, the chip yield of these composite semiconductor chips is lower than that of silicon semiconductor chips due to crystal defects resulting from the substrate and manufacturing process issues. Therefore, the external dimensions (chip size) of composite semiconductor chips are reduced to improve the yield. Consequently, to configure a power semiconductor module that meets a specified rated current, it is necessary to mount multiple composite semiconductor chips connected in parallel on an insulated substrate within the module.

[0006] As prior art in the technical field of the present invention, there is, for example, a technology such as in PTL 1. PTL 1 discloses “a structure in which several pieces of transistor elements 4 and diode elements 31 are arranged in parallel on an insulated substrate 2” ( Fig. 5) On the surface of the insulated substrate 2, the following wiring patterns are arranged in place: a wiring pattern 3B that connects the collector electrodes (or drain electrodes) of the several transistor elements 5 to the cathode electrodes of the diode elements 31; also a wiring pattern 3A that connects the emitter electrodes (or source electrodes) of the respective transistor elements 31 to the anode electrodes of the diode elements 31 via connection terminals 36; a wiring pattern 3C that connects the gate electrodes of the respective transistor elements 31; and a wiring pattern 3D for the source sensing wiring, which is paired with the gate electrode wiring.

[0007] Furthermore, PTL 2 discloses “a wiring structure which causes several segments 1 to operate in parallel, the structure in which a connecting wiring 7, which is formed to bridge each electrode terminal surface using a (made of aluminum) wire, is used to establish a connection between the terminal surfaces of the gate electrodes of the several segments 1, and in which the gate electrode terminal surfaces of three segments 1 are connected to a gate electrode terminal 43” ( Fig. 1 therein). By connecting the multiple gate electrode connection surfaces of segments 1 together with the gate electrode connection 43, the area that must be occupied by the gate electrode connection 43 is reduced.

[0008] In PTL3, the gates of a plurality of semiconductor switching elements are electrically connected to a common gate control pattern via wires; and the sources of the plurality of semiconductor switching elements are electrically connected to a common source control pattern via wires. List of oppositions patent literature PTL 1: JP 2015 - 142 059 A PTL 2: JP 2004 - 289 103 A PTL 3: WO 2019 / 044 748 A1 Summary of the invention: Technical problem

[0009] Composite semiconductor chips, whose introduction into power semiconductor modules is progressing, have smaller external dimensions than conventional silicon-based chips in order to improve yield. A primary challenge is enabling them to be mounted in a larger number of power semiconductor chips on the power semiconductor chip mounting substrate compared to the prior art.

[0010] To reduce the size of a power semiconductor module or to increase the number of power semiconductor chips to be mounted within the module, it is effective to establish the connection between the gate electrodes of several power semiconductor chips mounted on the power semiconductor chip mounting substrate by means of wiring formed as in the PTL 2 mentioned above to bridge each electrode connection area.

[0011] To fully utilize the performance of power semiconductor chips, a gate drive voltage observed at a gate drive terminal of a power semiconductor module must, however, follow the waveform of the gate drive voltage for the power semiconductor chips mounted in the power semiconductor module without differing from it.

[0012] If the gate drive voltage has a tracking capability as described above, it is possible to adjust the gate drive signal shape at high speed or with the highest possible voltage, while suppressing any noise voltage generated by switching within the nominal gate voltage range of the power semiconductor chips, and it is possible to fully utilize the performance capabilities of the power semiconductor chips.

[0013] In the structure mentioned above according to PTL 2, a difference occurs between the gate drive voltage observed at a gate drive terminal of a power semiconductor module and the signal waveform of the gate drive voltage for the power semiconductor chips mounted on the substrate inside the module due to a noise voltage generated by switching.

[0014] Composite semiconductor chips offer the advantages of lower equivalent resistance during conduction and lower switching-related losses compared to conventional silicon chips. However, proper gate drive is necessary to allow the power semiconductor module to realize these benefits. A second challenge is reducing the difference between the gate drive voltage observed at the power semiconductor module's gate drive terminal and the gate drive voltage waveform for the power semiconductor chips mounted within the module, compared to the prior art.

[0015] In the structure according to the aforementioned PTL 2 ( Fig. 5) The percentage of the area occupied by semiconductor elements, such as transistor elements 4 and diode elements 31, across the entire insulated substrate is 50% or lower, and the surface mount efficiency of the semiconductor elements is low. As mentioned previously, it is necessary to improve the surface mount efficiency to configure a smaller power semiconductor module that meets a specified current rating. It is desirable to reduce the area of ​​the patterns, e.g., wiring patterns 3A, 3C, and 3D.

[0016] In the above-mentioned structure according to PTL 2 ( Fig. 1) The controllability of the gate drive voltage becomes a problem. In accordance with PTL 2, a source electrode terminal 41, through which a high source current flows, is also used as an input terminal for a control reference signal as a gate control signal. Consequently, a noise voltage is superimposed on the gate drive voltage between the gate electrode terminal 43 and the source electrode terminal 41 when switching occurs, due to the impedance of a path over which a main current flows. The connecting wiring (the wire) 6, which is formed to bridge each electrode terminal area, and the wiring pattern for the source electrode terminal 41 create an impedance that causes the noise voltage to be generated.

[0017] Although the voltage between the gate electrode terminal 43 and the source electrode terminal 41 can be measured as a terminal voltage of the power semiconductor module, it appears as a transition response waveform that is different from the gate drive voltage between the gate and source electrodes of the power semiconductor chips within the power semiconductor module.

[0018] In other words, since there is a difference between the gate drive voltage that appears when the power semiconductor module is connected and the gate drive voltage for the power semiconductor chips inside the power semiconductor module, the controllability of the gate drive voltage of the power semiconductor module is poor, and it can be said that it is difficult to operate at maximum efficiency within the rated voltage and current ranges when driving the power semiconductor chips.

[0019] Therefore, one object of the present invention is to create a power semiconductor module in which several semiconductor chips are arranged in parallel on an isolated substrate, wherein the above module enables a high-density assembly of semiconductor chips and is highly reliable with less difference in operating characteristics from one semiconductor chip to another. Solution to the problem

[0020] The present invention is defined by the appended claims. In the following, parts of the description and the drawings relating to earlier embodiments and not necessarily including all features for implementing embodiments of the claimed invention are to be understood as not representing embodiments of the invention, but serving as examples to facilitate understanding of the embodiments of the invention.

[0021] To solve the problems mentioned above, a power semiconductor module of the present invention comprises an insulated substrate; a first conductive pattern laid on the insulated substrate; several power semiconductor chips arranged on the first conductive pattern; a first wiring configuration formed for bridging and directly connecting respective gate electrodes of the several power semiconductor chips; and a second wiring configuration formed for bridging and directly connecting respective source electrodes of the several power semiconductor chips, characterized in that the first wiring configuration is arranged next to the second wiring configuration and may be angled within 30 degrees with respect to the second wiring configuration. Advantageous effects of the invention

[0022] According to the present invention, it is possible to realize a power semiconductor module in which several semiconductor chips are arranged in parallel on an isolated substrate, wherein the above module enables a high-density assembly of semiconductor chips and is highly reliable with less difference in the operating characteristics from one semiconductor chip to another.

[0023] Consequently, both a reduction in size and an improvement in the reliability of power converters are achievable.

[0024] Other problems, structures and beneficial effects than those described above will emerge from the following description of examples. Brief description of the drawings Fig. Figure 1 is a schematic representation showing an internal structure of a power semiconductor module relating to Example 1 of the present invention. Fig. Figure 2 is a schematic representation showing the internal structure of a state-of-the-art power semiconductor module. Fig. 3 is an equivalent circuit diagram of the one in Fig. 1 of the power semiconductor module shown. Fig. Figure 4 is a schematic overview of a computing circuit for verifying advantageous effects of the present invention. Fig. Figure 5 is a set of schematic diagrams that illustrate an example of advantageous effects of the present invention. Fig. Figure 6 is an equivalent circuit diagram of a state-of-the-art power semiconductor module. Fig. Figure 7 is an equivalent circuit diagram of a state-of-the-art power semiconductor module. Fig. Figure 8 is a set of schematic diagrams that illustrate an example of advantageous effects of the present invention. Fig. Figure 9 is a schematic representation showing an internal structure of a power semiconductor module relating to Example 2 of the present invention. Fig. Figure 10 is a schematic representation showing an internal structure of a power semiconductor module according to the invention. Description of examples and the embodiment according to the invention

[0025] Examples of the present invention and the embodiment according to the invention are described below with reference to the drawings. In the respective drawings, identical components are assigned the same reference numerals, and their detailed description, which is considered repetitive, has been omitted. Example 1

[0026] Based on the Fig. In sections 1 to 8, a power semiconductor module of example 1 of the present invention is described.

[0027] This example illustrates that the present invention can simultaneously achieve the following: 1) The invention can improve the efficiency of mounting multiple power semiconductor chips on a power semiconductor chip mounting substrate (the main substrate) contained in the power semiconductor module; and 2) the invention can improve gate controllability by reducing the noise voltage superimposed on a voltage Vgs between a gate control terminal and a source control terminal of the power semiconductor module when switching takes place.

[0028] By making an observable transition response signal shape of the voltage Vgs between the gate and source control terminals suitable for a voltage Vgschip applied between the gate and source electrodes of the power semiconductor chips mounted inside the power semiconductor, it is possible to know the behavior of the voltage Vgschip when switching takes place and to assess an operating margin with respect to the nominal voltage Vgschip and an operating margin with respect to a disturbance.

[0029] As a result, the main voltage and the rate of change of the main voltage over time when switching takes place (dv / dt and di / dt) can be set as high as possible in an operating range of the power semiconductor module without exceeding the nominal voltage and without experiencing a disturbance.

[0030] If, for example, it is assumed that Vgs is superimposed with a noise voltage, a smaller margin should be estimated with respect to the nominal voltage compared to an actual transition waveform of Vgschip. Since the dv / dt and di / dt settings must be set smaller, a problem of increased switching losses arises.

[0031] First, an arrangement of several power semiconductor chips mounted on the power semiconductor chip mounting substrate (main substrate) is described. When power semiconductor chips are arranged on the insulated substrate (chip mounting substrate), it is necessary to ensure the isolation distance between the chips and to form a gate control wiring of switching element chips (the description here uses MOSFET chips as an example). Fig. 5 of the previously mentioned PTL 1 are wiring pattern 3C as a gate control wiring pattern and wiring pattern 3D as a source control wiring pattern, to which surface areas of the isolated substrate (chip mounting substrate) 2 are assigned.

[0032] Fig. Figure 1 shows an internal structure of the power semiconductor module of the present example; (a) is a top view and (b) is a cross-sectional view along the line AA' in (a). Fig. Figure 1 shows the internal structure of a 2-in-1 module in which MOSFET-type power semiconductor chips are mounted. A power semiconductor chip mounting substrate 100 is arranged over a base plate 300 with an interposed solder bonding layer 9. Power semiconductor chips for an upper branch of the 2-in-1 module and power semiconductor chips for a lower branch are mounted together on the power semiconductor chip mounting substrate 100.

[0033] A terminal 51 of drain 1, which is a high-potential (P-terminal) of the 2-in-1 module, is connected to a feed point 51 of drain 1 of the power semiconductor chip mounting substrate 100. A terminal 64 of drain 2, which is an intermediate-potential (AC-terminal) is connected to a feed point 64 of drain 2 of the power semiconductor chip mounting substrate 100. The terminals 63 of source 2 (63A, 63B), which are low-potential (N-terminals), are connected to feed points 63 of source 2 (63A, 63B) of the power semiconductor chip mounting substrate 100.

[0034] A control terminal 91 of gate 1, which controls the gates in the upper branch of the power semiconductor module, is connected via a contact wire 13 to a gate electrode of a power semiconductor chip 13 mounted on the power semiconductor chip mounting substrate 100. A control terminal 92 of source sensing 1 in the upper branch is connected via a contact wire 32 to a source electrode of the power semiconductor chip 13.

[0035] Similarly, a control terminal 93 of gate 2 in the lower branch is connected via a contact wire 41 to a gate electrode of a power semiconductor chip 23, which is mounted on the power semiconductor chip mounting substrate 100. Furthermore, a control terminal 94 of source sensing 2 in the lower branch is connected via a contact wire 42 to a source electrode of the power semiconductor chip 23.

[0036] A control terminal 52 of drain sensing 1 is connected to a feed point 52 of drain sensing 1, and a control terminal 62 of drain sensing 2 is connected to a feed point 62 of drain sensing 2; these terminals are used to monitor a drain voltage in the upper and lower branches. The terminals of the power semiconductor module are electrically connected to the terminals of the power semiconductor chip mounting substrate 100 in the manner described above.

[0037] Although several connections of Drain 1, Drain Capture 1, Drain 2, Drain Capture 2 and Source 2 in Fig. 1 not shown, it is noted that these connections are conductive connections which are electrically connected to feed points of the power semiconductor chip mounting substrate 100, and of course these must have sufficient voltage withstand and current withstand capabilities against a voltage applied between the connections and a current passing through them.

[0038] The power semiconductor chip mounting substrate 100 is provided on one side of the insulated substrate 99 with a conductive pattern 1 of drain 1 (a pattern for applying a high potential P), with a conductive pattern 2 of drain 2 (a pattern for applying an intermediate potential AC) and with a conductive pattern 3 of source 2 (a pattern for applying a low potential N) and is provided on the other side with a conductive backside pattern 5.

[0039] The conductive pattern 1 of the drain 1 should be formed in such a way that the pattern electrically connects with drain electrodes provided on the back sides of several power semiconductor chips 11 to 13 of a vertical structure with solder joint layers 10 placed between the pattern and each electrode, and can thus establish a connection with the terminal 51 of the drain 1 of the power semiconductor module and with the control terminal 52 of the drain 1, which is used for potential observation.

[0040] A current passing through the power semiconductor chips 11 to 13 for the lower branch flows from the source electrode terminals 502 of the power semiconductor chips 11 to 13 via several contact wires 35A, 35B, 35C to the conductive pattern 2 of the drain 2, which is arranged on the power semiconductor chip mounting substrate 100. Since a high current in the range of several hundred to thousands of amperes flows through the conductive pattern 1 of the drain 1, through the conductive pattern 2 of the drain 2, and through the conductive pattern 3 of the source 2, the cross-sectional area of ​​the conductive patterns is designed for a value that prevents the patterns from melting due to the heat generated by the current flowing through them.

[0041] The conductive pattern 2 of the drain 2 should be formed in such a way that the pattern can make a connection with the terminal 64 of the drain 2 and with the control terminal 62 of the drain 2, which is used for potential observation, and furthermore electrically connects with drain electrodes provided on the back sides of the power semiconductor chips 21 to 23 for the lower branch with solder joint layers 10 placed between the pattern and each electrode.

[0042] The gate electrode terminals 501 of the power semiconductor chips 11 to 13 are electrically connected to a gate control terminal 91 by a contact wire 31, which is formed bridging each electrode terminal and is arranged in contact with each electrode terminal.

[0043] In addition to the contact wires 35A, 35B, 35C, which are the main current paths, a contact wire 32, which establishes a connection between the source electrode terminal pads 502 of the power semiconductor chips 11 to 13, is arranged to electrically connect these terminal pads to a source detection control terminal 92 of the power semiconductor module.

[0044] A current passing through the power semiconductor chips 21 to 23 for the lower branch flows from the source electrode terminals 502 of the power semiconductor chips 21 to 23 via several contact wires 45A, 45B, 45C to the conductive pattern 3 of Source 2, which is arranged on the power semiconductor chip mounting substrate 100. The conductive pattern 3 of Source 2 should be configured such that the pattern can make contact with the terminals 63A, 63B of Source 2.

[0045] Furthermore, the gate electrode terminals 501 of the power semiconductor chips 21 to 23 are electrically connected to a gate control terminal 93 by a contact wire 41, which bridges each electrode terminal and is in contact with each electrode terminal. Apart from the contact wires 45A, 45B, 45C, which are the main current paths, a contact wire 42, which establishes a connection between the source electrode terminals 502 of the power semiconductor chips 21 to 23, is also arranged such that it electrically connects these terminals to a source sensing control terminal 94 of the power semiconductor module.

[0046] To directly connect the gate electrode pads 501 and the source electrode pads 502, the contact wires 41 and 42 mentioned above, which bridge each electrode pad, are arranged in this example to make contact with each electrode pad without connection via wiring patterns; that is, the gate control wiring pattern and the source control wiring pattern (wiring patterns 3C and 3D) described in the aforementioned PTL 1 are omitted. As a result, it is possible to realize a power semiconductor chip mounting substrate whose area is reduced for a prescribed number of power semiconductor chips mounted on the substrate.Alternatively, it is possible to increase the number of power semiconductor chips to be mounted on the substrate and the total chip area, while the prescribed area of ​​the power semiconductor chip mounting substrate remains unchanged.

[0047] In the present example, contact wire 31, which connects the gate electrode terminals 501 of the power semiconductor chips 11, 12, 13, is provided, as is contact wire 32, which connects the source electrode terminals 502. These contact wires are arranged close to each other, with electrical insulation between them, and are characterized by being arranged essentially parallel to each other.

[0048] When switching occurs, the phases of a gate control current and a source control current for the power semiconductor chips are opposite. Switching creates an alternating current loop (AC loop) from the contact wire 31, through the gate electrode pads 501 of the power semiconductor chips and the source electrode pads 502, to the contact wire 32. By arranging the contact wires 31 and 32 parallel to each other, or in such a way that they are nearly parallel but slightly angled relative to each other, a negative mutual inductance is created between the contact wires 31 and 32, and the loop inductance Lgloop of the AC current loop can be reduced.

[0049] It is noted that it is necessary to maintain an angle between the contact wires 31 and 32 within 30 degrees in order to effectively reduce the loop inductance Lgloop of the AC current loop. Preferably, the wiring should be arranged such that the contact wire 32 is positioned alongside the contact wire 31, thus maintaining the angle between them within 20 degrees.

[0050] By reducing the loop inductance Lgloop, the gate loop inductances of the internal module paths, as seen from the gate control terminal 91 or 93 and the source sensing control terminal 92 or 94 of the power semiconductor module, can be reduced. It is possible to suppress resonance with a gate drive circuit (not shown) of the power semiconductor module and to suppress oscillatory noise voltage that appears in the voltage Vgs between the gate control terminal 91 or 93 and the source sensing control terminal 92 or 94 when switching occurs.

[0051] Furthermore, in the present example, contact wires 31 and 32 are connected to control terminal 91 of gate 1 and control terminal 92 of source sensing 1, respectively; these control terminals are located in the resin housing 310 of the power semiconductor module. Contact wires 41 and 32 are connected to control terminal 93 of gate 2 and control terminal 94 of source sensing 2, respectively; these control terminals are located on the resin housing 310 of the power semiconductor module. Thus, it is possible to implement a power semiconductor chip mounting substrate 100 with a reduced surface area without the need to arrange dedicated conductive patterns on the power semiconductor chip mounting substrate 100.Together with the further improvement of the effect by increasing the number of power semiconductor chips to be mounted on the substrate and the total chip area, it is simultaneously possible to achieve an effect of suppressing the vibrational noise voltage appearing in Vgs.

[0052] Additionally, the structure of the in Fig. The present example shown in Figure 1 is characterized by the fact that the conductive pattern 3 of the source 2 is arranged between a region containing the power semiconductor chips 11 to 13 for the upper branch and a region containing the power semiconductor chips 21 to 23 for the lower branch. In a Fig. Within the area enclosed by a dashed line, the conductive patterns are arranged such that the current flowing through conductive pattern 2 of drain 2 and the current flowing through conductive pattern 3 of source 2 are parallel and adjacent to each other. Since the currents flow through conductive patterns 2 and 3 in opposite directions, a negative mutual inductance is generated, which can reduce the inductance value generated in the area enclosed by the dashed line. This makes it possible to reduce noise voltage when switching occurs.

[0053] In other words, if that in Fig. If the area enclosed by a dashed line is considered, a metal pattern 3 (the third conductive pattern) is located adjacent to a metal pattern 2 (the second conductive pattern) and between metal pattern 1 (the first conductive pattern) and metal pattern 2 (the second conductive pattern). The directions of the currents flowing through metal pattern 2 (the second conductive pattern) and metal pattern 3 (the third conductive pattern) differ from each other by 180 degrees.

[0054] Furthermore, the conductive pattern 3 of Source 2 provides a distance between the gate wiring (31 and 41) and the source sensing wiring (32 and 42) in the upper and lower branches of the inverter branches; this causes magnetic interference between them to be reduced.

[0055] Fig. Figure 1(b) shows a cross-sectional view along the line A-A', which is a dashed-dotted line shown in the plan view (a). The cross-sectional view shows an example of the wire 31, which is formed into convex bridges to span each electrode contact surface. Its shape is not limiting as long as it ensures the function of establishing a connection between the power semiconductor chips and isolating them from other wiring on the power semiconductor chip mounting substrate 100. That is to say, no restriction is intended for the connection by the contact wire, and the use of a contact strip or a narrow-width conductor also achieves the same effect as the contact wire.

[0056] Although the cross-sectional structure shows that the solder joint layer 9 is used to connect the power semiconductor chip mounting substrate 100 to the base plate 300, the means for such a connection is also not limiting.

[0057] Fig. Figure 2 is a schematic representation showing the internal structure of a prior art power semiconductor module as a comparative example to make the structure of the present invention easily understandable. The number of components in Figure 2 is 1. Fig. The number of power semiconductor chips shown in the 2 is equal to the number of chips on the power semiconductor chip mounting substrate: 100 in Fig. 1 assembled power semiconductor chip. When explaining a Fig. In the power semiconductor chip mounting substrate 101 shown in Figure 2, for example with regard to the power semiconductor chips 11 to 13 for the upper branch, the connection between their gate electrode terminals 501 is established by arranging a conductive gate pattern 4 and via contact wires 31A, 31B, 31C. Similarly, the connection between the source electrode terminals 502 of the power semiconductor chips 11 to 13 is established by arranging a conductive source detection pattern 5 and via contact wires 32A, 32B, 32C.

[0058] These conductive patterns 4 and 5 are necessary to connect the gates of three in Fig. to control the two power semiconductor chips shown. Adjacent to the locations of the power semiconductor chips, there must simultaneously be areas for wiring several contact wires 31A to 31C and 32A to 32C.

[0059] For the power semiconductor chip mounting substrate 100 in which in Fig. The present example, as shown in point 1, can have a different area compared to the one in Fig. The area reduction of the power semiconductor chip mounting substrate 101 shown in Figure 2 of the prior art can be reduced to 80%. Although the reduction rate depends, as above, on a design rule applied to a power semiconductor chip mounting substrate, it is noted that the area reduction effect is obviously reduced by the area reduction shown in the present example ( Fig. 1) The structure of the power semiconductor chip mounting substrate 100 shown can be obtained.

[0060] The in Fig. The example shown in Figure 1 is one in which one type of power semiconductor chip, e.g., several MOSFET-type power semiconductor chips with integrated diodes, is mounted on the power semiconductor chip mounting substrate 100. The effects described in this example can also be obtained in the case where two types of power semiconductor chips, e.g., IGBT chips and diode chips or IGBT chips and SBD chips, are mounted.

[0061] In particular, the present invention would be highly effective if power semiconductor chips of a type that allows forward current flow and reverse current flow (blocking current flow), such as MOSFET-type power semiconductor chips or IGBT-type power semiconductor chips that allow reverse current flow, are used.

[0062] Therefore, it is preferred that each of the multiple power semiconductor chips 11 to 13 and 21 to 23 has both a current switching function and a reverse flow function.

[0063] Although, as in Fig. As shown in Figure 1, which shows the feed points, one for terminal 51 of Drain 1, one for terminal 64 of Drain 2, and one for terminal 63 of Source 2, it can be seen that the number of feed points for the terminals may be increased in accordance with a value of the current passing through the terminals.

[0064] The following explains how the gate controllability of the power semiconductor module, when switching takes place, can be improved using the present example. Fig. 3 is a simplified equivalent circuit 601, which is equivalent to the one in Fig. The power semiconductor module shown in Figure 1 is described below. A circuit section of the upper branch and its structure are described below. The gates of the three MOSFET symbols M11 to M13, representing the MOSFET-type power semiconductor chips, are connected via inductors Lg1 and Lg2, which are equivalent to a contact wire, and similarly their source sensings are connected via inductors Lss1 and Lss2.

[0065] The gate of MOSFET M13 is equivalent to the control terminal 91 of gate 1 and is connected to node 91 via an inductor Lg3. The source of MOSFET M13 is equivalent to the control terminal 92 of source sensing 1 and is connected to node 92. Since the in Fig. When the contact wires 31 and 32 shown in Figure 1 are arranged parallel to each other or almost parallel, but slightly angled towards each other, mutual inductances are generated between the contact wires 31 and 32.

[0066] In the equivalent circuit from Fig. The mutual inductances Mg1 to Mg3, which are set between inductances Lg1 and Lss1, between inductances Lg2 and Lss2, and between inductances Lg3 and Lss3, are represented by the mutual inductances. Since the mutual inductances are negative, they can reduce the loop inductance Lgloop of the aforementioned AC current loop across the gates. The connection between a node 51 (equivalent to the drain feed point 51 in Fig. 1) and each of the drains of the MOSFETs M11 to M13 is connected via inductors Ld1 to Ld3, which represent impedances on the power semiconductor chip mounting substrate 100 in Fig. 1 are generated in the conductive pattern 1 of drain 1.

[0067] Furthermore, the connection between a node 64 (equivalent to the source point 64 in Fig. 1) and each of the sources of the MOSFETs M11 to M13 is manufactured via inductors Ls1 to Ls3, representing impedances in the source contacting wires 35A to 35C and in the conductive pattern 2 of the drain 2 on the power semiconductor chip assembly structure 100 in Fig. 1 are generated. For a circuit section of the lower branch, in which the MOSFET symbols M21 to M23 are switching elements, its structure is the same as that of the circuit section of the upper branch and its detailed description is omitted.

[0068] It is noted that mutual inductances in the Fig. The area enclosed by a dashed line, created by arranging the conductive pattern 2 of drain 2 and the conductive pattern 3 of source 2 in parallel and adjacent to each other, is included in the equivalent circuit as M16, M25, and M34. Although the impedances of the contact wires and the conductive patterns are represented by inductance symbols, such a representation is not shown in a simulation circuit described later; however, the influence of a parasitic resistance value is also taken into account in the simulation circuit.

[0069] Furthermore, the replacement circuit consists of Fig. Three resistors, Rgc11 to Rgc13 and Rgc21 to Rgc23, are connected in series with the respective gates of the MOSFETs. Although this is in Fig. Not shown in Figure 1, these resistors are built-in gate resistors of the power semiconductor chips and their effect will be described later.

[0070] It is noted that arrow symbols Is1 to Is6 in Fig. 3. Each indicates the direction of the current flowing through parasitic inductances Ls1 to Ls6 of the MOSFET source main current paths. Additionally, VgsChipSIM denotes the gate-source voltage of a power semiconductor chip.

[0071] Fig. 4 is a simulation circuit that corresponds to the equivalent circuit 601 of the in Fig. The 2-in-1 power semiconductor module shown in Figure 3 is configured with its gate drive circuits (GDC1, GDC2), an inductive load L1, a power supply Vcc, and a power supply stabilization capacitor C1. Nodes 91 to 94, node 51, node 63, and node 64 are shown in the simplified equivalent circuit 601. Fig. 3 are wired to the above elements of the simulation circuit.

[0072] In Fig. Figure 5 shows switching transition signal waveforms obtained through circuit simulation. A graph (a)-1 in Fig. 5 is a transition response waveform resulting from the activation of the gate control terminal 91 and the source detection control terminal 92 in the circuit section of the upper branch of the equivalent circuit 601 by the gate drive circuit GDC1 in the Fig. The simulation circuit shown in section 4 results.

[0073] A solid line in Fig. 5(a) represents the waveform of a voltage VgsSIM between the gate control terminal 91 and the source sensing control terminal 92, and a dashed line represents the waveform of the gate-source voltage VgsChipSIM (see Fig. 5) one in the equivalent circuit 601 ( Fig. 3) the MOSFETs M11 contained therein. Here, the signal waveforms are those when the MOSFET is switched on, and those during the change from an off-drive voltage VGSN to an on-drive voltage VGSP of the GDC1. Fig. Figure 5(a)-2 shows an enlarged view around a gate plateau voltage, which becomes most important when switching takes place.

[0074] It is evident that the VgsSIM signal waveform, which can be observed as a voltage between terminals of the power semiconductor module, satisfactorily reproduces the gate-source voltage VgsChipSIM of a power semiconductor chip on the chip mounting substrate 100 contained in the module. By achieving such a satisfactory reproduction, it is possible, after installation of the power semiconductor module in a power converter, to implement drive control such as optimizing the dv / dt and di / dt values ​​and loss based on transition signal waveforms obtained at the gate drive terminals (including the gate control terminal and the source sensing control terminal) of the power semiconductor module, without providing unnecessary headroom.

[0075] A replacement circuit 602 made of Fig. 6 is a circuit for comparison with the one in Fig. Equivalent circuit 601 is shown in Figure 3. Equivalent circuit 602 is the same as equivalent circuit 601 in that the gates of the MOSFET-type power semiconductor chips M11 to M13 are connected via inductors Lg1 and Lg2, and their source sensings are connected via inductors Lss1 and Lss2. However, equivalent circuit 62 is an example where node 64, through which the main current flows (equivalent to terminal 64 in Figure 3), is not connected to the corresponding terminal. Fig. 1), also serves as node 92, i.e., as the contact where the source detection control voltage is detected. Regarding the circuit section of the lower branch of the equivalent circuit 602, the same modification is made as in the circuit section of the upper branch.

[0076] In Fig. 5(b)-1 and Fig. 5(b)-2 shows switching transition signal waveforms. As in Fig. 5(a) shows the signal waveforms at which the MOSFET is switched on, and those during the change from the off-drive voltage VGSN to the on-drive voltage VGSP of the GDC1. Fig. 5(b)-2 it is evident that in the voltage (VgsSIM) between the gate control terminal 91 (the node 91 in the equivalent circuit) and the source sensing control terminal 92 (the node 92 in the equivalent circuit) an oscillation is generated, which is represented by a solid line, while in the gate-source voltage VgsChipSIM of a MOSFET M11 contained in the equivalent circuit 602 there is essentially no oscillation.

[0077] In other words, it is stated that a noise voltage (oscillation voltage) is superimposed on the voltage between the gate control and source detection control terminals of the power semiconductor module, which appears in the module as different from the transition signal waveform of the gate-source voltage of a power semiconductor chip mounted on the chip mounting substrate.

[0078] As in Fig. 6 is a replacement circuit 603 from Fig. Figure 7 also shows a circuit for comparison with equivalent circuit 601. In equivalent circuit 603, compared to equivalent circuit 601, the gates of the MOSFET-type power semiconductor chips M11 to M13 are connected via inductors Lg1 and Lg2, while the source detection path is removed from each chip. This wiring eliminates the effect of the source electrode wiring in the circuit arrangement. Fig. 1 and in the equivalent circuit from Fig. The 3 chips shown are ineffective.

[0079] Node 64, through which the main current passes (equivalent to terminal 64 in Fig. 1) also serves as node 92, i.e., as the contact where the source detection control voltage is detected. The same modification is made to the circuit section of the lower branch of equivalent circuit 603 as to the circuit section of the upper branch.

[0080] In Fig. 5(c)-1 and Fig. 5(c)-2 shows switching transition signal waveforms. As in the above Fig. 5(b) is in Fig. 5(c)-1 and Fig. 5(c)-2 obviously that in the voltage (VgsSIM) between the gate control terminal 91 and the source sensing control terminal 92 an oscillation is generated, which is represented by a solid line, while in the gate-source voltage VgsChipSIM of a MOSFET M11 contained in the equivalent circuit of the substrate there is essentially no oscillation.

[0081] For the replacement circuit 603 from Fig. 7 also states that a noise voltage (oscillation voltage) is superimposed on the voltage between the gate control and the source detection control terminal of the power semiconductor module, which appears different from the transition signal shape of the gate-source voltage of a power semiconductor chip mounted on the chip mounting substrate in the module.

[0082] In other words, for the two signal forms in Fig. 5(b) and Fig. 5(c) states that the voltage Vgs observed between the gate control and source sensing control terminals of the power semiconductor module exhibits a different signal shape than the transition signal shape of the gate-source voltage Vgs of a power semiconductor chip mounted on the power semiconductor chip mounting substrate in the module.

[0083] Essentially, it is necessary to optimize the gate drive rate within a voltage range that does not exceed the gate rated voltage, based on the transition waveforms appearing in VgsChip, and to utilize the characteristics specific to power semiconductor chips. If a difference arises between the observable transition waveforms of VgsChip and Vgs, the gate drive rate must be optimized, as mentioned above, depending on the observable Vgs waveform.

[0084] Consequently, a moderate gate drive speed must be selected in accordance with the Vgs signal shape, even though power semiconductor chips are intrinsically capable of high-speed operation. Switching losses would increase, and it would become difficult to utilize characteristics specific to power semiconductor chips.

[0085] On the other hand, in accordance with the connection configuration between the chips and with the gate control and source sensing control connections on the power semiconductor chip mounting substrate shown in the present example, it is possible to configure the power semiconductor module to fully utilize the capabilities of the power semiconductor chips, thus overcoming the problem mentioned above.

[0086] As described in the preceding context, it is evident that, in accordance with the present example, it is possible to improve the efficiency of mounting multiple power semiconductor chips on the power semiconductor chip mounting substrate (the main substrate) contained in the power semiconductor module, while simultaneously improving the gate controllability of the power semiconductor module when switching takes place.

[0087] In the equivalent circuit diagram from Fig. 3. Resistors Rgc11 to Rgc13 are connected in series with the gates of MOSFET-type transistors M11 to M13. The effect of this is described below.

[0088] Parallel contact connections between the gate electrodes and between the source electrodes of the multiple in Fig. The chips shown in Figure 1 can improve the efficiency of mounting chips on the power semiconductor chip mounting substrate or can reduce the surface area of ​​the power semiconductor chip mounting substrate. Furthermore, the thermal stress history with respect to the power semiconductor chips and wiring component materials, including contact wires and solder, should be made as uniform as possible to improve the reliability of the mounted power semiconductor chips and extend the lifetime of the power semiconductor module.

[0089] The previously mentioned built-in gate resistors Rgc of the power semiconductor chips are used to make the current balance between the power MOSFET chips as even as possible when switching takes place, and to balance the thermal history with respect to the power semiconductor chips and wiring component materials around the chips.

[0090] Fig. Section 8 presents circuit simulation results from increasing and decreasing the resistance values ​​of the built-in gate resistors Rgc11 to Rgc13 of the MOSFETs M11 to M13 and the built-in gate resistors Rgc21 to Rgc23 of the MOSFETs M21 to M23 in the equivalent circuit using the switching simulation circuit. Fig. 4 dar.

[0091] Fig. Figure 8 shows transition signal shapes of the drain currents of the power MOSFET chips when they are switched on. Fig. 8(a) represents general signal shapes, Fig. 8(b) represents signal shapes when the resistance value of resistors Rgc11 to Rgc13 and Rgc21 to Rgc23 has been set to a large value, e.g. 32 Ω, and Fig. 8(c) represents signal shapes when the resistance value of resistors Rgc11 to Rgc13 and Rgc21 to Rgc23 has been set to a small value, e.g. 2 Ω.

[0092] Obviously, the use of parallel contact connections between the gate electrodes and between the source electrodes of the multiple chips causes an impedance inconsistency of the paths from the gate drive circuit GDC1 to the gate electrodes and to the source electrodes of the power semiconductor chips.

[0093] Thus, the arrangement of the aforementioned built-in gate resistors Rgc with a suitable resistance value dampens the impedance inconsistency and allows the current conduction timing settings of the power semiconductor chips to converge.

[0094] A comparison between Fig. 8(b) and Fig. 8(c) clarifies that by setting the resistance value of the resistors Rgc to a predefined value or higher, it is possible to reduce the change in currents across the power MOSFET chips when switching takes place to below a certain level.

[0095] As described in the preceding context, the power semiconductor module of the present example comprises the following: the insulated substrate 99; the first conductive pattern (the metal pattern 1) placed on the insulated substrate 99; the multiple power semiconductor chips 11 to 13 arranged on the first conductive pattern (the metal pattern 1); the first wiring (the contact wire 31) formed bridging each electrode terminal and directly connecting the respective gate electrodes (gate electrode terminals 501) of the multiple power semiconductor chips 11 to 13; and the second wiring (the contact wire 32) formed bridging each electrode terminal and directly connecting the respective source electrodes (source electrode terminals 501) of the multiple power semiconductor chips 11 to 13.The first wiring (the contact wire 31) is arranged next to the second wiring (the contact wire 32) and can be angled within 30 degrees with respect to the second wiring (the contact wire 32).

[0096] Furthermore, the power semiconductor module includes the gate control terminal 91, which is electrically isolated from the first wiring pattern (the metal pattern 1), and the source sensing control terminal 92, which is remotely separated from the first wiring pattern (the metal pattern 1). The first wire (the contact wire 31) is connected to the gate control terminal 91, and the second wire (the contact wire 32) is connected to the source sensing control terminal 32.

[0097] Furthermore, the multiple power semiconductor chips 11 to 13, which are arranged on the first conductor pattern (the metal pattern 1), and the multiple power semiconductor chips 21 to 23, which are arranged on the second conductor pattern (the metal pattern 2), are arranged at point-symmetric positions.

[0098] Furthermore, each of the multiple power semiconductor chips 11 to 13 and 21 to 23 is provided with a built-in resistor having a predefined resistance value to act on the impedances of the chip's internal paths, as seen from the gate electrode connection pads 501. It is noted that each of the multiple power semiconductor chips 11 to 13 and 21 to 23 has a built-in resistor made of polysilicon, which is advantageous for reducing the size of the power semiconductor module. Built-in resistors made of polysilicon are easy to form on the semiconductor chips and are less temperature-dependent.

[0099] Consequently, it is possible to realize a power semiconductor module in which several semiconductor chips are arranged in parallel on an isolated substrate, whereby the above module allows the high-density mounting of semiconductor chips and is highly reliable with less difference in operating characteristics from one semiconductor chip to another.

[0100] Furthermore, both size reduction and reliability improvement of a power converter using this power semiconductor module are achievable. Example 2

[0101] A power semiconductor module of Example 2 of the present invention is based on Fig. 9 described. As in the case of Example 1 ( Fig. 1) Here, an internal structure of a 2-in-1 module is shown, in which MOSFET-type power semiconductor chips are mounted. Its cross-sectional structure is also the same as in Fig. 1(b), so that it is not shown again here.

[0102] Power semiconductor chips for an upper branch of the 2-in-1 module and power semiconductor chips for a lower branch are mounted together on a power semiconductor chip mounting substrate 102. A terminal 51 of drain 1, which is a high-potential (P-terminal) of the 2-in-1 module, is connected to a feed point 51 of drain 1 of the power semiconductor chip mounting substrate 102. A terminal 64 of drain 2, which is an intermediate-potential (AC-terminal) connection, is connected to a feed point 64 of drain 2 of the power semiconductor chip mounting substrate 102. The terminals 63 of source 2, which are low-potential (N-terminals), are connected to feed points 63 of source 2 of the power semiconductor chip mounting substrate 102.

[0103] A control terminal 52 of drain sensing 1 is connected to a feed point 52 of drain sensing 1, and a control terminal 62 of drain sensing 2 is connected to a feed point 62 of drain sensing 2; these terminals are used for monitoring a drain voltage in the upper and lower branches. The terminals of the power semiconductor module are electrically connected to the power semiconductor chip mounting substrate as described above.

[0104] This example represents a case of mounting a larger number of power semiconductor chips to increase the rated current of the power semiconductor module or to increase the total area occupied by the mounted power semiconductor chips within a prescribed module area.

[0105] As in Fig. As shown in Figure 9, power semiconductor chips 11 to 16, which function as switching elements in a circuit section of the upper branch, are organized in groups of three. Electrical connections between the gate electrodes and source electrodes of the chips in each group are established using wiring that bridges each electrode terminal. The power semiconductor chips 21 to 26, which function as switching elements in a circuit section of the lower branch, are also organized in groups of three. Electrical connections between the gate electrodes and source electrodes of the chips in each group are established using wiring that bridges each electrode terminal.

[0106] Descriptions of the characteristics of the present example are given, using the circuit section of the upper branch as an example. In the circuit section of the upper branch, a first chip group contains power semiconductor chips 11 to 13, and a second chip group contains power semiconductor chips 14 to 16. As described in the section of Example 1, gate electrode wiring and source electrode wiring are configured between the chips in the first and second chip groups.

[0107] One configuration characteristic of the present example is that the wiring leads between the gate electrodes in the first and second chip groups are electrically connected by a conductor 95, which is arranged on or embedded in the resin housing 310. Likewise, the wiring leads between the source electrodes are electrically connected by a conductor 96, which is arranged on or embedded in the resin housing 310.

[0108] Such an electrical connection is conventionally provided using power patterns laid out on the same chip mounting substrate, the conduction patterns being a factor in increasing the area of ​​the power semiconductor chip mounting substrate or in preventing an increase in the number of chips to be mounted.

[0109] Accordingly, adopting the configuration of the present example, in addition to the advantageous effects of the present invention described in the section of Example 1, makes it possible to prevent the substrate area from increasing, even in a case where several power semiconductor chips are arranged in parallel in two columns.

[0110] For the circuit section of the upper branch, control signals can be supplied to the gate electrodes of the power semiconductor chips 11 to 16 via the control terminal 91 of gate 1, which is electrically connected to conductor 95, and via the control terminal 92 of source detection 1, which is electrically connected to conductor 96.

[0111] Similarly, control signals for the circuit section of the lower branch can also be supplied to the gate electrodes of the power semiconductor chips 21 to 26 via the control terminal 93 of the gate 1, which is electrically connected to a conductor 97, and via the control terminal 94 of the source sensing 1, which is electrically connected to a conductor 98.

[0112] Compared to the corresponding module structure of the state of the art, the area of ​​the base area of ​​the power semiconductor module assumed in the present example can be reduced to 83%.

[0113] Although the reduction rate, as above, depends on the design rule applied to a power semiconductor chip mounting substrate, it is noted that the area reduction effect is evidently due to the structure of the substrate. Fig. 2 shown power semiconductor chip mounting substrate is obtained.

[0114] As described above, in the power semiconductor module of the present example, several power semiconductor chips 11 to 16 are arranged in several chip groups on the conductive pattern (the metal pattern 1), each group containing a given number of chips. The first wiring (the contact wires 31, 33) of each chip group is connected to a common gate control terminal 91, and the second wiring (the contact wires 32, 34) of each chip group is connected to a common source sensing control terminal 92.

[0115] The present example illustrates an instance in which the circuit sections of the upper and lower branches have the same number of power semiconductor chips, wherein each chip group contains three chips and there are two chip groups. The advantageous effects of the present invention can be obtained even if the number of chips belonging to each chip group and the number of chip groups differ from those shown. For example, advantageous effects of the present invention can be obtained even if two chip groups are arranged side by side and each chip group contains a different number of chips. This is also true even if the number of chip groups present in each branch circuit section is three or more. Inventive embodiment

[0116] Based on Fig. Section 10 describes a power semiconductor module according to the invention. Fig. The power semiconductor module shown in Figure 10 contains slot patterns 71A and 71B, which are formed in place of the conductive pattern 2 of drain 2 and the conductive pattern 3 of source 2, respectively, on the power semiconductor chip mounting substrate 103. The slot patterns 71A and 71B are arranged in point-symmetrical positions relative to each other.

[0117] A slot pattern 71A reduces the imbalance of the inductances of the paths of the source main current, which flows from the source electrode terminal surfaces of several MOSFET-type power semiconductor chips 11 to 13 via several contact wires 35A, 35B, 35C and flows into the feed point 64 of the drain 2, which is connected to the terminal at an intermediate potential (AC terminal).

[0118] A path of the source current flowing from a power semiconductor chip 13 via the conductive pattern 2 of drain 2 to the feed point 64 of drain 2 is the shortest, and such a path from the power semiconductor chip 11 is the longest. The slot pattern 71A, which, as in Fig. The slot 71A, shown in Figure 10, is formed in place of the conductive pattern 2 of drain 2 and is formed in the form of an inverted L to redirect the current path from the power semiconductor chip 13, which is closest to the feed point 64 of drain 2. The introduction of slot 71A allows for a reduction in the inductance variation of the source current paths from the power semiconductor chips 11 to 13.

[0119] Similarly, the power semiconductor chips 14 to 16 are also connected from the source electrode terminals via several contact wires 35D, 35E, 35F to the feed point 64 of drain 2, which is connected to the terminal at an intermediate potential (AC terminal). However, no slot pattern is formed in the conductive pattern 2 of drain 2 in its place for the power semiconductor chips 14 to 16. The power semiconductor chips 14 to 16 are electrically far apart from the power semiconductor chips 11 to 13, so a slot pattern that would further increase the inductance is not applied.

[0120] The above description concerns the circuit section of the upper branch. The function of a slot pattern 71B formed in its place in the line pattern 3 of Source 2 is the same as above, so its description has been omitted.

[0121] Although the slot patterns formed in the shape of an inverted L are shown as an example of their shape, it is noted that an advantageous effect of the present example can be obtained with L-shaped or I-shaped slot patterns or the like within a range that does not deviate from the above description.

[0122] As described in the preceding context, in the power semiconductor module according to the invention, the second conductive pattern (the metal pattern 2) is connected to the source electrode terminals 502 of the multiple power semiconductor chips 11 to 13 on the first conductive pattern (the metal pattern 1) by the multiple contact wires 35A, 35B, 35C and has a first slot pattern 71A formed in an L-shape or in an I-shape to reduce variation in the inductances of the source current paths between connection points where the contact wires 35A, 35B, 35C are connected to the second conductive pattern (the metal pattern 2) and to the feed point 64 on the second conductive pattern (the metal pattern 2).Furthermore, the third conductive pattern (the metal pattern 3) is connected to the source electrodes of the multiple power semiconductor chips on the second conductive pattern (the metal pattern 2) by several contact wires 45A, 45B, 45C and has the second slot pattern 71B, which is formed in an L-shape or in an I-shape, to reduce the variation in the inductances of the source current paths between connection points where the contact wires 45A, 45B, 45C are connected to the third conductive pattern (the metal pattern 3) and to the feed point 63 on the third conductive pattern (the metal pattern 3).

[0123] The structure of the power semiconductor chip mounting substrate 103 according to the invention, which employs the slot patterns 71A and 71B, makes it possible, in comparison to the structure of the one described in section 2 of Example 2 ( Fig.9) to improve the current balance between the mounted power semiconductor chips in the power semiconductor module shown.

[0124] According to each previously described example of the present invention and embodiment, the power semiconductor module has the internal structure that makes it possible to improve the efficiency of mounting power semiconductor chips on the power semiconductor chip mounting substrate and to reduce the area of ​​the power semiconductor chip mounting substrate or to increase the number of power semiconductor chips that can be mounted on the substrate with a prescribed area.

[0125] Simultaneously, the structure of the present invention enables a reduction in the difference between the gate drive voltage observed at the gate drive terminals of the semiconductor module and the gate drive voltage waveform for the power semiconductor chips mounted in the power semiconductor module. The aforementioned advantageous effects allow for a reduction in the size of a power semiconductor module, on which, in particular, high-performance composite semiconductor chips with a smaller chip area are mounted, or for the realization of a high-current power semiconductor module by mounting a larger number of chips. At the same time, it makes it possible to adjust the gate drive signal waveform at high speed or with the highest possible voltage, while suppressing any noise voltage generated by switching within the gate voltage range of the power semiconductor chips.It is possible to create a power semiconductor module that allows it to fully utilize the capabilities of the power semiconductor module.

[0126] More precisely, the internal structure of the power semiconductor module enables fast switching with multiple power semiconductor chips arranged in parallel. Consequently, it is possible to improve the performance of a power semiconductor module by mounting composite semiconductor chips made of SiC (silicon carbide) or GaN (gallium nitride) on it. The chip area of ​​these chips is smaller than that of Si semiconductor chips due to their lower chip yield; that is, the module's rated current can be increased while switching losses can be reduced.

[0127] It is noted that the present invention would be more effective if applied to composite semiconductor chips with a smaller form factor, since their chip yield is low due to crystal defects arising from the substrate and manufacturing process problems. In particular, when applied to vertically structured SiC power MOSFET chips fabricated using a SiC substrate, only one type of SiC power MOSFET chip needs to be mounted on the circuit board, thus achieving higher chip assembly efficiency, as the chips also incorporate a return-flux diode function.

[0128] Advantageous effects of the present invention remain unchanged, for example, even if the switching elements of the MOSFET type (MOS field-effect transistors) used in the present examples are changed to other unipolar devices of the J-FET field (junction field-effect transistors) or bipolar devices such as of the IGBT type (insulated-film bipolar transistors), and furthermore, if the functions of the terminals are reversed, e.g., by changing from drain to collector, from source to emitter, and from gate to base. It is also evident for diode elements that advantageous effects of the present invention remain unchanged even when either PN junction diodes or SB diodes (Schottky junction diodes) are used. Reference symbol list 1 to 7 metal patterns (conductive patterns) on the isolated substrate 9, 10 solder joint layers 11 to 16, 21 to 26 power semiconductor chips, 31 to 34, 35A to 35C, 41 to 44, 45A to 45C contact wires, 36, 46 wires for wiring the gates, 37, 47 wires for wiring the sources, 51, 63A, 63B, 64 connections (feed points for connections on the substrate), 52, 62 connections (feed points for monitoring the potential on the substrate), 71A, 71B slot pattern, 91, 93 Gate control connectors, 92, 94 Source acquisition control connections, 95, 97 conductors (for the gate connection between chips), 96, 98 conductors (for the source detection connection between chips), 99 isolated substrate, 100 to 103 power semiconductor chip mounting substrate, 300 base plate 310 resin housing 501 Gate electrode connection area (of a power semiconductor chip), 502 Source electrode connection area (of a power semiconductor chip), 601, 602, 603 (simplified) equivalent circuits, Mg1 to Mg6, M16, M25, M34 mutual inductances, Ld1 to Ld6 parasitic inductances of MOSFET drain paths, Ls1 to Ls6 parasitic inductances of MOSFET source main current paths, Lg1 to L[s]g6 parasitic inductances of MOSFET gate paths, Lss1 to Lss6 parasitic inductances of MOSFET source control paths, Rgc11 to Rgc13, Rgc21 to Rgc23 are values ​​of resistors on gate paths within MOSFET chips.

Claims

[1] Power semiconductor module comprising: an isolated substrate (99); a first conductive pattern (1) laid on the isolated substrate (99); several first power semiconductor chips (11, 12, 13) arranged on the first conductive pattern (1); a first wiring (31) which is formed in a bridging configuration and which is formed for directly connecting respective gate electrodes of the several first power semiconductor chips (11, 12, 13); and a second wiring (32) which is formed in a bridging manner and which is formed for directly connecting respective source electrodes of the several first power semiconductor chips (11, 12, 13); a gate control terminal (91) which is electrically isolated from the first conductive pattern (1) and is arranged in a resin housing; and a source detection control terminal (92) which is arranged separately in a housing away from the first conductive pattern (1), wherein the first wiring (31) is arranged next to the second wiring and is angled within 30 degrees with respect to the second wiring (32), and connects the gate control terminal (91) to a gate electrode of a power semiconductor chip, and wherein the second wiring (32) connects the source sensing control terminal (92) to a source electrode of the power semiconductor chip; wherein the power semiconductor module further comprises: a second conductive pattern (2) laid on the isolated substrate; several second power semiconductor chips arranged on the second conductive pattern (2); a third wiring (43) formed for bridging and directly connecting respective gate electrodes of the several second power semiconductor chips on the second conductive pattern (2); and a fourth wiring (44) formed to bridge and directly connect respective source electrodes of the multiple second power semiconductor chips on the second conductive pattern (2); wherein the third wiring (43) is arranged next to the fourth wiring (44) and is angled within 30 degrees with respect to the fourth wiring (42); wherein a third conductive pattern (3) is arranged between the first conductive pattern (1) and the second conductive pattern (2), adjacent to the second conductive pattern (2); and there is a section where the directions of the currents flowing through the second conductive pattern (2) and through the third conductive pattern (3) differ by 180 degrees; wherein the second conductive pattern (2) is connected by several contact wires (35A, 35B, 35C) to the source electrodes of the several first power semiconductor chips (11, 12, 13) on the first conductive pattern (1), wherein the source current path of a source current flowing from a power semiconductor chip (13) of the several first power semiconductor chips (11, 12, 13) that is closest to a feed point (64) of the second conductive pattern (2) via the second conductive pattern (2) to the feed point (64) is the shortest, and the source current path of a source current flowing from another power semiconductor chip (11) of the several first power semiconductor chips (11, 12, 13) via the second conductive pattern (2) to the feed point (64) is the longest, and wherein a first slot pattern (71A) is formed in an L-shape or in an I-shape in the second conductive pattern (2) to guide the source current path from the power semiconductor chip (13),to redirect the current path that is closest to the feed point (64), thereby reducing variations in the inductances of the source current paths from the several first power semiconductor chips (11, 12, 13) to the feed point (64); and, The third conductive pattern (3) is connected to the source electrodes of the multiple second power semiconductor chips on the second conductive pattern (2) by multiple contact wires (45A, 45B, 45C), wherein the source current path of a source current flowing from a power semiconductor chip of the multiple second power semiconductor chips nearest to a feed point (63) of the third conductive pattern (3) across the third conductive pattern (3) to the feed point (63) is the shortest, and the source current path of a source current flowing from another power semiconductor chip of the multiple second power semiconductor chips across the third conductive pattern to the feed point (63) is the longest, and wherein a second slot pattern (71B) is formed in an L-shape or in an I-shape in the third conductive pattern (3) to define the source current path from the power semiconductor chip nearest to the feed point (63) is nearest, to redirect,and thus reduce the variation in inductances of the source current paths from the multiple second power semiconductor chips to the feed point (63). [2] Power semiconductor module according to claim 1, wherein the first slot pattern (71A) and the second slot pattern (71B) are arranged at point-symmetric positions. [3] Power semiconductor module according to claim 1, wherein each of the multiple first and second power semiconductor chips (11, 12, 13) has both a current switching function and a reverse flow function. [4] Power semiconductor module according to claim 1, wherein each of the multiple first and second power semiconductor chips (11, 12, 13) includes a built-in resistor having a predefined resistance value to act on impedances of the chip internal paths, as seen from gate electrode connection surfaces. [5] Power semiconductor module according to claim 4, wherein each of the multiple first and second power semiconductor chips (11, 12, 13) includes a built-in resistor made of polysilicon. [6] Power semiconductor module according to any one of claims 1 to 5, wherein the multiple first and second power semiconductor chips (11, 12, 13) are SiC power semiconductor chips.

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