OPTOELECTRONIC SEMICONDUCTOR CHIP AND METHOD FOR MANUFACTURING AN OPTOELECTRONIC SEMICONDUCTOR CHIP

Abstract

Optoelectronic semiconductor chip, including: - a composite (1) comprising a front face (10), a first semiconductor layer sequence (11) and a second semiconductor layer sequence (12) between the front face (10) and the first semiconductor layer sequence (1), - a first contact element (21) and a second contact element (22) on one side of the composite (1) opposite the front side (10), - a first via (31) and a second via (32), each extending from the side opposite the front face (10) into the composite (1), wherein - the first (11) and the second (12) semiconductor layer sequence (11) each comprise an active layer (11b, 12b) for generating or absorbing electromagnetic radiation, - the first contact element (21) and the first via (31) are set up for electrical contacting the first semiconductor layer sequence (11), - the second contact element (22) and the second via (32) are set up for electrical contacting the second semiconductor layer sequence (12), - the first via (31) passes through the active layer (11b) of the first semiconductor layer sequence (11) and the second via (32) passes through the active layer (12b) of the second semiconductor layer sequence (12), - the contact elements (21, 22) and the vias (31, 32) are arranged such that the first semiconductor layer sequence (11) and the second semiconductor layer sequence (12) are electrically connected in parallel, so that charge carriers can flow through both semiconductor layer sequences (11, 12) simultaneously during operation, whereby charge carriers flowing through the first semiconductor layer sequence (11) do not enter the second semiconductor layer sequence (12) and vice versa, and - the second via (32) is guided through the second contact element (22) and is electrically insulated from the second contact element (22).

Description

[0001] An optoelectronic semiconductor chip and a method for producing an optoelectronic semiconductor chip are specified.

[0002] One problem to be solved is to provide an optoelectronic semiconductor chip with high luminance. Another problem to be solved is to provide a method for producing such a semiconductor chip.

[0003] These objects are achieved, among other things, by the subject matter and method of the independent patent claims. Advantageous embodiments and further developments are the subject matter of the dependent patent claims.

[0004] From the documents DE 10 2016 104 280 A1, DE 10 2017 113 573 A1, DE 10 2017 105 739 A1 and US 2005 / 0 067 627 A1 an optoelectronic semiconductor chip and a method for producing an optoelectronic semiconductor chip are known.

[0005] First, the optoelectronic semiconductor chip is specified. The optoelectronic semiconductor chip is, in particular, an LED chip for emitting electromagnetic radiation in the UV, visible, or infrared range. In particular, the semiconductor chip is intended for use in a headlight, for example, a projection headlight or a car headlight. The semiconductor chip can also be used in lamps for interior or exterior lighting, or as a flashlight or display illumination in a mobile phone.

[0006] A semiconductor chip is understood here and below to be a separately handled and electrically contactable element. A semiconductor chip is created, in particular, by severing a wafer composite. In particular, the side surfaces of a semiconductor chip then exhibit traces from the wafer composite separation process, for example.

[0007] The optoelectronic semiconductor chip comprises a composite having a front side, a first semiconductor layer sequence, and a second semiconductor layer sequence. The second semiconductor layer sequence is arranged between the front side and the first semiconductor layer sequence.

[0008] The front side is, in particular, a cover surface of the composite. The front side is, for example, a radiation exit surface of the composite or the semiconductor chip. During normal operation of the semiconductor chip, for example, at least 50% or at least 75% of the radiation generated in the semiconductor chip is coupled out via the front side. The front side can be formed by the second semiconductor layer sequence.

[0009] The semiconductor layer sequences are each based on a III-V compound semiconductor material. The semiconductor material is, for example, a nitride compound semiconductor material, such as Al n In1-n-m Ga m N, or a phosphide compound semiconductor material such as Al n In 1-n-m Ga m P, or an arsenide compound semiconductor material such as Al n In 1-n-m Ga m Ace or Al n In 1-n-m Ga m AsP, where 0 ≤ n ≤ 1, 0 ≤ m ≤ 1, and m + n ≤ 1. The semiconductor layer sequences can contain dopants as well as additional components. For the sake of simplicity, however, only the essential components of the crystal lattice of the semiconductor layer sequence, i.e., Al, As, Ga, In, N, or P, are specified, even though these may be partially replaced and / or supplemented by small amounts of other substances. The semiconductor layer sequences are preferably based on AlInGaN.

[0010] The first semiconductor layer sequence can directly border the second semiconductor layer sequence, or a connecting layer, in particular an electrically insulating connecting layer, can be arranged between the first semiconductor layer sequence and the second semiconductor layer sequence. The connecting layer comprises, for example, SiO2, SiN, or silicon. The first semiconductor layer sequence and the second semiconductor layer sequence are preferably electrically insulated from one another. This means that, during normal operation, no current flows between two facing sides of the two semiconductor layer sequences.

[0011] The optoelectronic semiconductor chip comprises a first contact element and a second contact element on a side of the composite opposite the front side. The two contact elements are electrically conductive, in particular metallic. For example, the first and second contact elements each comprise one or more of the following materials: Al, Ag, Au, Cu, Ni, Ti, Cr.

[0012] The optoelectronic semiconductor chip comprises a first via and a second via, each extending into the composite from the side of the composite opposite the front side. The vias are electrically conductive. They comprise, for example, a metal, such as one of the metals mentioned in the last paragraph. The vias extend into the composite without completely penetrating it. This means that the vias end within the composite.

[0013] The first and second semiconductor layer sequences each comprise an active layer. The active layers are each configured to generate or absorb electromagnetic radiation. The active layers of the two semiconductor layer sequences are arranged differently from one another and spaced apart from one another in a direction perpendicular to the front side.

[0014] Preferably, the first and second semiconductor layer sequences each further comprise a first and a second layer of semiconductor material, between which the associated active layer is arranged. The first and second layers can each have a multilayer structure. The first layers of both semiconductor layer sequences are, for example, n-doped and the second layers p-doped, or vice versa. The two semiconductor layer sequences are preferably arranged one above the other such that the second layer of the first semiconductor layer sequence and the first layer of the second semiconductor layer sequence face each other.

[0015] The active layers of the two semiconductor layer sequences run, in particular, parallel or substantially parallel to one another. The lateral extent of the semiconductor chip, measured along the front side or along a main extension plane of the front side, is, for example, at most 20%, at most 10%, or at most 5% larger than the lateral extent of the second semiconductor layer sequence or its active layer.

[0016] The active layers of the semiconductor layer sequences each contain at least one pn junction and / or at least one quantum well structure in the form of a single quantum well (SQW) or a multi-quantum well (MQW) structure. During normal operation, the active layers generate, for example, electromagnetic radiation in the blue, green, or red spectral range, or in the UV or IR range.

[0017] The contact elements are each made of a material that reflects the radiation generated by the active layers, for example, on a side facing the composite. Alternatively or additionally, a dielectric mirror is arranged between the contact elements and the composite, with an electrical connection from the contact elements to the composite then being formed, for example, via contact pins through the dielectric mirror.

[0018] The first contact element and the first via are configured to electrically contact the first semiconductor layer sequence. The second contact element and the second via are configured to electrically contact the second semiconductor layer sequence.

[0019] During intended operation of the semiconductor chip, the first contact element and the first via are at different potentials. For example, the first contact element is electrically connected to the first layer of the first semiconductor layer sequence, and the first via is electrically connected to the second layer of the first semiconductor layer sequence. The first contact element and the first via can directly border the respective layers of the first semiconductor layer sequence. The above disclosure applies accordingly to the second contact element and the second via.

[0020] The contact elements and vias are configured so that the first semiconductor layer sequence and the second semiconductor layer sequence can be contacted in parallel, i.e., electrically connected in parallel. This means that during operation, charge carriers can flow through both semiconductor layer sequences simultaneously, with charge carriers flowing through the first semiconductor layer sequence not reaching the second semiconductor layer sequence, and vice versa.

[0021] The first via is routed through the active layer of the first semiconductor layer sequence, and the second via is routed through the active layer of the second semiconductor layer sequence. For example, the second via is also routed through the first semiconductor layer sequence, so that the second via is partially or completely laterally surrounded by the first semiconductor layer sequence in the region of the first semiconductor layer sequence. "Lateral" here and below means in the lateral direction, i.e., in a direction parallel to the front side or the main extension plane of the front side.

[0022] The first via penetrates the first layer and the active layer of the first semiconductor layer sequence and ends in the second layer of the first semiconductor layer sequence. The second via penetrates the first layer and the active layer of the second semiconductor layer sequence and ends in the second layer of the second semiconductor layer sequence. In particular, the first and second vias end at different distances from the front side.

[0023] Advantageously, the first via is electrically insulated from the first semiconductor layer sequence in the region of the first layer and the active layer of the first semiconductor layer sequence. The first via is preferably completely surrounded laterally by the active layer of the first semiconductor layer sequence. Preferably, the first via does not protrude into the second semiconductor layer sequence. Advantageously, the second via is electrically insulated from the first semiconductor layer sequence in the region of the first semiconductor layer sequence. In the region of the first layer and the active layer of the second semiconductor layer sequence, the second via is preferably electrically insulated from the second semiconductor layer sequence. The second via is preferably completely surrounded laterally by the active layer of the second semiconductor layer sequence.

[0024] The optoelectronic semiconductor chip comprises a composite with a front side, a first semiconductor layer sequence, and a second semiconductor layer sequence between the front side and the first semiconductor layer sequence. The semiconductor chip comprises a first contact element and a second contact element on a side of the composite opposite the front side, as well as a first via and a second via, each extending into the composite from the side of the composite opposite the front side. The first and second semiconductor layer sequences each comprise an active layer for generating or absorbing electromagnetic radiation.The first contact element and the first via are configured to electrically contact the first semiconductor layer sequence, and the second contact element and the second via are configured to electrically contact the second semiconductor layer sequence. The first via is routed through the active layer of the first semiconductor layer sequence, and the second via is routed through the active layer of the second semiconductor layer sequence.

[0025] Advantageously, the semiconductor chip structure described here, with two semiconductor layer sequences, each comprising an active layer, and contacting the semiconductor layer sequences using a via, results in an increase in the active area during operation while maintaining a relatively small radiating area (front surface area). This achieves high luminance. In contrast to the use of contact elements on both the front and the side opposite the front, the structure described here allows for reduced power loss because a transition region in the form of a tunnel barrier is omitted.

[0026] According to at least one embodiment, the second contact element is guided through the first semiconductor layer sequence to the second semiconductor layer sequence. The second contact element therefore extends from the side of the composite opposite the front side into the composite and reaches to the second semiconductor layer sequence. In the region of the first semiconductor layer sequence, the second contact element is partially or completely surrounded by the first semiconductor layer sequence. However, the second contact element does not penetrate the active layer of the second semiconductor layer sequence. Preferably, the second contact element borders the first layer of the second semiconductor layer sequence and is in direct electrical contact with this layer.

[0027] According to at least one embodiment, the first and second contact elements are electrically connected to one another and, during normal operation, are at the same potential. For example, the first contact element and the second contact element are formed integrally, in particular as a single piece.

[0028] According to at least one embodiment, the first and second vias are electrically conductively connected to one another and are at the same potential during normal operation. The first via and the second via are, in particular, formed integrally with one another, for example, as one piece.

[0029] According to at least one embodiment, the first and second contact elements can be electrically contacted independently of one another. Alternatively or additionally, the first and second vias can be electrically contacted independently of one another. As a result, in particular, the first and second semiconductor layer sequences can be contacted or operated independently of one another. Thus, radiation can be generated or absorbed in the active layer of the first semiconductor layer sequence while the active layer of the second semiconductor layer sequence is inoperative, and vice versa.

[0030] According to at least one embodiment, the active layers of the first and second semiconductor layer sequences are configured to emit radiation of different wavelengths. For example, a global intensity maximum of the radiation generated by the active layer of the first semiconductor layer sequence lies at a different wavelength, for example, at a wavelength shifted by at least 20 nm or at least 50 nm, than a global intensity maximum of the radiation emitted by the active layer of the second semiconductor layer sequence.

[0031] The second via is routed through the second contact element and is electrically insulated from the second contact element. Particularly in the region of the first semiconductor layer sequence, the second via is preferably completely surrounded laterally by the second contact element.

[0032] According to at least one embodiment, the second semiconductor layer sequence is formed contiguously. In particular, the active layer of the second semiconductor layer sequence is contiguous. In the region of the second via, the active layer is interrupted by the second via.

[0033] According to at least one embodiment, the first semiconductor layer sequence comprises a plurality of semiconductor blocks laterally spaced from one another. In other words, the first semiconductor layer sequence is not formed contiguously, but is divided into a plurality of non-contiguous semiconductor blocks. The semiconductor blocks are distributed along the second semiconductor layer sequence. For example, the semiconductor blocks of the first semiconductor layer sequence are arranged at regular intervals from one another on the second semiconductor layer sequence. The semiconductor blocks are arranged, for example, in a rectangular pattern on the second semiconductor layer sequence. For example, the first semiconductor layer sequence comprises at least 10, or at least 100, or at least 10,000 such semiconductor blocks.

[0034] Each semiconductor block comprises an active layer. The active layer of each semiconductor block is preferably formed as a continuous layer. The active layers of different semiconductor blocks are separated from each other and are not connected.

[0035] The semiconductor blocks of the first semiconductor layer sequence each have, for example, a square base area. In particular, the lateral dimensions of the semiconductor blocks can each be between 5 µm and 500 µm inclusive. Preferably, the lateral dimensions of the semiconductor blocks are each in the range between 10 µm and 200 µm inclusive or between 10 µm and 100 µm inclusive.

[0036] According to at least one embodiment, the second contact element extends in the region between the semiconductor blocks up to the second semiconductor layer sequence. For example, the second contact element forms a frame, in particular a coherent and closed frame, around at least one or each of the semiconductor blocks in the lateral direction. Viewed in a cross-sectional view along the first semiconductor layer sequence, the second contact element preferably forms a grid, wherein the semiconductor blocks lie in the meshes of the grid and each mesh is uniquely assigned to a semiconductor block. The second vias preferably run in the region of the intersection points of the grid lines.

[0037] According to at least one embodiment, the semiconductor chip comprises a plurality of the first and / or second vias. For example, the semiconductor chip comprises at least 10, or at least 100, or at least 10,000 of the first and / or second vias. All features disclosed for the first and second vias are also disclosed for all further first and second vias.

[0038] The first vias are preferably all electrically connected to one another and can only be operated together. Likewise, the second vias are preferably all electrically connected to one another and can only be operated together.

[0039] Alternatively, the first vias can be contacted individually and independently of one another. For example, the first semiconductor layer sequence is divided into a plurality of emission fields or pixels, wherein each first via is uniquely or one-to-one assigned to a pixel. First vias assigned to different pixels of the first semiconductor layer sequence can, for example, be contacted individually and independently of one another, so that the individual pixels of the first semiconductor layer sequence can be operated individually and independently of one another. The semiconductor blocks can form the pixels of the first semiconductor layer sequence. The semiconductor blocks can, for example, be controlled individually and independently of one another.

[0040] Likewise, the second vias can be contacted individually and independently of one another. For example, the second semiconductor layer sequence is divided into a plurality of emission fields or pixels, with each second via being uniquely or one-to-one assigned to a pixel. Second vias assigned to different pixels of the second semiconductor layer sequence can be contacted individually and independently of one another, for example, so that the individual pixels of the second semiconductor layer sequence can be operated individually and independently of one another.

[0041] The optoelectronic semiconductor chip can therefore in particular be a pixelated, optoelectronic semiconductor chip, which can be advantageous, for example, when used in a car headlight.

[0042] According to at least one embodiment, at least one first via is uniquely, preferably uniquely, assigned to each semiconductor block of the first semiconductor layer sequence. The assigned first via preferably extends through the semiconductor block and is completely surrounded laterally by the semiconductor material of the semiconductor block.

[0043] According to at least one embodiment, the first semiconductor layer sequence is formed contiguously. In particular, the active layer of the first semiconductor layer sequence is formed contiguously. In the region of the first vias, the active layer of the first semiconductor layer sequence is interrupted by the first vias.

[0044] According to at least one embodiment, the first and second semiconductor layer sequences, preferably also the respectively associated active layer, each extend over at least 80% or at least 90% of the lateral extent of the semiconductor chip.

[0045] According to at least one embodiment, the first semiconductor layer sequence has a thickness between 1 µm and 5 µm, preferably between 1.5 µm and 2.5 µm. The second semiconductor layer sequence has, for example, a thickness between 3 µm and 10 µm, preferably between 4 µm and 6 µm. The thickness is measured perpendicular to the front side or perpendicular to the main extension plane of the front side. Here and below, the thickness is understood to mean the maximum, average, or minimum thickness.

[0046] According to at least one embodiment, the optoelectronic semiconductor chip comprises a carrier on a side of the composite opposite the front side. The carrier is formed, for example, from an electrically insulating material, such as a plastic. The carrier can be an active or passive matrix element. The carrier stabilizes the composite.

[0047] According to at least one embodiment, the second contact element comprises a mirror, for example a metallic mirror or a Bragg mirror, on a side facing the second semiconductor layer sequence. The mirror is reflective of the radiation generated by the active layer of the second semiconductor layer sequence.

[0048] Next, the method for producing an optoelectronic semiconductor chip is specified. In particular, the method can be used to produce an optoelectronic semiconductor chip as described here. All features disclosed in connection with the optoelectronic semiconductor chip are therefore also disclosed for the method, and vice versa.

[0049] The method comprises a step A) in which a composite comprising a first semiconductor layer sequence with an active layer and a second semiconductor layer sequence with an active layer is formed. The composite comprises a front side. The second semiconductor layer sequence is arranged between the front side and the first semiconductor layer sequence.

[0050] In a step B1) of the method, a first contact element is formed. In a step B2) of the method, a first via is formed. The first via is passed through the active layer of the first semiconductor layer sequence. The first contact element and the first via are configured to electrically contact the first semiconductor layer sequence.

[0051] In a step C1) of the method, a second contact element is formed on a side of the composite opposite the front side. In a step C2) of the method, a second via is formed, wherein the second contact element and the second via are configured to electrically contact the second semiconductor layer sequence. The second via is guided through the active layer of the second semiconductor layer sequence.

[0052] Steps B1), B2), C1), and C2 can be performed after step A. Steps B1 and C1 are then performed together, for example, thus constituting a single process step. Steps B2 and C2 can also be performed together.

[0053] Alternatively, steps B1) and B2) are performed before step A). ​​Steps C1) and C2) are then performed after step A).

[0054] According to at least one embodiment, a plurality of semiconductor blocks, each with an active layer, is provided in step A). ​​The semiconductor blocks are applied as separate elements spaced apart from one another on the second semiconductor layer sequence and together form the first semiconductor layer sequence. The distance between any two adjacent semiconductor blocks is, for example, at least 2 µm and / or at most 100 µm.

[0055] According to at least one embodiment, step B2) is performed before step A). ​​In particular, the semiconductor blocks are provided with first vias before they are applied to the second semiconductor layer sequence. Likewise, step B1) can be performed before step A). ​​This means that the semiconductor blocks are then each provided with a first contact element before the semiconductor blocks are applied to the second semiconductor layer sequence. In particular, the semiconductor blocks are provided in the form of functional micro-LED chips. The micro-LED chips can also be operated without the second semiconductor layer sequence and emit electromagnetic radiation during operation.

[0056] According to at least one embodiment, in step A), the first semiconductor layer sequence is applied as a coherent semiconductor layer sequence on the second semiconductor layer sequence.

[0057] According to at least one embodiment, after step A), the first semiconductor layer sequence, in particular the contiguous first semiconductor layer sequence, is segmented into a plurality of semiconductor blocks. For this purpose, a mask and an etching process are used, for example.

[0058] According to at least one embodiment, in step A), the first semiconductor layer sequence and the second semiconductor layer sequence are bonded to one another. In particular, a wafer-to-wafer bonding process is used. For example, a direct bonding process or thermocompression bonding is used. In particular, the individual semiconductor blocks or micro-LED chips are bonded to the second semiconductor layer sequence.

[0059] According to at least one embodiment, in step A), the second semiconductor layer sequence and the first semiconductor layer sequence, or the individual semiconductor blocks, are bonded to one another. A connecting layer, for example in the form of an adhesive layer, is then present between the first semiconductor layer sequence and the second semiconductor layer sequence. The connecting layer has, for example, a thickness of at most 200 nm or at most 100 nm. The connecting layer is based, for example, on a silicone. The connecting layer is, in particular, electrically insulating.

[0060] According to at least one embodiment, in step A), the first semiconductor layer sequence and the second semiconductor layer sequence are epitaxially grown on top of one another. For example, an electrically insulating connecting layer made of a semiconductor material is then grown between the first semiconductor layer sequence and the second semiconductor layer sequence. The connecting layer is then, for example, nominally undoped.

[0061] Further advantageous embodiments and developments of the optoelectronic semiconductor chip and of the method for producing an optoelectronic semiconductor chip will become apparent from the exemplary embodiments described below in conjunction with the figures. Identical, similar, or similarly acting elements are provided with the same reference numerals in the figures. The figures and the relative sizes of the elements shown in the figures are not to be considered to scale. Rather, individual elements, in particular layer thicknesses, may be exaggerated for clarity and / or clarity.

[0062] They show: Fig. 1A to 1C show various views of a first embodiment of the optoelectronic semiconductor chip, Fig. 2 to 4 cross-sectional views of further embodiments of the optoelectronic semiconductor chip, Fig. 5A and Fig. 5B shows another embodiment of the optoelectronic semiconductor chip in different views, Fig. 6A to 7E show different positions in two embodiments of the method for producing an optoelectronic semiconductor chip.

[0063] In the Fig. Figure 1A shows a first embodiment of the optoelectronic semiconductor chip in a cross-sectional view. The semiconductor chip is, for example, an LED chip. The optoelectronic semiconductor chip comprises a composite 1 with a front side 10 and a rear side 13 opposite the front side 10. The front side 10 forms, in particular, a radiation exit surface of the semiconductor chip, via which a large portion of the generated radiation is coupled out during normal operation of the semiconductor chip.

[0064] The composite 1 comprises a first semiconductor layer sequence 11 and a second semiconductor layer sequence 12, wherein the first semiconductor layer sequence 11 is arranged downstream of the second semiconductor layer sequence 12 in the direction away from the front side 10. A connecting layer 14 is provided between the first semiconductor layer sequence 11 and the second semiconductor layer sequence 12, which mechanically connects the two semiconductor layer sequences 11, 12 to one another. The connecting layer 14 is preferably electrically insulating. In the present case, the connecting layer 14 is, for example, an adhesive layer, for example, made of a silicone adhesive.

[0065] The first semiconductor layer sequence 11 comprises a first layer 11a of semiconductor material, a second layer 11c of semiconductor material, and an active layer 11b between the first layer 11a and the second layer 11c. The second semiconductor layer sequence 12 comprises a first layer 12a of semiconductor material, a second layer 12a of semiconductor material, and an active layer 12b therebetween. The first layers 11a, 12a are doped oppositely to the second layers 11c, 12c. The two first layers 11a, 12a have, for example, a p-doping, while the two second layers 11c, 12c have, for example, an n-doping, or vice versa.

[0066] The optoelectronic semiconductor chip comprises a first contact element 21 and a second contact element 22 on the rear side 13 of the composite 1, opposite the front side 10. In this case, the two contact elements 21, 22 are connected, even integrally formed with one another. The two contact elements 21, 22 are formed, for example, from a metal such as silver.

[0067] The first contact element 21 borders on the first layer 11a of the first semiconductor layer sequence 11 and contacts it. The second contact element 22 comprises regions that extend through the first semiconductor layer sequence 11 to the first layer 12a of the second semiconductor layer sequence 12. In these regions, the second contact element 22 contacts the first layer 12a. In these regions, the second contact element 22 is electrically insulated from the first semiconductor layer sequence 11 by an insulating material 5. The insulating material 5 is, for example, SiO2 or SiN. The insulating material 5 between the second contact element 22 and the first semiconductor layer sequence 11 can also be a dielectric mirror.

[0068] Furthermore, the semiconductor chip comprises first vias 31, which extend from the rear side 13 into the composite 1. The first vias 31 penetrate the first layer 11a and the active layer 11b of the first semiconductor layer sequence 11 and open into the second layer 11c of the first semiconductor layer sequence 11. There, the first vias 31 contact the second layer 11c. The first semiconductor layer sequence 11 is thus electrically contacted via the first contact element 21 and the first vias 31. The first vias 31 are insulated from the semiconductor layer sequence 11 by the insulating material 5 in the region of the first layer 11a and the active layer 11b.

[0069] Furthermore, second vias 32 are provided in the semiconductor chip, each extending from the rear side 13 through the first semiconductor layer sequence 11 into the second semiconductor layer sequence 12. They completely penetrate the first semiconductor layer sequence 11. The second vias 32 further penetrate the first layer 12a and the active layer 12b of the second semiconductor layer sequence 12 and open into the second layer 12c of the second semiconductor layer sequence 12. The second vias 32 are electrically insulated from the second semiconductor layer sequence 12 by the insulating material 5 in the region of the first layer 12a and the active layer 12b.

[0070] In the Fig. 1A also shows that the second vias 32 are guided through the regions of the second contact element 22, which in turn are guided through the first semiconductor layer sequence 11.

[0071] In the present exemplary embodiment, the first vias 31 and the second vias 32 are electrically connected to one another and are at the same potential during normal operation of the semiconductor chip. The same applies to the first and second contact elements 21, 22. The first and second vias comprise or consist of, for example, Al.

[0072] The semiconductor chip of the Fig. 1A comprises a carrier 6, for example a plastic carrier. The carrier 6 carries the composite 1 and stabilizes it. On a side of the carrier 6 facing away from the composite 1, connection regions 7, 8 are provided. One connection region 7 is electrically conductively connected to the first contact element 21 and the second contact element 22. Another connection region 8 is electrically conductively connected to the first and second vias 31, 32. In the unmounted state of the semiconductor chip, the connection regions 7, 8 are exposed. In the semiconductor chip of Fig. 1A is a surface-mount semiconductor chip.

[0073] In the Fig. 1B is the semiconductor chip of the Fig. 1A in perspective view. For reasons of clarity, the carrier 6 and the first 21 and second 22 contact elements are not shown. Fig. 1A is a sectional view along the dashed-dotted line of the Fig. 1B.

[0074] In the Fig. 1B shows that the second semiconductor layer sequence 12 is formed contiguously, and the first semiconductor layer sequence 11 is formed from a plurality of semiconductor blocks 11d. The semiconductor blocks 11d are arranged along the second semiconductor layer sequence 12 and spaced apart from one another in pairs. A grid of trenches separates the semiconductor blocks 11d, with a semiconductor block located in each mesh of the grid. The second contact element 22 (not shown) extends in the region between each two adjacent semiconductor blocks 11d up to the second semiconductor layer sequence 12 and fills the grid of trenches.

[0075] The second vias 32 are arranged in the region of the intersection points of the grid lines. Each of the semiconductor blocks 11d is uniquely assigned one of the first vias 31. The first vias 31 each extend through the assigned semiconductor block 11d.

[0076] In the Fig. 1C is the optoelectronic semiconductor chip of the Fig. 1B shows another perspective view, again without the carrier and contact elements. A section of the semiconductor chip is also shown enlarged.

[0077] In the Fig. 2, a second embodiment of the semiconductor chip is shown in a cross-sectional view. In contrast to the semiconductor chip of Fig. 1A, the first contact element 21 and the second contact element 22 can be electrically contacted independently of one another. In particular, the first contact element 21 and the second contact element 22 are not formed contiguously. The first contact element 21 is electrically connected to a connection area 7a on a rear side of the carrier 6. The second contact element 22 is electrically connected to a connection area 7b on the rear side of the carrier 6, which is different from the connection area 7a. The two connection areas 7a, 7b can be contacted or energized individually and independently of one another.

[0078] In the Fig. 3 shows a third embodiment of the semiconductor chip. Unlike in the Fig. 2, it is not the first contact element 21 and the second contact element 22 that can be contacted individually and independently of one another, but rather the first vias 31 and the second vias 32. The first vias 31 are electrically connected to a dedicated connection area 8a on the rear side of the carrier 6, and the second vias 32 are electrically connected to a dedicated connection area 8b on the rear side of the carrier 6. The connection areas 8a, 8b can be contacted or energized individually and independently of one another.

[0079] In the Fig. 4 shows a fourth embodiment of the optoelectronic semiconductor chip. In contrast to the optoelectronic semiconductor chip of Fig. 1, the second contact element 22 in the region adjacent to the second semiconductor layer sequence 12 is not formed of metal, but rather by an electrically conductive Bragg mirror 22a made of several transparent layers with different refractive indices. The layers of the mirror 22a comprise, for example, different conductive oxides.

[0080] In the Fig. 5A shows a fifth embodiment of the optoelectronic semiconductor chip, again in cross-sectional view. In contrast to the embodiment of Fig. 4, the Bragg mirror 22a is not made of electrically conductive, transparent layers, but of dielectric layers. To still enable contact with the second semiconductor layer sequence 12, the mirror 22a is interspersed with metallic contact pins 22b, which electrically connect the electrically conductive material of the second contact element 22 to the second semiconductor layer sequence 12.

[0081] Likewise, a dielectric mirror can be arranged between the first contact element 21 and the first semiconductor layer sequence 11, wherein an electrical connection between the first semiconductor layer sequence 11 and the first contact element 21 is provided by contact mandrels.

[0082] In the Fig. 5B is the optoelectronic semiconductor chip of the Fig. 5A in a cross-sectional view during a section through and along the connecting layer 14. Here, it can be seen, firstly, that in the present exemplary embodiment, the second contact element 22 does not form a grid around semiconductor blocks of the first semiconductor layer sequence. Rather, the second contact element 22 is guided in the region of rectangular openings through the first semiconductor layer sequence 11. The first semiconductor layer sequence 11 is, for example, formed contiguously over its entire lateral extent. In the region of the openings through the first semiconductor layer sequence 11, the second vias 32 are also guided through the second contact element 22. The first vias 31 are indicated as dashed circles and are arranged in the region outside the openings. The second contact element 22 comprises a dielectric Bragg mirror 22a through which the contact mandrels 22b extend.

[0083] In the Fig. 6A to 6F show a first embodiment of the method for producing an optoelectronic semiconductor chip using several intermediate positions.

[0084] In the first position of the Fig. 6A, a first semiconductor layer sequence 11 and a second semiconductor layer sequence 12 are applied to one another by means of a connecting layer 14, in particular an adhesive layer 14. This results in a composite 1.

[0085] In the second position of the Fig. 6B, openings are introduced into the first semiconductor layer sequence 11 from a rear side 13 opposite a front side 10 of the composite 1. The openings penetrate the first semiconductor layer sequence 11 and the connecting layer 14 completely and extend to the second semiconductor layer sequence 12. The openings can form a connected grid (see, for example, Fig. 1B) or they may be pairs of spaced-apart breakthroughs that are not connected (see, for example, Fig. 5B).

[0086] In the Fig. 6C shows a position in which a first contact element 22 is formed in the openings, which is electrically conductively connected to a first layer 12a of the second semiconductor layer sequence 12. In the region of the openings, the second contact element 22 is electrically insulated from the first semiconductor layer sequence 11 by an insulating material 5.

[0087] In the Fig. 6D shows a further position in the method in which a first contact element 21 is formed on the rear side 13. The first contact element 21 serves to contact the first semiconductor layer sequence 11 and is electrically conductively connected to a first layer 11a of the first semiconductor layer sequence 11. In the present case, the first contact element 21 is also electrically conductively connected to the second contact element 22. Unlike in the Fig. 6C and Fig. 6D, the two contact elements 21, 22 could also be formed simultaneously in a common process step.

[0088] In the Fig. 6E shows a position in the process in which first vias 31 and second vias 32 are formed. The first vias 31 extend from the rear side 13 through the first layer 11a and the active layer 11b of the first semiconductor layer sequence 11 and terminate in a second layer 11c of the first semiconductor layer sequence 11. The second vias 32 extend from the rear side 13 completely through the first semiconductor layer sequence 11 and the connecting layer 14, cross the first layer 12a and the active layer 12b of the second semiconductor layer sequence 12, and terminate in a second layer 12c of the second semiconductor layer sequence 12. The first and second vias 31, 32 can be produced simultaneously or sequentially.

[0089] In the Fig. Figure 6F shows a position in the process after a carrier 6 has been applied to the back side 13 of the assembly 1. The contact elements 21, 22 and vias 31, 32 can be electrically contacted on a side of the carrier 6 facing away from the assembly 1 by means of connection areas 7, 8. Fig. 6F also shows an embodiment of a finished optoelectronic semiconductor chip.

[0090] In the Fig. 7A to 7E show a second embodiment of the method using intermediate positions.

[0091] In the position of Fig. 7A, a second semiconductor layer sequence 12 is provided. Furthermore, a plurality of semiconductor blocks 11d are provided. In the present case, the semiconductor blocks 11d are provided in the form of micro-LED chips 11d. These micro-LED chips 11d each already comprise a second via 32 extending from one side through the active layer 11b. On the same side from which the second via 32 extends, a first contact element 21 is also arranged. The micro-LED chips 11d can be contacted via the first contact element 21 and the first via 31.

[0092] In the Fig. 7A, the semiconductor blocks 11d are arranged spaced apart from one another on the second semiconductor layer sequence 12 using a connecting layer 14.

[0093] In the Fig. 7B shows a position after the semiconductor blocks 11d have been attached to the second semiconductor layer sequence 12, thus forming a composite 1. All semiconductor blocks 11d together form a first semiconductor layer sequence 11 of the composite 1.

[0094] In the position of Fig. 7C, a second contact element 22 is now formed in the region between the semiconductor blocks 11d. The second contact element 22 extends to the second semiconductor layer sequence 12 and contacts it.

[0095] In the Fig. 7D shows a position in the process in which second vias 32 are formed, which are guided through the second contact element 22 in the region between the semiconductor blocks 11d and then protrude into the second semiconductor layer sequence 12, thereby penetrating the active layer 12b of the second semiconductor layer sequence 12.

[0096] In the Fig. 7E shows another position in which a carrier 6 is applied to the back 13 of the composite 1. Fig. 7E also shows an embodiment of a finished optoelectronic semiconductor chip. List of reference symbols 1 network 5 Insulation material 6 carriers 7, 7a, 7b, 8 connection area 10 Front 11 first semiconductor layer sequence 11a first layer of the first semiconductor layer sequence 11b active layer of the first semiconductor layer sequence 11c second layer of the first semiconductor layer sequence 11d semiconductor block 12 second semiconductor layer sequence 12a first layer of the second semiconductor layer sequence 12b active layer of the second semiconductor layer sequence 12c second layer of the second semiconductor layer sequence 13 Back 21 first contact element 22 second contact element 22a Mirror 22b Contact mandrel 31 first via 32 second via

Claims

[1] Optoelectronic semiconductor chip, comprising: - a composite (1) with a front side (10), a first semiconductor layer sequence (11) and a second semiconductor layer sequence (12) between the front side (10) and the first semiconductor layer sequence (1), - a first contact element (21) and a second contact element (22) on a side of the assembly (1) opposite the front side (10), - a first through-connection (31) and a second through-connection (32), each extending from the side opposite the front side (10) into the assembly (1), wherein - the first (11) and the second (12) semiconductor layer sequence (11) each comprise an active layer (11b, 12b) for generating or absorbing electromagnetic radiation, - the first contact element (21) and the first via (31) are designed for electrically contacting the first semiconductor layer sequence (11), - the second contact element (22) and the second via (32) are arranged for electrically contacting the second semiconductor layer sequence (12), - the first via (31) is passed through the active layer (11b) of the first semiconductor layer sequence (11) and the second via (32) is passed through the active layer (12b) of the second semiconductor layer sequence (12), - the contact elements (21, 22) and the through-contacts (31, 32) are arranged such that the first semiconductor layer sequence (11) and the second semiconductor layer sequence (12) are electrically connected in parallel, so that during operation charge carriers can flow through both semiconductor layer sequences (11, 12) simultaneously, wherein charge carriers flowing through the first semiconductor layer sequence (11) do not reach the second semiconductor layer sequence (12) and vice versa, and - the second via (32) is guided through the second contact element (22) and is electrically insulated from the second contact element (22). [2] Semiconductor chip according to claim 1, wherein the second contact element (22) is guided through the first semiconductor layer sequence (11) to the second semiconductor layer sequence (12). [3] Semiconductor chip according to claim 1 or 2, wherein - the first (21) and second (22) contact elements are electrically connected to each other and are at the same potential during normal operation, - the first (31) and the second (32) vias are electrically connected to one another and are at the same potential during normal operation. [4] Semiconductor chip according to claim 1 or 2, wherein - the first (21) and the second (22) contact element can be contacted independently of each other and / or - the first (31) and the second (32) vias can be contacted independently of each other. [5] Semiconductor chip according to one of the preceding claims, wherein the active layers (11b, 12b) are arranged to emit radiation of different wavelengths. [6] Semiconductor chip according to one of the preceding claims, wherein - the second semiconductor layer sequence (12) is formed continuously, - the first semiconductor layer sequence (11) comprises a plurality of laterally spaced semiconductor blocks (11d), - the semiconductor blocks (11d) are distributed along the second semiconductor layer sequence (12), - the second contact element (22) extends in the region between the semiconductor blocks (11d) up to the second semiconductor layer sequence (12). [7] Semiconductor chip according to one of the preceding claims, wherein the semiconductor chip comprises a plurality of the first (31) and / or second (32) vias. [8] Semiconductor chip according to claims 6 and 7, wherein at least one first via (31) is uniquely assigned to each semiconductor block (11d) of the first semiconductor layer sequence (11). [9] Semiconductor chip according to one of claims 1 to 5, wherein - the first (11) and the second (12) semiconductor layer sequences are each formed contiguously, - the first (11) and second (12) semiconductor layer sequences each extend over at least 80% of the lateral extent of the semiconductor chip. [10] A method for manufacturing a semiconductor chip, comprising the steps of: A) forming a composite (1) comprising a first semiconductor layer sequence (11) with an active layer (11b) and a second semiconductor layer sequence (12) with an active layer (12b), wherein the second semiconductor layer sequence (12) is arranged between a front side (10) of the composite (1) and the first semiconductor layer sequence (11), B1) forming a first contact element (21), B2) forming a first through-plating (31), wherein - the first via (31) is passed through the active layer (11b) of the first semiconductor layer sequence (11), - the first contact element (21) and the first via (31) are arranged for electrically contacting the first semiconductor layer sequence (11), C1) forming a second contact element (22) on a side of the assembly (1) opposite the front side (10), C2) forming a second through-contact (32), wherein - the second contact element (22) and the second via (32) are arranged for electrically contacting the second semiconductor layer sequence (12), - the second via (32) is guided through the active layer (12b) of the second semiconductor layer sequence (12), - the contact elements (21, 22) and the through-contacts (31, 32) are arranged such that the first semiconductor layer sequence (11) and the second semiconductor layer sequence (12) are electrically connected in parallel, so that during operation charge carriers can flow through both semiconductor layer sequences (11, 12) simultaneously, wherein charge carriers flowing through the first semiconductor layer sequence (11) do not reach the second semiconductor layer sequence (12) and vice versa, and wherein the second via (32) is guided through the second contact element (22) and is electrically insulated from the second contact element (22). [11] Method according to claim 10, wherein in step A) - a plurality of semiconductor blocks (11d) each having an active layer (11b) is provided, - the semiconductor blocks (11d) are applied as separate elements spaced apart from one another on the second semiconductor layer sequence (12) and together form the first semiconductor layer sequence (11). [12] Method according to claim 11, wherein step B2) is carried out before step A). [13] The method of claim 10, wherein - in step A) the first semiconductor layer sequence (11) is applied as a continuous semiconductor layer sequence on the second semiconductor layer sequence (12), - the first semiconductor layer sequence (11) is then segmented into a plurality of semiconductor blocks (11d). [14] Method according to one of claims 10 to 13, wherein in step A) the first semiconductor layer sequence (11) and the second semiconductor layer sequence (12) are fixed to one another by bonding. [15] Method according to one of claims 10 to 13, wherein in step A) the first semiconductor layer sequence (11) and the second semiconductor layer sequence (12) are glued to one another. [16] Method according to one of claims 10 to 13, wherein in step A) the first semiconductor layer sequence (11) and the second semiconductor layer sequence (12) are grown epitaxially on one another.

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