Light-emitting diodes that improve stress and their fabrication methods

Abstract

This disclosure provides a stress-improving light-emitting diode and its fabrication method, belonging to the field of semiconductor technology. The fabrication method includes: sequentially forming a buffer layer and a filler layer on a substrate; alternately performing multiple cooling growth stages and multiple heating growth stages to form a first insertion layer on the filler layer, wherein, during the cooling growth stage, a first sub-layer is formed at a first temperature, which is lower than the growth temperature of the filler layer; during the heating growth stage, a second sub-layer is formed at a second temperature, which is higher than the first temperature; and sequentially forming a first semiconductor layer, a light-emitting layer, and a second semiconductor layer on the first insertion layer, where the second temperature is lower than the growth temperature of the first semiconductor layer. This disclosure can improve the radiative recombination efficiency of charge carriers and improve the luminous efficiency of the LED.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a stress-improving light-emitting diode and a method for its fabrication. Background Technology

[0002] Light-emitting diodes (LEDs) are widely used in various light source fields such as backlighting, lighting, and landscaping due to their small size, long lifespan, rich and colorful colors, and low energy consumption.

[0003] In related technologies, the method for preparing an LED includes: forming a buffer layer, a leveling layer, a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked sequentially on a substrate.

[0004] However, there is a large lattice mismatch between the substrate and the semiconductor material. The lattice mismatch generates stress, and the high-temperature growth of the fill layer can also easily introduce stress. These stresses accumulate in the first semiconductor layer and extend upwards to the light-emitting layer, affecting the quality of the light-emitting layer. This leads to a decrease in the radiative recombination efficiency of electrons and holes in the light-emitting layer, thus affecting the luminous efficiency of the LED. Summary of the Invention

[0005] This disclosure provides a stress-improving light-emitting diode and its fabrication method, which can improve the radiative recombination efficiency of charge carriers and thus improve the luminous efficiency of the LED. The technical solution is as follows:

[0006] On one hand, a method for fabricating a light-emitting diode is provided, comprising: sequentially forming a buffer layer and a filler layer on a substrate; alternately performing multiple cooling growth stages and multiple heating growth stages to form a first insertion layer on the filler layer, wherein, in the cooling growth stage, a first sub-layer is formed at a first temperature, the first temperature being lower than the growth temperature of the filler layer; in the heating growth stage, a second sub-layer is formed at a second temperature, the second temperature being higher than the first temperature; and sequentially forming a first semiconductor layer, a light-emitting layer, and a second semiconductor layer on the first insertion layer, the second temperature being lower than the growth temperature of the first semiconductor layer.

[0007] Optionally, the difference between the second temperature and the first temperature is 20°C to 50°C.

[0008] Optionally, the first temperature is 1020°C to 1050°C, and the second temperature is 1040°C to 1070°C.

[0009] Optionally, forming the first insertion layer on the filler layer further includes: forming a third sub-layer at a third temperature, which is greater than the first temperature and less than the second temperature, before alternating between the plurality of cooling growth stages and the plurality of heating growth stages.

[0010] Optionally, the difference between the third temperature and the first temperature is 30°C to 60°C.

[0011] Optionally, the thickness of the third sub-layer is greater than the thickness of the first sub-layer and greater than the thickness of the second sub-layer.

[0012] Optionally, the method further includes: before forming the light-emitting layer, forming a second insertion layer on the first semiconductor layer in the following manner: forming a fourth sub-layer at a fourth temperature, the fourth temperature being lower than the growth temperature of the first semiconductor layer; forming a fifth sub-layer at a fifth temperature, the fifth temperature being lower than the fourth temperature; and forming a sixth sub-layer at a sixth temperature, the sixth temperature being lower than the fifth temperature and higher than the growth temperature of the light-emitting layer.

[0013] Optionally, the difference between the fourth temperature and the fifth temperature is 10°C to 40°C, and the difference between the fifth temperature and the sixth temperature is 20°C to 50°C.

[0014] Optionally, the fourth temperature is 1030°C to 1060°C, the fifth temperature is 1020°C to 1050°C, and the sixth temperature is 1000°C to 1040°C.

[0015] On the other hand, a light-emitting diode is provided, comprising a substrate, a buffer layer, a filler layer, a first insertion layer, a first semiconductor layer, a light-emitting layer, and a second semiconductor layer stacked sequentially; the first insertion layer comprises alternatingly stacked multiple first sub-layers and multiple second sub-layers, the first sub-layers being formed at a first temperature, the first temperature being lower than the growth temperature of the filler layer, and the second sub-layers being formed at a second temperature, the second temperature being higher than the first temperature and lower than the growth temperature of the first semiconductor layer.

[0016] The beneficial effects of the technical solutions provided in this disclosure are:

[0017] In this embodiment, since the growth temperature of the filler layer is generally high, a cooling growth stage is performed after the filler layer is formed. The first sublayer is formed at a first temperature lower than the growth temperature of the filler layer, which reduces the stress introduced during the high-temperature growth of the filler layer. Then, a heating growth stage is performed, forming the second sublayer at a second temperature higher than the growth temperature of the first sublayer but lower than the growth temperature of the first semiconductor layer. This stabilizes the strain of the first sublayer, ensuring good quality for both the first and second sublayers. Furthermore, since the growth temperature of the first semiconductor layer is also high, the second temperature is closer to the growth temperature of the first semiconductor layer than the first temperature, which helps reduce the probability of LED cracking due to stress abrupt changes caused by temperature changes during the subsequent formation of the first semiconductor layer. By alternating between multiple cooling growth stages and multiple heating growth stages, stress is released stably multiple times. The first insertion layer can effectively reduce the probability of stress extending upwards to the first semiconductor layer and the light-emitting layer, thereby improving the radiative recombination efficiency of charge carriers and increasing the luminous efficiency of the LED. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart of an LED manufacturing method provided in an embodiment of this disclosure;

[0020] Figure 2 This is a flowchart of another LED manufacturing method provided in this embodiment;

[0021] Figure 3 This is a schematic diagram of the structure of an LED provided in an embodiment of this disclosure.

[0022] Figure label:

[0023] 10: Substrate; 20: Buffer layer; 30: Filler layer; 40: First insertion layer; 41: First sublayer; 42: Second sublayer; 43: Third sublayer; 50: First semiconductor layer; 60: Light-emitting layer; 70: Second semiconductor layer; 80: Second insertion layer; 81: Fourth sublayer; 82: Fifth sublayer; 83: Sixth sublayer; 90: Electron blocking layer. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0025] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” and similar terms mean that the elements or objects preceding “comprising” encompass the elements or objects listed following “comprising” and their equivalents, and do not exclude other elements or objects. The terms “connection” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “top,” “bottom,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.

[0026] Figure 1 This is a flowchart illustrating a method for manufacturing an LED according to an embodiment of this disclosure. Figure 1 As shown, the preparation method includes:

[0027] In step S101, a buffer layer and a leveling layer are sequentially formed on the substrate.

[0028] In step S102, multiple cooling growth stages and multiple heating growth stages are performed alternately to form a first insertion layer on the filler layer.

[0029] In the cooling growth stage, the first sublayer is formed at a first temperature, which is lower than the growth temperature of the filler layer; in the heating growth stage, the second sublayer is formed at a second temperature, which is higher than the first temperature.

[0030] In step S103, a first semiconductor layer, a light-emitting layer, and a second semiconductor layer are sequentially formed on the first insertion layer.

[0031] The second temperature is lower than the growth temperature of the first semiconductor layer.

[0032] In this embodiment, since the growth temperature of the filler layer is generally high, a cooling growth stage is performed after the filler layer is formed. The first sublayer is formed at a first temperature lower than the growth temperature of the filler layer, which reduces the stress introduced during the high-temperature growth of the filler layer. Then, a heating growth stage is performed, forming the second sublayer at a second temperature higher than the growth temperature of the first sublayer but lower than the growth temperature of the first semiconductor layer. This stabilizes the strain of the first sublayer, ensuring good quality for both the first and second sublayers. Furthermore, since the growth temperature of the first semiconductor layer is also high, the second temperature is closer to the growth temperature of the first semiconductor layer than the first temperature, which helps reduce the probability of LED cracking due to stress abrupt changes caused by temperature changes during the subsequent formation of the first semiconductor layer. By alternating between multiple cooling growth stages and multiple heating growth stages, stress is released stably multiple times. The first insertion layer can effectively reduce the probability of stress extending upwards to the first semiconductor layer and the light-emitting layer, thereby improving the radiative recombination efficiency of charge carriers and increasing the luminous efficiency of the LED.

[0033] Figure 2 This is a flowchart of another LED fabrication method provided in this disclosure. Figure 2 As shown, the preparation method includes:

[0034] In step S201, a buffer layer is formed on the substrate.

[0035] Optionally, the substrate can be a sapphire substrate. Sapphire substrates are transparent substrates with good light transmittance, and they also have high mechanical strength and are easy to handle and clean.

[0036] For example, the substrate can be a patterned sapphire substrate with an array of protrusions on its surface.

[0037] In other embodiments, the substrate may also be a Si substrate or a SiC substrate, and this disclosure does not limit it.

[0038] Optionally, the buffer layer includes at least one of GaN, AlN, and AlGaN layers.

[0039] For example, the buffer layer includes a stacked low-temperature GaN layer and a high-temperature GaN layer.

[0040] Figure 3 This is a schematic diagram of the structure of an LED provided in an embodiment of this disclosure. Figure 3As shown, a low-temperature GaN layer can be grown in the metal-organic chemical vapor deposition (MOCVD) reaction chamber by controlling the temperature of the reaction chamber at 530°C to 560°C, and then a high-temperature GaN layer can be grown by controlling the temperature of the reaction chamber at 1000°C to 1100°C, thereby forming a buffer layer 20 on the substrate 10. The buffer layer 20 helps to reduce the lattice mismatch and thermal mismatch between the substrate 10 and the semiconductor material, thus ensuring better LED quality.

[0041] In step S202, a fill layer is formed on the buffer layer.

[0042] Optionally, the fill layer 30 is a GaN layer.

[0043] For example, the temperature of the reaction chamber can be controlled to be between 1090°C and 1120°C to grow a GaN layer, thereby forming a fill layer 30 on the buffer layer 20. The fill layer 30 is used to fill the surface of the buffer layer 20 away from the substrate 10, which helps to ensure better crystal quality.

[0044] In step S203, a first insertion layer is formed on the fill layer.

[0045] Step S203 includes alternating between multiple cooling growth stages and multiple heating growth stages. Specifically, during the cooling growth stage, a first sublayer 41 is formed at a first temperature, which is lower than the growth temperature of the filler layer 30; during the heating growth stage, a second sublayer 42 is formed at a second temperature, which is higher than the first temperature but lower than the growth temperature of the first semiconductor layer 50.

[0046] For example, the second temperature is lower than the growth temperature of the filler layer 30.

[0047] In other embodiments, the second temperature may also be greater than or equal to the growth temperature of the filler layer 30, and this disclosure does not limit this.

[0048] Optionally, the first insertion layer 40 is a GaN layer.

[0049] Optionally, the difference between the second temperature and the first temperature is between 20°C and 50°C. Within this range, the alternating cooling and heating growth stages can effectively reduce the stress caused by lattice mismatch, high-temperature growth, and sudden temperature changes, and can ensure good quality of the first sublayer 41 and the second sublayer 42.

[0050] For example, the difference between the second temperature and the first temperature can be 20°C, 40°C, or 50°C, etc.

[0051] Optionally, the first temperature is between 1020°C and 1050°C. If the first temperature is too low, the difference between the growth temperature of the cooling growth stage and the growth temperature of the filler layer 30 may be too large, causing stress abrupt changes due to temperature changes. If the first temperature is too high, it may affect the stress reduction effect of the cooling growth stage. If the first temperature is within this range, the stress introduced when the filler layer 30 is grown at high temperature can be effectively reduced without causing stress abrupt changes.

[0052] For example, the first temperature can be 1020°C, 1040°C, or 1050°C, etc.

[0053] Optionally, the second temperature is between 1040°C and 1070°C. If the second temperature is too low, the stress release effect during the heating growth stage will be poor; if the second temperature is too high, the temperature change from the cooling growth stage to the heating growth stage may be too large, causing stress abrupt changes. Within this range, the second temperature can effectively reduce the stress during the low-temperature growth of the first sublayer 41 after the cooling growth stage, stabilize the strain of the first sublayer 41, ensure good quality of the first sublayer 41 and the second sublayer 42, and help reduce the probability of LED cracking caused by stress abrupt changes due to temperature changes during the subsequent formation of the first semiconductor layer 50.

[0054] For example, the second temperature is 1040°C, 1060°C, or 1070°C, etc.

[0055] It should be noted that the first and second temperature ranges mentioned above overlap; the first temperature simply needs to be lower than the second temperature.

[0056] like Figure 3 As shown, the first insertion layer 40 of the LED includes two alternately stacked first sublayers 41 and second sublayers 42.

[0057] For example, the first sublayer 41 and the second sublayer 42 are made of the same material, which is GaN layer.

[0058] For example, the cooling growth stage forming the first sublayer 41 and the heating growth stage forming the second sublayer 42 differ only in temperature conditions and growth time. Other growth conditions can be the same, such as pressure conditions, Ga source type, Ga source flow rate, N source type and N source flow rate.

[0059] In other embodiments, the formation of the first sublayer 41 during the cooling growth stage and the formation of the second sublayer 42 during the heating growth stage differ not only in temperature conditions and growth time, but also in other growth conditions. For example, the pressure conditions, Ga source flow rate, N source flow rate, and growth rate may also be different, and this disclosure does not limit this.

[0060] Optionally, the thicknesses of the first first sublayer 41, the first second sublayer 42, the second first sublayer 41, and the second second sublayer 42 are all different along the direction from the filler layer 30 to the first semiconductor layer 50.

[0061] For example, the thickness of the first sublayer 41 is greater than the thickness of the second sublayer 41, and the thickness of the first second sublayer 42 is greater than the thickness of the second sublayer 42. Thus, forming a thicker first sublayer 41 and a thicker second sublayer 42 during the first cooling growth stage and the first heating growth stage after the high-temperature growth of the filler layer 30, respectively, can effectively reduce the stress introduced during the high-temperature growth of the filler layer 30 and ensure good quality of the first sublayer 41 and the second sublayer 42. Forming a thinner first sublayer 41 and a thinner second sublayer 42 during the second cooling growth stage and the second heating growth stage, respectively, can shorten the time for forming the first insertion layer 40 while ensuring stable stress release multiple times, thereby improving fabrication efficiency.

[0062] For example, the thickness of the first sublayer 41 is 30 nm to 60 nm.

[0063] For example, the thickness of the first second sublayer 42 is 35 nm to 70 nm.

[0064] For example, the thickness of the second first sublayer 41 is 20 nm to 50 nm.

[0065] For example, the thickness of the second sublayer 42 is 25 nm to 50 nm.

[0066] Optionally, the growth time of the first sublayer 41 is longer than that of the second sublayer 41, and the growth time of the first second sublayer 42 is longer than that of the second second sublayer 42. This helps to reduce the stress introduced by prolonged high-temperature growth or prolonged low-temperature growth, and also helps to improve the preparation efficiency.

[0067] Optionally, the growth time of the first sublayer 41 is 1 min to 3 min.

[0068] Optionally, the growth time of the first second sublayer 42 is 1 min to 3 min.

[0069] Optionally, the growth time of the second first sublayer 41 is 1 min to 2 min.

[0070] Optionally, the growth time of the second sublayer 42 is 1 min to 2 min.

[0071] In other embodiments, the thickness of the first sublayer 41 is the same, and the thickness of the second sublayer 42 is the same; or, the growth time of the first sublayer 41 is the same, and the growth time of the second sublayer 42 is the same; or, the first insertion layer 40 includes more first sublayers 41 and more second sublayers 42 stacked alternately, etc., which are not limited in this disclosure.

[0072] Optionally, step S203 further includes: before alternating between multiple cooling growth stages and multiple heating growth stages, forming a third sub-layer 43 at a third temperature, where the third temperature is higher than the first temperature but lower than the second temperature. This adds a cooling growth process between the formation of the filler layer 30 and the cooling growth stages, serving as a transition and facilitating effective stress release after the filler layer 30 is formed at high temperatures, while also preventing stress abrupt changes.

[0073] Optionally, the difference between the third temperature and the first temperature is 30°C to 60°C. In this way, performing an additional cooling growth between the filler layer 30 and the first sublayer 41 to form the third sublayer 43 can reduce the stress introduced by the high-temperature formation of the filler layer 30, and will not cause stress abrupt changes during the growth of the first sublayer 41, thus preventing LED cracking.

[0074] Optionally, the third temperature is between 1050°C and 1080°C. Within this temperature range, the third sublayer 43 can prevent stress abrupt changes caused by temperature sudden changes during the intermediate cooling process, effectively reducing stress and decreasing the probability of stress extending upwards.

[0075] For example, the third sublayer 43 is made of the same material as the first sublayer 41 and the second sublayer 42, which is a GaN layer.

[0076] Optionally, the thickness of the third sub-layer 43 is greater than the thickness of the first sub-layer 41 and greater than the thickness of the second sub-layer 42. In this way, by forming a thicker third sub-layer 43 between the filler layer 30 and the first sub-layer 41, it is beneficial to effectively release stress after the filler layer 30 is formed at high temperature.

[0077] For example, the thickness of the third sublayer 43 is 40 nm to 80 nm.

[0078] It should be noted that the thickness of the third sublayer 43 overlaps with the thickness range of the first sublayer 41 and the second sublayer 42. It is sufficient to ensure that the thickness of the third sublayer 43 is greater than the thickness of the first sublayer 41 and greater than the thickness of the second sublayer 42.

[0079] Optionally, the growth time of the third sublayer 43 is 2 to 3 minutes.

[0080] In step S204, a first semiconductor layer is formed on the first insertion layer.

[0081] Optionally, the first semiconductor layer 50 can be an N-type GaN layer.

[0082] For example, the first semiconductor layer 50 is a Si-doped GaN layer.

[0083] For example, the temperature of the reaction chamber can be controlled to be between 950°C and 1150°C to grow an N-type GaN layer in order to form a first semiconductor layer 50 on the first insertion layer 40.

[0084] In step S205, a second insertion layer is formed on the first semiconductor layer.

[0085] Optionally, step S205 includes: forming a fourth sub-layer 81 at a fourth temperature, where the fourth temperature is lower than the growth temperature of the first semiconductor layer 50; forming a fifth sub-layer 82 at a fifth temperature, where the fifth temperature is lower than the fourth temperature; and forming a sixth sub-layer 83 at a sixth temperature, where the sixth temperature is lower than the fifth temperature but higher than the growth temperature of the light-emitting layer 60. This ensures that less stress is introduced during the formation of the second insertion layer 80, while stably releasing the stress from the high-temperature growth of the first semiconductor layer 50. This reduces the probability of cracking due to stress abrupt changes caused by excessive temperature differences, improves LED reliability, and effectively reduces the probability of stress extending to the light-emitting layer 60, thereby improving the radiative recombination efficiency of charge carriers and increasing the luminous efficiency of the LED.

[0086] Optionally, the second insertion layer 80 is an N-type GaN layer.

[0087] For example, the second insertion layer 80 is a Si-doped GaN layer.

[0088] Optionally, the difference between the fourth and fifth temperatures is between 10°C and 40°C.

[0089] Optionally, the difference between the fifth and sixth temperatures is 20°C to 50°C.

[0090] In this way, during the formation of the second insertion layer 80, the temperature difference during the formation of the fourth sublayer 81, the fifth sublayer 82 and the sixth sublayer 83 through three cooling processes is small, which can stably release stress and prevent stress abrupt changes between different sublayers due to temperature changes.

[0091] Optionally, the fourth temperature is 1030°C to 1060°C.

[0092] For example, the fourth temperature can be 1030°C, 1050°C, or 1060°C, etc.

[0093] Optionally, the fifth temperature is 1020°C to 1050°C.

[0094] For example, the fifth temperature can be 1020°C, 1040°C, or 1050°C, etc.

[0095] Optionally, the sixth temperature is 1000°C to 1040°C.

[0096] For example, the sixth temperature can be 1000℃, 1020℃, or 1040℃, etc.

[0097] In this way, the fourth sublayer 81, the fifth sublayer 82, and the sixth sublayer 83 can allow the stress to be released stably multiple times, and the sixth temperature is closer to the growth temperature of the light-emitting layer 60, which can further reduce the probability of stress extending upward to the light-emitting layer 60 and improve the radiative recombination efficiency of charge carriers.

[0098] It should be noted that the above-mentioned fourth, fifth, and sixth temperature ranges overlap. It is sufficient to ensure that the fifth temperature is lower than the fourth temperature and the sixth temperature is lower than the fifth temperature.

[0099] For example, the fourth sublayer 81, the fifth sublayer 82 and the sixth sublayer 83 are all made of the same material, which is a Si-doped GaN layer.

[0100] For example, the thickness of the fourth sublayer 81 is 30 nm to 60 nm.

[0101] For example, the thickness of the fifth sublayer 82 is 20 nm to 50 nm.

[0102] For example, the thickness of the sixth sublayer 83 is 10 nm to 50 nm.

[0103] Optionally, the growth time of the fourth sublayer 81 is 1.5 min to 3 min.

[0104] Optionally, the growth time of the fifth sublayer 82 is 1 to 2 minutes.

[0105] Optionally, the growth time of the sixth sublayer 83 is 0.5 min to 2 min.

[0106] In other embodiments, the number of sublayers of the second insertion layer 80 may be more or fewer, and this disclosure does not limit this.

[0107] In step S206, a light-emitting layer is formed on the second insertion layer.

[0108] Optionally, the light-emitting layer 60 is a multi-quantum-well layer, comprising alternating pairs of quantum well layers and quantum barrier layers. Depending on the emission wavelength range of the LED, the light-emitting layer 60 can be made of different materials. For example, the light-emitting layer 60 of a blue-green LED can be made of alternating pairs of InGaN and GaN layers, while the light-emitting layer 60 of a red LED can be made of alternating pairs of InGaAs and GaAs layers.

[0109] For example, the light-emitting layer 60 includes 6 to 12 pairs of alternately stacked InGaN and GaN layers. For example, it may be 9 pairs of alternately stacked InGaN and GaN layers, or of course other pairs, which are not limited in this disclosure.

[0110] For example, the growth temperature of the quantum well layer is 700°C to 850°C.

[0111] For example, the growth temperature of the quantum barrier layer is 850°C to 950°C.

[0112] In step S207, an electron blocking layer is formed on the light-emitting layer.

[0113] Optionally, the electron blocking layer 90 is a p-type AlGaN layer.

[0114] For example, the electron blocking layer 90 is a Mg-doped AlGaN layer.

[0115] For example, the temperature of the reaction chamber can be controlled to be between 1000°C and 1100°C to grow a Mg-doped AlGaN layer, thereby forming an electron blocking layer 90 on the light-emitting layer 60. The electron blocking layer 90 can block electrons, reducing the probability of electrons escaping from the light-emitting layer 60 to the second semiconductor layer 70, thereby improving the radiative recombination efficiency of charge carriers and improving the luminous efficiency of the LED.

[0116] In step S208, a second semiconductor layer is formed on the electron blocking layer.

[0117] Optionally, the second semiconductor layer 70 can be a P-type GaN layer.

[0118] For example, the second semiconductor layer 70 is a Mg-doped GaN layer.

[0119] For example, the temperature of the reaction chamber can be controlled to be between 950°C and 1050°C to grow a P-type GaN layer in order to form a second semiconductor layer 70 on the electron blocking layer 90.

[0120] It should be noted that, Figure 3 The film structure of the LED shown and the materials of the film layers are only examples. In other embodiments, the LED may include more or fewer film layers, and the materials of each film layer may be selected according to actual needs. The disclosure does not limit these aspects.

[0121] like Figure 3 As shown, this disclosure also provides an LED that uses... Figure 1 or Figure 2 Prepared by the method shown.

[0122] like Figure 3As shown, the LED includes a substrate 10, a buffer layer 20, a filler layer 30, a first insertion layer 40, a first semiconductor layer 50, a light-emitting layer 60, and a second semiconductor layer 70 stacked in sequence.

[0123] The first insertion layer 40 includes a plurality of alternating first sub-layers 41 and a plurality of second sub-layers 42. The first sub-layers 41 are formed at a first temperature, which is lower than the growth temperature of the filler layer 30. The second sub-layers 42 are formed at a second temperature, which is higher than the first temperature and lower than the growth temperature of the first semiconductor layer 50.

[0124] The beneficial effects of the embodiments disclosed herein are described in [reference]. Figure 1 The preparation method and related embodiments are not described in detail here.

[0125] like Figure 3 As shown, the first insertion layer 40 includes a third sub-layer 43, a first sub-layer 41, a second sub-layer 42, and a second sub-layer 42 stacked sequentially in a direction away from the fill layer 30.

[0126] Optionally, the LED further includes a second insertion layer 80 located between the first semiconductor layer 50 and the light-emitting layer 60.

[0127] For example, the second insertion layer 80 includes a fourth sublayer 81, a fifth sublayer 82 and a sixth sublayer 83 stacked sequentially in a direction away from the first semiconductor layer 50.

[0128] Optionally, the LED also includes an electron blocking layer 90 located between the light-emitting layer 60 and the second semiconductor layer 70.

[0129] Optionally, the material, thickness, number of cycles, and growth temperature of each layer can be found in [reference needed]. Figures 1 to 3 Detailed descriptions of the preparation method and related embodiments are omitted here.

[0130] The above description is not intended to limit this disclosure in any way. Although this disclosure has been disclosed above through embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this disclosure. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this disclosure without departing from the content of the technical solution of this disclosure shall still fall within the scope of the technical solution of this disclosure.

Claims

1. A method for fabricating a light-emitting diode, characterized in that, include: A buffer layer (20) and a leveling layer (30) are sequentially formed on the substrate (10); Multiple cooling growth stages and multiple heating growth stages are alternately performed to form a first insertion layer on the filler layer (30), wherein, in the cooling growth stage, a first sublayer (41) is formed at a first temperature, the first temperature being lower than the growth temperature of the filler layer (30); in the heating growth stage, a second sublayer (42) is formed at a second temperature, the second temperature being higher than the first temperature; A first semiconductor layer (50), a light-emitting layer (60), and a second semiconductor layer (70) are sequentially formed on the first insertion layer (40), wherein the second temperature is lower than the growth temperature of the first semiconductor layer (50).

2. The preparation method according to claim 1, characterized in that, The difference between the second temperature and the first temperature is 20°C to 50°C.

3. The preparation method according to claim 2, characterized in that, The first temperature is 1020°C to 1050°C, and the second temperature is 1040°C to 1070°C.

4. The preparation method according to any one of claims 1 to 3, characterized in that, The formation of the first insertion layer (40) on the filler layer (30) further includes: Before alternating between the plurality of cooling growth stages and the plurality of heating growth stages, a third sublayer (43) is formed at a third temperature, which is greater than the first temperature and less than the second temperature.

5. The preparation method according to claim 4, characterized in that, The difference between the third temperature and the first temperature is 30°C to 60°C.

6. The preparation method according to claim 4, characterized in that, The thickness of the third sublayer (43) is greater than the thickness of the first sublayer (41) and greater than the thickness of the second sublayer (42).

7. The preparation method according to any one of claims 1 to 3 and claims 5 to 6, characterized in that, The method further includes: Before forming the light-emitting layer (60), a second insertion layer (80) is formed on the first semiconductor layer (50) in the following manner: a fourth sublayer (81) is formed at a fourth temperature, the fourth temperature being lower than the growth temperature of the first semiconductor layer (50); a fifth sublayer (82) is formed at a fifth temperature, the fifth temperature being lower than the fourth temperature; and a sixth sublayer (83) is formed at a sixth temperature, the sixth temperature being lower than the fifth temperature and higher than the growth temperature of the light-emitting layer (60).

8. The preparation method according to claim 7, characterized in that, The difference between the fourth temperature and the fifth temperature is 10°C to 40°C, and the difference between the fifth temperature and the sixth temperature is 20°C to 50°C.

9. The preparation method according to claim 8, characterized in that, The fourth temperature is 1030°C to 1060°C, the fifth temperature is 1020°C to 1050°C, and the sixth temperature is 1000°C to 1040°C.

10. A light-emitting diode, characterized in that, It includes a substrate (10), a buffer layer (20), a fill layer (30), a first insertion layer (40), a first semiconductor layer (50), a light-emitting layer (60), and a second semiconductor layer (70) stacked in sequence; The first insertion layer (40) includes alternating layers of a plurality of first sublayers (41) and a plurality of second sublayers (42). The first sublayers (41) are formed at a first temperature, which is lower than the growth temperature of the filler layer (30). The second sublayers (42) are formed at a second temperature, which is higher than the first temperature and lower than the growth temperature of the first semiconductor layer (50).

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